50 mA/500 mA, Ultralow Power Step-Down
Regulator With Battery Voltage Monitor
Data Sheet ADP5303
Rev. B Document Feedback
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FEATURES
Input supply voltage range: 2.15 V to 6.50 V
Operates down to 2.00 V
Ultralow 240 nA quiescent current with no load
Selectable output voltages of 1.2 V to 3.6 V, or 0.8 V to 5.0 V
±1.5% output accuracy over the full temperature range in
pulse-width modulation (PWM) mode
Selectable hysteresis mode or PWM operation mode
Output current
Up to 50 mA in hysteresis mode
Up to 500 mA in PWM mode
VINOK flag to monitor input battery voltage
100% duty cycle operation mode
2 MHz switching frequency with optional synchronization
input from 1.5 MHz to 2.5 MHz
Quick output discharge (QOD) option
UVLO, OCP, and TSD protection
9-ball, 1.65 mm × 1.87 mm WLCSP
Junction temperature: −40°C to +125°C
APPLICATIONS
Energy (gas, water) metering
Portable and battery-powered equipment
Medical applications
Keep-alive power supply
TYPICAL APPLICATION CIRCUIT
PWM
2.2µH
SW
PGND
FB
10µF
10µF
V
OUT
PVIN
SYNC/
MODE
EN
VID
V
IN
=
2.15V TO 6.50V
ADP5303
(WLCSP-9)
HYS
R0
OFF
ON
VID0: 1.2V
VID1: 1.5V
VID2: 1.8V
VID3: 2.0V
VID4: 2.1V
VID5: 2.2V
VID6: 2.3V
VID7: 2.4V
VID8: 2.5V
VID9: 2.6V
VID10: 2.7V
VID11: 2.8V
VID12: 2.9V
VID13: 3.0V
VID14: 3.3V
VID15: 3.6V
AGND
VINOK
13444-001
Figure 1.
GENERAL DESCRIPTION
The ADP5303 is high efficiency, ultralow quiescent current
step-down regulator that draws only 240 nA quiescent current
to regulate the output at no load.
The ADP5303 runs from an input voltage of 2.15 V to 6.50 V,
allowing the use of multiple alkaline or NiMH cells, Li-Ion cells,
or other power sources. The output voltage is selectable from 0.8 V
to 5.0 V by an external VID resistor and a factory fuse. The
total solution requires only four tiny external components.
The ADP5303 can operate between hysteresis mode and PWM
mode via the SYNC/MODE pin. In hysteresis mode, the regulator
achieves excellent efficiency at less than 1 mW and provides up
to 50 mA of output current. In PWM mode, the regulator
produces a lower output ripple and supplies up to 500 mA of
output current. The flexible configuration capability during
operation of the device enables very efficient power management
to meet both long battery life and low system noise requirements.
The ADP5303 integrates an ultralow power comparator with a
factory programmable voltage reference to monitor the input
battery voltage. The regulator runs at a 2 MHz switching frequency
in PWM mode and the SYNC/MODE pin can be synchronized
to an external clock from 1.5 MHz to 2.5 MHz.
Other key features in the ADP5303 include separate enabling,
QOD, and safety features such as overcurrent protection (OCP),
thermal shutdown (TSD), and input undervoltage
lockout (UVLO).
The ADP5303 is available in 9-ball, 1.65 mm × 1.87 mm
WLCSP package rated for the −40°C to +125°C junction
temperature range.
ADP5303 Data Sheet
Rev. B | Page 2 of 21
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Typical Application Circuit ............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Detailed Functional Block Diagram .............................................. 3
Specifications ..................................................................................... 4
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 14
Buck Regulator Operational Modes ......................................... 14
Oscillator and Synchronization ................................................ 14
Adjustable and Fixed Output Voltages .................................... 14
Undervoltage Lockout (UVLO) ............................................... 15
Enable/Disable ............................................................................ 15
Current Limit .............................................................................. 15
Short-Circuit Protection............................................................ 15
Soft Start ...................................................................................... 15
Startup with Precharged Output .............................................. 15
100% Duty Cycle Operation ..................................................... 15
Active Discharge ......................................................................... 15
VINOK Function........................................................................ 15
Thermal Shutdown .................................................................... 15
Applications Information .............................................................. 16
External Component Selection ................................................ 16
Selecting the Inductor ................................................................ 16
Output Capacitor ........................................................................ 16
Input Capacitor ........................................................................... 17
Efficiency ..................................................................................... 17
Printed Circuit Board Layout Recommendations ................. 18
Typical Application Circuits ......................................................... 19
Factory Programmable Options ................................................... 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 21
REVISION HISTORY
3/2019—Rev. A to Rev. B
Changes to Adjustable and Fixed Output Voltages Section ...... 14
Changes to Table 8, Table 9, Table 10, and Table 11 .................. 20
Changes to Ordering Guide .......................................................... 21
6/2016—Rev. 0 to Rev. A
Change to Features Section and General Description
Section ................................................................................................ 1
Change to SYNC Clock Range Parameter, Table 1 ....................... 4
Change to Table 4 .............................................................................. 7
Change to Oscillator and Synchronization Section ................... 14
Changes to Table 8 .......................................................................... 20
10/2015—Revision 0: Initial Version
Data Sheet ADP5303
Rev. B | Page 3 of 21
DETAILED FUNCTIONAL BLOCK DIAGRAM
MODE
INTERNAL
FEEDBACK
RESISTOR
DIVIDER
SOFT
START
VINOK_TH
V
INO
K
PVIN
CONTROL
LOGIC
I
LIM_PWM
I
LIM_HYS
STANDBY
0.808V
–0.6A(PWM)
0.8V
V TO I
0A(HYS)
0.8V
PWM
DRIVER
PVIN PVIN
SW
PGND
FB
1.2V
0.4V
SYNC
MODE
1.2V
0.4V
PVIN
UVLO
BAND GAP BIAS
AND
HOUSEKEEPING
KEEP ALIVE BLOCK
2.06V
2.00V
EN
SYNC/
MODE
DRIVER
PVIN
Σ
VID
AGND
2MHz
OSC
SLOPE
COMPENSATION
13444-002
ADP5303
Figure 2. Detailed Functional Block Diagram
ADP5303 Data Sheet
Rev. B | Page 4 of 21
SPECIFICATIONS
VIN = 3.6 V, V OUT = 2.5 V, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications,
unless otherwise noted.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
INPUT SUPPLY VOLTAGE RANGE
V
IN
2.15
6.50
V
SHUTDOWN CURRENT ISHUTDOWN 18 40 nA VEN = 0 V, −40°C ≤ TJ ≤ +85°C
18 130 nA VEN = 0 V, −40°C ≤ TJ ≤ +125°C
QUIESCENT CURRENT
Operating Quiescent Current in Hysteresis
Mode
IQ_HYS 240 360 nA −40°C ≤ TJ ≤ +85°C
240 520 nA −40°C ≤ TJ ≤ +125°C
640 1500 nA 100% duty cycle operation, VIN = 3.0 V,
VOUT set to 3.3 V
Operating Quiescent Current in PWM Mode IQ_PWM 425 630 µA
UNDERVOLTAGE LOCKOUT UVLO
UVLO Threshold
Rising VUVLO_RISING 2.06 2.14 V
Falling VUVLO_FALLING 1.90 2.00 V
OSCILLATOR CIRCUIT
Switching Frequency in PWM Mode fSW 1.7 2.0 2.3 MHz
Feedback (FB) Threshold of Frequency Fold VOSC_FOLD 0.3 V
SYNCHRONIZATION THRESHOLD1
SYNC Clock Range SYNCCLOCK 1.5 2.5 MHz
SYNC High Level Threshold SYNCHIGH 1.2 V
SYNC Low Level Threshold SYNCLOW 0.4 V
SYNC Duty Cycle Range SYNCDUTY 100 1/fSW −
150
ns
SYNC/MODE Leakage Current ISYNC_LEAKAGE 50 150 nA VSYNC/MODE = 3.6 V
MODE TRANSITION
Transition Delay from Hysteresis Mode to
PWM Mode
tHYS_TO_PWM 20 Clock
cycles
SYNC/MODE goes logic high from
logic low
EN PIN
Input Voltage Threshold
High VIH 1.2 V
Low VIL 0.4 V
Input Leakage Current IEN_LEAKAGE 25 nA
FB PIN
Output Options by VID Resistor VOUT_OPT 0.8 5.0 V 0.8 V to 5.0 V in various factory options
PWM Mode
Fixed VID Code Voltage Accuracy VFB_PWM_FIX −0.6 +0.6 % TJ = 25°C, output voltage setting via
factory fuse
−1.2 +1.2 % −40°C ≤ TJ ≤ +125°C
Adjustable VID Code Voltage Accuracy VFB_PWM_ADJ −1.5 +1.5 % Output voltage setting via the VID
resistor
Hysteresis Mode
Fixed VID Code Threshold Accuracy from
Active Mode to Standby Mode
VFB_HYS_FIX −0.75 +0.75 % TJ = 25°C
−2.5 +2.5 % −40°C ≤ TJ ≤ +125°C
Adjustable VID Code Threshold Accuracy
from Active Mode to Standby Mode
VFB_HYS_ADJ −3 +3 % −40°C ≤ TJ ≤ +125°C
Data Sheet ADP5303
Rev. B | Page 5 of 21
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Hysteresis of Threshold Accuracy from
Active Mode to Standby Mode
VFB_HYS (HYS) 1 %
Feedback Bias Current IFB 66 95 nA Output Option 0, VOUT = 2.5 V
25 45 nA Output Option 1, VOUT = 1.3 V
SW PIN
High-Side Power FET On Resistance RDS (ON) H 386 520 mΩ Pin to pin measurement
Low-Side Power FET On Resistance RDS (ON) L 299 470 mΩ Pin to pin measurement
Current-Limit in PWM Mode
I
LIM_PWM
800
1000
1200
mA
SYNC/MODE = high
Peak Current in Hysteresis Mode ILIM_HYS 265 mA SYNC/MODE = low
Minimum On Time tMIN_ON 40 70 ns
VINOK PIN
VINOK Monitor Threshold Range VVINOK(RISE) 2.05
5.15 V Factory programmable
VINOK Monitor Accuracy
−1.5
+1.5 % TJ = 25°C
−3
+3 % −40°C ≤ TJ ≤ +125°C
VINOK Monitor Threshold Hysteresis VVINOK(HYS) 1.5
%
VINOK Rising Delay tVINOK_RISE 190 µs
VINOK Falling Delay tVINOK_FALL 130 µs
Leakage Current for VINOK Pin IVINOK_LEAKAGE 0.1 1 µA
Output Low Voltage for VINOK Pin VVINOK_LOW 50 100 mV IVINOK = 100 µA
SOFT START
Default Soft Start Time tSS 350 µs Factory trim, 1 bit (350 µs, 2800 µs)
Start-Up Delay tSTART_DELAY 2 ms Delay from the EN pin being pulled high
COUT DISCHARGE SWITCH ON RESISTANCE RDIS 290 Ω
THERMAL SHUTDOWN
Threshold TSHDN 142 °C
Hysteresis THYS 127 °C
1 SYNC refers to the synchronization function of the multifunction SYNC/MODE pin only.
ADP5303 Data Sheet
Rev. B | Page 6 of 21
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
PVIN to PGND −0.3 V to +7 V
−0.3 V to PVIN + 0.3 V
FB to AGND −0.3 V to +7 V
VID to AGND −0.3 V to +7 V
EN to AGND −0.3 V to +7 V
VINOK to AGND −0.3 V to +7 V
SYNC/MODE to AGND −0.3 V to +7 V
PGND to AGND −0.3 V to +0.3 V
Storage Temperate Range −65°C to +150°C
Operational Junction Temperature Range −40°C to +125°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θJA Unit
9-Ball, 1.5 mm × 1.5 mm WLCSP 132 °C/W
ESD CAUTION
Data Sheet ADP5303
Rev. B | Page 7 of 21
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
13444-003
A1 A2 A3
B1 B2 B3
C1 C2 C3
EN
PGND
PVIN
AGND
VINOK
SYNC/
MODE
VID
FB
SW
ADP5303
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
A1 SW Switching Node Output for the Regulator.
A2 PVIN Power Input for the Regulator.
A3 EN Enable Input for the Regulator. Set this pin to logic low to disable the regulator.
B1 PGND Power Ground.
B2 AGND Analog Ground.
B3 SYNC/MODE
Synchronization Input Pin (SYNC). To synchronize the switching frequency of the device to an external
clock, connect this pin to an external clock with a frequency from 1.5 MHz to 2.5 MHz.
PWM or Hysteresis Mode Selection Pin (MODE). When this pin is logic high, the regulator operates in PWM
mode. When this pin is logic low, the regulator operates in hysteresis mode.
C1 VINOK Output Power-Good Signal. This open-drain output is the power-good signal for the input voltage.
C2 FB Feedback Sensing Input for the Regulator.
C3 VID Voltage Configuration Pin. Connect an external resistor (RVID) from this pin to ground to configure the
output voltage of the regulator (see Table 5).
ADP5303 Data Sheet
Rev. B | Page 8 of 21
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 3.6 V, V OUT = 2.5 V, L 1 = 2.2 µH, CIN = COUT = 10 µF, fSW = 2 MHz, TA = 25°C, unless otherwise noted.
EF FICIENCY ( %)
LOAD CURRENT ( mA)
100
90
80
70
60
50
40
30
0.001 0.01 0.1 110
VIN = 2.5V
VIN = 3.0V
VIN = 3.6V
VIN = 4.2V
VIN = 5.0V
VIN = 6.0V
13444-004
Figure 4. Hysteresis Efficiency vs. Load Current, VOUT = 1.2 V
EFFI CIENCY (%)
LOAD CURRENT ( mA)
100
90
80
70
60
50
40
0.001 0.01 0.1 110
V
IN
= 2.5V
V
IN
= 3.0V
V
IN
= 3.6V
V
IN
= 4.2V
V
IN
= 5.0V
V
IN
= 6.0V
13444-005
Figure 5. Hysteresis Efficiency vs. Load Current, VOUT = 1.8 V
EFFI CIENCY (%)
LOAD CURRENT ( mA)
100
90
80
70
60
50
0.001 0.01 0.1 110
V
IN
= 3.6V
V
IN
= 4.2V
V
IN
= 5.0V
V
IN
= 6.0V
13444-006
Figure 6. Hysteresis Efficiency vs. Load Current, VOUT = 3.3 V
EF FICIENCY ( %)
LOAD CURRENT ( mA)
100
90
80
70
60
50
40
0.001 0.01 0.1 110
VIN = 2.5V
VIN = 3.0V
VIN = 3.6V
VIN = 4.2V
VIN = 5.0V
VIN = 6.0V
13444-007
Figure 7. Hysteresis Efficiency vs. Load Current, VOUT = 1.5 V
EF FICIENCY ( %)
LOAD CURRENT ( mA)
100
90
80
70
60
50
0.001 0.01 0.1 110
VIN = 3.6V
VIN = 3.0V
VIN = 4.2V
VIN = 5.0V
VIN = 6.0V
13444-008
Figure 8. Hysteresis Efficiency vs. Load Current, VOUT = 2.5 V
EFFICIENCY (%)
LO AD CURRE NT (mA)
0
10
20
30
40
50
60
70
80
90
100
0100 200 300 400 500
VIN = 2.5V
VIN = 3.0V
VIN = 3.6V
VIN = 4.2V
VIN = 5.0V
VIN = 6.0V
13444-009
Figure 9. PWM Efficiency vs. Load Current, VOUT = 1.2 V
Data Sheet ADP5303
Rev. B | Page 9 of 21
EFFICIENCY (%)
LO AD CURRE NT (mA)
0
10
20
30
40
50
60
70
80
90
100
0100 200 300 400 500
VIN = 2.5V
VIN = 3.0V
VIN = 3.6V
VIN = 4.2V
VIN = 5.0V
VIN = 6.0V
13444-010
Figure 10. PWM Efficiency vs. Load Current, VOUT = 1.5 V
EFFICIENCY (%)
LO AD CURRE NT (mA)
0
10
20
30
40
50
60
70
80
90
100
0100 200 300 400 500
VIN = 3.0V
VIN = 3.6V
VIN = 4.2V
VIN = 5.0V
VIN = 6.0V
13444-011
Figure 11. PWM Efficiency vs. Load Current, VOUT = 2.5 V
SHUTDOW N CURRE NT (nA)
VIN (V)
2.3 2.9 3.5 4.1 4.7 5.3 5.9 6.5
–40°C
+25°C
+85°C
+125°C
0
20
40
60
80
100
120
140
160
13444-012
Figure 12. Shutdown Current vs. VIN, EN = Low
EFFICIENCY (%)
LO AD CURRE NT (mA)
0
10
20
30
40
50
60
70
80
90
100
0100 200 300 400 500
VIN = 3.0V
VIN = 3.6V
VIN = 4.2V
VIN = 5.0V
VIN = 6.0V
VIN = 2.5V
13444-013
Figure 13. PWM Efficiency vs. Load Current, VOUT = 1.8 V
EFFICIENCY (%)
LO AD CURRE NT (mA)
0
10
20
30
40
50
60
70
80
90
100
0100 200 300 400 500
V
IN
= 3.6V
V
IN
= 4.2V
V
IN
= 5.0V
V
IN
= 6.0V
13444-014
Figure 14. PWM Efficiency vs. Load Current, VOUT = 3.3 V
QUI E S CE NT CURRENT (nA)
VIN (V)
100
200
300
400
500
600
700
2.3 2.9 3.5 4.1 4.7 5.3 5.9 6.5
–40°C
+25°C
+85°C
+125°C
13444-015
Figure 15. Hysteresis Quiescent Current vs. VIN, SYNC/MODE = Low
ADP5303 Data Sheet
Rev. B | Page 10 of 21
FE EDBACK V OL TAG E ( mV )
TEMPERATURE (°C)
797
798
799
800
801
–40 25 85 125
13444-016
Figure 16. Feedback Voltage vs. Temperature, PWM Mode
13444-017
HIGH-SIDE RDS (ON) H (mΩ)
V
IN
(V)
200
300
400
500
600
700
800
2.3 2.9 3.5 4.1 4.7 5.3 5.9 6.5
–40ºC
+25ºC
+125ºC
Figure 17. High-Side RDS (ON) H vs. VIN
PEAK CURRENT L IMIT ( mA)
TEMPERATURE (°C)
–40 25 85 125
840
890
940
990
1040
1090
13444-018
Figure 18. Peak Current Limit vs. Temperature
FEE DBACK V OL TAG E (mV)
TEMPERATURE (°C)
–40 25 85 125
792
794
796
798
800
802
804
806
808
810
ACTIVE TO S TANDBY
ST ANDBY TO ACTI V E
13444-019
Figure 19. Feedback Voltage vs. Temperature, Hysteresis Mode
LOW -SIDE R
DS (ON) L
(mΩ)
V
IN
(V)
2.3 2.9 3.5 4.1 4.7 5.3 5.9 6.5
–40ºC
+25ºC
+125ºC
200
250
300
350
400
450
500
13444-020
Figure 20. Low-Side RDS (ON) L vs. VIN
PEAK CURRENT L IMIT ( mA)
V
IN
(V)
2.3 2.9 3.5 4.1 4.7 5.3 5.9 6.5
800
850
900
950
1000
1050
1100
1150
1200
–40°C
+25°C
+125°C
13444-021
Figure 21. Peak Current Limit vs. VIN
Data Sheet ADP5303
Rev. B | Page 11 of 21
UVLO T HRE S HOLD (V)
TEMPERATURE (°C)
–40 25 85 125
1.96
1.98
2.00
2.02
2.04
2.06
2.08
2.10
RISING
FALLING
13444-022
Figure 22. UVLO Threshold, Rising and Falling, vs. Temperature
CH4 140mA
4
1
2
CH2 2.00V
CH4 500mA Ω
CH1 100mV M 200 µs A
T39.60%
V
OUT
I
L
SW
13444-023
Figure 23. Steady Waveform of Hysteresis Mode, ILOAD = 1 mA (IL is the
Inductor Current)
CH1 1.22V
2
1
3
4
CH2 5.00V
CH4 500mA Ω
CH1 1.00V M 200 µs A
T50.60%
CH3 2.00V
V
IN
V
OUT
I
L
SW
13444-024
BW
BWBW
Figure 24. Soft Start, ILOAD = 300 mA
SW I TCHI NG F RE Q UE NCY ( kHz )
V
IN
(V)
2.3 2.9 3.5 4.1 4.7 5.3 5.9 6.5
1.7
1.8
1.9
2.0
2.1
2.2
2.3
–40ºC
+25ºC
+125ºC
13444-025
Figure 25. Switching Frequency vs. VIN
CH2 1.52V
2
1
4
13444-026
CH22.00V
CH4200mA Ω
CH110.0mVM 1.00µs A
T45.20%
BWBW
VOUT(AC)
IL
SW
Figure 26. Steady Waveform of PWM Mode, ILOAD = 300 mA
2
1
4
VOUT
VIN
IL
SW
CH1 1.05V
CH2 5.00V
CH4 500mA Ω
CH1 500mV M 100 µs A
T40.00%
CH3 2.00V
13444-027
BW
BWBW
Figure 27. Soft Start with Precharge Function
ADP5303 Data Sheet
Rev. B | Page 12 of 21
1
4
V
OUT
(AC)
I
OUT
CH4 111mA
CH4 50.0mA Ω
CH1 50.0mV M 200 µs A
T20.80%
13444-028
BW
Figure 28. Load Transient of Hysteresis Mode, ILOAD from 0 mA to 50 mA
1
2
4
V
OUT
(AC)
V
IN
I
L
SW
CH3 4.72V
CH2 5.00V
CH4 500mA Ω
CH1 50.0mV M 2. 00 ms A
T30.00%
CH3 2.00V
13444-029
BW
BW
Figure 29. Line Transient of Hysteresis Mode, ILOAD = 10 µA, VIN from 2.5 V to 6 V
1
4
VOUT
VIN
IL
CH3 4.80V
CH4 200mA Ω
CH1 1.00V M 10. 0 ms A
T40.20%
CH3 1.00V
13444-030
BW
BWBW
Figure 30. Input Voltage Ramp-Up and Ramp-Down in Hysteresis Mode
1
4
VOUT (AC)
IOUT
CH4 308mA
CH4 200mA Ω
CH1 50.0mV M 200 µs A
T20.40%
13444-031
BWBW
Figure 31. Load Transient of PWM Mode, ILOAD from 125 mA to 375 mA
1
2
3
4
V
OUT
(AC)
V
IN
I
L
SW
CH3 4.28VCH2 5.00V
CH4 500mA Ω
CH1 10.0mV M 2. 00 ms A
T30.20%
CH3 2.00V
13444-032
BW
BWBW
Figure 32. Line Transient of PWM Mode, ILOAD = 500 mA, VIN from 2.5 V to 6 V
1
3
2
V
OUT
V
IN
CH3 980mVCH2 1.00VCH1 2.00V M 4.00ms A
T 20. 20%
CH3 1.00V
V
IN_OK
13444-033
BWBW
BW
Figure 33. VINOK Function at VINOK Threshold = 3.0 V
Data Sheet ADP5303
Rev. B | Page 13 of 21
1
4
2
13169-034
V
OUT
I
L
SW
CH1 1.44V
CH2 2.00V
CH1 2.00V M 10. 0 µs A
T40.20%
BW
CH4 500mA Ω
Figure 34. Output Short
SYNC/
MODE
SW
CH2 1.40V
CH2 2.00V
CH1 2.00V M 400 ns A
T50.00%
1
2
13444-035
BW
Figure 35. Synchronized to 2.5 MHz
1
2
3
V
OUT
(AC)
SYNC/MODE
CH3 1.56V
CH2 2.00VCH1 100mV M 20.0µs A
T 39. 80%
CH3 2.00V
SW
13444-036
BW
BW
Figure 36. Hysteresis Mode to PWM Mode with 10 mA Load Current
VOUT
IL
SW
CH1 1.44V
CH2 2.00V
CH1 2.00V M 1. 00 ms A
T40.20%
CH4 500mA Ω
4
1
2
13444-037
BW
Figure 37. Output Short Recovery
VOUT
IL
SW
CH1 1.44V
CH2 2.00V
CH1 2.00V M 1. 00 ms A
T40.20%
CH4 500mA Ω
4
1
2
13444-037
BW
Figure 38. Quick Output Discharge Function
1
2
3
V
OUT
V
STOP
CH3 520mVCH2 2.00VCH1 2.00V M 100 ms A
CH3 2.00V
SW
13444-039
Figure 39. PWM Mode to Hysteresis Mode with 10 mA Load Current
ADP5303 Data Sheet
Rev. B | Page 14 of 21
THEORY OF OPERATION
The ADP5303 is a high efficiency, ultralow quiescent current
step-down regulator in a 9-ball WLCSP to meet demanding
performance and board space requirements. The device enables
direct connection to a wide input voltage range of 2.15 V to
6.50 V, allowing the use of multiple alkaline/NiMH or Li-Ion
cells and other power sources.
BUCK REGULATOR OPERATIONAL MODES
PWM Mode
In PWM mode, the buck regulator in the ADP5303 operates at
a fixed frequency set by an internal oscillator. At the start of
each oscillator cycle, the high-side MOSFET switch turns on and
sends a positive voltage across the inductor. The inductor current
increases until the current sense signal exceeds the peak inductor
current threshold, which turns off the high-side MOSFET switch.
This threshold is set by the error amplifier output. During the high-
side MOSFET off time, the inductor current decreases through
the low-side MOSFET until the next oscillator clock pulse starts
a new cycle.
Hysteresis Mode
In hysteresis mode, the buck regulator in the ADP5303 charges
the output voltage slightly higher than its nominal output voltage
with PWM pulses by regulating the constant peak inductor
current. When the output voltage increases until the output
sense signal exceeds the hysteresis upper threshold, the regulator
enters standby mode. In standby mode, the high-side and low-side
MOSFETs and a majority of the circuitry are disabled to allow a
low quiescent current as well as high efficiency performance.
During standby mode, the output capacitor supplies energy into
the load and the output voltage decreases until it falls below the
hysteresis comparator lower threshold. The buck regulator wakes
up and generates the PWM pulses to charge the output again.
Because the output voltage occasionally enters standby mode
and then recovers, the output voltage ripple in hysteresis mode
is larger than the ripple in PWM mode.
Mode Selection
The ADP5303 includes the SYNC/MODE pin to allow flexible
configuration in hysteresis mode or PWM mode.
When a logic high level is applied to the SYNC/MODE pin, the
buck regulator is forced to operate in PWM mode. In PWM mode,
the regulator can supply up to 500 mA of output current. The
regulator can provide lower output ripple and output noise in
PWM mode, which is useful for noise sensitive applications.
When a logic low level is applied to the SYNC/MODE pin, the buck
regulator is forced to operate in hysteresis mode. In hysteresis mode,
the regulator draws only 240 nA of quiescent current typical to
regulate the output under zero load, which allows the regulator to
act as a keep-alive power supply in a battery-powered system. In
hysteresis mode, the regulator supplies up to 50 mA of output cur-
rent with a relatively large output ripple compared to PWM mode.
The user can alternate between hysteresis mode and PWM mode
during operation. The flexible configuration capability during
operation of the device enables efficient power management to
meet high efficiency and low output ripple requirements when
the system switches between active mode and standby mode.
OSCILLATOR AND SYNCHRONIZATION
The ADP5303 operates at a typical 2 MHz switching frequency
in PWM operation mode.
The switching frequency of the ADP5303 can be synchronized
to an external clock with a frequency range from 1.5 MHz to
2.5 MHz. The ADP5303 automatically detects the presence of
an external clock applied to the SYNC/MODE pin, and the
switching frequency transitions to the frequency of the external
clock. When the external clock signal stops, the device
automatically switches back to the internal clock.
ADJUSTABLE AND FIXED OUTPUT VOLTAGES
The ADP5303 provides adjustable output voltage settings by
connecting one resistor through the VID pin to AGND. The
VID detection circuitry works in the start-up, and the voltage
ID code is sampled and held in the internal register and does
not change until the next power cycle. Furthermore, the ADP5303
provides a fixed output voltage programmed via the factory
fuse. In this condition, connect the VID pin to the PVIN pin.
The feedback resistor divider is built into the ADP5303, and the
feedback pin (FB) must be tied directly to the output. An
ultralow power voltage reference and an integrated high
impedance feedback divider network contribute to the low
quiescent current. Table 5 lists the output voltage options by the
VID pin configurations. A 1% accuracy resistor through VID to
ground is recommended.
Table 5. Output Voltage (VOUT) Options Using the VID Pin
VID Configuration
VOUT
Factory Option 0 (V) Factory Option 1 (V)
Short to ground 3.0 3.1
Short to PVIN 2.5 1.3
RVID = 499 kΩ 3.6 5.0
RVID = 316 kΩ 3.3 4.5
RVID = 226 kΩ 2.9 4.2
RVID = 174 kΩ 2.8 3.9
RVID = 127 kΩ 2.7 3.4
RVID = 97.6 kΩ 2.6 3.2
RVID = 76.8 kΩ 2.4 1.9
RVID = 56.2 kΩ 2.3 1.7
RVID = 43 kΩ 2.2 1.6
RVID = 32.4 kΩ 2.1 1.4
RVID = 25.5 kΩ 2.0 1.1
RVID = 19.6 kΩ 1.8 1.0
RVID = 15 kΩ 1.5 0.9
RVID = 11.8 kΩ 1.2 0.8
Data Sheet ADP5303
Rev. B | Page 15 of 21
Any of the individual VID settings are available as internally
fixed options. Contact an Analog Devices, Inc. sales
representative for more information on generating new models.
UNDERVOLTAGE LOCKOUT (UVLO)
The UVLO circuitry monitors the input voltage level on the
PVIN pin. If the input voltage falls below 2.00 V (typical), the
regulator turns off. After the input voltage rises above 2.06 V
(typical), the soft start period initiates, and the regulator is
enabled when the EN pin is high.
ENABLE/DISABLE
The ADP5303 includes a separate enable pin (EN). A logic high
on the enable pin starts the regulator. Due to the low quiescent
current design, it is typical for the regulator to start switching
after a delay of few milliseconds from the enable pin (EN) being
pulled high.
A logic low on the enable pin immediately disables the regulator
and brings the regulator into an extremely low current consump-
tion state.
CURRENT LIMIT
The buck regulator in the ADP5303 has protection circuitry
that limits the direction and the amount of current to a certain
level that flows through the high-side MOSFET and the low-
side MOSFET in cycle-by-cycle mode. The positive current
limit on the high-side MOSFET limits the amount of current
that can flow from the input to the output. The negative current
limit on the low-side MOSFET prevents the inductor current
from reversing direction and flowing out of the load.
SHORT-CIRCUIT PROTECTION
The buck regulator in the ADP5303 includes frequency foldback to
prevent current runaway on a hard short. When the output voltage
at the feedback pin falls below 0.3 V (typical), indicating the
possibility of a hard short at the output, the switching frequency
in PWM mode is reduced to one-fourth of the internal oscillator
frequency. The reduction in the switching frequency allows more
time for the inductor to discharge, preventing a runaway of
output current.
SOFT START
The ADP5303 has an internal soft start function that ramps up
the output voltage in a controlled manner upon startup, thereby
limiting the inrush current. This control prevents possible input
voltage drops when a battery or a high impedance power source
is connected to the input of the device. The typical default soft
start time for the regulator is 350 µs.
A different soft start time (2800 µs) can be programmed for
ADP5303 by the factory fuse.
STARTUP WITH PRECHARGED OUTPUT
The buck regulator in the ADP5303 includes a precharged
start-up feature to protect the low-side MOSFET from damage
during startup. If the output voltage is precharged before the
regulator turns on, the regulator prevents reverse inductor
current—which discharges the output capacitor—until the
internal soft start reference voltage exceeds the precharged
voltage on the feedback pin.
100% DUTY CYCLE OPERATION
When the input voltage approaches the output voltage, the
ADP5303 stops switching and enters 100% duty cycle operation.
The device connects the output via the inductor and the internal
high-side power switch to the input. When the input voltage is
charged again and the required duty cycle falls to 95% (typical), the
buck regulator immediately restarts switching and regulation
without allowing overshoot on the output voltage. In hysteresis
mode, the ADP5303 draws an ultralow quiescent current of only
640 nA (typical) during 100% duty cycle operation.
ACTIVE DISCHARGE
The regulator in the ADP5303 integrates an optional, factory
programmable discharge switch from the switching node to
ground. This switch turns on when its associated regulator is
disabled, which helps discharge the output capacitor quickly.
The typical value of the discharge switch is 290 Ω for the
regulator.
By default, the discharge function is not enabled. The active
discharge function can be enabled by the factory fuse.
VINOK FUNCTION
The ADP5303 includes an open-drain VINOK output that
indicates the battery voltage status. The VINOK output becomes
active high when the input voltage on the PVIN pin is above
the reference threshold. When the input voltage falls below the
reference threshold, the VINOK pin goes low. Note that a
relatively typical long validation time of 130 µs exists for the
VINOK output status change due to the ultralow power
comparator design.
Different VINOK thresholds are factory programmable from
2.05 V to 5.15 V in 50 mV steps. To order a device with options
other than the default options, contact your local Analog
Devices sales or distribution representative.
THERMAL SHUTDOWN
If the ADP5303 junction temperature exceeds 142°C, the thermal
shutdown circuit turns off the IC except for the internal linear
regulator. Extreme junction temperatures may be the result of
high current operation, poor circuit board design, or high ambient
temperature. A 15°C hysteresis is included so that the ADP5303
does not return to operation after thermal shutdown until the
junction temperature falls below 127°C. When the device exits
thermal shutdown, a soft start is initiated for each enabled channel.
ADP5303 Data Sheet
Rev. B | Page 16 of 21
APPLICATIONS INFORMATION
This section describes the external components selection for the
ADP5303. A typical application circuit is shown in Figure 40.
SW
PGND
FB
V
OUT
= 1.8V
PVIN
10µF
MLCC
SYNC/
MODE
EN
AGND
AGND
VID
V
IN
=
2.15V TO 6.50V 2.2µH
10µF
MLCC
ADP5303
(WLFCSP-9)
VINOK
R2
1MΩ
R1
19.6kΩ
13444-040
Figure 40. Typical Application Circuit
EXTERNAL COMPONENT SELECTION
The ADP5303 is optimized for operation with a 2.2 μH
inductor and 10 μF output capacitors for various output
voltages using the closed-loop compensation and adaptive slope
compensation circuits. The selection of components depends
on the efficiency, the load current transient, and other application
requirements. The trade-offs among performance parameters,
such as efficiency and transient response, are made by varying
the choice of external components.
SELECTING THE INDUCTOR
The high frequency switching of the ADP5303 allows the use of
small surface-mount power inductors. The dc resistance (DCR)
value of the selected inductor affects efficiency. In addition, it is
recommended to select a multilayer inductor rather than a
magnetic iron inductor because the high switching frequency
increases the core temperature rise and enlarges the core loss.
A minimum requirement of the dc current rating of the inductor
is for it to be equal to the maximum load current plus half of the
inductor current ripple (ΔIL), as shown by the following equations:
×
×=∆
SW
IN
OUT
OUTL
fL V
V
VI –1
∆
+= 2
)( L
MAXLOADPK
I
II
where IPK is the peak inductor current.
Use the inductor series from different vendors shown in Table 6.
OUTPUT CAPACITOR
Output capacitance is required to minimize the voltage overshoot,
the voltage undershoot, and the ripple voltage present on the
output. Capacitors with low equivalent series resistance (ESR)
values produce the lowest output ripple. Furthermore, use
capacitors such as X5R and X7R dielectric capacitors. Do not use
Y5V and Z5U capacitors, which are unsuitable choices due to
their large capacitance variation over temperature and their dc
bias voltage changes. Because ESR is important, select the
capacitor using the following equation:
L
RIPPLE
COUT
I
V
ESR Δ
≤
where:
ESRCOUT is the ESR of the chosen capacitor.
VRIPPLE is the peak-to-peak output voltage ripple.
Increasing the output capacitor value has no effect on stability
and may reduce output ripple and enhance load transient response.
When choosing the output capacitor value, it is important to
account for the loss of capacitance due to output voltage dc bias.
Choose the capacitor series from the different vendors shown in
Table 7.
Table 6. Recommended Inductors
Vendor Model Inductance (μH) Dimensions (mm) DCR (mΩ) ISAT 1 (A)
TDK MLP2016V2R2MT0S1 2.2 2.0 × 1.6 × 0.85 280 1.0
Würth 74479889222 2.2 2.5 × 2.0 × 1.2 250 1.7
Coilcraft LPS3314-222MR 2.2 3.3 × 3.3 × 1.3 100 1.5
1 ISAT is the dc current at which the inductance drops 30% (typical) from its value without current.
Table 7. Input and Output Capacitors
Vendor Model Capacitance (μF) Size
Murata GRM188D71A106MA73 10 0603
Murata GRM21BR71A106KE51 10 0805
Murata
GRM31CR71A106KA01
10
1206
Data Sheet ADP5303
Rev. B | Page 17 of 21
INPUT CAPACITOR
An input capacitor is required to reduce the input voltage ripple,
input ripple current, and source impedance. Place the input
capacitor as close as possible to the PVIN pin. A low ESR X7R or
X5R capacitor is highly recommended to minimize the input
voltage ripple. Use the following equation to determine the rms
input current:
( )
IN
OUTINOUT
MAXLOADRMS
VVVV
II −
≥
)(
For most applications, a 10 μF capacitor is sufficient. The input
capacitor can be increased without any limit for better input
voltage filtering.
EFFICIENCY
Efficiency is the ratio of output power to input power. The high
efficiency of the ADP5303 has two distinct advantages. First,
only a small amount of power is lost in the dc-to-dc converter
package, which in turn reduces thermal constraints. Second, the
high efficiency delivers the maximum output power for the
given input power, thereby extending battery life in portable
applications.
Power Switch Conduction Losses
Power switch dc conduction losses are caused by the flow of
output current through the high-side P-channel power switch
and the low-side N-channel synchronous rectifier, which have
internal resistances (RDS (ON)) associated with them. The amount
of power loss is approximated by
PSW_COND = (RDS (ON) H × D + RDS (ON) L × (1 − D)) × IOUT2
where D =
IN
OUT
V
V
.
The internal resistance of the power switches increases with
temperature and with the input voltage decrease.
Inductor Losses
Inductor conduction losses are caused by the flow of current
through the inductor, which has an associated internal DCR.
Larger inductors have a smaller DCR, which can decrease
inductor conduction losses. Inductor core losses relate to the
magnetic permeability of the core material. Because the ADP5303
is a high switching frequency dc-to-dc regulator, shielded ferrite
core material is recommended because of its low core losses and
low electromagnetic interference (EMI).
To estimate the total amount of power lost in the inductor (PL),
use the following equation:
PL = DCR × IOUT2 + Core Losses
Driver Losses
Driver losses are associated with the current drawn by the driver to
turn on and turn off the power devices at the switching frequency.
Each time a power device gate is turned on and turned off, the
driver transfers a charge from the input supply to the gate, and
then from the gate to ground.
Estimate driver losses (PDRIVER) using the following equation:
PDRIVER = (CGATE_H + CGATE_L) × VIN2 × fSW
where:
CGATE_H is the gate capacitance of the internal high-side switch.
CGATE_L is the gate capacitance of the internal low-side switch.
fSW is the switching frequency in PWM mode.
The typical values for the gate capacitances are 69 pF for CGATE_H
and 31 pF for CGATE_L.
Transition Losses
Transition losses occur because the P-channel switch cannot
turn on or turn off instantaneously. In the middle of a switch
node transition, the power switch provides all of the inductor
current. The source to drain voltage of the power switch is half
of the input voltage, resulting in power loss. Transition losses
increase with both load current and input voltage and occur
twice for each switching cycle.
Use the following equation to estimate transition losses (PTRAN):
PTRAN = VIN/2 × IOUT × (tR + tF) × fSW
where:
tR is the rise time of the SW node.
tF is the fall time of the SW node.
The typical value for the rise and fall times, tR and tF, is 2 ns.
ADP5303 Data Sheet
Rev. B | Page 18 of 21
PRINTED CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Figure 41 shows the typical printed circuit board (PCB) layout for the ADP5303.
13444-041
EN
PGND
PVIN
AGND
GND
SYNC/
MODE
VID
FB
SW
ADP5303
VIN
3.00
3.60
VOUT
10µF
10V/XR5
0603
10µF
6.3V/XR5
0603
VOUTOK
L1 – 2.2µH
0603
100kΩ
0201
B1 B2 B3
A1 A2 A3
C1 C2 C3
Figure 41. Typical PCB Layout for the ADP5303
Data Sheet ADP5303
Rev. B | Page 19 of 21
TYPICAL APPLICATION CIRCUITS
The ADP5303 can be used as a keep-alive, ultralow power step-
down regulator to extend battery life (see Figure 42), and as a
battery-powered equipment or wireless sensor network
controlled by a microcontroller or a processor (see Figure 43).
13444-042
2.2µH
SW
PGND
FB
10µF
10µF
V
OUT
= 1.8V
PVIN
VID
EN
Li-Ion BATTERY
SYNC/MODE
V
IN
= 3.0V TO 4.2V
ADP5303
R2
20kΩ
1% VINOK
AGND
Figure 42. Typical Application Circuit with Li-Ion Battery
TWO
ALKALINE
OR Li-Ion
BATTERIES
2.2µH
SW
PGND
FB
10µF
R2
1MΩ
10µF
PVIN
EN
SYNC/MODE
V
IN
= 2.0V TO 3.0V V
OUT
= 1.8V
ADP5303
ADC/RF/AFE
MCU
(ALWAYS-ON)
VID
AGND
VINOK
13444-043
R1
19.6kΩ
1%
Figure 43. Typical Application Circuit with Two Alkaline or NiMH Batteries
ADP5303 Data Sheet
Rev. B | Page 20 of 21
FACTORY PROGRAMMABLE OPTIONS
To order a device with options other than the default options, contact your local Analog Devices sales or distribution representative.
Table 8. Output Voltage VID Setting Options
Option Description
Option 0 VID resistor to set the output voltage as follows: 1.2 V, 1.5 V, 1.8 V, 2.0 V, 2.1 V, 2.2 V, 2.3 V, 2.4 V, 2.5 V, 2.6 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V,
3.6 V, or 3.3 V (ADP5303ACBZ-1, ADP5303ACBZ-2, and ADP5303ACBZ-3 default)
Option 1 VID resistor to set the output voltage as follows: 0.8 V, 0.9 V, 1.0 V, 1.1 V, 1.3 V, 1.4 V, 1.6 V, 1.7 V, 1.9 V, 3.1 V, 3.2 V, 3.4 V, 3.9 V, 4.2 V,
4.5 V, or 5.0 V
Table 9. VINOK Monitor Threshold Options
Option VINOK Monitor Threshold Setting (V)
Option 0 2.05
Option 1 2.10
Option 2 2.15
Option 3 2.20 (ADP5303ACBZ-3 default)
… …
Option 20 3.00 (ADP5303ACBZ-1 and ADP5303ACBZ-2 default)
… …
Option 62
5.10
Option 63 5.15
Table 10. Output Discharge Functionality Options
Option Description
Option 0 Output discharge function disabled for the buck regulator (ADP5303ACBZ-2 default)
Option 1 Output discharge function enabled for the buck regulator (ADP5303ACBZ-1 and ADP5303ACBZ-3 default)
Table 11. Soft Start Timer Options
Option Description
Option 0 350 µs (ADP5303ACBZ-1 and ADP5303ACBZ-2 default)
Option 1 2800 µs (ADP5303ACBZ-3 default)
Data Sheet ADP5303
Rev. B | Page 21 of 21
OUTLINE DIMENSIONS
05-20-2014-A
A
B
C
0.660
0.600
0.540
1.690
1.650
1.610
1.910
1.870
1.830
1
2
3
BOTTOM VIEW
(BALL SIDE UP)
TOP VIEW
(BALL SIDE DO W N)
END VIEW
0.360
0.320
0.280
1.00
REF
0.50
BSC
SEATING
PLANE 0.270
0.240
0.210
0.345
0.325
0.305
0.455
0.435
0.415
0.390
0.360
0.330
COPLANARITY
0.04
BALLA1
IDENTIFIER
PKG-003136
Figure 44. 9-Ball Wafer Level Chip Scale Package [WLCSP]
1.65 mm × 1.87 mm Body
(CB-9-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADP5303ACBZ-1-R7
−40°C to +125°C
9-Ball Wafer Level Chip Scale Package [WLCSP]
CB-9-6
ADP5303ACBZ-2-R7 −40°C to +125°C 9-Ball Wafer Level Chip Scale Package [WLCSP] CB-9-6
ADP5303ACBZ-3-R7 −40°C to +125°C 9-Ball Wafer Level Chip Scale Package [WLCSP] CB-9-6
ADP5303-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
©2015–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13444-0-3/19(B)