SST27SF020-70-3C-WHE - Microchip Technology, Inc.

S71152-12-000 9/08

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MTP is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit (x8) Many-Time Programmable Flash

SST27SF512 / SST27SF010 / SST27SF020

FEATURES:

• Organized as 64K x8 / 128K x8 / 256K x8

• 4.5-5.5V Read Operation

• Superior Reliability

– Endurance: At least 1000 Cycles

– Greater than 100 years Data Retention

• Low Power Consumption

– Active Current: 20 mA (typical)

– Standby Current: 10 µA (typical)

• Fast Read Access Time

– 70 ns

• Fast Byte-Program Operation

– Byte-Program Time: 20 µs (typical)

– Chip Program Time:

1.4 seconds (typical) for SST27SF512

2.8 seconds (typical) for SST27SF010

5.6 seconds (typical) for SST27SF020

• Electrical Erase Using Programmer

– Does not require UV source

– Chip-Erase Time: 100 ms (typical)

• TTL I/O Compatibility

• JEDEC Standard Byte-wide EPROM Pinouts

• Packages Available

– 32-lead PLCC

– 32-lead TSOP (8mm x 14mm)

– 32-pin PDIP for SST27SF010/020

• All non-Pb (lead-free) devices are RoHS compliant

PRODUCT DESCRIPTION

The SST27SF512/010/020 are a 64K x8 / 128K x8 / 256K

x8 CMOS, Many-Time Programmable (MTP) low cost

flash, manufactured with SST’s proprietary, high perfor-

mance SuperFlash technology. The split-gate cell design

and thick oxide tunneling injector attain better reliability and

manufacturability compared with alternate approaches.

These MTP devices can be electrically erased and pro-

grammed at least 1000 times using an external program-

mer with a 12V power supply. They have to be erased prior

to programming. These devices conform to JEDEC stan-

dard pinouts for byte-wide memories.

Featuring high-performance Byte-Program, the

SST27SF512/010/020 provide a Byte-Program time of 20

µs. Designed, manufactured, and tested for a wide spec-

trum of applications, these devices are offered with an

endurance of at least 1000 cycles. Data retention is rated at

greater than 100 years.

The SST27SF512/010/020 are suited for applications that

require infrequent writes and low power nonvolatile stor-

age. These devices will improve flexibility, efficiency, and

performance while matching the low cost in nonvolatile

applications that currently use UV-EPROMs, OTPs, and

mask ROMs.

To meet surface mount and conventional through hole

requirements, the SST27SF512 are offered in 32-lead

PLCC, 32-lead TSOP, and 28-pin PDIP packages. The

SST27SF010/020 are offered in 32-pin PDIP, 32-lead

PLCC, and 32-lead TSOP packages. See Figures 3, 4, and

5 for pin assignments.

Device Operation

The SST27SF512/010/020 are a low cost flash solution

that can be used to replace existing UV-EPROM, OTP,

and mask ROM sockets. These devices are functionally

(read and program) and pin compatible with industry

standard EPROM products. In addition to EPROM func-

tionality, these devices also support electrical Erase

operation via an external programmer. They do not

require a UV source to erase, and therefore the pack-

ages do not have a window.

Read

The Read operation of the SST27SF512/010/020 is con-

trolled by CE# and OE#. Both CE# and OE# have to be low

for the system to obtain data from the outputs. Once the

address is stable, the address access time is equal to the

delay from CE# to output (TCE). Data is available at the out-

put after a delay of TOE from the falling edge of OE#,

assuming that CE# pin has been low and the addresses

have been stable for at least TCE-TOE. When the CE# pin is

high, the chip is deselected and a typical standby current of

10 µA is consumed. OE# is the output control and is used

to gate data from the output pins. The data bus is in high

impedance state when either CE# or OE# is high.

SST27SF512 / 010 / 0205.0V-Read 512Kb / 1Mb / 2Mb (x8) MTP flash memories

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash

SST27SF512 / SST27SF010 / SST27SF020

Byte-Program Operation

The SST27SF512/010/020 are programmed by using an

external programmer. The programming mode for

SST27SF010/020 is activated by asserting 11.4-12V on

VPP pin, VDD = 4.5-5.5V, VIL on CE# pin, and VIH on OE#

pin. The programming mode for SST27SF512 is activated

by asserting 11.4-12V on OE#/VPP pin, VDD = 4.5-5.5V,

and VIL on CE# pin. These devices are programmed byte-

by-byte with the desired data at the desired address using

a single pulse (CE# pin low for SST27SF512 and PGM#

pin low for SST27SF010/020) of 20 µs. Using the MTP pro-

gramming algorithm, the Byte-Programming process con-

tinues byte-by-byte until the entire chip has been

programmed.

Chip-Erase Operation

The only way to change a data from a “0” to “1” is by electri-

cal erase that changes every bit in the device to “1”. Unlike

traditional EPROMs, which use UV light to do the Chip-

Erase, the SST27SF512/010/020 uses an electrical Chip-

Erase operation. This saves a significant amount of time

(about 30 minutes for each Erase operation). The entire

chip can be erased in a single pulse of 100 ms (CE# pin

low for SST27SF512 and PGM# pin for SST27SF010/

020). In order to activate the Erase mode for SST27SF010/

020, the 11.4-12V is applied to VPP and A9 pins, VDD = 4.5-

5.5V, VIL on CE# pin, and VIH on OE# pin. In order to acti-

vate Erase mode for SST27SF512, the 11.4-12V is applied

to OE#/VPP and A9 pins, VDD = 4.5-5.5V, and VIL on CE#

pin. All other address and data pins are “don’t care”. The

falling edge of CE# (PGM# for SST27SF010/020) will start

the Chip-Erase operation. Once the chip has been erased,

all bytes must be verified for FFH. Refer to Figures 13 and

14 for the flowcharts.

Product Identification Mode

The Product Identification mode identifies the devices as

the SST27SF512, SST27SF010 and SST27SF020 and

manufacturer as SST. This mode may be accessed by the

hardware method. To activate this mode for SST27SF010/

020, the programming equipment must force VH (11.4-12V)

on address A9 with VPP pin at VDD (4.5-5.5V) or VSS. To

activate this mode for SST27SF512, the programming

equipment must force VH (11.4-12V) on address A9 with

OE#/VPP pin at VIL. Two identifier bytes may then be

sequenced from the device outputs by toggling address line

A0. For details, see Tables 3 and 4 for hardware operation.

TABLE 1: Product Identification

Address Data

Manufacturer’s ID 0000H BFH

Device ID

SST27SF512 0001H A4H

SST27SF010 0001H A5H

SST27SF020 0001H A6H

T1.2 1152

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash

SST27SF512 / SST27SF010 / SST27SF020

FIGURE 1: Functional Block Diagram - SST27SF512

FIGURE 2: Functional Block Diagram - SST27SF010/020

Y-Decoder

I/O Buffers

1152 B2.1

Address Buffer

X-Decoder

DQ7 - DQ0

A15 - A0

OE#/VPP

CE#

SuperFlash

Memory

Control Logic

Y-Decoder

I/O Buffers

1152 B3.2

Address Buffer

X-Decoder

DQ7 - DQ0

AMS - A0

OE#

CE#

SuperFlash

Memory

Control Logic

PGM#

VPP

AMS = A17 for SST27SF020, A16 for SST27SF010

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash

SST27SF512 / SST27SF010 / SST27SF020

FIGURE 3: Pin Assignments for 32-lead PLCC

FIGURE 4: Pin Assignments for 32-lead TSOP (8mm x 14mm)

1152 32-plcc P1.5

SST27SF512SST27SF010/020 SST27SF010/020SST27SF512

SST27SF512

SST27SF010/020

SST27SF010

SST27SF020

DQ0

A11

OE#/VPP

A10

CE#

DQ7

DQ6

A14

A13

A11

OE#

A10

CE#

DQ7

4 3 2 1 32 31 30

A12

A15

VDD

A14

A13

A12

A15

A16

VPP

VDD

PGM#

A12

A15

A16

VPP

VDD

PGM#

A17

32-lead PLCC

Top View

14 15 16 17 18 19 20

DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ6

1152 32-tsop P2.3

A11

A13

A14

VDD

A15

A12

PGM#

VPP

A16

A17

PGM#

VPP

A16

OE#/VPP

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

OE# OE#

Standard Pinout

Top View

Die Up

SST27SF512 SST27SF010 SST27SF020SST27SF512SST27SF020 SST27SF010

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash

SST27SF512 / SST27SF010 / SST27SF020

FIGURE 5: Pin Assignments for 28-pin and 32-pin PDIP

TABLE 2: Pin Description

Symbol Pin Name Functions

AMS1-A0

1. AMS = Most significant address

AMS = A15 for SST27SF512, A16 for SST27SF010, and A17 for SST27SF020

Address Inputs To provide memory addresses

DQ7-DQ0Data Input/output To output data during Read cycles and receive input data during Program cycles

The outputs are in tri-state when OE# or CE# is high.

CE# Chip Enable To activate the device when CE# is low

OE# Output Enable For SST27SF010/020, to gate the data output buffers during Read operation

OE#/VPP Output Enable/VPP For SST27SF512, to gate the data output buffers during Read operation and high voltage

pin during Chip-Erase and programming operation

VPP Power Supply for

Program or Erase

For SST27SF010/020, high voltage pin during Chip-Erase and programming operation

11.4-12V

VDD Power Supply To provide 5.0V supply (4.5-5.5V)

VSS Ground

NC No Connection Unconnected pins.

T2.4 1152

32-pin

PDIP

Top View

VPP

A16

A15

A12

DQ0

DQ1

DQ2

VSS

VPP

A16

A15

A12

DQ0

DQ1

DQ2

VSS

VDD

PGM#

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VDD

PGM#

A17

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

1152 32-pdip P4.2

SST27SF010 SST27SF010SST27SF020 SST27SF020

28-pin

PDIP

To p V i ew

A15

A12

DQ0

DQ1

DQ2

VSS

VDD

A14

A13

A11

OE#/VPP

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

1152 28-pdip P3.2

SST27SF512SST27SF512

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash

SST27SF512 / SST27SF010 / SST27SF020

Note: VPPH = 11.4-12V, VH = 11.4-12V

TABLE 3: Operation Modes Selection for SST27SF512

Mode CE# OE#/VPP A9DQ Address

Read VIL VIL AIN DOUT AIN

Output Disable VIL VIH X1High Z X

Program VIL VPPH AIN DIN AIN

Standby VIH X X High Z X

Chip-Erase VIL VPPH VHHigh Z X

Program/Erase Inhibit VIH VPPH X High Z X

Product Identification VIL VIL VHManufacturer’s ID (BFH)

Device ID (A4H)

A15-A1=VIL, A0=VIL

A15-A1=VIL, A0=VIH

T3.2 1152

1. X can be VIL or VIH, but no other value.

TABLE 4: Operation Modes Selection for SST27SF010/020

Mode CE# OE# PGM# A9VPP DQ Address

Read VIL VIL X1

1. X can be VIL or VIH, but no other value.

AIN VDD or VSS DOUT AIN

Output Disable VIL VIH XXV

DD or VSS High Z AIN

Program VIL VIH VIL AIN VPPH DIN AIN

Standby VIH XXXV

DD or VSS High Z X

Chip-Erase VIL VIH VIL VHVPPH High Z X

Program/Erase Inhibit VIH XXXV

PPH High Z X

Product Identification VIL VIL XV

HVDD or VSS Manufacturer’s ID (BFH)

Device ID2

2. Device ID = A5H for SST27SF010 and A6H for SST27SF020

AMS3 - A1=VIL, A0=VIL

AMS3 - A1=VIL, A0=VIH

3. AMS = Most significant address

AMS = A16 for SST27SF010 and A17 for SST27SF020

T4.2 1152

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash

SST27SF512 / SST27SF010 / SST27SF020

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V

Voltage on A9 and VPP Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 14.0V

Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Through Hole Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

Surface Mount Solder Reflow Temperature1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds

Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

1. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.

Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest information.

2. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE

Range Ambient Temp VDD VPP

Commercial 0°C to +70°C 4.5-5.5V 11.4-12V

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . 10 ns

Output Load . . . . . . . . . . . . . . . . . CL = 30 pF for 70 ns

See Figures 11 and 12

TABLE 5: Read Mode DC Operating Characteristics for SST27SF512/010/020

VDD = 4.5-5.5V, VPP=VDD or VSS (TA = 0°C to +70°C (Commercial))

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD VDD Read Current Address input=VILT/VIHT at f=1/TRC Min

VDD=VDD Max

30 mA CE#=OE#=VIL, all I/Os open

IPPR VPP Read Current Address input=VILT/VIHT at f=1/TRC Min

VDD=VDD Max, VPP=VDD

100 µA CE#=OE#=VIL, all I/Os open

ISB1 Standby VDD Current

(TTL input)

3mACE#=V

IH, VDD=VDD Max

ISB2 Standby VDD Current

(CMOS input)

100 µA CE#=VDD-0.3

VDD=VDD Max

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VIH Input High Voltage 2.0 VDD+0.5 V VDD=VDD Max

VOL Output Low Voltage 0.2 V IOL=2.1 mA, VDD=VDD Min

VOH Output High Voltage 2.4 V IOH=-400 µA, VDD=VDD Min

IHSupervoltage Current for A9200 µA CE#=OE#=VIL, A9=VH Max

T5.6 1152

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash

SST27SF512 / SST27SF010 / SST27SF020

TABLE 6: Program/Erase DC Operating Characteristics for SST27SF512

VDD=4.5-5.5V, VPP=VPPH (TA=25°C±5°C)

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD VDD Erase or Program Current 30 mA CE#=VIL, OE#/VPP=11.4-12V, VDD=VDD Max

IPP VPP Erase or Program Current 3 mA CE#=VIL, OE#/VPP=11.4-12V, VDD=VDD Max

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max

VHSupervoltage for A911.4 12 V CE#=OE#/VPP=VIL,

IHSupervoltage Current for A9200 µA CE#=OE#/VPP=VIL, A9=VH Max

VPPH High Voltage for OE#/VPP Pin 11.4 12 V

T6.5 1152

TABLE 7: Program/Erase DC Operating Characteristics for SST27SF010/020

VDD=4.5-5.5V, VPP=VPPH (TA=25°C±5°C)

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD VDD Erase or Program Current 30 mA CE#=PGM#=VIL, OE#=VIH, VPP=11.4-12V,

VDD=VDD Max

IPP VPP Erase or Program Current 3 mA CE#=PGM#=VIL, OE#=VIH, VPP=11.4-12V,

VDD=VDD Max

ILI Input Leakage Current 1 µA VIN =GND to VDD, VDD=VDD Max

ILO Output Leakage Current 10 µA VOUT =GND to VDD, VDD=VDD Max

VHSupervoltage for A911.4 12 V CE#=OE#=VIL,

IHSupervoltage Current for A9200 µA CE#=OE#=VIL, A9=VH Max

VPPH High Voltage for VPP Pin 11.4 12 V

T7.5 1152

TABLE 8: Recommended System Power-up Timings

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Write Operation 100 µs

T8.1 1152

TABLE 9: Capacitance (TA = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

I/O Pin Capacitance VI/O = 0V 12 pF

CIN1Input Capacitance VIN = 0V 6 pF

T9.0 1152

TABLE 10: Reliability Characteristics

Symbol Parameter Minimum Specification Units Test Method

NEND1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

Endurance 1000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

T10.3 1152

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash

SST27SF512 / SST27SF010 / SST27SF020

AC CHARACTERISTICS

TABLE 11: Read Cycle Timing Parameters VDD = 4.5-5.5V (TA = 0°C to +70°C (Commercial))

Symbol Parameter Min Max Units

TRC Read Cycle Time 70 ns

TCE Chip Enable Access Time 70 ns

TAA Address Access Time 70 ns

TOE Output Enable Access Time 35 ns

TCLZ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

CE# Low to Active Output 0 ns

TOLZ1OE# Low to Active Output 0 ns

TCHZ1CE# High to High-Z Output 25 ns

TOHZ1OE# High to High-Z Output 25 ns

TOH1Output Hold from Address Change 0 ns

T11.3 1152

TABLE 12: Program/Erase Cycle Timing Parameters for SST27SF512

Symbol Parameter Min Max Units

TAS Address Setup Time 1 µs

TAH Address Hold Time 1 µs

TPRT OE#/VPP Pulse Rise Time 50 ns

TVPS OE#/VPP Setup Time 1 µs

TVPH OE#/VPP Hold Time 1 µs

TPW CE# Program Pulse Width 20 30 µs

TEW CE# Erase Pulse Width 100 500 ms

TDS Data Setup Time 1 µs

TDH Data Hold Time 1 µs

TVR OE#/VPP and A9 Recovery Time 1 µs

TART A9 Rise Time to 12V during Erase 50 ns

TA9S A9 Setup Time during Erase 1 µs

TA9H A9 Hold Time during Erase 1 µs

T12.0 1152

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash

SST27SF512 / SST27SF010 / SST27SF020

TABLE 13: Program/Erase Cycle Timing Parameters for SST27SF010/020

Symbol Parameter Min Max Units

TCES CE# Setup Time 1 µs

TCEH CE# Hold Time 1 µs

TAS Address Setup Time 1 µs

TAH Address Hold Time 1 µs

TPRT VPP Pulse Rise Time 50 ns

TVPS VPP Setup Time 1 µs

TVPH VPP Hold Time 1 µs

TPW PGM# Program Pulse Width 20 30 µs

TEW PGM# Erase Pulse Width 100 500 ms

TDS Data Setup Time 1 µs

TDH Data Hold Time 1 µs

TVR A9 Recovery Time for Erase 1 µs

TART A9 Rise Time to 12V during Erase 50 ns

TA9S A9 Setup Time during Erase 1 µs

TA9H A9 Hold Time during Erase 1 µs

T13.0 1152

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash

SST27SF512 / SST27SF010 / SST27SF020

FIGURE 6: Read Cycle Timing Diagram for SST27SF512/010/020

FIGURE 7: Chip-Erase Timing Diagram for SST27SF512

1152 F03.0

DATA VALIDDATA VALID

TCLZ

TOLZ TOH

TRC TAA

TOE

TOHZ

TCHZ

HIGH-Z

DQ7-0

OE#

CE#

ADDRESS

TCE

1152 F04b.1

TA9H

TVR

TVPH

TVPS

TEW

PRT

VDD

VSS

OE#/VPP

VPPH

VIH

VIL

DQ7-0

CE#

ADDRESS

(EXCEPT A9)

TA9S

TART

TVR

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash

SST27SF512 / SST27SF010 / SST27SF020

FIGURE 8: Chip-Erase Timing Diagram for SST27SF010/020

FIGURE 9: Byte-Program Timing Diagram for SST27SF512

1152 F04c.1

A9H

VPH

VPS

CEH

TPRT

PGM#

PPH

7-0

OE#

CE#

ADDRESS

(EXCEPT A

)

A9S

ART

CES

1152 F05b.2

DATA VALID

ADDRESS VALID

TAH TPW

TDH

TAS

TDS

TVR

VDD

VPPH

HIGH-Z

VSS

TVPH

TPRT

TVPS

OE#/VPP

DQ7-0

CE#

ADDRESS

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash

SST27SF512 / SST27SF010 / SST27SF020

FIGURE 10: Byte-Program Timing Diagram for SST27SF010/020

1152 F05c.1

DATA VALID

ADDRESS VALID

TAH

TCEH

TAS

TDS TDH

VDD

VPPH

HIGH-Z

VIH

VSS

TCES

TPW TVPH

TPRT

TVPS

VPP

PGM#

DQ7-0

OE#

CE#

ADDRESS

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash

SST27SF512 / SST27SF010 / SST27SF020

FIGURE 11: AC Input/Output Reference Waveforms

FIGURE 12: A Test Load Example

1152 F06.0

REFERENCE POINTS OUTPUTINPUT

VHT

VLT

VHT

VLT

VIHT

VILT

AC test inputs are driven at VIHT (2.4 V) for a logic “1” and VILT (0.4 V) for a logic “0”. Measurement reference points for

inputs and outputs are VHT (2.0 V) and VLT (0.8 V). Input rise and fall times (10% ↔ 90%) are <10 ns.

Note: VHT - VHIGHTe s t

VLT - VLOW Te st

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

1152 F07.1

TO TESTER

TO DUT

CLRL LOW

RL HIGH

VDD

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash

SST27SF512 / SST27SF010 / SST27SF020

FIGURE 13: Chip-Erase Algorithm for SST27SF512

OE#/VPP = VPPH

OE#/VPP = VDD or VSS

A9 = VIL or VIH

Wait for OE#/VPP and

A9 Recovery Time

Erase 100ms pulse

(CE# = VIL)

Read Device

(CE# = OE# = VIL)

Device Passed

Compare All

bytes to FFH

Device Failed

1152 F08b.2

Start

A9 = VH

Ye s

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash

SST27SF512 / SST27SF010 / SST27SF020

FIGURE 14: Chip-Erase Algorithm for SST27SF010/020

Start

A9 = VH, VPP = VPPH

A9 = VIL or VIH

CE# = VIL, OE# = VIH

Wait A9 Recovery Time

Erase 100ms pulse

(PGM# = VIL)

Read Device

Device Passed

Compare all

bytes to FFH

Device Failed

1152 F08c.1

PGM# = VIH

Ye s

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash

SST27SF512 / SST27SF010 / SST27SF020

FIGURE 15: Byte-Program Algorithm for SST27SF512

Start

Erase*

OE#/VPP = VPPH

Address = First Location

Program 20µs pulse

(CE# = VIL)

Read Device

(CE# = OE# = VIL)

Device Passed

Compare all bytes

to original data

Increment Address

Device Failed

1152 F09b.2

Last Address?

Wait for OE#/VPP

RecoveryTime

OE#/VPP = VDD or VSS

Ye s

* See Figure 13

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash

SST27SF512 / SST27SF010 / SST27SF020

FIGURE 16: Byte-Program Algorithm for SST27SF010/020

Start

Erase*

VPP = VPPH

Address = First Location

CE# = VIL, OE# = VIH

Program 20µs pulse

(PGM# = VIL)

Read Device

Device Passed

Compare all bytes

to original data

Increment Address

Device Failed

1152 F09c.1

Last Address?

Ye s

* See Figure 14

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash

SST27SF512 / SST27SF010 / SST27SF020

PRODUCT ORDERING INFORMATION

Valid combinations for SST27SF512

SST27SF512-70-3C-NHE SST27SF512-70-3C-WHE

Valid combinations for SST27SF010

SST27SF010-70-3C-NHE SST27SF010-70-3C-WHE SST27SF010-70-3C-PHE

Valid combinations for SST27SF020

SST27SF020-70-3C-NHE SST27SF020-70-3C-WHE SST27SF020-70-3C-PHE

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

Environmental Attribute

E1 = non-Pb

Package Modifier

H = 32 pins or leads

Package Type

N = PLCC

P = PDIP

W = TSOP (type 1, die up, 8mm x 14mm)

Temperature Range

C = Commercial = 0°C to +70°C

Minimum Endurance

3 = 1,000 cycles

Read Access Speed

70 = 70 ns

Device Density - x8 Organization

020 = 2 Mbit

010 = 1 Mbit

512 = 512 Kbit

Voltage Range

S = 4.5-5.5V

Product Series

27 = Many-Time Programmable Flash

OTP/EPROM replacement with

EPROM pinout

1. Environmental suffix “E” denotes non-Pb solder.

SST non-Pb solder devices are “RoHS Compliant”.

SST 27 SF 020 - 70 - 3C - NH E

XX XX XXXX - XXX -XX-XXX X

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash

SST27SF512 / SST27SF010 / SST27SF020

PACKAGING DIAGRAMS

FIGURE 17: 32-lead Plastic Lead Chip Carrier (PLCC)

SST Package Code: NH

.040

.030

.021

.013

.530

.490

.095

.075

.140

.125

.032

.026

.032

.026

.029

.023

.453

.447

.553

.547

.595

.585

.495

.485 .112

.106

.042

.048

.042

.015 Min.

TOP VIEW SIDE VIEW BOTTOM VIEW

1232

.400

BSC

32-plcc-NH-3

Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (max/min).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.

4. Coplanarity: 4 mils.

.050

BSC

.050

BSC

Optional

Pin #1

Identifier .020 R.

MAX. R.

x 30°

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash

SST27SF512 / SST27SF010 / SST27SF020

FIGURE 18: 32-lead Thin Small Outline Package (TSOP) 8mm x 14mm

SST Package Code: WH

32-tsop-WH-7

Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

1.20

max.

1mm

Pin # 1 Identifier

12.50

12.30

14.20

13.80

0.70

0.50

8.10

7.90 0.27

0.17

0.50

BSC

1.05

0.95

0.15

0.05

0.70

0.50

0°- 5°

DETAIL

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash

SST27SF512 / SST27SF010 / SST27SF020

FIGURE 19: 32-pin Plastic Dual In-line Pins (PDIP)

SST Package Code: PH

32-pdip-PH-3

Pin #1 Identifier

Base

Plane

Seating

Plane

Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (max/min).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.

.200

.170

7°

4 PLCS.

.600 BSC

.100 BSC

.150

.120

.022

.016

.065

.045

.080

.070

.050

.015

.075

.065

1.655

1.645

.012

.008

0°

15°

.625

.600

.550

.530

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash

SST27SF512 / SST27SF010 / SST27SF020

TABLE 14: Revision History

Number Description Date

02 •2002 Data Book Feb 2002

03 •Document Control Release (SST Internal): No technical changes Apr 2002

04 •Corrected IH Supervoltage Current for A9 from 100 µA to 200 µA in Tables 5, 6, and 7 Jul 2002

05 •Corrected the Test Conditions for IDD and IPPR in Table 5 on page 7 Sep 2003

06 •Corrected the Max value for IPP from 1 mA to 3 mA (See Tables 6 and 7)

•Added MPNs for non-PB packages (See page 19)

Nov 2003

07 •2004 Data Book

•Corrected caption for Figure 7 from “Read Cycle” to “Chip-Erase”

Nov 2003

08 •Removed 256 Kbit parts - refer to EOL Product Data Sheet S71152(02) Apr 2004

09 •Removed all 90 ns parts - refer to EOL Product Data Sheet S71152(03)

•Added RoHS compliance information on page 1 and in the “Product Ordering Infor-

mation” on page 19

•Added the solder reflow temperature to the “Absolute Maximum Stress Ratings” on

page 7.

Mar 2005

10 •Removed obsolete Latch-up parameter from Table 10 on page 8 May 2005

11 •Corrected VPP voltage from 11.4-12.6V to 11.4-12V Sep 2005

12 •Removed leaded parts. See S71152(04)

•End-of-Life PG package and PG valid combination. See S71152(04)

Sep 2008

Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036