1. Product profile
1.1 General description
Ultra low capacitance bidirectional quadruple ElectroStatic Discharge (ESD) protection
arrays in ultra small Surface-Mounted Device (SMD) plastic packages designed to protect
up to four signal lines from the damage caused by ESD and other transients.
1.2 Features
1.3 Applications
PESD5V0U4BF; PESD5V0U4BW
Ultra low capacitance bidirectional quadruple ESD
protection arrays
Rev. 01 — 15 August 2008 Product data sheet
Table 1. Product overview
Type number Package Package configuration
NXP JEDEC
PESD5V0U4BF SOT886 MO-252 leadless ultra small
PESD5V0U4BW SOT665 - ultra small and flat lead
nBidirectional ESD protection of up to
four lines
nESD protection up to 10 kV
nUltra low diode capacitance: Cd= 2.9 pF nIEC 61000-4-2; level 4 (ESD)
nUltra low leakage current: IRM =5nA nAEC-Q101 qualified
nComputers and peripherals nPortable electronics
nAudio and video equipment nSubscriber Identity Module (SIM) card
protection
nCellular handsets and accessories nFireWire
n10/100/1000 Mbit/s Ethernet nHigh-speed data lines
nCommunication systems
PESD5V0U4BF_PESD5V0U4BW_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 15 August 2008 2 of 12
NXP Semiconductors PESD5V0U4BF; PESD5V0U4BW
Ultra low capacitance bidirectional quadruple ESD protection arrays
1.4 Quick reference data
2. Pinning information
3. Ordering information
Table 2. Quick reference data
T
amb
=25
°
C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Per diode
VRWM reverse standoff voltage - - 5 V
Cddiode capacitance f = 1 MHz; VR= 0 V - 2.9 3.5 pF
Table 3. Pinning
Pin Description Simplified outline Graphic symbol
PESD5V0U4BF
1 cathode (diode 1)
2 common cathode
3 cathode (diode 2)
4 cathode (diode 3)
5 common cathode
6 cathode (diode 4)
PESD5V0U4BW
1 cathode (diode 1)
2 common cathode
3 cathode (diode 2)
4 cathode (diode 3)
5 cathode (diode 4)
bottom view
321
456
006aab333
1
3
25
6
4
123
45
006aab334
1
3
2
5
4
Table 4. Ordering information
Type number Package
Name Description Version
PESD5V0U4BF XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 1 ×1.45 ×0.5 mm SOT886
PESD5V0U4BW - plastic surface-mounted package; 5 leads SOT665
PESD5V0U4BF_PESD5V0U4BW_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 15 August 2008 3 of 12
NXP Semiconductors PESD5V0U4BF; PESD5V0U4BW
Ultra low capacitance bidirectional quadruple ESD protection arrays
4. Marking
5. Limiting values
[1] Device stressed with ten non-repetitive ESD pulses.
[2] Measured from pin 1, 3, 4 or 6 to pin 2 or 5.
[3] Measured from pin 1, 3, 4 or 5 to pin 2.
Table 5. Marking codes
Type number Marking code
PESD5V0U4BF B1
PESD5V0U4BW A6
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Per device
Tjjunction temperature - 150 °C
Tamb ambient temperature −55 +150 °C
Tstg storage temperature −65 +150 °C
Table 7. ESD maximum ratings
T
amb
=25
°
C unless otherwise specified.
Symbol Parameter Conditions Min Max Unit
Per diode
VESD electrostatic discharge voltage [1]
PESD5V0U4BF IEC 61000-4-2
(contact discharge) [2] -10kV
PESD5V0U4BW IEC 61000-4-2
(contact discharge) [3] -10kV
PESD5V0U4BF MIL-STD-883 (human
body model) [2] -8kV
PESD5V0U4BW MIL-STD-883 (human
body model) [3] -8kV
PESD5V0U4BF_PESD5V0U4BW_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 15 August 2008 4 of 12
NXP Semiconductors PESD5V0U4BF; PESD5V0U4BW
Ultra low capacitance bidirectional quadruple ESD protection arrays
Table 8. ESD standards compliance
Standard Conditions
Per diode
IEC 61000-4-2; level 4 (ESD) > 15 kV (air); > 8 kV (contact)
MIL-STD-883; class 3 (human body model) > 4 kV
Fig 1. ESD pulse waveform according to IEC 61000-4-2
001aaa631
IPP
100 %
90 %
t
30 ns 60 ns
10 %
tr = 0.7 ns to 1 ns
PESD5V0U4BF_PESD5V0U4BW_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 15 August 2008 5 of 12
NXP Semiconductors PESD5V0U4BF; PESD5V0U4BW
Ultra low capacitance bidirectional quadruple ESD protection arrays
6. Characteristics
Table 9. Characteristics
T
amb
=25
°
C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Per diode
VRWM reverse standoff
voltage --5V
IRM reverse leakage current VRWM = 5 V - 5 100 nA
VBR breakdown voltage IR= 5 mA 5.5 6.5 9.5 V
Cddiode capacitance f=1MHz
VR= 0 V - 2.9 3.5 pF
VR= 5 V - 1.9 - pF
rdif differential resistance IR= 1 mA - - 100 Ω
f = 1 MHz; Tamb =25°C
Fig 2. Diode capacitance as a function of reverse
voltage; typical values Fig 3. V-I characteristics for a bidirectional
ESD protection diode
VR (V)
054231
006aab036
2.2
2.6
3.0
Cd
(pF)
1.8
006aaa676
−VCL −VBR −VRWM VCL
VBR
VRWM
−IRM
IRM
−IR
IR
−IPP
IPP
−+
PESD5V0U4BF_PESD5V0U4BW_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 15 August 2008 6 of 12
NXP Semiconductors PESD5V0U4BF; PESD5V0U4BW
Ultra low capacitance bidirectional quadruple ESD protection arrays
Fig 4. ESD clamping test setup and waveforms
006aab037
50 Ω
RZ
CZ
DUT
(DEVICE
UNDER
TEST)
GND
GND
450 ΩRG 223/U
50 Ω coax
ESD TESTER
IEC 61000-4-2 network
CZ = 150 pF; RZ = 330 Ω
4 GHz DIGITAL
OSCILLOSCOPE
10×
ATTENUATOR
GND
GND
unclamped +8 kV ESD pulse waveform
(IEC 61000-4-2 network) clamped +8 kV ESD pulse waveform
(IEC 61000-4-2 network) pin 1 to 2
unclamped −8 kV ESD pulse waveform
(IEC 61000-4-2 network) clamped −8 kV ESD pulse waveform
(IEC 61000-4-2 network) pin 1 to 2
vertical scale = 10 A/div
horizontal scale = 15 ns/div
vertical scale = 10 A/div
horizontal scale = 15 ns/div vertical scale = 10 V/div
horizontal scale = 100 ns/div
vertical scale = 10 V/div
horizontal scale = 100 ns/div
PESD5V0U4BF_PESD5V0U4BW_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 15 August 2008 7 of 12
NXP Semiconductors PESD5V0U4BF; PESD5V0U4BW
Ultra low capacitance bidirectional quadruple ESD protection arrays
7. Application information
The PESD5V0U4BF and the PESD5V0U4BW are designed for the protection of up to four
bidirectional data or signal lines from the damage caused by ESD and surge pulses. The
devices may be used on lines where the signal polarities are both, positive and negative
with respect to ground.
Circuit board layout and protection device placement
Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT)
and surge transients. The following guidelines are recommended:
1. Place the device as close to the input terminal or connector as possible.
2. The path length between the device and the protected line should be minimized.
3. Keep parallel signal paths to a minimum.
4. Avoid running protected conductors in parallel with unprotected conductors.
5. Minimize all Printed-Circuit Board (PCB) conductive loops including power and
ground loops.
6. Minimize the length of the transient return path to ground.
7. Avoid using shared transient return paths to a common ground point.
8. Ground planes should be used whenever possible. For multilayer PCBs, use ground
vias.
8. Test information
8.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard
Q101 - Stress test qualification for discrete semiconductors
, and is
suitable for use in automotive applications.
Fig 5. Application diagram
006aab335
data- or transmission lines
DUT
1
2
3
5
4
6
PESD5V0U4BF_PESD5V0U4BW_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 15 August 2008 8 of 12
NXP Semiconductors PESD5V0U4BF; PESD5V0U4BW
Ultra low capacitance bidirectional quadruple ESD protection arrays
9. Package outline
10. Packing information
[1] For further information and the availability of packing methods, see Section 14.
[2] T1: normal taping
[3] T4: 90° rotated reverse taping
Fig 6. Package outline PESD5V0U4BF (SOT886) Fig 7. Package outline PESD5V0U4BW (SOT665)
04-07-22Dimensions in mm
0.25
0.17
0.40
0.32 0.35
0.27
0.5
0.6
1.05
0.95
1.5
1.4 0.5
0.50
max 0.04
max
3
2
1
4
5
6
Dimensions in mm 04-11-08
1.7
1.5
1.7
1.5 1.3
1.1
1
0.18
0.08
0.27
0.17
0.5
123
45
0.6
0.5
0.3
0.1
Table 10. Packing methods
The indicated -xxx are the last three digits of the 12NC ordering code.
[1]
Type number Package Description Packing quantity
4000 5000 8000
PESD5V0U4BF SOT886 4 mm pitch, 8 mm tape and reel; T1 [2] - -115 -
4 mm pitch, 8 mm tape and reel; T4 [3] - -132 -
PESD5V0U4BW SOT665 2 mm pitch, 8 mm tape and reel - - -315
4 mm pitch, 8 mm tape and reel -115 - -
PESD5V0U4BF_PESD5V0U4BW_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 15 August 2008 9 of 12
NXP Semiconductors PESD5V0U4BF; PESD5V0U4BW
Ultra low capacitance bidirectional quadruple ESD protection arrays
11. Soldering
Reflow soldering is the only recommended soldering method.
Fig 8. Reflow soldering footprint PESD5V0U4BF (SOT886)
Reflow soldering is the only recommended soldering method.
Fig 9. Reflow soldering footprint PESD5V0U4BW (SOT665)
sot886_fr
solder lands
occupied area
solder paste
Dimensions in mm
0.425
(6×)
1.250
0.675
1.700
0.325
(6×)
0.270
(6×)
0.370
(6×)
0.500
0.500
2.45
2.1
1.6
20.25 0.3
0.6
0.65
0.55
0.325
(2×)
0.45
(4×)
0.4
(2×)
0.45
(2×)
0.7
(2×)
0.5
(4×)
0.375
(2×)
0.4
(5×)
1.7
1
0.538
solder lands
placement area
occupied area
solder paste
sot665_fr
Dimensions in mm
PESD5V0U4BF_PESD5V0U4BW_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 15 August 2008 10 of 12
NXP Semiconductors PESD5V0U4BF; PESD5V0U4BW
Ultra low capacitance bidirectional quadruple ESD protection arrays
12. Revision history
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PESD5V0U4BF_PESD5V0U4BW_1 20080815 Product data sheet - -
PESD5V0U4BF_PESD5V0U4BW_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 15 August 2008 11 of 12
NXP Semiconductors PESD5V0U4BF; PESD5V0U4BW
Ultra low capacitance bidirectional quadruple ESD protection arrays
13. Legal information
13.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
13.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
13.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
ESD protection devices — These products are only intended for protection
against ElectroStatic Discharge (ESD) pulses and are not intended for any
other usage including, without limitation, voltage regulation applications. NXP
Semiconductors accepts no liability for use in such applications and therefore
such use is at the customer’s own risk.
13.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
14. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors PESD5V0U4BF; PESD5V0U4BW
Ultra low capacitance bidirectional quadruple ESD protection arrays
© NXP B.V. 2008. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 August 2008
Document identifier: PESD5V0U4BF_PESD5V0U4BW_1
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
15. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description. . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Quick reference data. . . . . . . . . . . . . . . . . . . . . 2
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
7 Application information. . . . . . . . . . . . . . . . . . . 7
8 Test information. . . . . . . . . . . . . . . . . . . . . . . . . 7
8.1 Quality information . . . . . . . . . . . . . . . . . . . . . . 7
9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
10 Packing information. . . . . . . . . . . . . . . . . . . . . . 8
11 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
12 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10
13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11
13.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11
13.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
13.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
13.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
14 Contact information. . . . . . . . . . . . . . . . . . . . . 11
15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
