POWER MANAGEMENT
1www.semtech.com
SC1114
Synchronous PWM Controller with Dual
Low Dropout Regulator Controllers
PRELIMINARY
Features
Applications
Revision 1, April 2001
Typical Application Circuit
Description
The SC1114 was designed for the latest high speed
motherboards. It combines a synchronous voltage mode
controller (switching section) with two low-dropout linear
regulator controllers. The voltage mode controller provides
the power supply for the system or the dual linear regula-
tors. The Dual linear controllers provide necessary system
voltages.
The SC1114 switching section features lossless current
sensing and latched driver outputs for enhanced noise im-
munity. It operates at a fixed frequency of 200kHz, with
an externaly programable output voltage.
The SC1114 linear sections are low dropout regulators de-
signed to track their input power supply during power up
and down. A Power Good signal is also available once the
the LDO1 output is within regulation.
KDual linear controllers
KLDOs track input voltage within 200mV (function of
the MOSFETs used) until regulation
KIntegrated drivers
KPower Good Signal
KSoft Start
KLossless Current Sense
KPentium® IV Motherboards
KTriple power supplies
+
C12
330uF
5V IN
Q2
MOSFET N
+
C7
3x1500uF
U1
SC1114CS
12
5
3
7
6
9
10
13
14
4
11
8
15 2
116
PWRGD
BCAP-
STBY
PHASE
GND
DH
BST
VOSENSE
SS/EN
BCAP+
VCC
DL
GATE2 GATE1
LDOS1LDOS2
POWER GOOD
C6
0.1uF L1 4uH
Q4
MOSFET N
C4
0.1uF
1.5V
5V STBY
Vout
+
C2
2x1500uF
12V IN
1.2V
R1 2.2
Q3
MOSFET N
R2 2.2
C3
0.1uF
C8
0.1uF
+
C11
330uF
C9
0.1uF
C5
0.1uF
C1
0.1uF
+
C10
330uF
Q1
MOSFET N
RT
RB
22001 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1114
PRELIMINARY
Electrical Characteristics
Absolute Maximum Ratings
retemaraPlobmySmumixaMstinU
CCVDNGot 7+ot3.0-V
DNGotYBTS 7+ot3.0-V
DNGotTSB 51+ot3.0-V
DNGotESAHP 8+ot1-V
xSODL 5ot3.0-V
egnaRerutarepmeTgnitarepOT
A
07+ot0C°
egnaRerutarepmeTnoitcnuJT
J
521+ot0C°
egnaRerutarepmeTegarotST
GTS
051+ot56-C°
sdnoceS01)gniredloS(erutarepmeTdaeLT
L
003C°
tneibmAotnoitcnuJecnatsiseRlamrehT θ
AJ
031W/C°
esaCotnoitcnuJecnadepmIlamrehT θ
CJ
03W/C°
Unless specified: VOSENSE = VO; Vcc=4.75V to 5.25V; STBY=4.75V to 5.25V; BST = 11.4V to 12.6V; TA = 0 to 70°C
retemaraPlobmySsnoitidnoCNIMPYTXAMSTINU
V(ylppuS
CC
)
egatloVylppuSV
CC
4.45 52.5V
tnerruCtnecseiuQylppuSI
QCC
V
CC
V0=NE/SS,V5=821Am
tnerruCgnitarepOylppuS
)1(
I
CC
V
CC
V1>NE/SS,V5=02Am
noitceSgnihctiwS
egatloVtuptuO
)1(
V
tuo
I
O
A4=671.1002.1422.1V
(noitalugeRdaoL
)1(
DAOL
GER
I
O
A4otA0=1%
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)1(
ENIL
GER
V52.5otV57.4=niV51.0±%
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)pirtV
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LO
)
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NIAG
tuoV
VotESNESOV
O
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dlohserhTCCV
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9.31.44.4V
siseretsyHCCV
TSYH
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dooGrewoP
egatloVdlohserhTdooGrewoP
)6(
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ht
881SODL211%
elbanE/tratStfoS
tnerrucecruoSNE/SS
)2(
ecruosI
NE/SS
V
NE/SS
V5.1=50121Aµ
tnerruckniSNE/SS
)2(
knisI
NE/SS
V
NE/SS
V5.1=123Aµ
egatloVnwodtuhSV
NE/SS
006056Vm
3
2001 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1114
PRELIMINARY
retemaraPlobmySsnoitidnoCNIMPYTXAMSTINU
srevirDlanretnI
tnerruCecruoSHDkaePecruosI
HD
V5.4=HD-TSB005Am
tnerruCkniSHDkaePknisI
HD
V1.3=ESAHP-HD005Am
V5.1=ESAHP-HD001Am
tnerruCecruoSLDkaePecruosI
LD
V5.4=LD-CCV005Am
tnerruCkniSLDkaePknisI
LD
V1.3=DNG-LD005Am
V5.1=DNG-LD001Am
emitdaeDT
DAED
04001sn
snoitceSraeniL
egatloVybdnatSV
YBTS
4.45 52.5V
tnerructnecseiuQybdnatSI
QYBDTS
V0=NE/SS,V5=YBTSV8Am
ecnereffiDgnikcarT
)4()1(
atleD
KCART
002Vm
1ODLegatloVtuptuOV
1ODL
I
O
V5=niV,Am05ot0=671.1002.1422.1V
2ODLegatloVtuptuOV
2ODL
I
O
V5=niV,A3ot0=074.1005.1035.1V
noitalugeRdaoLDAOL
GER
I1ODL
O
V5=niV,Am05ot0=3.0%
I2ODL
O
V5=niV,A3ot0=3.0%
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GER
,Am05=oI1ODL
V52.5otV57.4=niV 3.0%
,A3=oI2ODL
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)LOA(niaG
)3(
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Electrical Characteristics (Cont.)
Notes:
(1) All electrical characteristics are for the application circuit on page 15.
(2) Soft start function is performed after Vcc is above the UVLO and SS/EN is above 600mV. The Soft start
capacitor is then charged at a 10uA constant current until SS/EN is charged to above 1V.
(3) Guaranteed by design
(4) Tracking Difference is defined as the delta between Vin and the LDO1, LDO2 output voltages during the
linear ramp up until regulation is achieved. The tracking voltage differance might vary depending on MOSFETs
RdSON, and load conditions.
(5) This device is ESD sensitive. Use of standard ESD handling precautions is required.
(6) An open Collector flag (PWRGD Pin) is held low until the LDOS1 is with in 12% of regulation.
Unless specified: VOSENSE = VO; Vcc=4.75V to 5.25V; STBY=4.75V to 5.25V; BST = 11.4V to 12.6V; TA = 0 to 70°C
42001 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1114
PRELIMINARY
Pin Configuration Ordering Information
Pin Descriptions
rebmuNtraP
)1(
egakcaP raeniL
egatloV
pmeT
T(egnaR
J
)
RTS4111CS61-OSV5.1/V2.1C°521ot°0
BVE4111CSdraoBnoitaulavE
Note:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices.
Top View
(16-Pin SOIC)
#niPemaNniPnoitcnuFniP
11SODL)V2.1(1ODLroftupnIesneS
21ETAG)V2.1(1ODLtuptuOevirDetaG
3YBTS srellortnocTEFdnarotallicsO,pmuPegrahC,feRrofrewopseilppus,tupnIybdnatSV5
4+PACBroticapaCtsooBotnoitcennoCevitisoP
5-PACBroticapaCtsooBotnoitcennoCevitageN
6DNGdnuorG
7ESAHPedoNesahP
8LDtuptuOrevirDediSwoL
9HDtuptuOrevirDediShgiH
01TSBtupnItsooB
11CCVtupnIylppuSrewoP
21DGRWPtuptuO1ODLrofgalFdooGrewoProtceloCnepO
31ESNESOVtuptuOSPMSroftupnIesneStuptuO
41NE/SSelbanE/tratStfoS
512ETAG)V5.1(2ODLtuptuoevirDetaG
612SODL)V5.1(2ODLroftupnIesneS
GATE1
LDOS1
STBY
BCAP+
BCAP-
GND
PHASE
DH
LDOS2
GATE2
SS/EN
PWRGD
VOSENSE
VCC
BST
DL
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
5
2001 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1114
PRELIMINARY
Block Diagram
R
S
Q
STBY
VOSENSE
GND
+
-
OSCILLATOR
5VSTBY
+
-
PHASE
BCAP+
BST
SET DOMINATES
PWM
0.8V
VCC
+
-
+10%
+
-
BCAP-
+
-
0.6V
VBG
LOW
SIDE
DRIVE
200mV
+
-
SHOOT
THRU
CONTROL
LDOS1
FAULT LOW SIDE OFF
+
-
PWRGD
2uA
-10%
DL
10uA
5VSTBY
VBG
CHARGE
PUMP
5VSTBY
+
-
GATE2
VBG
+
-
DH
VBG
R
S
Q
LDOS2
1.2V
VCC
OVER
CURRENT
Bandgap
VCC
+
-
GATE1
OSCILLATOR
5VSTBY
HIGH
SIDE
DRIVE
ERROR AMP
HICCUP LATCH
SS/EN
UVLO
SS/EN
Marking Information
yyww = Datecode (Example: 9912)
xxxxx = Semtech Lot # (Example: 90101)
SC1114S
yyww
xxxxx ES
62001 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1114
PRELIMINARY
to cross the oscillator triangular ramp of 1V to 2V.
As the SS/EN pin continues to rise, the error amplifier out-
put also rises at the same rate and the duty cycle increases.
Once the Vout has reached regulation, the error amplifier
output will no longer be clamped to the SS/EN voltage and
will stay between 1V to 2V. The SS/EN voltage continues
to rise up to 2.5V and will stay at that voltage level during
normal operation.
If an over current condition occurs, the SS/EN pin will dis-
charge by a 2uA current source, from 2.5V to 800mV. Dur-
ing this time both DH, and DL will be turned off. Once the
SS/EN reaches 800mV, the low side gate will be turned
on, and the SS/EN pin will again start to be charged by the
10uA current source, and the same soft start sequence
mentioned above will be repeated.
OVER CURRENT
Upper Mosfets Rdson is used to monitor the drop across
the top FET due to an over current condition. This Method
of current sensing minimizes any unnecessary losses due
to external sense resistance.
An internal comparator with a 200mV reference monitors
the Drop across the upper FET, Once the Vdson of the
Mosfet exceeds the 200mV limit, the low side gate is turned
on and the upper FET is turned off. Also an internal latch
is set and the Soft start capacitor is discharged. Once the
lower threshold of the soft start circuit is crossed, the same
Softstart sequence mentioned previously is repeated. This
sequence is repeated until the over condition is removed.
THEORY OF OPERATION
The SC1114 has integrated a synchronous buck control-
ler and two Low drop out regulator controllers into a 16
Pin SOIC package. The switching regulator provides a 1.2V
Vout voltage for use in Pentium® III Motherboards., while
the dual LDO regulators provide 1.2V, and 1.5V to power
up the Chipset and the Clock circuitry.
SUPPLIES
Two supplies, VSTBY, and VCC are used to power the
SC1114. VSTBY supply provides the bias for the Internal
Reference, Oscillator, and the LDO FET controllers. The VCC
supply provides the bias for the Power Good circuitry, and
the high side FET Rdson sensing/over current circuitry,
VCC also is used to drive the low side Mosfet gate. An ex-
ternal 12V supply or a classical boot strapping technique
can provide the gate drive for the upper Mosfet.
PWM CONTROLLER
SC1114 is a voltage mode buck controller that utilizes an
internally compensated high bandwidth error amplifier to
sense the Vout output voltage. External compensation com-
ponents are not needed and a stable closed loop responce
is insured due to the internal compensation.
START UP SEQUENCE
Initially during the power up, the SC1114 is in under volt-
age lock out condition. The latch (SET dominant) in the
hiccup section is set , and the SS/EN pin is pulled low by
the 2uA soft start current source.
Mean while the high side and low side gate drivers DH,
and DL are kept low. Once the VCC exceeds the UVLO
threshold of 4.2V, the latch is reset and the external soft
start capacitor starts to be charged by a 10uA current
source.
The gate drives are still kept off until the soft start capaci-
tors voltage rises above 600mV, when the low side gate is
turned on , and the high side gate is kept off.
The gate drive status stays the same until the capacitors
voltage reaches 1V, when the error amplifier output starts
Application Information
VCC
SS/EN
Phase Node
7
2001 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1114
PRELIMINARY
GATE DRIVERS
The Low side gate driver is supplied from VCC and provide
a peak source/sink current of and 500mA.
The high side gate drive is also capable of sourcing and
sinking peak currents of 500mA. The high side Mosfet gate
drive can be provided by an external 12V supply that is
connected from BST to GND. The actual gate to source
voltage of the upper Mosfet will approximately equal 7V
(12V-VCC). If the external 12V supply is not available, a
classical boot strap technique can be implemented from
the VCC supply. A boot strap capacitor is connected from
BST to Phase while VCC is connected through a diode
(Schottky or other fast low VF diode) to the BST. This will
provide a gate to source voltage approximately to VCC-
Vdiode drop.
Shoot through control circuitry provides a 100ns dead time
to ensure both upper and lower MOSFET will not turn on
simultaneously and cause a shoot through condition.
DUAL LDO CONTROLLERS
SC1114 also provides two low drop out linear regulator
controllers that can be used to generate a 1.2V and a 1.5V
outputs. The LDO output voltage is achieved by controlling
the voltage drop across an external Mosfet from an exter-
nal or the PWM ( Vout should be set > 2V) output voltage.
The output voltage is sensed at the LDOS pin of the SC1114
and compared to an internal reference. The gate drive to
the external Mosfet is then adjusted until regulation is
achieved. In order to have sufficient voltage to the gate
drives of the external Mosfet, an internal charge pump is
utilized to boost the gate drive voltage to about two times
the VSTBY.
The internal charge pump charges an external Bucket ca-
pacitor to VSTBY and then connects it in series with VSTBY
to the LDOs supply at a frequency of about 200kHz. This
Application Information (Cont.)
82001 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1114
PRELIMINARY
ensures sufficient gate drive voltage for the LDOs inde-
pendent of the VCC or the 12V external supply being avail-
able due to start up timing sequence from the silver box.
The LDO1, and LDO2 output voltages are forced to track
the 3.3V input supply. This feature ensures that during the
start up application of the 3.3V, the LDO1, and LDO2 out-
puts track the 3.3V within 200mV typical until regulation
is achieved. However, the VSTBY should be established at
least 500us, to allow the charge pump to reach its maxi-
mum voltage, before the linear section will track within
200mV. This tracking will sequence the correct start up
timing for the external Chipset and Clock circuitry.
POWER GOOD
The ouput voltage from LDOS1 is monitored, and once it
has reached regulation and is within 1.2V ± 12%, an open
Collector power good flag is activated.
LAYOUT GUIDELINES
Careful attention to layout requirements are necessary for
successful implementation of the SC1114 PWM control-
ler.
High currents switching at 200kHz are present in the ap-
plication and their effect on ground plane voltage differ-
entials must be understood and minimized.
1). The high power parts of the circuit should be laid out
first. A ground plane should be used, the number and po-
sition of ground plane interruptions should be such as to
not unnecessarily compromise ground plane integrity. Iso-
lated or semi-isolated areas of the ground plane may be
deliberately introduced to constrain ground currents to
particular areas, for example the input capacitor and bot-
tom FET ground.
2). The loop formed by the Input Capacitor(s) (Cin), the Top
FET (Q1) and the Bottom FET (Q2) must be kept as small
as possible. This loop contains all the high current, fast
transition switching. Connections should be as wide and
as short as possible to minimize loop inductance. Mini-
mizing this loop area will a) reduce EMI, b) lower ground
injection currents, resulting in electrically cleaner grounds
for the rest of the system and c) minimize source ringing,
resulting in more reliable gate switching signals.
3). The connection between the junction of Q1, Q2 and
the output inductor should be a wide trace or copper re-
gion. It should be as short as practical. Since this connec-
tion has fast voltage transitions, keeping this connection
short will minimize EMI. Also keep the Phase connection
to the IC short, top FET gate charge currents flow in this
trace.
4) The Output Capacitor(s) (Cout) should be located as
close to the load as possible, fast transient load cur
+
1.5V
+
1.2V
3.3V IN
+
C10
330uF
Vout
5V IN
U1 SC1114CS
PWRGD
BCAP-
STBY
PHASE
GND
DH
BST
VOSENSE
SS/EN
BCAP+
VCC
DL
GATE2 GATE1
LDOS1LDOS2
+
5V STBY
+
12V IN
hi
g
h current paths.
Heav
y
Lines indicate
Application Information (Cont.)
9
2001 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1114
PRELIMINARY
rents are supplied by Cout only, and connections between
Cout and the load must be short, wide copper areas to
minimize inductance and resistance.
5) The SC1114 is best placed over a quiet ground plane
area, avoid pulse currents in the Cin, Q1, Q2 loop flowing
in this area. GND should be returned to the ground plane
close to the package and close to the ground side of (one
of) the output capacitor(s). If this is not possible, the GND
pin may be connected to the ground path between the
Output Capacitor(s) and the Cin, Q1, Q2 loop. Under no
circumstances should GND be returned to a ground in-
side the Cin, Q1, Q2 loop.
6) BST for the SC1114 should be supplied from the 12V
supply, the BST pin should be decoupled directly to GND
by a 0.1mF ceramic capacitor, trace lengths should be as
short as possible. If a 12V supply is not available, a classi-
cal boot strap method could be implemented to achieve
the upper Mosfets gate drive.
Vout
5V
+
+
7) The connection from the Phase Node to the Phase pin
of the SC1114 should be minimized to avoid any stary in-
ductance. If the layout can not be optomized due to
constranints, a small Schottky diode (See page 17) maybe
connected from the Phase pin to the ground directly at the
IC. This will clamp excessive negative voltages at the IC.
8) Ideally, the grounds for the two LDO sections should be
returned to the ground side of (one of) the output
capacitor(s).
Application Information (Cont.)
102001 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1114
PRELIMINARY
COMPONENT SELECTION
SWITCHING SECTION
OUTPUT CAPACITORS - Selection begins with the most
critical component. Because of fast transient load current
requirements in modern microprocessor core supplies, the
output capacitors must supply all transient load current
requirements until the current in the output inductor ramps
up to the new level. Output capacitor ESR is therefore one
of the most important criteria. The maximum ESR can be
simply calculated from:
step current Transient
excursion voltage transient Maximum
Where
==
≤
t
t
t
t
ESR
I
V
I
V
R
For example, to meet a 100mV transient limit with a 10A
load step, the output capacitor ESR must be less than
10mΩ. To meet this kind of ESR level, there are three avail-
able capacitor technologies.
ygolonhceT
hcaE
roticapaC ytQ
.dqR
latoT
C
)Fu(
RSE
m( Ω)
C
)Fu(
RSE
m( Ω)
mulatnaTRSEwoL033066 000201
NOC-SO033523 0993.8
munimulARSEwoL0051445 00578.8
The choice of which to use is simply a cost/performance
issue, with Low ESR Aluminum being the cheapest, but
taking up the most space.
INDUCTOR - Having decided on a suitable type and value
of output capacitor, the maximum allowable value of in-
ductor can be calculated. Too large an inductor will pro-
duce a slow current ramp rate and will cause the output
capacitor to supply more of the transient load current for
longer - leading to an output voltage sag below the ESR
excursion calculated above.
The maximum inductor value may be calculated from:
()
OIN
t
ESR VV
I
CR
L−≤
The calculated maximum inductor value assumes 100%
duty cycle, so some allowance must be made. Choosing
an inductor value of 50 to 75% of the calculated maxi-
mum will guarantee that the inductor current will ramp fast
enough to reduce the voltage dropped across the ESR at a
faster rate than the capacitor sags, hence ensuring a good
recovery from transient with no additional excursions. We
must also be concerned with ripple current in the output
inductor and a general rule of thumb has been to allow
10% of maximum output current as ripple current. Note
that most of the output voltage ripple is produced by the
inductor ripple current flowing in the output capacitor ESR.
Ripple current can be calculated from:
OSC
IN
LfL4
V
IRIPPLE ⋅⋅
=
Ripple current allowance will define the minimum permit-
ted inductor value.
POWER FETS - The FETs are chosen based on several cri-
teria with probably the most important being power dissi-
pation and power handling capability.
TOP FET - The power dissipation in the top FET is a combi-
nation of conduction losses, switching losses and bottom
FET body diode recovery losses.
a) Conduction losses are simply calculated as:
IN
O
)on(DS
2
OCOND
V
V
RIP
≈
⋅⋅=
cycle duty =
where
δ
δ
b) Switching losses can be estimated by assuming a switch-
ing time, if we assume 100ns then:
3
INOSW 10VIP −
⋅⋅=
or more generally,
4
f)tt(VI
POSCfrINO
SW ⋅+⋅⋅
=
c) Body diode recovery losses are more difficult to esti-
Application Information (Cont.)
11
2001 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1114
PRELIMINARY
mate, but to a first approximation, it is reasonable to as-
sume that the stored charge on the bottom FET body di-
ode will be moved through the top FET as it starts to turn
on. The resulting power dissipation in the top FET will be:
OSCINRRRR fVQP ⋅⋅=
To a first order approximation, it is convenient to only con-
sider conduction losses to determine FET suitability.
For a 5V in; 2.8V out at 14.2A requirement, typical FET
losses would be:
Using 1.5X Room temp RDS(ON) to allow for temperature rise.
epyTTEFR
)no(SD
m( Ω))W(DPegakcaP
S2043LRI5196.1D
2
KAP
3022LRI5.0191.1D
2
KAP
0144iS0262.28-OS
BOTTOM FET - Bottom FET losses are almost entirely due
to conduction. The body diode is forced into conduction at
the beginning and end of the bottom switch conduction
period, so when the FET turns on and off, there is very
little voltage across it, resulting in low switching losses.
Conduction losses for the FET can be determined by:
)1(RIP )on(DS
2
OCOND δ−⋅⋅=
For the example above:
epyTTEFR
)no(SD
m( Ω)P
D
)W(egakcaP
S2043LRI5133.1D
2
KAP
3022LRI5.0139.0D
2
KAP
0144iS0277.18-OS
Each of the package types has a characteristic thermal
impedance, for the TO-220 package, thermal impedance
is mostly determined by the heatsink used. For the sur-
face mount packages on double sided FR4, 2 oz printed
circuit board material, thermal impedances of 40oC/W for
the D2PAK and 80oC/W for the SO-8 are readily achiev-
able. The corresponding temperature rise is detailed be-
low:
(esirerutarepmeT
0
)C
epyTTEFTEFpoTTEFmottoB
S2043LRI6.762.35
3022LRI6.742.73
0144iS8.0816.141
It is apparent that single SO-8 Si4410 are not adequate
for this application, but by using parallel pairs in each po-
sition, power dissipation will be approximately halved and
temperature rise reduced by a factor of 4.
INPUT CAPACITORS - since the RMS ripple current in the
input capacitors may be as high as 50% of the output cur-
rent, suitable capacitors must be chosen accordingly. Also,
during fast load transients, there may be restrictions on
input di/dt. These restrictions require useable energy stor-
age within the converter circuitry, either as extra output
capacitance or, more usually, additional input capacitors.
Choosing low ESR input capacitors will help maximize ripple
rating for a given size.
Application Information (Cont.)
122001 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1114
PRELIMINARY
SC1114 Gain & Phase Margin
Typical Vout Gain/Phase plot at Vin = 5V, Iout = 3A
SC1114 Vout Gain / Phase
3A Load
-10
0
10
20
30
40
50
10 100 1000 10000 100000
Freq (Hz)
Gain (dB)
0
20
40
60
80
100
120
140
160
180
200
Phase (de g)
Gain
Phase
13
2001 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1114
PRELIMINARY
SC1114 Gain & Phase Margin
Typical LDO1 Gain/Phase plot at Vin = 1.8V, Iout = 30mA
SC1114 LDO1 Gain / Phase
30mA Load
-20
-10
0
10
20
30
40
50
60
10 100 1000 10000 100000
Freq
(
Hz
)
Gain (dB)
0
20
40
60
80
100
120
140
160
180
200
Phase ( deg)
Gain
Phase
Typical LDO1 Gain/Phase plot at Vin = 1.8V, Iout = 1A
SC1114 LDO2 Gain / Phase
1A Load
-10
0
10
20
30
40
50
10 100 1000 10000 100000
Freq
(
Hz
)
Gain (dB )
0
20
40
60
80
100
120
140
160
180
200
Phase (deg)
Gain
Phase
142001 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1114
PRELIMINARY
Typical Characteristics
TBD
15
2001 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1114
PRELIMINARY
5V IN J6
JP1_LDO IN
**
+
C8
1500uF
R3 0
GND J2
D1
D1N4148
C17
0.1uF
LDO IN
1
Q4
IRFR120N
1.2V
J16
C7
0.1uF
C3
0.1uF
*
JP2_VTT
1 2
+
C10
1500uF
L1 4uH
GND
J18
LDO IN
J14
C18
0.1uF
1 0
1.5V
J15
C20
0.1uF
+C15
330uF
0
JP1_VTT
12
C11
0.1uF
+C13
330uF
R1
10k
**
Q5
2N7002
Q2
IRLR3103
+
C2
1500uF
*
GND
J12
C4
0.1uF
Q3
IRFR120N
12V IN J1
Vout
J7
0
JP2_VTT
GND
J17
RT
TBD
GND J4
VTT
5V IN J5
U1
SC1114CS
12
5
3
7
6
9
10
13
14
4
11
8
15 2
116
PWRGD
BCAP-
STBY
PHASE
GND
DH
BST
VOSENSE
SS/EN
BCAP+
VCC
DL
GATE2 GATE1
LDOS1LDOS2
+C14
330uF
GND J8 R4 2.2
**
R2 0
1
POWER GOOD J11
LDO1 Input Voltage
+
C9
1500uF
JP1_LDO IN
12
R5
0
LDO2 Input Voltage
C12
0.1uF
JP1_VTT
1
Vout
J9
0
C6
0.1uF
5V STBY J3
**
C16
22uF
**
Q1
IRLR3103
GND J10
C19
0.1uF
JP2_LDO IN
VTT
+
C5
1500uF
RB
TBD
GND
J19
GND
J13
C1
0.1uF
* Q5 & C16 to be used for lower power
applications instead of Q4, C15.
LDO IN
JP2_LDO IN
1 2
Evaluation Board Bill of Materials
Evaluation Board Schematics
SC1114 Evaluation board Revised: Friday, April 6, 2001
SC1114EVB Revision: 1.2
Bill Of Materials April 6,2001
Item Q u an tity Reference Part Foo t print
C1,C3,C4,C6,C7,C11,C12,
C17,C18,C19,C20
2 5 C2,C5,C8,C9,C10 1500uF CPCYL/D.400/LS.200/.034
3 3 C13,C14,C15 330uF CPCYL/D.275/LS.100/.031
4 1 C16 22uF SM/C_1206
5 1 D1 D1N4148 SM/D_1206
6 4 JP1_VTT,JP1_LDO IN, TP2 VIA\2P
JP2_VTT,JP2_LDO IN
7 1 J1 12V IN ED5052
J2,J4,J8,J10,J12,J13,J17,
J18,J19
91J3 5V STBY ED5052
10 2 J5,J6 5V IN ED5052
11 2 J7,J9 Vout ED5052
12 1 J11 POWER GOOD ED5052
13 1 J14 LDO IN ED5052
14 1 J15 1.5V ED5052
15 1 J16 1.2V ED5052
16 1 L1 4uH DO5022
17 2 Q2,Q1 IRLR3103 DPAKFET
18 2 Q4,Q3 IRFR120N DPAKFET
19 1 Q5 2N7002 or IRFR120N SM/SOT23_GSD or DPAKFET
20 1 R1 10k SM/R_0805
21 1 RB TBD SM/R_0805
22 1 RT TBD SM/R_0805
23 3 R2,R3,R5 0 SM/R_0805
24 1 R4 2.2 SM/R_0805
25 1 U1 SC1114CS SO-16
98
81 0.1uF SM/C_0805
GND ED5052
162001 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1114
PRELIMINARY
Evaluation Board Gerber Plots
Board Layout Assembly Top Board Layout Bottom
Board Layout Top
17
2001 Semtech Corp. www.semtech.com
POWER MANAGEMENT
SC1114
PRELIMINARY
Semtech Corporation
Power Management Products Division
652 Mitchell Rd., Newbury Park, CA 91320
Phone: (805)498-2111 FAX (805)498-3804
Outline Drawing - SO-16
Contact Information
Land Pattern