SC1114 Synchronous PWM Controller with Dual Low Dropout Regulator Controllers POWER MANAGEMENT Description PRELIMINARY Features K Dual linear controllers K LDOs track input voltage within 200mV (function of The SC1114 was designed for the latest high speed motherboards. It combines a synchronous voltage mode controller (switching section) with two low-dropout linear regulator controllers. The voltage mode controller provides the power supply for the system or the dual linear regulators. The Dual linear controllers provide necessary system voltages. K K K K The SC1114 switching section features lossless current sensing and latched driver outputs for enhanced noise immunity. It operates at a fixed frequency of 200kHz, with an externaly programable output voltage. the MOSFETs used) until regulation Integrated drivers Power Good Signal Soft Start Lossless Current Sense Applications K Pentium(R) IV Motherboards K Triple power supplies The SC1114 linear sections are low dropout regulators designed to track their input power supply during power up and down. A Power Good signal is also available once the the LDO1 output is within regulation. Typical Application Circuit 12V IN 5V STBY C1 0.1uF 5V IN C2 2x1500uF + C3 0.1uF C4 0.1uF U1 11 C5 0.1uF 4 C6 0.1uF 5 14 12 POWER GOOD C9 0.1uF 13 15 16 VCC 3 STBY 10 BST BCAP+ 9 DH BCAP- 7 PHASE SS/EN 8 DL PWRGD VOSENSE GATE1 LDOS2 LDOS1 Q1 MOSFET N L1 4uH Vout R2 2.2 C7 Q2 3x1500uF MOSFET N C8 0.1uF + 6 GND GATE2 R1 2.2 2 1 RT SC1114CS + Q3 MOSFET N C10 330uF + Revision 1, April 2001 Q4 MOSFET N 1.2V 1.5V C11 330uF + 1 RB C12 330uF www.semtech.com SC1114 PRELIMINARY POWER MANAGEMENT Absolute Maximum Ratings Parameter Symbol Maximum Units VCC to GND -0.3 to +7 V STBY to GND -0.3 to +7 V BST to GND -0.3 to +15 V PHASE to GND -1 to +8 V LDOSx -0.3 to 5 V Operating Temperature Range TA 0 to +70 C Junction Temperature Range TJ 0 to +125 C Storage Temperature Range TSTG -65 to +150 C Lead Temperature (Soldering) 10 Seconds TL 300 C Thermal Resistance Junction to Ambient JA 130 C/W Thermal Impedance Junction to Case JC 30 C/W Electrical Characteristics Unless specified: VOSENSE = VO; Vcc=4.75V to 5.25V; STBY=4.75V to 5.25V; BST = 11.4V to 12.6V; TA = 0 to 70C Parameter Symbol Conditions MIN TYP MAX UNITS 4.4 5 5.25 V 8 12 mA 20 mA 1.224 V Supply (VCC) Supply Voltage VCC ICCQ VCC = 5V, SS/EN = 0V ICC VCC = 5V, SS/EN > 1V Output Voltage (1) Vout IO = 4A Load Regulation((1) LOADREG IO = 0A to 4A 1 % Line Regulation LINEREG Vin = 4.75V to 5.25V 0.15 % Supply Quiescent Current Supply Operating Current (1) Switching Section (1) 1.176 1.200 fOSC 175 200 D 90 95 Current Limit trip (Vin-VPHASE) VtripIlimit 180 200 OscillatorGain (AOL) GAINVout Oscillator Frequency Oscillator Max Duty Cycle (3) VOSENSE to VO 225 kHz % 220 35 mV dB Under Voltage Lock Out Threshold VCCHIGH 3.9 4.1 4.4 V Hysteresis VCCHYST 110 140 170 mV PGth 88 LDOS1 112 % Power Good Power Good Threshold Voltage(6) Soft Start / Enable IsourceSS/EN VSS/EN = 1.5V 5 10 12 A SS/EN Sink current IsinkSS/EN VSS/EN = 1.5V 1 2 3 A Shutdown Voltage VSS/EN 600 650 mV SS/EN Source current (2) (2) 2001 Semtech Corp. 2 www.semtech.com SC1114 POWER MANAGEMENT Electrical Characteristics (Cont.) PRELIMINARY Unless specified: VOSENSE = VO; Vcc=4.75V to 5.25V; STBY=4.75V to 5.25V; BST = 11.4V to 12.6V; TA = 0 to 70C Parameter Symbol Conditions MIN TYP MAX UNITS BST-DH = 4.5V 500 mA DH-PHASE = 3.1V 500 mA DH-PHASE = 1.5V 100 mA VCC-DL = 4.5V 500 mA DL-GND = 3.1V 500 mA DL-GND = 1.5V 100 mA Internal Drivers Peak DH Source Current IsourceDH Peak DH Sink Current IsinkDH Peak DL Source Current IsourceDL Peak DL Sink Current IsinkDL Dead time TDEAD 40 100 Standby Voltage VSTBY 4.4 5 Standby Quiescent current ISTDBYQ Tracking Difference(1)(4) DeltaTRACK Output Voltage LDO1 VLDO1 IO = 0 to 50mA, Vin = 5V 1.176 1.200 1.224 V Output Voltage LDO2 VLDO2 IO = 0 to 3A, Vin = 5V 1.470 1.500 1.530 V Load Regulation LOADREG ns Linear Sections Line Regulation LINEREG LDOS(1,2) Input Impedance(3) ZIN Gain (AOL)(3) GAINLDO VSTBY = 5V, SS/EN = 0V 5.25 V 8 mA 200 mV LDO1 IO = 0 to 50mA, Vin = 5V 0.3 % LDO2 IO = 0 to 3A, Vin = 5V 0.3 % LDO1 Io = 50mA, Vin = 4.75V to 5.25V 0.3 % LDO2 Io = 3A, Vin = 4.75V to 5.25V 0.3 % 10 LDOS (1,2) to GATE (1,2) k 50 dB Notes: (1) All electrical characteristics are for the application circuit on page 15. (2) Soft start function is performed after Vcc is above the UVLO and SS/EN is above 600mV. The Soft start capacitor is then charged at a 10uA constant current until SS/EN is charged to above 1V. (3) Guaranteed by design (4) Tracking Difference is defined as the delta between Vin and the LDO1, LDO2 output voltages during the linear ramp up until regulation is achieved. The tracking voltage differance might vary depending on MOSFETs RdSON, and load conditions. (5) This device is ESD sensitive. Use of standard ESD handling precautions is required. (6) An open Collector flag (PWRGD Pin) is held low until the LDOS1 is with in 12% of regulation. 2001 Semtech Corp. 3 www.semtech.com SC1114 POWER MANAGEMENT Pin Configuration Ordering Information Top View LDOS1 GATE1 STBY BCAP+ BCAPGND PHASE DL 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 LDOS2 GATE2 SS/EN VOSENSE PWRGD VCC BST DH PRELIMINARY Part Number (1) Package Linear Voltage Temp Range (TJ) SC1114STR SO-16 1.2V/1.5V 0 to 125C SC1114EVB Evaluation Board Note: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (16-Pin SOIC) Pin Descriptions Pin # Pin Name 1 LDOS1 Sense Input for LDO1(1.2V) 2 GATE1 Gate Drive Output LDO1 (1.2V) 3 STBY 5V Standby Input, supplies power for Ref, Charge Pump, Oscillator and FET controllers 4 BCAP+ Positive Connection to Boost Capacitor 5 BCAP- Negative Connection to Boost Capacitor 6 GND 7 PHASE 8 DL Low Side Driver Output 9 DH High Side Driver Output 10 BST Boost Input 11 VCC Power Supply Input 12 PWRGD 13 VOSENSE 14 SS/EN Soft Start/Enable 15 GATE2 Gate Drive output LDO2 (1.5V) 16 LDOS2 Sense Input for LDO2 (1.5V) 2001 Semtech Corp. Pin Function Ground Phase Node Open Colector Power Good Flag for LDO1 Output Output Sense Input for SMPS Output 4 www.semtech.com SC1114 POWER MANAGEMENT Block Diagram PRELIMINARY VCC VBG 200mV UVLO 1.2V + Bandgap OVER CURRENT + - BST -10% +10% HIGH SIDE DRIVE DH - PWRGD + PHASE OSCILLATOR SHOOT THRU CONTROL + VCC PWM ERROR AMP R - VOSENSE VCC Q + VBG + LOW SIDE DRIVE S SET DOMINATES S 10uA 0.8V SS/EN SS/EN Q + - GND R HICCUP LATCH FAULT + 0.6V DL LOW SIDE OFF 5VSTBY 2uA 5VSTBY VBG + GATE2 5VSTBY STBY 5VSTBY CHARGE PUMP OSCILLATOR VBG + - BCAP+ LDOS2 GATE1 LDOS1 BCAP- Marking Information SC1114S yyww xxxxx ES yyww = Datecode (Example: 9912) xxxxx = Semtech Lot # (Example: 90101) 2001 Semtech Corp. 5 www.semtech.com SC1114 PRELIMINARY POWER MANAGEMENT Application Information THEORY OF OPERATION to cross the oscillator triangular ramp of 1V to 2V. The SC1114 has integrated a synchronous buck controller and two Low drop out regulator controllers into a 16 Pin SOIC package. The switching regulator provides a 1.2V Vout voltage for use in Pentium(R) III Motherboards., while the dual LDO regulators provide 1.2V, and 1.5V to power up the Chipset and the Clock circuitry. As the SS/EN pin continues to rise, the error amplifier output also rises at the same rate and the duty cycle increases. Once the Vout has reached regulation, the error amplifier output will no longer be clamped to the SS/EN voltage and will stay between 1V to 2V. The SS/EN voltage continues to rise up to 2.5V and will stay at that voltage level during normal operation. SUPPLIES VCC Two supplies, VSTBY, and VCC are used to power the SC1114. VSTBY supply provides the bias for the Internal Reference, Oscillator, and the LDO FET controllers. The VCC supply provides the bias for the Power Good circuitry, and the high side FET Rdson sensing/over current circuitry, VCC also is used to drive the low side Mosfet gate. An external 12V supply or a classical boot strapping technique can provide the gate drive for the upper Mosfet. SS/EN Phase Node PWM CONTROLLER SC1114 is a voltage mode buck controller that utilizes an internally compensated high bandwidth error amplifier to sense the Vout output voltage. External compensation components are not needed and a stable closed loop responce is insured due to the internal compensation. If an over current condition occurs, the SS/EN pin will discharge by a 2uA current source, from 2.5V to 800mV. During this time both DH, and DL will be turned off. Once the SS/EN reaches 800mV, the low side gate will be turned on, and the SS/EN pin will again start to be charged by the 10uA current source, and the same soft start sequence mentioned above will be repeated. START UP SEQUENCE Initially during the power up, the SC1114 is in under voltage lock out condition. The latch (SET dominant) in the hiccup section is set , and the SS/EN pin is pulled low by the 2uA soft start current source. OVER CURRENT Upper Mosfets Rdson is used to monitor the drop across the top FET due to an over current condition. This Method of current sensing minimizes any unnecessary losses due to external sense resistance. Mean while the high side and low side gate drivers DH, and DL are kept low. Once the VCC exceeds the UVLO threshold of 4.2V, the latch is reset and the external soft start capacitor starts to be charged by a 10uA current source. An internal comparator with a 200mV reference monitors the Drop across the upper FET, Once the Vdson of the Mosfet exceeds the 200mV limit, the low side gate is turned on and the upper FET is turned off. Also an internal latch is set and the Soft start capacitor is discharged. Once the lower threshold of the soft start circuit is crossed, the same Softstart sequence mentioned previously is repeated. This sequence is repeated until the over condition is removed. The gate drives are still kept off until the soft start capacitors voltage rises above 600mV, when the low side gate is turned on , and the high side gate is kept off. The gate drive status stays the same until the capacitors voltage reaches 1V, when the error amplifier output starts 2001 Semtech Corp. 6 www.semtech.com SC1114 POWER MANAGEMENT Application Information (Cont.) PRELIMINARY Vdiode drop. Shoot through control circuitry provides a 100ns dead time to ensure both upper and lower MOSFET will not turn on simultaneously and cause a shoot through condition. GATE DRIVERS DUAL LDO CONTROLLERS The Low side gate driver is supplied from VCC and provide a peak source/sink current of and 500mA. The high side gate drive is also capable of sourcing and sinking peak currents of 500mA. The high side Mosfet gate drive can be provided by an external 12V supply that is connected from BST to GND. The actual gate to source voltage of the upper Mosfet will approximately equal 7V (12V-VCC). If the external 12V supply is not available, a classical boot strap technique can be implemented from the VCC supply. A boot strap capacitor is connected from BST to Phase while VCC is connected through a diode (Schottky or other fast low VF diode) to the BST. This will provide a gate to source voltage approximately to VCC- SC1114 also provides two low drop out linear regulator controllers that can be used to generate a 1.2V and a 1.5V outputs. The LDO output voltage is achieved by controlling the voltage drop across an external Mosfet from an external or the PWM ( Vout should be set > 2V) output voltage. The output voltage is sensed at the LDOS pin of the SC1114 and compared to an internal reference. The gate drive to the external Mosfet is then adjusted until regulation is achieved. In order to have sufficient voltage to the gate drives of the external Mosfet, an internal charge pump is utilized to boost the gate drive voltage to about two times the VSTBY. The internal charge pump charges an external Bucket capacitor to VSTBY and then connects it in series with VSTBY to the LDOs supply at a frequency of about 200kHz. This 2001 Semtech Corp. 7 www.semtech.com SC1114 PRELIMINARY POWER MANAGEMENT Application Information (Cont.) High currents switching at 200kHz are present in the application and their effect on ground plane voltage differentials must be understood and minimized. 1). The high power parts of the circuit should be laid out first. A ground plane should be used, the number and position of ground plane interruptions should be such as to not unnecessarily compromise ground plane integrity. Isolated or semi-isolated areas of the ground plane may be deliberately introduced to constrain ground currents to particular areas, for example the input capacitor and bottom FET ground. 2). The loop formed by the Input Capacitor(s) (Cin), the Top FET (Q1) and the Bottom FET (Q2) must be kept as small as possible. This loop contains all the high current, fast transition switching. Connections should be as wide and as short as possible to minimize loop inductance. Minimizing this loop area will a) reduce EMI, b) lower ground injection currents, resulting in electrically cleaner grounds for the rest of the system and c) minimize source ringing, resulting in more reliable gate switching signals. 3). The connection between the junction of Q1, Q2 and the output inductor should be a wide trace or copper region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection short will minimize EMI. Also keep the Phase connection to the IC short, top FET gate charge currents flow in this trace. 4) The Output Capacitor(s) (Cout) should be located as close to the load as possible, fast transient load cur ensures sufficient gate drive voltage for the LDOs independent of the VCC or the 12V external supply being available due to start up timing sequence from the silver box. The LDO1, and LDO2 output voltages are forced to track the 3.3V input supply. This feature ensures that during the start up application of the 3.3V, the LDO1, and LDO2 outputs track the 3.3V within 200mV typical until regulation is achieved. However, the VSTBY should be established at least 500us, to allow the charge pump to reach its maximum voltage, before the linear section will track within 200mV. This tracking will sequence the correct start up timing for the external Chipset and Clock circuitry. POWER GOOD The ouput voltage from LDOS1 is monitored, and once it has reached regulation and is within 1.2V 12%, an open Collector power good flag is activated. LAYOUT GUIDELINES Careful attention to layout requirements are necessary for successful implementation of the SC1114 PWM controller. 12V IN 5V STBY 5V IN U1 SC1114CS VCC STBY BCAP+ + BST DH BCAP- PHASE Vout SS/EN PWRGD VOSENSE DL + GND GATE2 GATE1 LDOS2 LDOS1 3.3V IN Heavy Lines indicate high current paths. + 2001 Semtech Corp. C10 330uF 1.5V 1.2V + + 8 www.semtech.com SC1114 POWER MANAGEMENT Application Information (Cont.) PRELIMINARY rents are supplied by Cout only, and connections between Cout and the load must be short, wide copper areas to minimize inductance and resistance. 5) The SC1114 is best placed over a quiet ground plane area, avoid pulse currents in the Cin, Q1, Q2 loop flowing in this area. GND should be returned to the ground plane close to the package and close to the ground side of (one of) the output capacitor(s). If this is not possible, the GND pin may be connected to the ground path between the Output Capacitor(s) and the Cin, Q1, Q2 loop. Under no circumstances should GND be returned to a ground inside the Cin, Q1, Q2 loop. 6) BST for the SC1114 should be supplied from the 12V supply, the BST pin should be decoupled directly to GND by a 0.1mF ceramic capacitor, trace lengths should be as short as possible. If a 12V supply is not available, a classical boot strap method could be implemented to achieve the upper Mosfets gate drive. 7) The connection from the Phase Node to the Phase pin of the SC1114 should be minimized to avoid any stary inductance. If the layout can not be optomized due to constranints, a small Schottky diode (See page 17) maybe connected from the Phase pin to the ground directly at the IC. This will clamp excessive negative voltages at the IC. 8) Ideally, the grounds for the two LDO sections should be returned to the ground side of (one of) the output capacitor(s). 5V + Vout + 2001 Semtech Corp. 9 www.semtech.com SC1114 PRELIMINARY POWER MANAGEMENT Application Information (Cont.) COMPONENT SELECTION SWITCHING SECTION OUTPUT CAPACITORS - Selection begins with the most critical component. Because of fast transient load current requirements in modern microprocessor core supplies, the output capacitors must supply all transient load current requirements until the current in the output inductor ramps up to the new level. Output capacitor ESR is therefore one of the most important criteria. The maximum ESR can be simply calculated from: RESR Vt It Where Vt = Maximum transient voltage excursion It = Transient current step For example, to meet a 100mV transient limit with a 10A load step, the output capacitor ESR must be less than 10m. To meet this kind of ESR level, there are three available capacitor technologies. Technology Each Capacitor C (uF) ESR (m) Low ESR Tantalum 330 60 OS-CON 330 Low ESR Aluminum 1500 Total Qty Rqd. C (uF) ESR (m) 6 2000 10 25 3 990 8.3 44 5 7500 8.8 The choice of which to use is simply a cost/performance issue, with Low ESR Aluminum being the cheapest, but taking up the most space. INDUCTOR - Having decided on a suitable type and value of output capacitor, the maximum allowable value of inductor can be calculated. Too large an inductor will produce a slow current ramp rate and will cause the output capacitor to supply more of the transient load current for longer - leading to an output voltage sag below the ESR excursion calculated above. 2001 Semtech Corp. The maximum inductor value may be calculated from: L R ESR C (VIN - VO ) It The calculated maximum inductor value assumes 100% duty cycle, so some allowance must be made. Choosing an inductor value of 50 to 75% of the calculated maximum will guarantee that the inductor current will ramp fast enough to reduce the voltage dropped across the ESR at a faster rate than the capacitor sags, hence ensuring a good recovery from transient with no additional excursions. We must also be concerned with ripple current in the output inductor and a general rule of thumb has been to allow 10% of maximum output current as ripple current. Note that most of the output voltage ripple is produced by the inductor ripple current flowing in the output capacitor ESR. Ripple current can be calculated from: = I L RIPPLE V IN 4 L f OSC Ripple current allowance will define the minimum permitted inductor value. POWER FETS - The FETs are chosen based on several criteria with probably the most important being power dissipation and power handling capability. TOP FET - The power dissipation in the top FET is a combination of conduction losses, switching losses and bottom FET body diode recovery losses. a) Conduction losses are simply calculated as: PCOND 2 = IO R DS ( on ) where = duty cycle VO V IN b) Switching losses can be estimated by assuming a switching time, if we assume 100ns then: P SW = I O V IN 10 -3 or more generally, IO VIN ( t r + t f ) fOSC 4 c) Body diode recovery losses are more difficult to estiPSW = 10 www.semtech.com SC1114 POWER MANAGEMENT Application Information (Cont.) PRELIMINARY mate, but to a first approximation, it is reasonable to assume that the stored charge on the bottom FET body diode will be moved through the top FET as it starts to turn on. The resulting power dissipation in the top FET will be: P RR = Q RR circuit board material, thermal impedances of 40oC/W for the D2PAK and 80oC/W for the SO-8 are readily achievable. The corresponding temperature rise is detailed below: V IN f OSC Temperature rise ( 0C) To a first order approximation, it is convenient to only consider conduction losses to determine FET suitability. For a 5V in; 2.8V out at 14.2A requirement, typical FET losses would be: Using 1.5X Room temp RDS(ON) to allow for temperature rise. FET Type RDS(on) (m) PD(W) Package IRL3402S 15 1.69 D2PAK IRL2203 10.5 1.19 D2PAK Si4410 20 2.26 SO-8 BOTTOM FET - Bottom FET losses are almost entirely due to conduction. The body diode is forced into conduction at the beginning and end of the bottom switch conduction period, so when the FET turns on and off, there is very little voltage across it, resulting in low switching losses. Conduction losses for the FET can be determined by: P COND 2 = IO R DS ( on ) (1 - ) FET Type Top FET Bottom FET IRL3402S 67.6 53.2 IRL2203 47.6 37.2 Si4410 180.8 141.6 It is apparent that single SO-8 Si4410 are not adequate for this application, but by using parallel pairs in each position, power dissipation will be approximately halved and temperature rise reduced by a factor of 4. INPUT CAPACITORS - since the RMS ripple current in the input capacitors may be as high as 50% of the output current, suitable capacitors must be chosen accordingly. Also, during fast load transients, there may be restrictions on input di/dt. These restrictions require useable energy storage within the converter circuitry, either as extra output capacitance or, more usually, additional input capacitors. Choosing low ESR input capacitors will help maximize ripple rating for a given size. For the example above: FET Type RDS(on) (m) PD(W) Package IRL3402S 15 1.33 D2PAK IRL2203 10.5 0.93 D2PAK Si4410 20 1.77 SO-8 Each of the package types has a characteristic thermal impedance, for the TO-220 package, thermal impedance is mostly determined by the heatsink used. For the surface mount packages on double sided FR4, 2 oz printed 2001 Semtech Corp. 11 www.semtech.com SC1114 PRELIMINARY POWER MANAGEMENT SC1114 Gain & Phase Margin SC1114 Vout Gain / Phase 3A Load 50 200 180 Gain 40 160 Gain (dB) 120 20 Phase 100 Phase (deg) 140 30 80 10 60 40 0 20 -10 10 100 1000 10000 0 100000 Freq (Hz) Typical Vout Gain/Phase plot at Vin = 5V, Iout = 3A 2001 Semtech Corp. 12 www.semtech.com SC1114 POWER MANAGEMENT SC1114 Gain & Phase Margin PRELIMINARY SC1114 LDO1 Gain / Phase 30mA Load 200 60 Phase 180 50 160 Gain 40 140 120 100 20 Phase (deg) Gain (dB) 30 80 10 60 0 40 -10 20 -20 10 100 1000 10000 0 100000 Freq (Hz) Typical LDO1 Gain/Phase plot at Vin = 1.8V, Iout = 30mA SC1114 LDO2 Gain / Phase 1A Load 200 50 180 Gain 40 140 Phase 120 100 20 Phase (deg) 30 Gain (dB) 160 80 10 60 40 0 20 -10 10 100 1000 10000 0 100000 Freq (Hz) Typical LDO1 Gain/Phase plot at Vin = 1.8V, Iout = 1A 2001 Semtech Corp. 13 www.semtech.com SC1114 PRELIMINARY POWER MANAGEMENT Typical Characteristics D TB 2001 Semtech Corp. 14 www.semtech.com SC1114 POWER MANAGEMENT Evaluation Board Schematics 12V IN J1 GND J2 5V STBY J3 GND J4 5V IN J5 5V IN J6 C1 0.1uF C2 R5 0 C3 0.1uF + 1500uF C5 C6 0.1uF + 4 C7 0.1uF 5 J8 GND J10 14 12 POWER GOOD J11 R1 C17 0.1uF 10k C12 0.1uF C4 0.1uF U1 11 1500uF GND PRELIMINARY 13 15 16 VCC STBY BCAP+ BST DH BCAP- PHASE 3 10 Q1 IRLR3103 R2 0 9 R4 7 L1 2.2 PWRGD VOSENSE GATE2 DL GND GATE1 LDOS2 LDOS1 8 6 R3 C8 Q2 IRLR3103 0 D1N4148 + C9 1500uF + C10 + 1500uF C11 0.1uF C20 0.1uF GND J12 2 J13 GND 1 RT TBD LDO IN J14 2 1 1 RB TBD ** JP1_VTT ** JP2_LDO IN C13 330uF 2 2 1 ** JP1_LDO IN * Q4 IRFR120N ** JP2_VTT 1 GND J17 2 + 1.5V J15 ** JP1_VTT 0 1 JP1_LDO IN 1 0 LDO1 Input Voltage LDO IN VTT JP2_VTT 0 1 JP2_LDO IN 1 0 LDO2 Input Voltage LDO IN VTT C18 C14 330uF 0.1uF * Q5 & C16 to be used for lower power applications instead of Q4, C15. Q5 2N7002 1.2V J16 Q3 IRFR120N + Vout 1500uF SC1114CS + J7 J9 D1 SS/EN Vout 4uH C15 330uF * C16 22uF C19 0.1uF GND J19 GND J18 Evaluation Board Bill of Materials SC1114 Evaluation board Revised: Friday, April 6, 2001 SC1114EVB Revision: 1.2 Bill Of Materials April 6,2001 Item Q uantity Reference Part Foot print C1,C3,C4,C6,C7,C11,C12, 0.1uF SM/C_0805 1 8 C17,C18,C19,C20 2 5 C2,C5,C8,C9,C10 1500uF CPCYL/D.400/LS.200/.034 3 3 C13,C14,C15 330uF CPCYL/D.275/LS.100/.031 4 1 C16 22uF SM/C_1206 5 1 D1 D1N4148 SM/D_1206 6 4 JP1_VTT,JP1_LDO IN, TP2 VIA\2P JP2_VTT,JP2_LDO IN 7 1 J1 12V IN ED5052 J2,J4,J8,J10,J12,J13,J17, GND ED5052 8 9 J18,J19 9 1 J3 5V STBY ED5052 10 2 J5,J6 5V IN ED5052 11 2 J7,J9 Vout ED5052 12 1 J11 POWER GOOD ED5052 13 1 J14 LDO IN ED5052 14 1 J15 1.5V ED5052 15 1 J16 1.2V ED5052 16 1 L1 4uH DO5022 17 2 Q2,Q1 IRLR3103 DPAKFET 18 2 Q4,Q3 IRFR120N DPAKFET 19 1 Q5 2N7002 or IRFR120N SM/SOT23_GSD or DPAKFET 20 1 R1 10k SM/R_0805 21 1 RB TBD SM/R_0805 22 1 RT TBD SM/R_0805 23 3 R2,R3,R5 0 SM/R_0805 24 1 R4 2.2 SM/R_0805 25 1 U1 SC1114CS SO-16 2001 Semtech Corp. 15 www.semtech.com SC1114 PRELIMINARY POWER MANAGEMENT Evaluation Board Gerber Plots Board Layout Assembly Top Board Layout Bottom Board Layout Top 2001 Semtech Corp. 16 www.semtech.com SC1114 POWER MANAGEMENT Outline Drawing - SO-16 PRELIMINARY Land Pattern Contact Information Semtech Corporation Power Management Products Division 652 Mitchell Rd., Newbury Park, CA 91320 Phone: (805)498-2111 FAX (805)498-3804 2001 Semtech Corp. 17 www.semtech.com