1© KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 11/9/2018
Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com
One world. One KEMET
Benets
• −30°Cto+85°Coperatingtemperaturerange
• Lead (Pb)-free, RoHS and REACH compliant
• EIA 0402, 0603, 0805, 1206, and 1210 case sizes
• DCvoltageratingsof6.3V,10V,16V,25V,and50V
• Capacitanceofferingsrangingfrom0.022μFto22μF
• Availablecapacitancetoleranceof±20%and+80%/−20%
• Non-polardevice,minimizinginstallationconcerns
• 100%puremattetin-platedterminationnishthatallows
for excellent solderability
Applications
Typicalapplicationsincludelimitedtemperature,decoupling
and bypass.
Overview
KEMET’sY5Vdielectricfeaturesan85°Cmaximum
operatingtemperatureandisconsidered“general-purpose.”
TheElectronicsIndustriesAlliance(EIA)characterizes
Y5VdielectricasaClassIIImaterial.Componentsofthis
classicationarexed,ceramicdielectriccapacitors,
suitedforbypassanddecouplingorotherapplications
inwhichdielectriclosses,highinsulationresistanceand
capacitance stability are not of major importance. Y5V
exhibitsapredictablechangeincapacitancewithrespectto
timeandvoltage,anddisplayswidevariationsincapacitance
withreferencetoambienttemperature.Capacitancechange
islimitedto+22%,−82%from−30°Cto+85°C.
SurfaceMountMultilayerCeramicChipCapacitors(SMDMLCCs)
Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)
Ordering Information
C1210 C226 Z 4 V A CTU
Ceramic Case Size
(L" x W")
Specication/
Series
Capacitance
Code (pF)
Capacitance
Tolerance
Rated
Voltage
(VDC)
Dielectric Failure Rate/
Design TerminationFinish1Packaging/
Grade (C-Spec)
0402
0603
0805
1206
1210
C = Standard Twosignicant
digitsand
number of
zeros
M = ±20%
Z=+80%/−20% 9 = 6.3
8 = 10
4 = 16
3 = 25
5 = 50
V = Y5V A = N/A C = 100% Matte Sn See
"Packaging
C-Spec
Ordering
Options
Table"
1 Additional termination nish options may be available. Contact KEMET for details.
Click image above for interactive 3D content
Open PDF in Adobe Reader for full functionality
2© KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 11/9/2018
Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)
Packaging C-Spec Ordering Options Table
Packaging Type1Packaging/Grade
Ordering Code (C-Spec)
BulkBag/Unmarked
Not required (Blank)
7" Reel/Unmarked
TU
13" Reel/Unmarked
7411 (EIA 0603 and smaller case sizes)
7210(EIA0805andlargercasesizes)
7" Reel/Marked
TM
13" Reel/Marked
7040 (EIA 0603)
7215(EIA0805andlargercasesizes)
7"Reel/Unmarked/2mmpitch
2
7081
13"Reel/Unmarked/2mmpitch
2
7082
1 Default packaging is "Bulk Bag". An ordering code C-Spec is not required for "Bulk Bag" packaging.
1 The terms "Marked" and "Unmarked" pertain to laser marking option of capacitors. All packaging options labeled as "Unmarked" will contain capacitors
that have not been laser marked. Please contact KEMET if you require a laser marked option. For more information see "Capacitor Marking".
2 The 2 mm pitch option allows for double the packaging quantity of capacitors on a given reel size. This option is limited to EIA 0603 (1608 metric) case
size devices. For more information regarding 2 mm pitch option see "Tape & Reel Packaging Information".
Dimensions – Millimeters (Inches)
L
B
W
S
T
EIA Size
Code
Metric Size
Code
L
Length
W
Width
T
Thickness
B
Bandwidth
S
Separation
Minimum
Mounting
Technique
0402 1005
1.00 (0.040)
±0.05 (0.002)
0.50 (0.020)
±0.05 (0.002)
See Table 2 for
Thickness
0.30 (0.012)
±0.10 (0.004)
0.30 (0.012)
SolderReow
Only
0603 1608
1.60 (0.063)
±0.15 (0.006)
0.80 (0.032)
±0.15 (0.006)
0.35 (0.014)
±0.15 (0.006)
0.70 (0.028)
Solder Wave or
SolderReow
0805 2012
2.00 (0.079)
±0.20 (0.008)
1.25 (0.049)
±0.20 (0.008)
0.50 (0.02)
±0.25 (0.010)
0.75 (0.030)
1206 3216
3.20 (0.126)
±0.20 (0.008)
1.60 (0.063)
±0.20 (0.008)
0.50 (0.02)
±0.25 (0.010)
N/A
1210 3225
3.20 (0.126)
±0.20 (0.008)
2.50 (0.098)
±0.20 (0.008)
0.50 (0.02)
±0.25 (0.010)
SolderReow
Only
3© KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 11/9/2018
Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)
Qualication/Certication
CommercialGradeproductsaresubjecttointernalqualication.Detailsregardingtestmethodsandconditionsare
referenced in Table 4, Performance & Reliability.
Environmental Compliance
Lead(Pb)-free,RoHS,andREACHcompliantwithoutexemptions.
Electrical Parameters/Characteristics
Item Parameters/Characteristics
OperatingTemperatureRange −30°Cto+85°C
CapacitanceChangewithReferenceto
+25°Cand0VdcApplied(TCC) +22%,−82%
1AgingRate(Maximum%CapacitanceLoss/DecadeHour) 7.0%
2DielectricWithstandingVoltage(DWV)
250%ofratedvoltage
(5±1secondsandcharge/dischargenotexceeding50mA)
3DissipationFactor(DF)MaximumLimitat25°C 10% (6.3 V and 10 V), 7% (16 V and 25 V) and 5% (50 V )
4InsulationResistance(IR)MinimumLimitat25°C
See Insulation Resistance Limit Table
(Ratedvoltageappliedfor120±5secondsat25°C)
1 Regarding Aging Rate: Capacitance measurements (including tolerance) are indexed to a referee time of 48 or 1,000 hours. Please refer to a part
number specic datasheet for referee time details.
2 DWV is the voltage a capacitor can withstand (survive) for a short period of time. It exceeds the nominal and continuous working voltage of the
capacitor.
3 Capacitance and dissipation factor (DF) measured under the following conditions:
1kHz ± 50Hz and 1.0 ± 0.2 Vrms if capacitance ≤10µF
120Hz ± 10Hz and 0.5 ± 0.1 Vrms if capacitance >10µF
4 To obtain IR limit, divide MΩ-µF value by the capacitance and compare to GΩ limit. Select the lower of the two limits.
Note: When measuring capacitance it is important to ensure the set voltage level is held constant. The HP4284 & Agilent E4980 have a feature known as
Automatic Level Control (ALC). The ALC feature should be switched to "ON".
Post Environmental Limits
High Temperature Life, Biased Humidity, Moisture Resistance
Dielectric Rated DC
Voltage
Capacitance
Value
Dissipation Factor
(Maximum %)
Capacitance
Shift
Insulation
Resistance
Y5V
> 25
All
7.5
±30% 10% of Initial
Limit
16/25 10.0
< 16 15.0
Insulation Resistance Limit Table
EIA Case Size 100 Megohm
Microfarads or 10 GΩ
50 Megohm
Microfarads or 10 GΩ
All ≥16V ≤10V
4© KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 11/9/2018
Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)
Table 1 – Capacitance Range/Selection Waterfall (0402 – 1210 Case Sizes)
Capacitance Capacitance
Code
Case Size/
Series C0402C C0603C C0805C C1206C C1210C
Voltage Code 984 9 84398435 9 8435 9 8435
Rated Voltage (VDC)
6.3
10
16
6.3
10
16
25
6.3
10
16
25
50
6.3
10
16
25
50
6.3
10
16
25
50
Capacitance Tolerance Product Availability and Chip Thickness Codes
See Table 2 for Chip Thickness Dimensions
22,000 pF 223 M Z BB BB BB CF CF CF CF DN DN DN DN DN
27,000 pF 273 M Z BB BB BB CF CF CF CF DN DN DN DN DN
33,000 pF 333 M Z BB BB BB CF CF CF CF DN DN DN DN DN
39,000 pF 393 M Z BB BB BB CF CF CF CF DP DP DP DP DP
47,000 pF 473 M Z BB BB BB CF CF CF CF DO DO DO DO DO
56,000 pF 563 M Z BB BB BB CF CF CF CF DP DP DP DP DP
68,000 pF 683 M Z BB BB BB CF CF CF CF DP DP DP DP DP
82,000 pF 823 M Z BB BB BB CF CF CF CF DP DP DP DP DP
0.10 µF 104 M Z BB BB BB CG CG CG CG DN DN DN DN DN
0.12 µF 124 M Z CG CG CG CG DN DN DN DN
0.15 µF 154 M Z CG CG CG CG DN DN DN DN
0.18 µF 184 M Z CG CG CG CG DN DN DN DN
0.22 µF 224 M Z BB CG CG CG CG DN DN DN DN DG EC EC EC EC FD FD FD FD FD
0.27 µF 274 M Z CG CG CG CG DN DN DN DN EB EB EB EB FD FD FD FD FD
0.33 µF 334 M Z CG CG CG CG DG DG DG DG EB EB EB EB FD FD FD FD FD
0.39 µF 394 M Z CG CG CG DN DN DN DN EB EB EB EB FD FD FD FD FD
0.47 µF 474 M Z BB CG CG CG DG DG DG DG EC EC EC EC FD FD FD FD FD
0.56 µF 564 M Z CG CG DP DP DP DP EB EB EB EB FD FD FD FD FD
0.68 µF 684 M Z CG CG DP DP DP DG EB EB EB EB FD FD FD FD FD
0.82 µF 824 M Z CG CG DG DG DG DG EB EB EB EB FF FF FF FF FF
1.0 µF 105 M Z BB BB CG CG CG CG DP DP DP DG DG EP EP EP EP FH FH FH FH FH
1.2 µF 125 M Z DN DN DN EC EC EC FD FD FD
1.5 µF 155 M Z DN DN DN EC EC EC FD FD FD
1.8 µF 185 M Z DP DP DP ED ED ED FD FD FD
2.2 µF 225 M Z BB BB DG DG DG EC EC EC FJ FJ FJ
3.3 µF 335 M Z DL DL DG EH EH EH FE FE FE
4.7 µF 475 M Z DG DG DG EH² EH² EH² FT FT FT
5.6 µF 565 M Z DF DF EJ EJ EJ FG FG FG
6.8 µF 685 M Z DG DG EJ EJ FH FH FH
10 µF 106 M Z DG DG EH EH EH EH FT² FT² FT²
15 µF 156 M Z FH FH FH
22 µF 226 M Z EH EH FT² FT² FS FS
Capacitance Capacitance
Code
Rated Voltage (VDC)
6.3
10
16
6.3
10
16
25
6.3
10
16
25
50
6.3
10
16
25
50
6.3
10
16
25
50
Voltage Code 984 9 84398435 9 8435 9 8435
Case Size/
Series C0402C C0603C C0805C C1206C C1210C
xx² Only available in Z tolerance.
5© KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 11/9/2018
Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)
Table 2A – Chip Thickness/Tape & Reel Packaging Quantities
Thickness
Code
Case
Size
Thickness ±
Range (mm)
Paper Quantity1Plastic Quantity
7" Reel 13" Reel 7" Reel 13" Reel
0402
0.50 ± 0.05
10,000
50,000
0
0
0603
0.80 ± 0.07*
4,000
15,000
0
0
0603
0.80 ± 0.10*
4,000
15,000
0
0
0805
0.78 ± 0.10*
4,000
15,000
0
0
0805
0.80 ± 0.10*
4,000
15,000
0
0
0805
0.90 ± 0.10*
4,000
15,000
0
0
0805
0.95 ± 0.10
0
0
4,000
10,000
0805
1.10 ± 0.10
0
0
2,500
10,000
0805
1.25 ± 0.15
0
0
2,500
10,000
1206
0.78 ± 0.10
4,000
10,000
4,000
10,000
1206
0.90 ± 0.10
0
0
4,000
10,000
1206
1.00 ± 0.10
0
0
2,500
10,000
1206
1.20 ± 0.20
0
0
2,500
10,000
1206
1.60 ± 0.20
0
0
2,000
8,000
1206
1.70 ± 0.20
0
0
2,000
8,000
1210
0.95 ± 0.10
0
0
4,000
10,000
1210
1.00 ± 0.10
0
0
2,500
10,000
1210
1.10 ± 0.10
0
0
2,500
10,000
1210
1.25 ± 0.15
0
0
2,500
10,000
1210
1.55 ± 0.15
0
0
2,000
8,000
1210
1.85 ± 0.20
0
0
2,000
8,000
1210
1.90 ± 0.20
0
0
2,000
8,000
1210
2.50 ± 0.30
0
0
1,000
4,000
Thickness
Code
Case
Size1
Thickness ±
Range (mm)
7" Reel 13" Reel 7" Reel 13" Reel
Paper Quantity1Plastic Quantity
Package quantity based on nished chip thickness specications.
1 If ordering using the 2 mm Tape and Reel pitch option, the packaging quantity outlined in the table above will be doubled. This option is limited to EIA
0603 (1608 metric) case size devices. For more information regarding 2 mm pitch option see “Tape & Reel Packaging Information”.
6© KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 11/9/2018
Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)
Table 2B – Bulk Packaging Quantities
Packaging Type Loose Packaging
BulkBag(default)
PackagingC-Spec1N/A2
Case Size Packaging Quantities (pieces/unit packaging)
EIA (in) Metric (mm) Minimum Maximum
0402
1005
1
50,000
0603
1608
0805
2012
1206
3216
1210
3225
1808
4520
20,000
1812
4532
1825
4564
2220
5650
2225
5664
1 The "Packaging C-Spec" is a 4 to 8 digit code which identies the packaging type and/or product grade. When ordering, the proper code must be
included in the 15th through 22nd character positions of the ordering code. See "Ordering Information" section of this document for further details.
Commercial Grade product ordered without a packaging C-Spec will default to our standard "Bulk Bag" packaging. Contact KEMET if you require a bulk
bag packaging option for Automotive Grade products.
2 A packaging C-Spec (see note 1 above) is not required for "Bulk Bag" packaging (excluding Anti-Static Bulk Bag and Automotive Grade products). The
15th through 22nd character positions of the ordering code should be left blank. All product ordered without a packaging C-Spec will default to our
standard "Bulk Bag" packaging.
7© KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 11/9/2018
Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)
Table 3 – Chip Capacitor Land Pattern Design Recommendations per IPC-7351
EIA
Size
Code
Metric
Size
Code
Density Level A:
Maximum (Most)
Land Protrusion (mm)
Density Level B:
Median (Nominal)
Land Protrusion (mm)
Density Level C:
Minimum (Least)
Land Protrusion (mm)
CY X V1 V2 CY X V1 V2 CY X V1 V2
0402 1005 0.50 0.72 0.72 2.20 1.20 0.45 0.62 0.62 1.90 1.00 0.40 0.52 0.52 1.60 0.80
0603 1608 0.90 1.15 1.10 4.00 2.10 0.80 0.95 1.00 3.10 1.50 0.60 0.75 0.90 2.40 1.20
0805 2012 1.00 1.35 1.55 4.40 2.60 0.90 1.15 1.45 3.50 2.00 0.75 0.95 1.35 2.80 1.70
1206 3216 1.60 1.35 1.90 5.60 2.90 1.50 1.15 1.80 4.70 2.30 1.40 0.95 1.70 4.00 2.00
1210 3225 1.60 1.35 2.80 5.65 3.80 1.50 1.15 2.70 4.70 3.20 1.40 0.95 2.60 4.00 2.90
121013225 1.50 1.60 2.90 5.60 3.90 1.40 1.40 2.80 4.70 3.30 1.30 1.20 2.70 4.00 3.00
1 Only for capacitance values ≥ 22 µF
Density Level A: For low-density product applications. Recommended for wave solder applications and provides a wider process window for reow
solder processes. KEMET only recommends wave soldering of EIA 0603, 0805, and 1206 case sizes.
Density Level B: For products with a moderate level of component density. Provides a robust solder attachment condition for reow solder processes.
Density Level C: For high component density product applications. Before adapting the minimum land pattern variations the user should perform
qualication testing based on the conditions outlined in IPC Standard 7351 (IPC–7351).
Image below based on Density Level B for an EIA 1210 case size.
Y
C C
X X
V1
V2
Grid Placement Courtyard
Y
8© KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 11/9/2018
Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)
Soldering Process
Recommended Soldering Technique:
•SolderwaveorsolderreowforEIAcasesizes0603,0805and1206
•AllotherEIAcasesizesarelimitedtosolderreowonly
Recommended Reow Soldering Prole:
KEMET’sfamiliesofsurfacemountmultilayerceramiccapacitors(SMDMLCCs)arecompatiblewithwave(singleordual),
convection,IRorvaporphasereowtechniques.Preheatingofthesecomponentsisrecommendedtoavoidextremethermal
stress.KEMET’srecommendedproleconditionsforconvectionandIRreowreecttheproleconditionsoftheIPC/
J-STD-020standardformoisturesensitivitytesting.Thesedevicescansafelywithstandamaximumofthreereowpasses
attheseconditions.
Prole Feature Termination Finish
SnPb 100% Matte Sn
Preheat/Soak
Temperature Minimum (TSmin)
100°C
150°C
Temperature Maximum (T
Smax
)150°C 200°C
Time (tS) from TSmin to TSmax
60 – 120 seconds
60 – 120 seconds
Ramp-Up Rate (TL to TP)3°C/second
maximum
3°C/second
maximum
Liquidous Temperature (TL)183°C 217°C
Time Above Liquidous (tL) 60 – 150 seconds 60 – 150 seconds
Peak Temperature (TP)235°C 260°C
TimeWithin5°CofMaximum
Peak Temperature (t
P
)
20 seconds
maximum
30 seconds
maximum
Ramp-Down Rate (TP to TL)6°C/second
maximum
6°C/second
maximum
Time25°CtoPeak
Temperature
6 minutes
maximum
8 minutes
maximum
Note 1: All temperatures refer to the center of the package, measured on the
capacitor body surface that is facing up during assembly reow.
Time
Temperature
Tsmin
25
Tsmax
TL
TPMaximum ramp up rate = 3°C/second
Maximum ramp down rate = 6°C/second
tP
tL
ts
25°C to Peak
9© KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 11/9/2018
Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)
Table 4 – Performance & Reliability: Test Methods and Conditions
Stress Reference Test or Inspection Method
TerminalStrength JIS–C–6429 Appendix1,Note:Forceof1.8kgfor60seconds.
Board Flex JIS–C–6429
Appendix 2, Note: Standard termination system – 2.0 mm (minimum) for all except 3 mm
for C0G. Flexible termination system – 3.0 mm (minimum).
Solderability J–STD–002
Magnication50X.Conditions:
a)MethodB,4hoursat155°C,dryheatat235°C
b)MethodBat215°Ccategory3
c)MethodD,category3at260°C
TemperatureCycling JESD22MethodJA–104
1,000Cycles(−55°Cto+125°C).Measurementat24hours+/−4hoursaftertest
conclusion.
Biased Humidity MIL–STD–202Method
103
LoadHumidity:1,000hours85°C/85%RHandratedvoltage.Add100Kohmresistor.
Measurementat24hours+/−4hoursaftertestconclusion.
LowVoltHumidity:1,000hours85°C/85%RHand1.5V.Add100Kohmresistor.
Measurementat24hours+/−4hoursaftertestconclusion.
Moisture Resistance
MIL–STD–202Method
106
t=24hours/cycle.Steps7aand7bnotrequired.
Measurementat24hours+/−4hoursaftertestconclusion.
ThermalShock
MIL–STD–202Method
107
−55°C/+125°C.Note:Numberofcyclesrequired–300,maximumtransfertime–20
seconds, dwell time – 15 minutes. Air – Air.
HighTemperatureLife
MIL–STD–202Method
108
/EIA–198
1,000hoursat125°C(85°CforX5R,Z5UandY5V)with2Xratedvoltageapplied.
StorageLife
MIL–STD–202Method
108
150°C,0VDCfor1,000hours.
Vibration MIL–STD–202Method
204
5g'sfor20minutes,12cycleseachof3orientations.Note:Use8"X5"PCB0.031"thick
7securepointsononelongsideand2securepointsatcornersofoppositesides.Parts
mountedwithin2"fromanysecurepoint.Testfrom10–2,000Hz
MechanicalShock
MIL–STD–202Method
213
Figure1ofMethod213,ConditionF.
Resistance to Solvents
MIL–STD–202Method
215
Addaqueouswashchemical,OKEMCleanorequivalent.
Storage and Handling
Ceramicchipcapacitorsshouldbestoredinnormalworkingenvironments.Whilethechipsthemselvesarequiterobustin
otherenvironments,solderabilitywillbedegradedbyexposuretohightemperatures,highhumidity,corrosiveatmospheres,
andlongtermstorage.Inaddition,packagingmaterialswillbedegradedbyhightemperature–reelsmaysoftenorwarp
andtapepeelforcemayincrease.KEMETrecommendsthatmaximumstoragetemperaturenotexceed40ºCandmaximum
storagehumiditynotexceed70%relativehumidity.Temperatureuctuationsshouldbeminimizedtoavoidcondensationon
thepartsandatmospheresshouldbefreeofchlorineandsulfurbearingcompounds.Foroptimizedsolderabilitychipstock
shouldbeusedpromptly,preferablywithin1.5yearsofreceipt.
10© KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 11/9/2018
Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)
Construction (Typical)
Dielectric
Material (BaTiO3)
Detailed Cross Section
Barrier Layer
(Ni)
Inner Electrodes
(Ni)
Barrier Layer
(Ni)
Inner Electrodes
(Ni)
Dielectric Material
(BaTiO3)
Termination
Finish
(100% Matte Sn)
Termination
Finish
(100% Matte Sn) End Termination/
External Electrode
(Cu)
End Termination/
External Electrode
(Cu)
Capacitor Marking (Optional):
Lasermarkingoptionisnotavailableon:
• C0G,UltraStableX8RandY5Vdielectricdevices
• EIA 0402 case size devices
• EIA0603casesizedeviceswithFlexibleTerminationoption.
• KPSCommercialandAutomotivegradestackeddevices.
Thesecapacitorsaresuppliedunmarkedonly.
11© KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 11/9/2018
Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)
Tape & Reel Packaging Information
KEMEToffersmultilayerceramicchipcapacitorspackagedin8,12and16mmtapeon7"and13"reelsinaccordancewith
EIAStandard481.Thispackagingsystemiscompatiblewithalltape-fedautomaticpickandplacesystems.SeeTable2for
detailsonreelingquantitiesforcommercialchips.
8 mm, 12 mm
or 16 mm carrier tape
180 mm (7.00")
or
330 mm (13.00")
Anti-static reel
Embossed plastic* or
punched paper carrier.
Embossment or punched cavity
Anti-static cover tape
(0.10 mm (0.004") maximum thickness)
Chip and KPS orientation in pocket
(except 1825 commercial, and 1825 and 2225 Military)
*EIA 01005, 0201, 0402 and 0603 case sizes available on punched paper carrier only.
KEMET
®
Bar code label
Sprocket holes
Table 5 – Carrier Tape Con guration, Embossed Plastic & Punched Paper (mm)
EIA Case Size
Tape
Size
(W)*
Embossed Plastic Punched Paper
7" Reel 13" Reel 7" Reel 13" Reel
Pitch(P
1
)* Pitch(P
1
)*
01005 – 0402 8 2 2
0603 82/4 2/4
0805 84444
1206 – 1210 84444
1805 – 1808 12 4 4
≥1812 12 8 8
KPS 1210 12 8 8
KPS 1812
and 2220
16 12 12
Array 0612 844
*Refer to Figures 1 and 2 for W and P1 carrier tape reference locations.
*Refer to Tables 6 and 7 for tolerance speci cations.
New 2 mm Pitch Reel Options*
Packaging
Ordering Code
(C-Spec)
Packaging Type/Options
C-3190
Automotivegrade7"reelunmarked
C-3191
Automotivegrade13"reelunmarked
C-7081
Commercialgrade7"reelunmarked
C-7082
Commercialgrade13"reelunmarked
* 2 mm pitch reel only available for 0603 EIA case size.
2 mm pitch reel for 0805 EIA case size under development.
Bene ts of Changing from 4 mm to 2 mm Pitching Spacing
• Lower placement costs.
• Doublethepartsoneachreelresultsinfewerreel
changesandincreasedefficiency.
• Fewerreelsresultinlowerpackaging,shippingand
storagecosts,reducingwaste.
12© KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 11/9/2018
Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)
Figure 1 – Embossed (Plastic) Carrier Tape Dimensions
P
0
T
F
W
Center Lines of Cavity
A
0
B
0
User Direction of Unreeling
Cover Tape
K
0
B
1
is for tape feeder reference only,
including draft concentric about B
0
.
T
2
ØD
1
ØD
0
B
1
S
1
T
1
E
1
E
2
P
1
P
2
Embossment
For cavity size,
see Note 1 Table 4
(10 pitches cumulative
tolerance on tape ±0.2 mm)
Table 6 – Embossed (Plastic) Carrier Tape Dimensions
Metricwillgovern
Constant Dimensions — Millimeters (Inches)
Tape Size D0
D
1
Minimum
Note 1
E1P0 P2
R Reference
Note 2
S
1
Minimum
Note 3
T
Maximum
T
1
Maximum
8 mm
1.5+0.10/−0.0
(0.059+0.004/−0.0)
1.0
(0.039)
1.75 ±0.10
(0.069 ±0.004) 4.0 ±0.10
(0.157 ±0.004) 2.0 ±0.05
(0.079 ±0.002)
25.0
(0.984)
0.600
(0.024) 0.600
(0.024) 0.100
(0.004)
12 mm 1.5
(0.059) 30
(1.181)
16 mm
Variable Dimensions — Millimeters (Inches)
Tape Size Pitch
B
1
Maximum
Note 4
E
2
Minimum
F P1
T
2
Maximum
W
Maximum
A0,B0 & K0
8 mm Single(4mm)
4.35
(0.171)
6.25
(0.246)
3.5 ±0.05
(0.138 ±0.002)
4.0 ±0.10
(0.157 ±0.004)
2.5
(0.098)
8.3
(0.327)
Note 512 mm Single(4mm)
and double (8 mm)
8.2
(0.323)
10.25
(0.404)
5.5 ±0.05
(0.217 ±0.002)
8.0 ±0.10
(0.315 ±0.004)
4.6
(0.181)
12.3
(0.484)
16 mm Triple (12 mm)
12.1
(0.476)
14.25
(0.561)
7.5 ±0.05
(0.138 ±0.002)
12.0 ±0.10
(0.157 ±0.004)
4.6
(0.181)
16.3
(0.642)
1. The embossment hole location shall be measured from the sprocket hole controlling the location of the embossment. Dimensions of the embossment
location and the hole location shall be applied independently of each other.
2. The tape with or without components shall pass around R without damage (see Figure 6.)
3. If S1 < 1.0 mm, there may not be enough area for a cover tape to be properly applied (see EIA Standard 481, paragraph 4.3, section b.)
4. B1 dimension is a reference dimension for tape feeder clearance only.
5. The cavity de ned by A0, B0 and K0 shall surround the component with suffi cient clearance that:
(a) the component does not protrude above the top surface of the carrier tape.
(b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been
removed.
(c) rotation of the component is limited to 20° maximum for 8 and 12 mm tapes and 10° maximum for 16 mm tapes (see Figure 3.)
(d) lateral movement of the component is restricted to 0.5 mm maximum for 8 and 12 mm wide tape and to 1.0 mm maximum for 16 mm tape
(see Figure 4.)
(e) for KPS product, A0 and B0 are measured on a plane 0.3 mm above the bottom of the pocket.
(f) see addendum in EIA Standard 481 for standards relating to more precise taping requirements.
13© KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 11/9/2018
Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)
Figure 2 – Punched (Paper) Carrier Tape Dimensions
User Direction of Unreeling
Top Cover Tape
T
Center Lines of Cavity
P1
ØDo Po E1
F
E2
W
G
A0
B0
Cavity Size,
See
Note 1, Table 7
Bottom Cover Tape
T1
T1
Bottom Cover Tape
(10 pitches cumulative
tolerance on tape ±0.2 mm)
Table 7 – Punched (Paper) Carrier Tape Dimensions
Metricwillgovern
Constant Dimensions — Millimeters (Inches)
Tape Size D
0
E
1
P
0
P
2
T
1
Maximum G Minimum
R Reference
Note 2
8 mm 1.5+0.10-0.0
(0.059+0.004-0.0) 1.75 ±0.10
(0.069 ±0.004) 4.0 ±0.10
(0.157 ±0.004) 2.0 ±0.05
(0.079 ±0.002)
0.10
(0.004)
maximum
0.75
(0.030) 25
(0.984)
Variable Dimensions — Millimeters (Inches)
Tape Size Pitch E2 Minimum F P1 T Maximum W Maximum A0 B0
8 mm Half (2 mm) 6.25
(0.246) 3.5 ±0.05
(0.138 ±0.002)
2.0 ±0.05
(0.079 ±0.002)
1.1
(0.098)
8.3
(0.327)
Note 1
8 mm Single(4mm)
4.0 ±0.10
(0.157 ±0.004)
8.3
(0.327)
1. The cavity de ned by A0, B0 and T shall surround the component with suffi cient clearance that:
a) the component does not protrude beyond either surface of the carrier tape.
b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been
removed.
c) rotation of the component is limited to 20° maximum (see Figure 3.)
d) lateral movement of the component is restricted to 0.5 mm maximum (see Figure 4.)
e) see addendum in EIA Standard 481 for standards relating to more precise taping requirements.
2. The tape with or without components shall pass around R without damage (see Figure 6.)
14© KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 11/9/2018
Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)
Packaging Information Performance Notes
1. Cover Tape Break Force:1.0kgminimum.
2. Cover Tape Peel Strength: Thetotalpeelstrengthofthecovertapefromthecarriertapeshallbe:
Tape Width Peel Strength
8 mm 0.1to1.0newton(10to100gf)
12 and 16 mm 0.1to1.3newton(10to130gf)
Thedirectionofthepullshallbeoppositethedirectionofthecarriertapetravel.Thepullangleofthecarriertapeshallbe
165°to180°fromtheplaneofthecarriertape.Duringpeeling,thecarrierand/orcovertapeshallbepulledatavelocityof
300 ±10 mm/minute.
3. Labeling:Barcodelabeling(standardorcustom)shallbeonthesideofthereeloppositethesprocketholes.Refer to EIA
Standards 556 and 624.
Figure 3 – Maximum Component Rotation
Ao
Bo
°
T
°
s
Maximum Component Rotation
Top View
Maximum Component Rotation
Side View
Tape Maximum
Width (mm) Rotation (°
T)
8,12 20
16 – 200 10 Tape Maximum
Width (mm) Rotation ( °
S)
8,12 20
16 – 56 10
72 – 200 5
Typical Pocket Centerline
Typical Component Centerline
Figure 4 – Maximum Lateral Movement
0.5 mm maximum
0.5 mm maximum
8 mm & 12 mm Tape
1.0 mm maximum
1.0 mm maximum
16 mm Tape
Figure 5 – Bending Radius
RR
Bending
Radius
Embossed
Carrier
Punched
Carrier
15© KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 11/9/2018
Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)
Figure 6 – Reel Dimensions
AD(See Note)
Full Radius,
See Note
B(see Note)
Access Hole at
Slot Location
(Ø 40 mm minimum)
If present,
tape slot in core
for tape start:
2.5 mm minimum width x
10.0 mm minimum depth
W3(Includes
flange distortion
at outer edge)
W2(Measured at hub)
W1(Measured at hub)
C
(Arbor hole
diameter)
Note: Drive spokes optional; if used, dimensions B and D shall apply.
N
Table 8 – Reel Dimensions
Metricwillgovern
Constant Dimensions — Millimeters (Inches)
Tape Size A B Minimum CD Minimum
8 mm 178 ±0.20
(7.008 ±0.008)
or
330 ±0.20
(13.000 ±0.008)
1.5
(0.059) 13.0+0.5/−0.2
(0.521+0.02/−0.008) 20.2
(0.795)
12 mm
16 mm
Variable Dimensions — Millimeters (Inches)
Tape Size N Minimum W1 W2 Maximum W3
8 mm
50
(1.969)
8.4+1.5/−0.0
(0.331+0.059/−0.0)
14.4
(0.567)
Shallaccommodatetape
widthwithoutinterference
12 mm
12.4+2.0/−0.0
(0.488+0.078/−0.0)
18.4
(0.724)
16 mm
16.4+2.0/−0.0
(0.646+0.078/−0.0)
22.4
(0.882)
16© KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 11/9/2018
Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)
Figure 7 – Tape Leader & Trailer Dimensions
Trailer
160 mm minimum
Carrier Tape
END START
Round Sprocket Holes
Elongated Sprocket Holes
(32 mm tape and wider)
Top Cover Tape
Top Cover Tape
Punched Carrier
8 mm & 12 mm only
Embossed Carrier
Components
100 mm
minimum leader
400 mm minimum
Figure 8 – Maximum Camber
Carrier Tape
Round Sprocket Holes
1 mm maximum, either direction
Straight Edge
250 mm
Elongated Sprocket Holes
(32 mm & wider tapes)
17© KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 11/9/2018
Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade)
KEMET Electronics Corporation Sales Offi ces
Foracompletelistofourglobalsalesoffices,pleasevisitwww.kemet.com/sales.
Disclaimer
Allproductspecications,statements,informationanddata(collectively,the“Information”)inthisdatasheetaresubjecttochange.Thecustomerisresponsiblefor
checkingandverifyingtheextenttowhichtheInformationcontainedinthispublicationisapplicabletoanorderatthetimetheorderisplaced.AllInformationgiven
hereinisbelievedtobeaccurateandreliable,butitispresentedwithoutguarantee,warranty,orresponsibilityofanykind,expressedorimplied.
StatementsofsuitabilityforcertainapplicationsarebasedonKEMETElectronicsCorporation’s(“KEMET”)knowledgeoftypicaloperatingconditionsforsuch
applications,butarenotintendedtoconstitute–andKEMETspecicallydisclaims–anywarrantyconcerningsuitabilityforaspeciccustomerapplicationoruse.
TheInformationisintendedforuseonlybycustomerswhohavetherequisiteexperienceandcapabilitytodeterminethecorrectproductsfortheirapplication.Any
technicaladviceinferredfromthisInformationorotherwiseprovidedbyKEMETwithreferencetotheuseofKEMET’sproductsisgivengratis,andKEMETassumes
noobligationorliabilityfortheadvicegivenorresultsobtained.
AlthoughKEMETdesignsandmanufacturesitsproductstothemoststringentqualityandsafetystandards,giventhecurrentstateoftheart,isolatedcomponent
failuresmaystilloccur.Accordingly,customerapplicationswhichrequireahighdegreeofreliabilityorsafetyshouldemploysuitabledesignsorothersafeguards
(suchasinstallationofprotectivecircuitryorredundancies)inordertoensurethatthefailureofanelectricalcomponentdoesnotresultinariskofpersonalinjury
orpropertydamage.
Althoughallproduct–relatedwarnings,cautionsandnotesmustbeobserved,thecustomershouldnotassumethatallsafetymeasuresareindictedorthatother
measures may not be required.
KEMET is a registered trademark of KEMET Electronics Corporation.