STM32F730x8 Arm(R) Cortex(R)-M7 32b MCU+FPU, 462DMIPS, 64KB Flash /256+16+4KB RAM, USB OTG HS/FS, 18 TIMs, 3 ADCs, 21 com IF Datasheet - production data Features * Core: Arm(R) 32-bit Cortex(R)-M7 CPU with FPU, adaptive real-time accelerator (ART AcceleratorTM) and L1-cache: 8 Kbytes of data cache and 8 Kbytes of instruction cache, allowing 0-wait state execution from embedded Flash memory and external memories, frequency up to 216 MHz, MPU, 462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1) and DSP instructions. * Memories - 64 Kbytes of Flash memory with protection mechanisms (read and write protections, proprietary code readout protection (PCROP)) - 528 bytes of OTP memory - SRAM: 256 Kbytes (including 64 Kbytes of data TCM RAM for critical real-time data) + 16 Kbytes of instruction TCM RAM (for critical real-time routines) + 4 Kbytes of backup SRAM (available in the lowest power modes) - Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories * Dual mode Quad-SPI * Clock, reset and supply management - 1.7 V to 3.6 V application supply and I/Os - POR, PDR, PVD and BOR - Dedicated USB power - 4-to-26 MHz crystal oscillator - Internal 16 MHz factory-trimmed RC (1% accuracy) - 32 kHz oscillator for RTC with calibration - Internal 32 kHz RC with calibration * Low-power - Sleep, Stop and Standby modes June 2018 This is information on a product in full production. FBGA LQFP64 (10 x 10 mm) UFBGA176 (10 x 10 mm) LQFP100 (14 x 14 mm) LQFP144 (20 x 20 mm) - VBAT supply for RTC, 32x32 bit backup registers + 4 Kbytes of backup SRAM * 3x12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode * 2x12-bit D/A converters * Up to 18 timers: up to thirteen 16-bit (1x lowpower 16-bit timer available in Stop mode) and two 32-bit timers, each with up to 4 IC/OC/PWMs or pulse counter and quadrature (incremental) encoder inputs. All 15 timers running up to 216 MHz. 2x watchdogs, SysTick timer * General-purpose DMA: 16-stream DMA controller with FIFOs and burst support * Debug mode - SWD & JTAG interfaces - Cortex(R)-M7 Trace MacrocellTM * Up to 138 I/O ports with interrupt capability - Up to 136 fast I/Os up to 108 MHz - Up to 138 5 V-tolerant I/Os * Up to 21 communication interfaces - Up to 3x I2C interfaces (SMBus/PMBus) - Up to 4 USARTs/4 UARTs (27 Mbit/s, ISO7816 interface, LIN, IrDA, modem control) - Up to 5 SPIs (up to 54 Mbit/s), 3 with muxed simplex I2Ss for audio class accuracy via internal audio PLL or external clock - 2 x SAIs (serial audio interface) DS12536 Rev 1 1/201 www.st.com STM32F730x8 - 1 x CAN (2.0B active) - 2 x SDMMCs * Advanced connectivity - USB 2.0 full-speed device/host/OTG controller with on-chip PHY - USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and on-chip Hi-speed PHY or ULPI depending on the part number * AES: 128/256-bit key encryption hardware accelerator * True random number generator * CRC calculation unit * RTC: subsecond accuracy, hardware calendar * 96-bit unique ID Table 1. Device summary Reference STM32F730x8 2/201 Part number STM32F730R8, STM32F730V8, STM32F730Z8, STM32F730I8 DS12536 Rev 1 STM32F730x8 Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 2.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 STM32F730x8 LQFP144 packages: . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 Arm(R) Cortex(R)-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 22 3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.6 AXI-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.7 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.8 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.9 Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.10 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 26 3.11 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.12 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.13 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.14 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.15 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.16 3.15.1 Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.15.2 Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.16.1 Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.16.2 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.16.3 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 35 3.17 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 35 3.18 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.19 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.20 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DS12536 Rev 1 3/201 6 Contents STM32F730x8 3.20.1 Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.20.2 General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.20.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.20.4 Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.20.5 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.20.6 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.20.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.21 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.22 Universal synchronous/asynchronous receiver transmitters (USART) . . 42 3.23 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 43 3.24 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.25 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.26 Audio PLL (PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.27 SD/SDIO/MMC card host interface (SDMMC) . . . . . . . . . . . . . . . . . . . . . 44 3.28 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.29 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 45 3.30 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 45 3.31 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.32 Advanced encryption standard hardware accelerator (AES) . . . . . . . . . . 46 3.33 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.34 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.35 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.36 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.37 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.38 Embedded Trace MacrocellTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.1 4/201 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 DS12536 Rev 1 STM32F730x8 Contents 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 93 6.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 93 6.3.5 Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . 93 6.3.6 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.3.7 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.3.8 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6.3.9 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.3.10 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6.3.11 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.3.12 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 123 6.3.13 USB OTG HS PHY PLLs characteristics 6.3.14 USB OTG HS PHY regulator characteristics 6.3.15 USB HS PHY external resistor characteristics . . . . . . . . . . . . . . . . . . 126 6.3.16 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 6.3.17 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 6.3.18 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 129 6.3.19 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 6.3.20 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 6.3.21 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 6.3.22 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 6.3.23 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 6.3.24 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 6.3.25 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 6.3.26 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 6.3.27 Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 6.3.28 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 6.3.29 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 6.3.30 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 6.3.31 Quad-SPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 DS12536 Rev 1 . . . . . . . . . . . . . . . . . . . . . . 125 . . . . . . . . . . . . . . . . . . . 125 5/201 6 Contents STM32F730x8 6.3.32 7 8 SD/SDIO MMC card host interface (SDMMC) characteristics . . . . . . . 182 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 7.1 LQFP64 - 10 x 10 mm, low-profile quad flat package information . . . . . 185 7.2 LQFP100, 14 x 14 mm low-profile quad flat package information . . . . . 188 7.3 LQFP144, 20 x 20 mm low-profile quad flat package information . . . . . 191 7.4 UFBGA176+25, 10 x 10, 0.65 mm ultra thin-pitch ball grid array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 7.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 199 A.1 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 6/201 DS12536 Rev 1 STM32F730x8 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 STM32F730x8 features and peripheral counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 32 Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 35 Voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 STM32F730x8 pin and ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 FMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 STM32F730x8 alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 92 VCAP1/VCAP2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 VCAP1 operating conditions in the LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 93 Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 93 reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Over-drive switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Typical and maximum current consumption in Run mode, code with data processing running from ITCM RAM, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART ON except prefetch / L1-cache ON) or SRAM on AXI (L1-cache ON), regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory or SRAM on AXI (L1-cache disabled), regulator ON . . . . . . 98 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory on ITCM interface (ART disabled), regulator ON . . . . . . . . . 99 Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART ON except prefetch / L1-cache ON) or SRAM on AXI (L1-cache ON), regulator OFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . 101 Typical and maximum current consumption in Sleep mode, regulator OFF . . . . . . . . . . . 101 Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . 102 Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . 103 Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . 104 Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 USB OTG HS and USB OTG PHY HS current consumption . . . . . . . . . . . . . . . . . . . . . . 113 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 HSE 4-26 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 DS12536 Rev 1 7/201 9 List of tables Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. 8/201 STM32F730x8 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 PLLI2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 PLLISAI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 USB OTG HS PLL1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 USB OTG HS PLL2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 USB OTG HS PHY regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 USB HS PHY external resistor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 ADC static accuracy at fADC = 18 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 ADC static accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 ADC static accuracy at fADC = 36 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 ADC dynamic accuracy at fADC = 18 MHz - limited test conditions . . . . . . . . . . . . . . . . . 141 ADC dynamic accuracy at fADC = 36 MHz - limited test conditions . . . . . . . . . . . . . . . . . 141 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 USB OTG full speed startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 USB OTG full speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 USB OTG full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 USB OTG high speed DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 USB OTG high speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 USB FS PHY BCD electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 162 DS12536 Rev 1 STM32F730x8 Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. List of tables Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 162 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 163 Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 164 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 165 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 167 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 172 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 176 SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Quad-SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Quad-SPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V . . . . . . . . . . . . . 183 Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 184 LQFP64 - 10 x 10 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . . 185 LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . . 188 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 UFBGA176+25, 10 x 10 x 0.65 mm ultra thin fine-pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 195 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 199 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 DS12536 Rev 1 9/201 9 List of figures STM32F730x8 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. 10/201 Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Compatible board design for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Compatible board design for LQFP144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 STM32F730x8 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 STM32F730x8 AXI-AHB bus matrix architecture(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 VDDUSB connected to VDD power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 VDDUSB connected to external power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 30 PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 34 Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 34 STM32F730R8 LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 STM32F730V8 LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 STM32F730Z8 LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 STM32F730I8 UFBGA176 ballout (with OTG PHY HS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 STM32F730x8 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 STM32F730x8 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Typical VBAT current consumption (RTC ON/BKP SRAM OFF and LSE in low drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Typical VBAT current consumption (RTC ON/BKP SRAM OFF and LSE in medium low drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Typical VBAT current consumption (RTC ON/BKP SRAM OFF and LSE in medium high drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Typical VBAT current consumption (RTC ON/BKP SRAM OFF and LSE in high drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Typical VBAT current consumption (RTC ON/BKP SRAM OFF and LSE in high medium drive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 LSI deviation versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 143 DS12536 Rev 1 STM32F730x8 Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. List of figures Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 143 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 USB OTG full speed timings: definition of data signal rise and fall time . . . . . . . . . . . . . . 157 ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 161 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 163 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 164 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 166 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 172 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 175 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 176 SDRAM read access waveforms (CL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Quad-SPI timing diagram - DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 LQFP64 - 10 x 10 mm, low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . 185 LQFP64 - 10 x 10 mm, low-profile quad flat package recommended footprint . . . . . . . . 186 LQFP64 - 10 x 10 mm, low-profile quad flat package top view example . . . . . . . . . . . . . 187 LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 188 LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 191 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 LQFP144, 20 x 20mm, 144-pin low-profile quad flat package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 UFBGA176+25, 10 x 10 x 0.65 mm ultra thin fine-pitch ball grid array package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 UFBGA176+25, 10 x 10 mm x 0.65 mm, ultra fine-pitch ball grid array package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 UFBGA176+25, 10 x 10 x 0.6 mm ultra thin fine-pitch ball grid array package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 DS12536 Rev 1 11/201 11 Introduction 1 STM32F730x8 Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F730x8 microcontrollers. This document should be ready in conjunction with the STM32F72xxx and STM32F73xxx advanced Arm(R)-based 32-bit MCUs reference manual (RM0431). The reference manual is available from the STMicroelectronics website www.st.com. For information on the Arm(R)(a) Cortex(R)-M7 core, refer to the Cortex(R)-M7 technical reference manual available from the http://www.arm.com website. a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere. 12/201 DS12536 Rev 1 STM32F730x8 2 Description Description The STM32F730x8 devices are based on the high-performance Arm(R) Cortex(R)-M7 32-bit RISC core operating at up to 216 MHz frequency. The Cortex(R)-M7 core features a single floating point unit (SFPU) precision which supports Arm(R) single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances the application security. The STM32F730x8 devices incorporate high-speed embedded memories with a Flash memory of 64 Kbytes, 256 Kbytes of SRAM (including 64 Kbytes of data TCM RAM for critical real-time data), 16 Kbytes of instruction TCM RAM (for critical real-time routines), 4 Kbytes of backup SRAM available in the lowest power modes, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses, a 32-bit multiAHB bus matrix and a multi layer AXI interconnect supporting internal and external memories access. All the devices offer three 12-bit ADCs, two DACs, a low-power RTC, thirteen generalpurpose 16-bit timers including two PWM timers for motor control, two general-purpose 32bit timers, a true random number generator (RNG). They also feature standard and advanced communication interfaces. * * * * * * * Up to three I2Cs Five SPIs, three I2Ss in half duplex mode. To achieve the audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization. Four USARTs plus four UARTs An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the ULPI only for the LQFP64 and LQFP100 packages and with the integrated HS PHY for the LQFP144 and UFBGA176 packages) One CAN Two SAI serial audio interfaces Two SDMMC host interfaces Advanced peripherals include two SDMMC interfaces, a flexible memory control (FMC) interface, a Quad-SPI Flash memory interface. The STM32F730x8 devices operate in the -40 to +105 C temperature range from a 1.7 to 3.6 V power supply. Dedicated supply inputs for the USB (OTG_FS and OTG_HS) and the SDMMC2 (clock, command and 4-bit data) are available on all the packages except LQFP100 and LQFP64 for a greater power supply choice. The supply voltage can drop to 1.7 V with the use of an external power supply supervisor. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F730x8 devices offer devices in 4 packages ranging from 64 pins to 176 pins. The set of included peripherals changes with the device chosen. DS12536 Rev 1 13/201 49 Description STM32F730x8 These features make the STM32F730x8 microcontrollers suitable for a wide range of applications: * Motor drive and application control, * Medical equipment, * Industrial applications: PLC, inverters, circuit breakers, * Printers, and scanners, * Alarm systems, video intercom, and HVAC, * Home audio appliances, * Mobile applications, Internet of Things, * Wearable devices: smartwatches. The following table lists the peripherals available on each part number. 14/201 DS12536 Rev 1 STM32F730x8 Description Table 2. STM32F730x8 features and peripheral counts Peripherals STM32F730R8 STM32F730V8 Flash memory in Kbytes SRAM in Kbytes System 256(176+16+64) Instruction 16 Backup 4 Yes(1) No Quad-SPI Yes General-purpose 10(2) Advanced-control 2 Basic 2 Low-power No 1 Random number generator SPI / I2S Yes 3/3 (simplex)(3) 4/3 (simplex)(3) I2C USART/UART Communication interfaces 5/3 (simplex)(3) 3 4/2 4/4 USB OTG FS Yes USB OTG HS Yes USB OTG PHY HS controller (USBPHYC) No Yes CAN 1 SAI 2 SDMMC1 SDMMC2 Yes Yes(4)(5) No AES GPIOs Yes 50 82 112 12-bit ADC 16 24 12-bit DAC Number of channels Yes 2 216 MHz(6) Maximum CPU frequency 1.7 to 3.6 V(7) Operating voltage Operating temperatures 138 3 Number of channels Package STM32F730I8 64 FMC memory controller Timers STM32F730Z8 Ambient temperatures: -40 to +85 C /-40 to +105 C Junction temperature: -40 to + 125 C LQFP64 LQFP100 LQFP144 UFBGA176 1. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. DS12536 Rev 1 15/201 49 Description STM32F730x8 2. On the STM32F730x8 device packages, except the 176-pin ones, the TIM12 is not available, so there are 9 generalpurpose timers. 3. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. 4. The SDMMC2 supports a dedicated power rail for clock, command and data 0..4 lines, feature available starting from 144 pin package. 5. The SDMMC2 is not available on the STM32F730Vx devices. 6. 216 MHz maximum frequency for - 40C to + 85C ambient temperature range (200 MHz maximum frequency for - 40C to + 105C ambient temperature range). 7. VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 3.15.2: Internal reset OFF). 16/201 DS12536 Rev 1 STM32F730x8 Full compatibility throughout the family The STM32F730x8 devices with LQFP64 and LQFP100 packages are fully pin-to-pin, compatible with the STM32F7x5xx, STM32F7x6xx, STM32F7x7xx devices. The STM32F730x8 devices with LQFP64 and LQFP100 packages are fully pin-to-pin, compatible with the STM32F4xxxx devices, allowing the user to try different peripherals, and reaching higher performances (higher frequency) for a greater degree of freedom during the development cycle. Figure 1 and Figure 2 give compatible board designs between the STM32F730x8, with LQFP64 and LQFP100 packages, and STM32F4xx families. Figure 1. Compatible board design for LQFP100 package PC3 VDD VSSA VREF+ VDDA PA0-WKUP PA1 PA2 STM32F427xx / STM32F437xx STM32F429xx / STM32F439xx STM32F415xx / STM32F417xx STM32F405xx / STM32F407xx 18 19 20 21 22 23 24 25 VDD PB11 VCAP1 PB10 PE15 PE14 PE12 PE13 PE11 PE9 PE10 PE7 PE8 PB1 PB2 PC5 PB0 PC4 PA7 PA5 PA6 PA4 VDD PA3 18 19 20 21 22 23 24 25 STM32F73xxx Pins 19 to 49 are not compatible VDD VSS VCAP1 PB11 PB10 PE15 PE14 PE12 PE13 PE11 PE10 PE9 PE8 PE7 PB2 PB1 PB0 PC5 PC4 PA7 PA6 PA4 PA5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDD PC3 VSSA VREF+ VDDA PA0-WKUP PA1 PA2 PA3 VSS 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VSS 2.1 Description MSv41002V2 DS12536 Rev 1 17/201 49 Description STM32F730x8 PC12 PC11 PC10 PA15 PA14 PC12 PC11 PC10 PA15 PA14 Figure 2. Compatible board design for LQFP64 package VDD VCAP_2 PA13 PA12 PA11 PA10 PA9 VSS PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 53 52 51 50 49 48 47 46 45 44 43 42 41 STM32F4x1 40 39 38 37 PB11 not available anymore 36 Replaced by V CAP_1 35 34 33 28 29 30 31 32 VDD VDD VSS PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 VDD VSS PB2 PB10 VCAP_1 VSS VDD PB2 PB10 PB11 VCAP_1 VDD 53 52 51 50 49 48 47 46 45 44 43 42 41 STM32F405/ 40 STM32F415 line 39 38 37 36 35 34 33 28 29 30 31 32 V CAP increased to 4.7 f ESR 1 ohm or below 1 ohm VDD VSS 57 56 55 54 53 52 51 50 49 48 VDD 47 VSS 46 PA13 45 44 PA12 PA11 PA10 PA9 41 40 PA8 PC9 39 PC8 38 PC7 37 36 PC6 PB15 35 PB14 34 PB13 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PB12 VSS VCAP_1 PB11 PB10 PB1 PB2 PB0 PC4 PA7 PA5 PA6 PA4 VSS VDD PA3 PC5 not available anymore Replaced by VCAP_1 VDD VSS VDD 43 42 STM32F730x8 VDD PA14 PC 11 PC10 PA15 PC12 PB3 PD2 PB4 PB5 VSS Not compatible STM32F732xx pins with either STM32F4x1 or STM32F405/F415 or both VCAP increased to 4.7 f ESR between 0.1 ohm and 0.2 ohm VSS VDD MSv50786V1 18/201 DS12536 Rev 1 STM32F730x8 STM32F730x8 LQFP144 packages: Figure 3. Compatible board design for LQFP144 package STM32F4xxx STM32F7x5xx, STM32F7x6xx, STM32F7x7xx 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 PG8 PG7 PG6 PG5 PG4 PG3 PG2 PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 STM32F730x8 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 PG8 PG5 PG4 PG3 PG2 PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 VDD12OTGHS OTG_HS_REXT PB13 PB12 72 VDD 72 VDD 2.2 Description PG6, PG7 removed on the STM32F730x8 Not compatible pins MSv50787V1 Figure 4 shows the general block diagram of the device family. DS12536 Rev 1 19/201 49 Description STM32F730x8 Figure 4. STM32F730x8 block diagram FS PHY PLL1 PLL2 BGR USB OTG HS PLL DMA/ FIFO LDO FIFO RNG SRAM1 176KB SRAM2 16KB Quad-SPI CLK, CS,D[7:0] @VDDA AHB1 216 MHz POR reset GPIO PORT A PB[15:0] GPIO PORT B PC[15:0] GPIO PORT C PD[15:0] GPIO PORT D PE[15:0] GPIO PORT E PF[15:0] GPIO PORT F PG[15:0] GPIO PORT G PH[15:0] GPIO PORT H Int RC HS RCC Reset M & control GT 1 channel as AF VBAT = 1.8 to 3.6 V LS FCLK HCLK APBP2CLK APBP1CLK AHB2PCLK AHB1PCLK LS XTAL 32 kHz OSC32_IN OSC32_OUT RTC AWU Backup register RTC_TS RTC_TAMPx RTC_OUT 4 KB BKPRAM FIFO FIFO EXT IT. WKUP SDMMC1 SDMMC2 GPDMA1 GPDMA2 TIM1 / PWM 16b TIM8 / PWM 16b TIM9 16b TIM10 16b TIM11 16b smcard USART1 irDA smcard USART6 irDA MOSI, MISO, SCK, NSS as AF SPI1/I2S1 MOSI, MISO, SCK, NSS as AF SPI4 MOSI, MISO, SCK, NSS as AF SPI5 SD, SCK, FS, MCLK as AF SAI1 SD, SCK, FS, MCLK as AF SAI2 SCL, SDA, INT, ID, VBUS OSC_IN OSC_OUT @VSW GPIO PORT I RX, TX, SCK, CTS, RTS as AF RX, TX, SCK, CTS, RTS as AF ULPI:CK, D[7:0], DIR, STP, NXT @VDD33 OTG HS PHY CONTROLLER AHB/ APB1 AHB/APB2 TIM2 32b 4 channels, ETR as AF TIM3 16b 4 channels, ETR as AF TIM4 16b 4 channels, ETR as AF TIM5 32b 4 channels TIM12 16b 2 channels as AF TIM13 16b 1 channel as AF 16b 1 channel as AF TIM14 smcard irDA RX, TX, SCK CTS, RTS as AF smcard USART3 irDA UART4 RX, TX, SCK CTS, RTS as AF RX, TX as AF UART5 RX, TX as AF UART7 RX, TX as AF USART2 WWDG LPTIM1 16b TIM6 16b TIM7 16b SPI2/I2S2 SPI3/I2S3 I2C1/SMBUS I2C2/SMBUS SYSCFG RX, TX as AF UART8 I2C3/SMBUS Digital filter 1 channel as AF WKUP[4:0] VDDMMC33 = 3.0 to 3.6V VDDUSB33 = 3.0 to 3.6 V VDD = 1.8 to 3.6 V VSS VCAP1 WDG32K APB1 0M 3Hz APB1 54 MHz (max) 2 channels as AF VOLT. REG 3.3V TO 1.2V Standby interface APB2 108 MHz (max) 4 compl. chan. (TIM1_CH1[1:4]N), 4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF 4 compl. chan.(TIM8_CH1[1:4]N), 4 chan. (TIM8_CH1[1:4], ETR, BKIN as AF BBgen + POWER MNGT XTAL OSC 4- 16MHz FIFO FIFO D[7:0] CMD, CK as AF VDDA, VSSA NRESET @VDD33 VDD12 CRC 168 AF D[7:0] CMD, CK as AF BOR PVD PLL1+PLL2+PLL3 PI[11:0] SUPPLY SUPERVISION POR/PDR @VDDA RC LS PA[15:0] DP DM SCL, SDA, INT, ID, VBUS CLK, NE [3:0], A[23:0], D[31:0], NOEN, NWEN, NBL[3:0], SDCLKE[1:0] SDNE[1:0], SDNWE, NL NRAS, NCAS, NADV NWAIT, INTN EXT MEM CTL (FMC) SRAM, SDRAM, NOR-Flash, NAND-Flash, SDRAM 8 Streams FIFO GP-DMA1 USB OTG FS AHB2 216 MHz 8 Streams FIFO GP-DMA2 AES128 FLASH 64KB AHBP AHBS LDO DP, DM ULPI:CK, D[7:0], DIR, STP, NXT SCL/SDA, INT, ID, VBUS ACCEL/ CACHE PHY D-Cache 8KB USB HS PHY ITCM RAM 16KB AXIM I-Cache 8KB 216MHz DTCM RAM 64KB FIFO Arm CPU Cortex-M7 AHB BUS-MATRIX 11S8M 8S7M AHB bus-matrix TRACECK TRACED[3:0] MPU FPU NVIC DTCM ICTM PWRCTRL JTAG & SW ETM AHB2AXI JTRST, JTDI, JTCK/SWCLK JTDO/SWD, JTDO MOSI, MISO, SCK NSS as AF MOSI, MISO, SCK NSS as AF SCL, SDA, SMBAL as AF SCL, SDA, SMBAL as AF SCL, SDA, SMBAL as AF VDDREF_ADC 8 analog inputs common to the 3 ADCs 8 analog inputs common to the ADC1 & 2 8 analog inputs for ADC3 U STemperature AR T 2 M B sensor ps ADC1 ADC2 ADC3 bxCAN1 FIFO @VDDA TX, RX @VDDA IF DAC1 ITF DAC2 DAC1 as AF DAC2 as AF MSv50788V1 1. The timers connected to APB2 are clocked from TIMxCLK up to 216 MHz, while the timers connected to APB1 are clocked from TIMxCLK either up to 108 MHz or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register. 20/201 DS12536 Rev 1 STM32F730x8 Functional overview 3 Functional overview 3.1 Arm(R) Cortex(R)-M7 with FPU The Arm(R) Cortex(R)-M7 with FPU processor is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and low interrupt latency. The Cortex(R)-M7 processor is a highly efficient high-performance featuring: - Six-stage dual-issue pipeline - Dynamic branch prediction - Harvard caches (8 Kbytes of I-cache and 8 Kbytes of D-cache) - 64-bit AXI4 interface - 64-bit ITCM interface - 2x32-bit DTCM interfaces The processor supports the following memory interfaces: * Tightly Coupled Memory (TCM) interface. * Harvard instruction and data caches and AXI master (AXIM) interface. * Dedicated low-latency AHB-Lite peripheral (AHBP) interface. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. It supports single precision FPU (floating point unit), speeds up software development by using metalanguage development tools, while avoiding saturation. Figure 4 shows the general block diagram of the STM32F730x8 family. Note: Cortex(R)-M7 with FPU core is binary compatible with the Cortex(R)-M4 core. 3.2 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. DS12536 Rev 1 21/201 49 Functional overview 3.3 STM32F730x8 Embedded Flash memory The STM32F730x8 devices embed a Flash memory of 64 Kbytes available for storing programs and data. The flexible protections can be configured thanks to option bytes: * 3.4 Readout protection (RDP) to protect the whole memory. Three levels are available: - Level 0: no readout protection - Level 1: No access (read, erase, program) to the Flash memory or backup SRAM can be performed while the debug feature is connected or while booting from RAM or system memory bootloader - Level 2: debug/chip read protection disabled. * Write protection (WRP): the protected area is protected against erasing and programming. * Proprietary code readout protection (PCROP): Flash memory user sectors (0 to 1) can be protected against D-bus read accesses by using the proprietary readout protection (PCROP). The protected area is execute-only. CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 3.5 Embedded SRAM All the devices feature: * * System SRAM up to 256 Kbytes: - SRAM1 on AHB bus Matrix: 176 Kbytes - SRAM2 on AHB bus Matrix: 16 Kbytes - DTCM-RAM on TCM interface (Tighly Coupled Memory interface): 64 Kbytes for critical real-time data. Instruction RAM (ITCM-RAM) 16 Kbytes: - It is mapped on TCM interface and reserved only for CPU Execution/Instruction useful for critical real-time routines. The Data TCM RAM is accessible by the GP-DMAs and peripheral DMAs through the specific AHB slave of the CPU.The instruction TCM RAM is reserved only for CPU. It is accessed at CPU clock speed with 0 wait states. * 4 Kbytes of backup SRAM This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode. 22/201 DS12536 Rev 1 STM32F730x8 3.6 Functional overview AXI-AHB bus matrix The STM32F730x8 system architecture is based on 2 sub-systems: * * An AXI to multi AHB bridge converting AXI4 protocol to AHB-Lite protocol: - 3x AXI to 32-bit AHB bridges connected to AHB bus matrix - 1x AXI to 64-bit AHB bridge connected to the embedded Flash memory A multi-AHB Bus-Matrix - The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, USB HS) and the slaves (Flash memory, RAM, FMC, Quad-SPI, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. AHBS USB_HS_M USB OTG HS DMA_P2 GP DMA2 DMA_MEM2 AHBP 8KB I/D Cache AXIM GP DMA1 DMA_PI Arm Cortex-M7 DMA_MEM1 ITCM DTCM Figure 5. STM32F730x8 AXI-AHB bus matrix architecture(1) DTCM RAM 64KB ITCM RAM 16KB AXI to multi-AHB ART ITCM 64-bit AHB FLASH 64KB 64-bit BuS Matrix SRAM1 176KB SRAM2 16KB AHB Periph1 AHB periph2 FMC external MemCtl APB1 APB2 Quad-SPI 32-bit Bus Matrix - S MSv50789V1 1. The above figure has large wires for 64-bits bus and thin wires for 32-bits bus. DS12536 Rev 1 23/201 49 Functional overview 3.7 STM32F730x8 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support a circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. The configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: 24/201 * SPI and I2S * I2C * USART * General-purpose, basic and advanced-control timers TIMx * DAC * SDMMC * ADC * SAI * Quad-SPI DS12536 Rev 1 STM32F730x8 3.8 Functional overview Flexible memory controller (FMC) The Flexible memory controller (FMC) includes three memory controllers: * The NOR/PSRAM memory controller * The NAND/memory controller * The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller The main features of the FMC controller are the following: * Interface with static-memory mapped devices including: - Static random access memory (SRAM) - NOR Flash memory/OneNAND Flash memory - PSRAM (4 memory banks) - NAND Flash memory with ECC hardware to check up to 8 Kbytes of data * Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories * 8-, 16-, 32-bit data bus width * Independent Chip Select control for each memory bank * Independent configuration for each memory bank * Write FIFO * Read FIFO for SDRAM controller * The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is HCLK/2 LCD parallel interface The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 3.9 Quad-SPI memory interface (QUADSPI) All the devices embed a Quad-SPI memory interface, which is a specialized communication interface targetting Single, Dual or Quad-SPI Flash memories. It can work in: * Direct mode through registers * External Flash status register polling mode * Memory mapped mode. Up to 256 Mbytes of external Flash are memory mapped, supporting 8, 16 and 32-bit access. The code execution is supported. The opcode and the frame format are fully programmable. The communication can be either in Single Data Rate or Dual Data Rate. DS12536 Rev 1 25/201 49 Functional overview 3.10 STM32F730x8 Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 110 maskable interrupt channels plus the 16 interrupt lines of the Cortex(R)M7 with FPU core. * Closely coupled NVIC gives low-latency interrupt processing * Interrupt entry vector table address passed directly to the core * Allows early processing of interrupts * Processing of late arriving, higher-priority interrupts * Support tail chaining * Processor state automatically saved * Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with a minimum interrupt latency. 3.11 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 24 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 138 GPIOs can be connected to the 16 external interrupt lines. 3.12 Clocks and startup On reset the 16 MHz internal HSI RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 216 MHz. Similarly, a full interrupt management of the PLL clock entry is available when necessary (for example if an indirectly used external oscillator fails). Several prescalers allow the configuration of the two AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB buses is 216 MHz while the maximum frequency of the high-speed APB domains is 108 MHz. The maximum allowed frequency of the low-speed APB domain is 54 MHz. The devices embed two dedicated PLLs (PLLI2S and PLLSAI) which allow to achieve audio class performance. In this case, the I2S and SAI master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz. The STM32F730x8 devices embed two PLLs inside the PHY HS controller: PLL1 and PLL2. The PLL1 allows to output 60 MHz used as an input for PLL2 which itself allows to generate the 480 Mbps in the USB OTG High Speed mode. The PLL1 has as input HSE clock. 26/201 DS12536 Rev 1 STM32F730x8 3.13 Functional overview Boot modes At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF which includes: * All Flash address space mapped on ITCM or AXIM interface * All RAM address space: ITCM, DTCM RAMs and SRAMs mapped on AXIM interface * The System memory bootloader The boot loader is located in system memory. It is used to reprogram the Flash memory through a serial interface. 3.14 Note: Power supply schemes * VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through VDD pins. * VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively. * VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. The VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 3.15.2: Internal reset OFF). Refer to Table 3: Voltage regulator configuration mode versus device operating mode to identify the packages supporting this option. * * The VDDSDMMC can be connected either to VDD or an external independent power supply (1.8 to 3.6V) for the SDMMC2 pins (clock, command, and 4-bit data). For example, when the device is powered at 1.8V, an independent power supply 2.7V can be connected to VDDSDMMC.When the VDDSDMMC is connected to a separated power supply, it is independent from VDD or VDDA but it must be the last supply to be provided and the first to disappear. The following conditions VDDSDMMC must be respected: - During the power-on phase (VDD < VDD_MIN), VDDSDMMC should be always lower than VDD - During the power-down phase (VDD < VDD_MIN), VDDSDMMC should be always lower than VDD - The VDDSDMMC rising and falling time rate specifications must be respected - In the operating mode phase, VDDSDMMC could be lower or higher than VDD: All associated GPIOs powered by VDDSDMMC are operating between VDDSDMMC_MIN and VDDSDMMC_MAX. The VDDUSB can be connected either to VDD or an external independent power supply (3.0 to 3.6V) for USB transceivers (refer to Figure 6 and Figure 7). For example, when the device is powered at 1.8V, an independent power supply 3.3V can be connected to the VDDUSB. When the VDDUSB is connected to a separated power supply, it is independent from VDD or VDDA but it must be the last supply to be provided and the first to disappear. The following conditions VDDUSB must be respected: - During the power-on phase (VDD < VDD_MIN), VDDUSB should be always lower than VDD - During the power-down phase (VDD < VDD_MIN), VDDUSB should be always lower than VDD DS12536 Rev 1 27/201 49 Functional overview STM32F730x8 - The VDDUSB rising and falling time rate specifications must be respected - In the operating mode phase, VDDUSB could be lower or higher than VDD: - If the USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by VDDUSB are operating between VDDUSB_MIN and VDDUSB_MAX. - The VDDUSB supplies both USB transceiver (USB OTG_HS and USB OTG_FS). If only one USB transceiver is used in the application, the GPIOs associated to the other USB transceiver are still supplied by VDDUSB. - If the USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered by VDDUSB are operating between VDD_MIN and VDD_MAX. Figure 6. VDDUSB connected to VDD power supply VDD VDD_MAX VDD= VDDA = VDDUSB VDD_MIN Power-on Operating mode Power-down time MS37591V1 Figure 7. VDDUSB connected to external power supply VDDUSB_MAX USB functional area VDDUSB VDDUSB_MIN USB non functional area VDD = VDDA Power-on Operating mode USB non functional area VDD_MIN Power-down time MS37590V1 28/201 DS12536 Rev 1 STM32F730x8 Functional overview On the STM32F7x3xx devices, the USB OTG HS sub-system uses an additional power supply pin: * The VDD12OTGHS pin is the output of PHY HS regulator (1.2V). An external capacitor of 2.2 F must be connected on the VDD12OTGHS pin. 3.15 Power supply supervisor 3.15.1 Internal reset ON On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On the other packages, the power supply supervisor is always enabled. The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default BOR thresholds, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit. The device also features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.15.2 Internal reset OFF This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin. An external power supply supervisor should monitor VDD and NRST and should maintain the device in reset mode as long as VDD is below a specified threshold. PDR_ON should be connected to VSS. Refer to Figure 8: Power supply supervisor interconnection with internal reset OFF. DS12536 Rev 1 29/201 49 Functional overview STM32F730x8 Figure 8. Power supply supervisor interconnection with internal reset OFF VDD External VDD power supply supervisor Ext. reset controller active when VDD < 1.7 V NRST VDD Application reset signal PDR_ON VSS MS31383V4 The VDD specified threshold, below which the device must be maintained under reset, is 1.7 V (see Figure 9). A comprehensive set of power-saving mode allows to design low-power applications. When the internal reset is OFF, the following integrated features are no more supported: * The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled * The brownout reset (BOR) circuitry must be disabled * The embedded programmable voltage detector (PVD) is disabled * VBAT functionality is no more available and VBAT pin should be connected to VDD. All packages, except for the LQFP100, allow to disable the internal reset through the PDR_ON signal when connected to VSS. Figure 9. PDR_ON control with internal reset OFF V DD PDR = 1.7 V time Reset by other source than power supply supervisor NRST PDR_ON PDR_ON time MS19009V7 30/201 DS12536 Rev 1 STM32F730x8 3.16 Functional overview Voltage regulator The regulator has four operating modes: * * 3.16.1 Regulator ON - Main regulator mode (MR) - Low power regulator (LPR) - Power-down Regulator OFF Regulator ON On packages embedding the BYPASS_REG pin, the regulator is enabled by holding BYPASS_REG low. On all other packages, the regulator is always enabled. There are three power modes configured by software when the regulator is ON: * MR mode used in Run/sleep modes or in Stop modes - In Run/Sleep modes The MR mode is used either in the normal mode (default mode) or the over-drive mode (enabled by software). A different voltage scaling is provided to reach the best compromise between maximum frequency and dynamic power consumption. The over-drive mode allows operating at a higher frequency than the normal mode for a given voltage scaling. - In Stop modes The MR can be configured in two ways during stop mode: MR operates in normal mode (default mode of MR in stop mode) MR operates in under-drive mode (reduced leakage mode). * LPR is used in the Stop modes: The LP regulator mode is configured by software when entering Stop mode. Like the MR mode, the LPR can be configured in two ways during stop mode: * - LPR operates in normal mode (default mode when LPR is ON) - LPR operates in under-drive mode (reduced leakage mode). Power-down is used in Standby mode. The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost. Refer to Table 3 for a summary of voltage regulator modes versus device operating modes. The VCAP_1 and VCAP_2 pins must be connected to 2*2.2 F, ESR < 2 (or 1*4.7 F, ESR between 0.1 and 0.2 if only the VCAP_1 pin is provided (on LQFP64 package)). All the packages have the regulator ON feature. DS12536 Rev 1 31/201 49 Functional overview STM32F730x8 Table 3. Voltage regulator configuration mode versus device operating mode(1) Voltage regulator configuration Run mode Sleep mode Stop mode Standby mode Normal mode MR MR MR or LPR - Over-drive mode(2) MR MR - - Under-drive mode - - MR or LPR - Power-down mode - - - Yes 1. `-' means that the corresponding configuration is not available. 2. The over-drive mode is not available when VDD = 1.7 to 2.1 V. 3.16.2 Regulator OFF This feature is available only on packages featuring the BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply externally a V12 voltage source through VCAP_1 and VCAP_2 pins. Since the internal voltage scaling is not managed internally, the external voltage value must be aligned with the targeted maximum frequency.The two 2.2 F ceramic capacitors should be replaced by two 100 nF decoupling capacitors. When the regulator is OFF, there is no more internal monitoring on V12. An external power supply supervisor should be used to monitor the V12 of the logic power domain. The PA0 pin should be used for this purpose, and act as power-on reset on V12 power domain. In regulator OFF mode, the following features are no more supported: 32/201 * PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power domain which is not reset by the NRST pin. * As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required. * The over-drive and under-drive modes are not available. * The Standby mode is not available. DS12536 Rev 1 STM32F730x8 Functional overview Figure 10. Regulator OFF V12 External VCAP_1/2 power Application reset supply supervisor Ext. reset controller active signal (optional) when VCAP_1/2 < Min V12 VDD PA0 VDD NRST BYPASS_REG V12 VCAP_1 VCAP_2 ai18498V3 The following conditions must be respected: * VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains. * If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for VDD to reach 1.7 V, then PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V (see Figure 11). * Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower than the time for VDD to reach 1.7 V, then PA0 could be asserted low externally (see Figure 12). * If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V, then a reset must be asserted on PA0 pin. Note: The minimum value of V12 depends on the maximum frequency targeted in the application. Note: On the LQFP64 pin package, the VCAP_2 is not available. DS12536 Rev 1 33/201 49 Functional overview STM32F730x8 Figure 11. Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization VDD PDR = 1.7 V or 1.8 V V12 Min V12 VCAP_1/VCAP_2 time NRST time ai18491f 1. This figure is valid whatever the internal reset mode (ON or OFF). Figure 12. Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization VDD PDR = 1.7 V or 1.8 V VCAP_1,VCAP_2 V12 Min V12 time NRST PA0 asserted externally time ai18492e 1. This figure is valid whatever the internal reset mode (ON or OFF). 34/201 DS12536 Rev 1 STM32F730x8 3.16.3 Functional overview Regulator ON/OFF and internal reset ON/OFF availability Table 4. Regulator ON/OFF and internal reset ON/OFF availability Package LQFP64, LQFP100 Regulator ON Regulator OFF Internal reset ON Internal reset OFF Yes No No Yes LQFP144 UFBGA176 3.17 Yes Yes Yes Yes PDR_ON set to VDD PDR_ON set to VSS BYPASS_REG set BYPASS_REG set to VDD to VSS Real-time clock (RTC), backup SRAM and backup registers The RTC is an independent BCD timer/counter. It supports the following features: * Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. * Automatic correction for 28, 29 (leap year), 30, and 31 days of the month. * Two programmable alarms. * On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock. * Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. * Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy. * Three anti-tamper detection pins with programmable filter. * Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to VBAT mode. * 17-bit auto-reload wakeup timer (WUT) for periodic events with programmable resolution and period. The RTC and the 32 backup registers are supplied through a switch that takes power either from the VDD supply when present or from the VBAT pin. The backup registers are 32-bit registers used to store 128 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, or when the device wakes up from Standby mode. The RTC clock sources can be: * A 32.768 kHz external crystal (LSE) * An external resonator or oscillator(LSE) * The internal low power RC oscillator (LSI, with typical frequency of 32 kHz) * The high-speed external clock (HSE) divided by 32 The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in all low-power modes. DS12536 Rev 1 35/201 49 Functional overview STM32F730x8 All the RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt and wakeup the device from the low-power modes. 3.18 Low-power modes The devices support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: * Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. * Stop mode The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can be put either in main regulator mode (MR) or in low-power mode (LPR). Both modes can be configured as follows (see Table 5: Voltage regulator modes in stop mode): - Normal mode (default mode when MR or LPR is enabled) - Under-drive mode. The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB OTG FS/HS wakeup and the LPTIM1 asynchronous interrupt). Table 5. Voltage regulator modes in stop mode * Voltage regulator configuration Main regulator (MR) Low-power regulator (LPR) Normal mode MR ON LPR ON Under-drive mode MR in under-drive mode LPR in under-drive mode Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.2 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising or falling edge on one of the 6 WKUP pins (PA0, PA2, PC1, PC13, PI8, PI11), or an RTC alarm / wakeup / tamper /time stamp event occurs. The Standby mode is not supported when the embedded voltage regulator is bypassed and the 1.2 V domain is controlled by an external power. 36/201 DS12536 Rev 1 STM32F730x8 3.19 Functional overview VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when no external battery and an external supercapacitor are present. The VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC, the backup registers and the backup SRAM. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. When the PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is no more available and the VBAT pin should be connected to VDD. 3.20 Timers and watchdogs The devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. All timer counters can be frozen in debug mode. Table 6 compares the features of the advanced-control, general-purpose and basic timers. DS12536 Rev 1 37/201 49 Functional overview STM32F730x8 Table 6. Timer feature comparison Max Max DMA Capture/ Complem interface timer request compare entary clock clock generation channels output (MHz) (MHz)(1) Timer type Timer Counter Counter Prescaler resolution type factor Advanced -control TIM1, TIM8 16-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 Yes 108 216 32-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 No 54 108/216 16-bit Any Up, integer Down, between 1 Up/down and 65536 Yes 4 No 54 108/216 16-bit Up Any integer between 1 and 65536 No 2 No 108 216 Up Any integer between 1 and 65536 No 1 No 108 216 Up Any integer between 1 and 65536 No 2 No 54 108/216 Up Any integer between 1 and 65536 No 1 No 54 108/216 Up Any integer between 1 and 65536 Yes 0 No 54 108/216 TIM2, TIM5 TIM3, TIM4 TIM9 General purpose TIM10, TIM11 TIM12 TIM13, TIM14 Basic TIM6, TIM7 16-bit 16-bit 16-bit 16-bit 1. The maximum timer clock is either 108 or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register. 38/201 DS12536 Rev 1 STM32F730x8 3.20.1 Functional overview Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. Their 4 independent channels can be used for: * Input capture * Output compare * PWM generation (edge- or center-aligned modes) * One-pulse mode output If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%). The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. The TIM1 and TIM8 support independent DMA request generation. 3.20.2 General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32F730x8 devices (see Table 6 for differences). * TIM2, TIM3, TIM4, TIM5 The STM32F730x8 include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages. The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the Timer Link feature for synchronization or event chaining. Any of these general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. * TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9 and TIM12 have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases. 3.20.3 Basic timers TIM6 and TIM7 These timers are mainly used for the DAC trigger and waveform generation. They can also be used as a generic 16-bit time base. The TIM6 and TIM7 support independent DMA request generation. DS12536 Rev 1 39/201 49 Functional overview 3.20.4 STM32F730x8 Low-power timer (LPTIM1) The low-power timer has an independent clock and is running also in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode. This low-power timer supports the following features: 3.20.5 * 16-bit up counter with 16-bit autoreload register * 16-bit compare register * Configurable output: pulse, PWM * Continuous / one-shot mode * Selectable software / hardware input trigger * Selectable clock source: * Internal clock source: LSE, LSI, HSI or APB clock * External clock source over LPTIM input (working even with no internal clock source running, used by the Pulse Counter Application) * Programmable digital glitch filter * Encoder mode Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. 3.20.6 Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.20.7 SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: 40/201 * A 24-bit downcounter * Autoreload capability * Maskable system interrupt generation when the counter reaches 0 * Programmable clock source DS12536 Rev 1 STM32F730x8 3.21 Functional overview Inter-integrated circuit interface (I2C) The devices embed 3 I2Cs. Refer to Table 7: I2C implementation for the features implementation. The I2C bus interface handles communications between the microcontroller and the serial I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing. The I2C peripheral supports: * * I2C-bus specification and user manual rev. 5 compatibility: - Slave and master modes, multimaster capability - Standard-mode (Sm), with a bitrate up to 100 kbit/s - Fast-mode (Fm), with a bitrate up to 400 kbit/s - Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os - 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses - Programmable setup and hold times - Optional clock stretching System Management Bus (SMBus) specification rev 2.0 compatibility: - Hardware PEC (Packet Error Checking) generation and verification with ACK control - Address resolution protocol (ARP) support - SMBus alert * Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility * Independent clock: a choice of independent clock sources allowing the I2C communication speed to be independent from the PCLK reprogramming. * Programmable analog and digital noise filters * 1-byte buffer with DMA capability Table 7. I2C implementation I2C features(1) I2C1 I2C2 I2C3 Standard-mode (up to 100 kbit/s) X X X Fast-mode (up to 400 kbit/s) X X X Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X X X Programmable analog and digital noise filters X X X SMBus/PMBus hardware support X X X Independent clock X X X 1. X: supported. DS12536 Rev 1 41/201 49 Functional overview 3.22 STM32F730x8 Universal synchronous/asynchronous receiver transmitters (USART) The devices embed USARTs. Refer to Table 8: USART implementation for the features implementation. The universal synchronous asynchronous receiver transmitter (USART) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The USART peripheral supports: * Full-duplex asynchronous communications * Configurable oversampling method by 16 or 8 to give flexibility between speed and clock tolerance * Dual clock domain allowing convenient baud rate programming independent from the PCLK reprogramming * A common programmable transmit and receive baud rate of up to 27 Mbit/s when USART clock source is system clock frequency (max is 216 MHz) and oversampling by 8 is used. * Auto baud rate detection * Programmable data word length (7 or 8 or 9 bits) word length * Programmable data order with MSB-first or LSB-first shifting * Progarmmable parity (odd, even, no parity) * Configurable stop bits (1 or 1.5 or 2 stop bits) * Synchronous mode and clock output for synchronous communications * Single-wire half-duplex communications * Separate signal polarity control for transmission and reception * Swappable Tx/Rx pin configuration * Hardware flow control for modem and RS-485 transceiver * Multiprocessor communications * LIN master synchronous break send capability and LIN slave break detection capability * IrDA SIR encoder decoder supporting 3/16 bit duration for normal mode * Smartcard mode ( T=0 and T=1 asynchronous protocols for Smartcards as defined in the ISO/IEC 7816-3 standard) * Support for Modbus communication Table 8 summarizes the implementation of all U(S)ARTs instances Table 8. USART implementation features(1) USART1/2/3/6 Data Length 42/201 UART4/5/7/8 7, 8 and 9 bits Hardware flow control for modem X X Continuous communication using DMA X X Multiprocessor communication X X Synchronous mode X - DS12536 Rev 1 STM32F730x8 Functional overview Table 8. USART implementation (continued) features(1) USART1/2/3/6 UART4/5/7/8 Smartcard mode X - Single-wire half-duplex communication X X IrDA SIR ENDEC block X X LIN mode X X Dual clock domain X X Receiver timeout interrupt X X Modbus communication X X Auto baud rate detection X X Driver Enable X X 1. X: supported. 3.23 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) The devices feature up to five SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1, SPI4, and SPI5 can communicate at up to 50 Mbit/s, SPI2 and SPI3 can communicate at up to 25 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable from 4 to 16 bits. The SPI interfaces support the NSS pulse mode, TI mode and Hardware CRC calculation. All the SPIs can be served by the DMA controller. Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They can be operated in master or slave mode, in simplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2Sx can be served by the DMA controller. 3.24 Serial audio interface (SAI) The devices embed two serial audio interfaces. The serial audio interface is based on two independent audio subblocks which can operate as transmitter or receiver with their FIFO. Many audio protocols are supported by each block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC'97 and SPDIF output, supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both subblocks can be configured in master or in slave mode. In master mode, the master clock can be output to the external DAC/CODEC at 256 times of the sampling frequency. The two sub-blocks can be configured in synchronous mode when full-duplex mode is required. DS12536 Rev 1 43/201 49 Functional overview STM32F730x8 SAI1 and SAI2 can be served by the DMA controller 3.25 Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows to achieve an error-free I2S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals. The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change without disabling the main PLL (PLL) used for CPU and USB interfaces. The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 KHz to 192 KHz. In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S/SAI flow with an external PLL (or Codec output). 3.26 Audio PLL (PLLSAI) An additional PLL dedicated to audio is used for the SAI1 peripheral in case the PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or 11.2896 MHz) and the audio application requires both sampling frequencies simultaneously. 3.27 SD/SDIO/MMC card host interface (SDMMC) SDMMC host interfaces are available, that support MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 50 MHz, and is compliant with the SD Memory Card Specification Version 2.0. The SDMMC Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDMMC/MMC4.2 card at any one time and a stack of MMC4.1 or previous. The SDMMC can be served by the DMA controller 3.28 Controller area network (bxCAN) The CAN is compliant with the 2.0A and B (active) specifications with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. The CAN has three transmit mailboxes, two receive FIFOs with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). 256 bytes of SRAM are allocated to the CAN. 44/201 DS12536 Rev 1 STM32F730x8 3.29 Functional overview Universal serial bus on-the-go full-speed (OTG_FS) The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: * Combined Rx and Tx FIFO size of 1.28 Kbytes with dynamic FIFO sizing * Supports the session request protocol (SRP) and host negotiation protocol (HNP) * 1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints * 12 host channels with periodic OUT support * Software configurable to OTG1.3 and OTG2.0 modes of operation * USB 2.0 LPM (Link Power Management) support * Internal FS OTG PHY support * HNP/SNP/IP inside (no need for any external resistor) * BCD support For the OTG/Host modes, a power switch is needed in case bus-powered devices are connected 3.30 Universal serial bus on-the-go high-speed (OTG_HS) The devices embed an USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 Mbit/s). The STM32F730x8 devices feature a UTMI low-pin interface (ULPI) for high-speed operation (480 Mbit/s). When using the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required. The STM32F730x8 devices feature an integrated PHY HS. The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG 2.0 specification. It has a software-configurable endpoint setting and supports suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: * Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing * Supports the session request protocol (SRP) and host negotiation protocol (HNP) * 8 bidirectional endpoints * 16 host channels with periodic OUT support * Software configurable to OTG1.3 and OTG2.0 modes of operation * USB 2.0 LPM (Link Power Management) support DS12536 Rev 1 45/201 49 Functional overview STM32F730x8 * Internal FS OTG PHY support * For the STM32F730x8 devices: External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output. * For the STM32F730x8 devices: Internal HS OTG PHY support. * Internal USB DMA * HNP/SNP/IP inside (no need for any external resistor) * For OTG/Host modes, a power switch is needed in case bus-powered devices are connected Universal Serial Bus controller on-the-go High-Speed PHY controller (USBPHYC) only on STM32F730x8 devices. The USB HS PHY controller: 3.31 - Sets the PHYPLL1/2 values for the PHY HS - Sets the other controls on the PHY HS - Controls and monitors the USB PHY's LDO Random number generator (RNG) All the devices embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. 3.32 Advanced encryption standard hardware accelerator (AES) The devices embed an AES hardware accelerator which can be used to both encipher and decipher data using AES algorithm. 46/201 DS12536 Rev 1 STM32F730x8 Functional overview The AES peripheral supports: 3.33 * Encryption/Decryption using AES Rijndael Block Cipher algorithm * NIST FIPS 197 compliant implementation of AES encryption/decryption algorithm * 128-bit and 256-bit register for storing the encryption, decryption or derivation key (4x 32-bit registers) * Electronic codebook (ECB), Cipher block chaining (CBC), Counter mode (CTR), Galois Counter Mode (GCM), Galois Message Authentication Code mode (GMAC) and Cipher Message Authentication Code mode (CMAC) supported. * Key scheduler * Key derivation for decryption * 128-bit data block processing * 128-bit, 256-bit key length * 1x32-bit INPUT buffer and 1x32-bit OUTPUT buffer. * Register access supporting 32-bit data width only. * One 128-bit Register for the initialization vector when AES is configured in CBC mode or for the 32-bit counter initialization when CTR mode is selected, GCM mode or CMAC mode. * Automatic data flow control with support of direct memory access (DMA) using 2 channels, one for incoming data, and one for outcoming data. * Suspend a message if another message with a higher priority needs to be processed General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. A Fast I/O handling allows a maximum I/O toggling up to 108 MHz. 3.34 Analog-to-digital converters (ADCs) Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In the scan mode, an automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: * Simultaneous sample and hold * Interleaved sample and hold The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. DS12536 Rev 1 47/201 49 Functional overview STM32F730x8 To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4, TIM5, or TIM8 timer. 3.35 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with the temperature. The conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally connected to the same input channel as VBAT, ADC1_IN18, which is used to convert the sensor output voltage into a digital value. When the temperature sensor and VBAT conversion are enabled at the same time, only VBAT conversion is performed. As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used. 3.36 Digital-to-analog converter (DAC) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. This dual digital Interface supports the following features: * Two DAC converters: one for each output channel * 8-bit or 12-bit monotonic output * Left or right data alignment in 12-bit mode * Synchronized update capability * Noise-wave generation * Triangular-wave generation * Dual DAC channel independent or simultaneous conversions * DMA capability for each channel * External triggers for conversion * Input voltage reference VREF+ Eight DAC trigger inputs are used in the device. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams. 3.37 Serial wire JTAG debug port (SWJ-DP) The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-used as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 48/201 DS12536 Rev 1 STM32F730x8 3.38 Functional overview Embedded Trace MacrocellTM The Arm Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F730x8 device through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using the USB or any other high-speed channel. The real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. The TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell operates with third party debugger software tools. DS12536 Rev 1 49/201 49 Pinouts and pin description 4 STM32F730x8 Pinouts and pin description VDD PA4 PA5 PA6 PA7 PC4 PB0 PB1 PB2 PB10 PB11 VCAP_1 VSS VDD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PA3 VSS VBAT PC13 PC14-OSC32_IN PC15-OSC32_OUT PH0-OSC_IN PH1-OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP PA1 PA2 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 VDD VSS PB9 PB8 Figure 13. STM32F730R8 LQFP64 pinout 1. The above figure shows the package top view. 50/201 DS12536 Rev 1 VDD VSS PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 MS40455V3 STM32F730x8 Pinouts and pin description 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD VSS PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 14. STM32F730V8 LQFP100 pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 LQFP100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDD VSS VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP_1 VSS VDD 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PE2 PE3 PE4 PE5 PE6 VBAT PC13 PC14-OSC32_IN PC15-OSC32_OUT VSS VDD PH0-OSC_IN PH1-OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREF+ VDDA PA0-WKUP PA1 PA2 PA3 MSv40457V1 1. The above figure shows the package top view. DS12536 Rev 1 51/201 83 Pinouts and pin description STM32F730x8 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD PDR_ON PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDDSDMMC VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 15. STM32F730Z8 LQFP144 pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 LQFP144 with HS PHY 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VDD VSS VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 VDDUSB VSS PG8 PG5 PG4 PG3 PG2 PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 VDD12OTGHS OTG_HS_REXT PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VSS VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP_1 VDD 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PE2 PE3 PE4 PE5 PE6 VBAT PC13 PC14 PC15 PF0 PF1 PF2 PF3 PF4 PF5 VSS VDD PF6 PF7 PF8 PF9 PF10 PH0 PH1 NRST PC0 PC1 PC2 PC3 VDD VSSA VREF+ VDDA PA0 PA1 PA2 MS41014V1 1. The above figure shows the package top view. 52/201 DS12536 Rev 1 STM32F730x8 Pinouts and pin description Figure 16. STM32F730I8 UFBGA176 ballout (with OTG PHY HS) 1 2 A PE3 PE2 B PE4 C 3 4 5 6 7 8 9 PE1 PE0 PB8 PB5 PG14 PG13 PB4 PE5 PE6 PB9 PB7 PB6 PG15 PG12 VBAT PI7 PI6 PI5 VDD 11 12 13 14 15 PB3 PD7 PC12 PA15 PA14 PA13 PG11 PG10 PD6 PD0 PC11 PC10 PA12 VDD SDMMC VDD PG9 PD5 PD1 PI3 PI2 PA11 D PC13 PI8 PI9 PI4 VSS VSS PD4 PD3 PD2 PH15 PI1 PA10 E PC14 PF0 PI10 PI11 PH13 PH14 PI0 PA9 F PC15 VSS VDD PH2 VSS VSS VSS VSS VSS VSS VCAP2 PC9 PA8 G PH0 VSS VDD PH3 VSS VSS VSS VSS VSS VSS VDD PC8 PC7 H PH1 PF2 PF1 PH4 VSS VSS VSS VSS VSS VSS VDDUSB PG8 PC6 J NRST PF3 PF4 PH5 VSS VSS VSS VSS VSS VDD VDD VDD12 OTG_HS OTGHS _REXT K PF7 PF6 PF5 VDD VSS VSS VSS VSS VSS PH12 PG5 PG4 PG3 L PF10 PF9 PF8 BYPASS_ REG PH11 PH10 PD15 PG2 M VSSA PC0 PC1 PC2 PC3 PB2 PG1 VSS VSS PH6 PH8 PH9 PD14 PD13 N VREF- PA1 PA0 PA4 PC4 PF13 PG0 VDD VDD VDD PE13 PH7 PD12 PD11 PD10 P VREF+ PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8 R VDDA PA3 PA7 PB1 PB0 PF11 PF14 PE7 PE10 PE12 PE15 PB10 PB11 PB14 PB15 PDR_ON VDD BOOT0 VSS VSS 10 VCAP_1 MS42001V1 1. The above figure shows the package top view. DS12536 Rev 1 53/201 83 Pinouts and pin description STM32F730x8 Table 9. Legend/abbreviations used in the pinout table Name Pin name Abbreviation Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name Pin type I/O structure Notes Definition S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O FTf 5V tolerant I/O, I2C Fm+ option. TTa 3.3 V tolerant I/O directly connected to ADC B Dedicated BOOT pin RST Bidirectional reset pin with weak pull-up resistor Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers Table 10. STM32F730x8 pin and ball definition 1 A2 PE2 I/O FT - - 2 2 A1 PE3 I/O FT - TRACED0, SAI1_SD_B, FMC_A19, EVENTOUT - - 3 3 B1 PE4 I/O FT - TRACED1, SPI4_NSS, SAI1_FS_A, FMC_A20, EVENTOUT - 54/201 UFBGA176 1 LQFP144 - TRACECLK, SPI4_SCK, SAI1_MCLK_A, QUADSPI_BK1_IO2, FMC_A23, EVENTOUT LQFP100 Alternate functions LQFP64 Notes I/O structure Pin type Pin Number Pin name (function after reset)(1) DS12536 Rev 1 Additional functions - STM32F730x8 Pinouts and pin description Table 10. STM32F730x8 pin and ball definition (continued) UFBGA176 4 B2 PE5 I/O Notes LQFP144 4 I/O structure LQFP100 - Pin name (function after reset)(1) Pin type LQFP64 Pin Number Alternate functions Additional functions FT - TRACED2, TIM9_CH1, SPI4_MISO, SAI1_SCK_A, FMC_A21, EVENTOUT - - - 5 5 B3 PE6 I/O FT - TRACED3, TIM1_BKIN2, TIM9_CH2, SPI4_MOSI, SAI1_SD_A, SAI2_MCK_B, FMC_A22, EVENTOUT 1 6 6 C1 VBAT S - - - - - - - D2 PI8 I/O FT EVENTOUT RTC_TAMP2/ RTC_TS, WKUP5 EVENTOUT RTC_TAMP1/ RTC_TS/ RTC_OUT, WKUP4 EVENTOUT OSC32_IN EVENTOUT OSC32_OUT (2) (3) (2) 2 7 7 D1 PC13 E1 PC14OSC32_IN(PC14) I/O FT (3) (2) 3 8 8 I/O FT (3) (5) (2) 4 9 9 F1 PC15OSC32_OUT(PC15) I/O FT (3) (5) - - - D3 PI9 I/O FT - UART4_RX, CAN1_RX, FMC_D30, EVENTOUT - - - - E3 PI10 I/O FT - FMC_D31, EVENTOUT - - - - E4 PI11 I/O FT (4) OTG_HS_ULPI_DIR, EVENTOUT WKUP6 - - - F2 VSS S - - - - - - - F3 VDD S - - - - - - 10 E2 PF0 I/O FTf - I2C2_SDA, FMC_A0, EVENTOUT - - - 11 H3 PF1 I/O FTf - I2C2_SCL, FMC_A1, EVENTOUT - - - 12 H2 PF2 I/O FT - I2C2_SMBA, FMC_A2, EVENTOUT - DS12536 Rev 1 55/201 83 Pinouts and pin description STM32F730x8 Table 10. STM32F730x8 pin and ball definition (continued) LQFP144 UFBGA176 I/O structure Notes LQFP100 Pin type Alternate functions LQFP64 Pin Number - - 13 J2 PF3 I/O FT - FMC_A3, EVENTOUT ADC3_IN9 - - 14 J3 PF4 I/O FT - FMC_A4, EVENTOUT ADC3_IN14 - - 15 K3 PF5 I/O FT - FMC_A5, EVENTOUT ADC3_IN15 - 10 16 G2 VSS S - - - - - 11 17 G3 VDD S - - - - - - 18 K2 PF6 I/O FT - TIM10_CH1, SPI5_NSS, SAI1_SD_B, UART7_RX, QUADSPI_BK1_IO3, EVENTOUT ADC3_IN4 - - 19 K1 PF7 I/O FT - TIM11_CH1, SPI5_SCK, SAI1_MCLK_B, UART7_TX, QUADSPI_BK1_IO2, EVENTOUT ADC3_IN5 - - 20 L3 PF8 I/O FT - SPI5_MISO, SAI1_SCK_B, UART7_RTS, TIM13_CH1, QUADSPI_BK1_IO0, EVENTOUT ADC3_IN6 - - 21 L2 PF9 I/O FT - SPI5_MOSI, SAI1_FS_B, UART7_CTS, TIM14_CH1, QUADSPI_BK1_IO1, EVENTOUT ADC3_IN7 - - 22 L1 PF10 I/O FT - EVENTOUT ADC3_IN8 EVENTOUT OSC_IN Pin name (function after reset)(1) Additional functions 5 12 23 G1 PH0-OSC_IN I/O FT (5) 6 13 24 H1 PH1-OSC_OUT I/O FT (5) EVENTOUT OSC_OUT 7 14 25 J1 NRST I/O RS T - - - 8 15 26 M2 PC0 I/O FT (4) SAI2_FS_B, OTG_HS_ULPI_STP, FMC_SDNWE, EVENTOUT ADC1_IN10, ADC2_IN10, ADC3_IN10 56/201 DS12536 Rev 1 STM32F730x8 Pinouts and pin description Table 10. STM32F730x8 pin and ball definition (continued) Notes I/O structure Pin name (function after reset)(1) Pin type UFBGA176 LQFP144 LQFP100 LQFP64 Pin Number Alternate functions Additional functions 9 16 27 M3 PC1 I/O FT - TRACED0, SPI2_MOSI/I2S2_SD, SAI1_SD_A, EVENTOUT ADC1_IN11, ADC2_IN11, ADC3_IN11, RTC_TAMP3, WKUP3 10 17 28 M4 PC2 I/O FT (4) SPI2_MISO, OTG_HS_ULPI_DIR, FMC_SDNE0, EVENTOUT ADC1_IN12, ADC2_IN12, ADC3_IN12 11 18 29 M5 PC3 I/O FT (4) SPI2_MOSI/I2S2_SD, OTG_HS_ULPI_NXT, FMC_SDCKE0, EVENTOUT ADC1_IN13, ADC2_IN13, ADC3_IN13 - - 30 - VDD S - - - - 12 19 31 M1 VSSA S - - - - - - - N1 VREF- S - - - - 13 20 32 P1 VREF+ S - - - - - 21 33 R1 VDDA S - - - - FT (6) TIM2_CH1/TIM2_ETR, TIM5_CH1, TIM8_ETR, USART2_CTS, UART4_TX, SAI2_SD_B, EVENTOUT ADC1_IN0, ADC2_IN0, ADC3_IN0, WKUP1 - TIM2_CH2, TIM5_CH2, USART2_RTS, UART4_RX, QUADSPI_BK1_IO3, SAI2_MCK_B, EVENTOUT ADC1_IN1, ADC2_IN1, ADC3_IN1 - TIM2_CH3, TIM5_CH3, TIM9_CH1, USART2_TX, SAI2_SCK_B, EVENTOUT ADC1_IN2, ADC2_IN2, ADC3_IN2, WKUP2 14 15 16 22 23 24 34 35 36 N3 N2 P2 PA0-WKUP PA1 PA2 I/O I/O I/O FT FT DS12536 Rev 1 57/201 83 Pinouts and pin description STM32F730x8 Table 10. STM32F730x8 pin and ball definition (continued) - F4 PH2 I/O FT - - - - G4 PH3 I/O FT - QUADSPI_BK2_IO1, SAI2_MCK_B, FMC_SDNE0, EVENTOUT - - - - H4 PH4 I/O FTf (4) I2C2_SCL, OTG_HS_ULPI_NXT, EVENTOUT - - - - J4 PH5 I/O FTf - I2C2_SDA, SPI5_NSS, FMC_SDNWE, EVENTOUT - 17 25 37 R2 PA3 I/O FT (4) TIM2_CH4, TIM5_CH4, TIM9_CH2, USART2_RX, OTG_HS_ULPI_D0, EVENTOUT ADC1_IN3, ADC2_IN3, ADC3_IN3 18 26 38 - VSS S - - - - - - - L4 BYPASS_REG I FT - - - 19 27 39 K4 VDD S - - - - - SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, OTG_HS_SOF, EVENTOUT ADC1_IN4, ADC2_IN4, DAC_OUT1 UFBGA176 - LQFP144 - LPTIM1_IN2, QUADSPI_BK2_IO0, SAI2_SCK_B, FMC_SDCKE0, EVENTOUT LQFP100 Alternate functions LQFP64 Notes I/O structure Pin type Pin Number Pin name (function after reset)(1) 20 28 40 N4 PA4 I/O TTa 21 29 41 P4 PA5 I/O TIM2_CH1/TIM2_ETR, TTa (4) TIM8_CH1N, SPI1_SCK/I2S1_CK, OTG_HS_ULPI_CK, EVENTOUT 22 30 42 P3 PA6 I/O FT - ADC1_IN5, ADC2_IN5, DAC_OUT2 - TIM1_BKIN, TIM3_CH1, TIM8_BKIN, SPI1_MISO, TIM13_CH1, EVENTOUT ADC1_IN6, ADC2_IN6 ADC1_IN7, ADC2_IN7 ADC1_IN14, ADC2_IN14 23 31 43 R3 PA7 I/O FT - TIM1_CH1N, TIM3_CH2, TIM8_CH1N, SPI1_MOSI/I2S1_SD, TIM14_CH1, FMC_SDNWE, EVENTOUT 24 32 44 N5 PC4 I/O FT - I2S1_MCK, FMC_SDNE0, EVENTOUT 58/201 Additional functions DS12536 Rev 1 STM32F730x8 Pinouts and pin description Table 10. STM32F730x8 pin and ball definition (continued) LQFP144 UFBGA176 I/O structure Notes LQFP100 Pin type Alternate functions LQFP64 Pin Number - 33 45 P5 PC5 I/O FT - FMC_SDCKE0, EVENTOUT ADC1_IN15, ADC2_IN15 25 34 46 R5 PB0 I/O FT (4) TIM1_CH2N, TIM3_CH3, TIM8_CH2N, UART4_CTS, OTG_HS_ULPI_D1, EVENTOUT ADC1_IN8, ADC2_IN8 26 35 47 R4 PB1 I/O FT (4) TIM1_CH3N, TIM3_CH4, TIM8_CH3N, OTG_HS_ULPI_D2, EVENTOUT ADC1_IN9, ADC2_IN9 27 36 48 M6 PB2 I/O FT - SAI1_SD_A, SPI3_MOSI/I2S3_SD, QUADSPI_CLK, EVENTOUT - - - 49 R6 PF11 I/O FT - SPI5_MOSI, SAI2_SD_B, FMC_SDNRAS, EVENTOUT - - - 50 P6 PF12 I/O FT - FMC_A6, EVENTOUT - - - 51 M8 VSS S - - - - - - 52 N8 VDD S - - - - - - 53 N6 PF13 I/O FT - FMC_A7, EVENTOUT - - - 54 R7 PF14 I/O FT - FMC_A8, EVENTOUT - - - 55 P7 PF15 I/O FT - FMC_A9, EVENTOUT - - - 56 N7 PG0 I/O FT - FMC_A10, EVENTOUT - - - 57 M7 PG1 I/O FT - FMC_A11, EVENTOUT - - 37 58 R8 PE7 I/O FT - TIM1_ETR, UART7_Rx, QUADSPI_BK2_IO0, FMC_D4, EVENTOUT - - 38 59 P8 PE8 I/O FT - TIM1_CH1N, UART7_Tx, QUADSPI_BK2_IO1, FMC_D5, EVENTOUT - - 39 60 P9 PE9 I/O FT - TIM1_CH1, UART7_RTS, QUADSPI_BK2_IO2, FMC_D6, EVENTOUT - - - 61 M9 VSS S - - - - - - 62 N9 VDD S - - - - Pin name (function after reset)(1) DS12536 Rev 1 Additional functions 59/201 83 Pinouts and pin description STM32F730x8 Table 10. STM32F730x8 pin and ball definition (continued) LQFP144 UFBGA176 I/O structure Notes LQFP100 Pin type Alternate functions LQFP64 Pin Number - 40 63 R9 PE10 I/O FT - TIM1_CH2N, UART7_CTS, QUADSPI_BK2_IO3, FMC_D7, EVENTOUT - - 41 64 P10 PE11 I/O FT - TIM1_CH2, SPI4_NSS, SAI2_SD_B, FMC_D8, EVENTOUT - - 42 65 R10 PE12 I/O FT - TIM1_CH3N, SPI4_SCK, SAI2_SCK_B, FMC_D9, EVENTOUT - - 43 66 N11 PE13 I/O FT - TIM1_CH3, SPI4_MISO, SAI2_FS_B, FMC_D10, EVENTOUT - - 44 67 P11 PE14 I/O FT - TIM1_CH4, SPI4_MOSI, SAI2_MCK_B, FMC_D11,, EVENTOUT - - 45 68 R11 PE15 I/O FT - TIM1_BKIN, FMC_D12, EVENTOUT - TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, USART3_TX, OTG_HS_ULPI_D3, EVENTOUT - Pin name (function after reset)(1) Additional functions 28 46 69 R12 PB10 I/O FTf (4) 29 47 70 R13 PB11 I/O FTf (4) TIM2_CH4, I2C2_SDA, USART3_RX, OTG_HS_ULPI_D4, EVENTOUT - 30 48 71 M10 VCAP_1 S - - - - 31 49 - - VSS S - - - - 32 50 72 N10 VDD S - - - - - - - M11 PH6 I/O FT - I2C2_SMBA, SPI5_SCK, TIM12_CH1, FMC_SDNE1, EVENTOUT - - - - N12 PH7 I/O FTf - I2C3_SCL, SPI5_MISO, FMC_SDCKE1, EVENTOUT - - - - M12 PH8 I/O FTf - I2C3_SDA, FMC_D16, EVENTOUT - 60/201 DS12536 Rev 1 STM32F730x8 Pinouts and pin description Table 10. STM32F730x8 pin and ball definition (continued) LQFP144 UFBGA176 I/O structure Notes LQFP100 Pin type Alternate functions LQFP64 Pin Number - - - M13 PH9 I/O FT - I2C3_SMBA, TIM12_CH2, FMC_D17, EVENTOUT - - - - L13 PH10 I/O FT - TIM5_CH1, FMC_D18, EVENTOUT - - - - L12 PH11 I/O FT - TIM5_CH2, FMC_D19, EVENTOUT - - - - K12 PH12 I/O FT - TIM5_CH3, FMC_D20, EVENTOUT - - - - H12 VSS S - - - - - - - J12 VDD S - - - - TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, USART3_CK, OTG_HS_ULPI_D5, OTG_HS_ID, EVENTOUT - Pin name (function after reset)(1) Additional functions 33 51 73 P12 PB12 I/O FT (4) 34 52 74 P13 PB13 I/O FT (4) TIM1_CH1N, SPI2_SCK/I2S2_CK, USART3_CTS, OTG_HS_VBUS OTG_HS_ULPI_D6, EVENTOUT - - 75 J15 OTG_HS_REXT - - - USB HS OTG PHY calibration resistor - - 76 J14 VDD12OTGHS - - - - - - 35 53 - - PB14 I/O FT - TIM1_CH2N, TIM8_CH2N, SPI2_MISO, USART3_RTS, TIM12_CH1, SDMMC2_D0, OTG_HS_DM, EVENTOUT - - 77 R14 PB14 I/O FT - OTG_HS_DM - - RTC_REFIN, TIM1_CH3N, TIM8_CH3N, SPI2_MOSI/I2S2_SD, TIM12_CH2, SDMMC2_D1, OTG_HS_DP, EVENTOUT - 36 54 - - PB15 I/O FT DS12536 Rev 1 61/201 83 Pinouts and pin description STM32F730x8 Table 10. STM32F730x8 pin and ball definition (continued) LQFP144 UFBGA176 I/O structure Notes LQFP100 Pin type Alternate functions LQFP64 Pin Number - - 78 R15 PB15 I/O FT - OTG_HS_DP - - 55 79 P15 PD8 I/O FT - USART3_TX, FMC_D13, EVENTOUT - - 56 80 P14 PD9 I/O FT - USART3_RX, FMC_D14, EVENTOUT - - 57 81 N15 PD10 I/O FT - USART3_CK, FMC_D15, EVENTOUT - - 58 82 N14 PD11 I/O FT - USART3_CTS, QUADSPI_BK1_IO0, SAI2_SD_A, FMC_A16/FMC_CLE, EVENTOUT - - TIM4_CH1, LPTIM1_IN1, USART3_RTS, QUADSPI_BK1_IO1, SAI2_FS_A, FMC_A17/FMC_ALE, EVENTOUT - - - 59 83 N13 Pin name (function after reset)(1) PD12 I/O FT Additional functions - 60 84 M15 PD13 I/O FT - TIM4_CH2, LPTIM1_OUT, QUADSPI_BK1_IO3, SAI2_SCK_A, FMC_A18, EVENTOUT - - 85 - VSS S - - - - - - 86 J13 VDD S - - - - - 61 87 M14 PD14 I/O FT - TIM4_CH3, UART8_CTS, FMC_D0, EVENTOUT - - 62 88 L14 PD15 I/O FT - TIM4_CH4, UART8_RTS, FMC_D1, EVENTOUT - - - 89 L15 PG2 I/O FT - FMC_A12, EVENTOUT - - - 90 K15 PG3 I/O FT - FMC_A13, EVENTOUT - - - 91 K14 PG4 I/O FT - FMC_A14/FMC_BA0, EVENTOUT - - - 92 K13 PG5 I/O FT - FMC_A15/FMC_BA1, EVENTOUT - - - - - PG6 I/O FT - EVENTOUT - - - - - PG7 I/O FT - USART6_CK, FMC_INT, EVENTOUT - 62/201 DS12536 Rev 1 STM32F730x8 Pinouts and pin description Table 10. STM32F730x8 pin and ball definition (continued) LQFP144 UFBGA176 I/O structure Notes LQFP100 Pin type Alternate functions LQFP64 Pin Number - - 93 H14 PG8 I/O FT - USART6_RTS, FMC_SDCLK, EVENTOUT - - - 94 G12 VSS S - - - - - - - - VDD - - - - - - - 95 H13 VDDUSB S - - - - - TIM3_CH1, TIM8_CH1, I2S2_MCK, USART6_TX, SDMMC2_D6, SDMMC1_D6, EVENTOUT - - TIM3_CH2, TIM8_CH2, I2S3_MCK, USART6_RX, SDMMC2_D7, SDMMC1_D7, EVENTOUT - - TRACED1, TIM3_CH3, TIM8_CH3, UART5_RTS, USART6_CK, SDMMC1_D0, EVENTOUT - - 37 38 39 63 64 65 96 97 98 H15 G15 G14 Pin name (function after reset)(1) PC6 PC7 PC8 I/O I/O I/O FT FT FT Additional functions 40 66 F14 PC9 I/O FTf - MCO2, TIM3_CH4, TIM8_CH4, I2C3_SDA, I2S_CKIN, UART5_CTS, QUADSPI_BK1_IO0, SDMMC1_D1, EVENTOUT 41 67 100 F15 PA8 I/O FTf - MCO1, TIM1_CH1, TIM8_BKIN2, I2C3_SCL, USART1_CK, OTG_FS_SOF, EVENTOUT - 42 68 101 E15 PA9 I/O FT - TIM1_CH2, I2C3_SMBA, SPI2_SCK/I2S2_CK, USART1_TX, EVENTOUT OTG_FS_VBUS 43 69 102 D15 PA10 I/O FT - TIM1_CH3, USART1_RX, OTG_FS_ID, EVENTOUT - 44 70 103 C15 PA11 I/O FT - TIM1_CH4, USART1_CTS, CAN1_RX, OTG_FS_DM, EVENTOUT - 45 71 104 B15 PA12 I/O FT - TIM1_ETR, USART1_RTS, SAI2_FS_B, CAN1_TX, OTG_FS_DP, EVENTOUT - 46 72 105 A15 PA13(JTMS-SWDIO) I/O FT - JTMS-SWDIO, EVENTOUT - 99 DS12536 Rev 1 63/201 83 Pinouts and pin description STM32F730x8 Table 10. STM32F730x8 pin and ball definition (continued) I/O structure Notes VCAP_2 S - - - - 47 74 107 F12 VSS S - - - - 48 75 108 G13 VDD S - - - - UFBGA176 73 106 F13 LQFP144 - LQFP100 Alternate functions LQFP64 Pin type Pin Number Pin name (function after reset)(1) Additional functions - - - E12 PH13 I/O FT - TIM8_CH1N, UART4_TX, CAN1_TX, FMC_D21, EVENTOUT - - - - E13 PH14 I/O FT - TIM8_CH2N, UART4_RX, CAN1_RX, FMC_D22, EVENTOUT - - - - D13 PH15 I/O FT - TIM8_CH3N, FMC_D23, EVENTOUT - - - - E14 PI0 I/O FT - TIM5_CH4, SPI2_NSS/I2S2_WS, FMC_D24, EVENTOUT - - - - D14 PI1 I/O FT - TIM8_BKIN2, SPI2_SCK/I2S2_CK, FMC_D25, EVENTOUT - - - - C14 PI2 I/O FT - TIM8_CH4, SPI2_MISO, FMC_D26, EVENTOUT - - - - C13 PI3 I/O FT - TIM8_ETR, SPI2_MOSI/I2S2_SD, FMC_D27, EVENTOUT - - - - D9 VSS S - - - - - - - C9 VDD S - - - - PA14(JTCKSWCLK) I/O FT - JTCK-SWCLK, EVENTOUT - - JTDI, TIM2_CH1/TIM2_ETR, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, UART4_RTS, EVENTOUT - - SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, QUADSPI_BK1_IO1, SDMMC1_D2, EVENTOUT - - SPI3_MISO, USART3_RX, UART4_RX, QUADSPI_BK2_NCS, SDMMC1_D3, EVENTOUT - 49 50 51 52 76 109 A14 77 110 A13 78 111 B14 79 112 B13 64/201 PA15(JTDI) PC10 PC11 I/O I/O I/O FT FT FT DS12536 Rev 1 STM32F730x8 Pinouts and pin description Table 10. STM32F730x8 pin and ball definition (continued) Pin type I/O structure Notes 80 113 A12 PC12 I/O FT - TRACED3, SPI3_MOSI/I2S3_SD, USART3_CK, UART5_TX, SDMMC1_CK, EVENTOUT - - 81 114 B12 PD0 I/O FT - CAN1_RX, FMC_D2, EVENTOUT - - 82 115 C12 PD1 I/O FT - CAN1_TX, FMC_D3, EVENTOUT - 54 83 116 D12 PD2 I/O FT - TRACED2, TIM3_ETR, UART5_RX, SDMMC1_CMD, EVENTOUT - - 84 117 D11 PD3 I/O FT - SPI2_SCK/I2S2_CK, USART2_CTS, FMC_CLK, EVENTOUT - - 85 118 D10 PD4 I/O FT - USART2_RTS, FMC_NOE, EVENTOUT - - 86 119 C11 PD5 I/O FT - USART2_TX, FMC_NWE, EVENTOUT - UFBGA176 LQFP100 53 LQFP144 Alternate functions LQFP64 Pin Number Pin name (function after reset)(1) Additional functions - - 120 D8 VSS S - - - - - - 121 C8 VDDSDMMC S - - - - - - 87 122 B11 PD6 I/O FT - SPI3_MOSI/I2S3_SD, SAI1_SD_A, USART2_RX, SDMMC2_CK, FMC_NWAIT, EVENTOUT - 88 123 A11 PD7 I/O FT - USART2_CK SDMMC2_CMD, FMC_NE1, EVENTOUT - - - - 124 C10 PG9 I/O FT - USART6_RX, QUADSPI_BK2_IO2, SAI2_FS_B, SDMMC2_D0, FMC_NE2/FMC_NCE, EVENTOUT - - 125 B10 PG10 I/O FT - SAI2_SD_B, SDMMC2_D1, FMC_NE3, EVENTOUT - - - 126 PG11 I/O FT - SDMMC2_D2, FMC_INT, EVENTOUT - B9 DS12536 Rev 1 65/201 83 Pinouts and pin description STM32F730x8 Table 10. STM32F730x8 pin and ball definition (continued) LQFP144 UFBGA176 I/O structure Notes LQFP100 Pin type Alternate functions LQFP64 Pin Number - - 127 B8 PG12 I/O FT - LPTIM1_IN1, USART6_RTS, SDMMC2_D3, FMC_NE4, EVENTOUT - - - 128 A8 PG13 I/O FT - TRACED0, LPTIM1_OUT, USART6_CTS, FMC_A24, EVENTOUT - - Pin name (function after reset)(1) Additional functions - - 129 A7 PG14 I/O FT - TRACED1, LPTIM1_ETR, USART6_TX, QUADSPI_BK2_IO3, FMC_A25, EVENTOUT - - 130 D7 VSS S - - - - - - 131 C7 VDD S - - - - - - 132 B7 PG15 I/O FT - USART6_CTS, FMC_SDNCAS, EVENTOUT - - 55 PB3(JTDO/TRACES 89 133 A10 WO) I/O FT - JTDO/TRACESWO, TIM2_CH2, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, SDMMC2_D2, EVENTOUT 56 90 134 I/O FT - NJTRST, TIM3_CH1, SPI1_MISO, SPI3_MISO, SPI2_NSS/I2S2_WS, SDMMC2_D3, EVENTOUT - (4) TIM3_CH2, I2C1_SMBA, SPI1_MOSI/I2S1_SD, SPI3_MOSI/I2S3_SD, OTG_HS_ULPI_D7, FMC_SDCKE1, EVENTOUT - 57 91 135 66/201 A9 A6 PB4(NJTRST) PB5 I/O FT DS12536 Rev 1 STM32F730x8 Pinouts and pin description Table 10. STM32F730x8 pin and ball definition (continued) B6 PB6 I/O FTf - 59 93 137 B5 PB7 I/O FTf - TIM4_CH2, I2C1_SDA, USART1_RX, FMC_NL, EVENTOUT - 60 94 138 D6 BOOT I B - - VPP - TIM4_CH3, TIM10_CH1, I2C1_SCL, CAN1_RX, SDMMC2_D4, SDMMC1_D4, EVENTOUT - - 61 95 139 UFBGA176 92 136 LQFP144 58 TIM4_CH1, I2C1_SCL, USART1_TX, QUAD SPI_BK1_NCS, FMC_SDNE1, EVENTOUT LQFP100 Alternate functions LQFP64 Notes I/O structure Pin type Pin Number A5 Pin name (function after reset)(1) PB8 I/O FTf Additional functions - 62 96 140 B4 PB9 I/O FTf - TIM4_CH4, TIM11_CH1, I2C1_SDA, SPI2_NSS/I2S2_WS, CAN1_TX, SDMMC2_D5, SDMMC1_D5, EVENTOUT - 97 141 A4 PE0 I/O FT - TIM4_ETR, LPTIM1_ETR, UART8_Rx, SAI2_MCK_A, FMC_NBL0, EVENTOUT - - 98 142 A3 PE1 I/O FT - LPTIM1_IN2, UART8_Tx, FMC_NBL1, EVENTOUT - 63 99 - D5 VSS S - - - - - - 143 C6 PDR_ON S - - - - 10 144 0 C5 VDD S - - - - D4 PI4 I/O FT - TIM8_BKIN, SAI2_MCK_A, FMC_NBL2, EVENTOUT - 64 - - - DS12536 Rev 1 67/201 83 Pinouts and pin description STM32F730x8 Table 10. STM32F730x8 pin and ball definition (continued) LQFP144 UFBGA176 I/O structure Notes LQFP100 Pin type Alternate functions LQFP64 Pin Number - - - C4 PI5 I/O FT - TIM8_CH1, SAI2_SCK_A, FMC_NBL3, EVENTOUT - - - - C3 PI6 I/O FT - TIM8_CH2, SAI2_SD_A, FMC_D28, EVENTOUT - - - - C2 PI7 I/O FT - TIM8_CH3, SAI2_FS_A, FMC_D29, EVENTOUT - - - - F6 VSS S - - - - - - - F7 VSS S - - - - - - - F8 VSS S - - - - - - - F9 VSS S - - - - - - - F10 VSS S - - - - - - - G6 VSS S - - - - - - - G7 VSS S - - - - - - - G8 VSS S - - - - - - - G9 VSS S - - - - - - - G10 VSS S - - - - - - - H6 VSS S - - - - - - - H7 VSS S - - - - - - - H8 VSS S - - - - - - - H9 VSS S - - - - - - - H10 VSS S - - - - - - - J6 VSS S - - - - - - - J7 VSS S - - - - - - - J8 VSS S - - - - - - - J9 VSS S - - - - - - - J10 VSS S - - - - 68/201 Pin name (function after reset)(1) DS12536 Rev 1 Additional functions STM32F730x8 Pinouts and pin description Table 10. STM32F730x8 pin and ball definition (continued) LQFP144 UFBGA176 I/O structure Notes LQFP100 Pin type Alternate functions LQFP64 Pin Number - - - K6 VSS S - - - - - - - K7 VSS S - - - - - - - K8 VSS S - - - - - - - K9 VSS S - - - - - - - K10 VSS S - - - - Pin name (function after reset)(1) Additional functions 1. Function availability depends on the chosen device. 2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF. - These I/Os must not be used as a current source (e.g. to drive an LED). 3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). 4. ULPI signals are not available when the USB HS PHY is available. 5. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1). 6. If the device is in regulator OFF/internal reset ON mode (BYPASS_REG pin is set to VDD), then PA0 is used as an internal reset (active low). DS12536 Rev 1 69/201 83 Pinouts and pin description STM32F730x8 Table 11. FMC pin definition 70/201 Pin name NOR/PSRAM/SR AM NOR/PSRAM Mux NAND16 SDRAM PF0 A0 - - A0 PF1 A1 - - A1 PF2 A2 - - A2 PF3 A3 - - A3 PF4 A4 - - A4 PF5 A5 - - A5 PF12 A6 - - A6 PF13 A7 - - A7 PF14 A8 - - A8 PF15 A9 - - A9 PG0 A10 - - A10 PG1 A11 - - A11 PG2 A12 - - A12 PG3 A13 - - - PG4 A14 - - BA0 PG5 A15 - - BA1 PD11 A16 A16 CLE - PD12 A17 A17 ALE - PD13 A18 A18 - - PE3 A19 A19 - - PE4 A20 A20 - - PE5 A21 A21 - - PE6 A22 A22 - - PE2 A23 A23 - - PG13 A24 A24 - - PG14 A25 A25 - - PD14 D0 DA0 D0 D0 PD15 D1 DA1 D1 D1 PD0 D2 DA2 D2 D2 PD1 D3 DA3 D3 D3 PE7 D4 DA4 D4 D4 PE8 D5 DA5 D5 D5 PE9 D6 DA6 D6 D6 PE10 D7 DA7 D7 D7 DS12536 Rev 1 STM32F730x8 Pinouts and pin description Table 11. FMC pin definition (continued) Pin name NOR/PSRAM/SR AM NOR/PSRAM Mux NAND16 SDRAM PE11 D8 DA8 D8 D8 PE12 D9 DA9 D9 D9 PE13 D10 DA10 D10 D10 PE14 D11 DA11 D11 D11 PE15 D12 DA12 D12 D12 PD8 D13 DA13 D13 D13 PD9 D14 DA14 D14 D14 PD10 D15 DA15 D15 D15 PH8 D16 - - D16 PH9 D17 - - D17 PH10 D18 - - D18 PH11 D19 - - D19 PH12 D20 - - D20 PH13 D21 - - D21 PH14 D22 - - D22 PH15 D23 - - D23 PI0 D24 - - D24 PI1 D25 - - D25 PI2 D26 - - D26 PI3 D27 - - D27 PI6 D28 - - D28 PI7 D29 - - D29 PI9 D30 - - D30 PI10 D31 - - D31 PD7 NE1 NE1 - - PG9 NE2 NE2 NCE - PG10 NE3 NE3 - - PG11 - - - - PG12 NE4 NE4 - - PD3 CLK CLK - - PD4 NOE NOE NOE - PD5 NWE NWE NWE - PD6 NWAIT NWAIT NWAIT - PB7 NADV NADV - - DS12536 Rev 1 71/201 83 Pinouts and pin description STM32F730x8 Table 11. FMC pin definition (continued) 72/201 Pin name NOR/PSRAM/SR AM NOR/PSRAM Mux NAND16 SDRAM PF6 - - - - PF7 - - - - PF8 - - - - PF9 - - - - PF10 - - - - PG6 - - - - PG7 - - INT - PE0 NBL0 NBL0 - NBL0 PE1 NBL1 NBL1 - NBL1 PI4 NBL2 - - NBL2 PI5 NBL3 - - NBL3 PG8 - - - SDCLK PC0 - - - SDNWE PF11 - - - SDNRAS PG15 - - - SDNCAS PH2 - - - SDCKE0 PH3 - - - SDNE0 PH6 - - - SDNE1 PH7 - - - SDCKE1 PH5 - - - SDNWE PC2 - - - SDNE0 PC3 - - - SDCKE0 PB5 - - - SDCKE1 PB6 - - - SDNE1 DS12536 Rev 1 AF0 AF1 AF2 AF3 AF4 TIM3/4/5 TIM8/9/10/1 1/LPTIM1 I2C1/2/3/U SART1 Port SYS DS12536 Rev 1 Port A TIM1/2 AF5 AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ 6/UART4/5/7/ ADSPI/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS - TIM2_CH1 /TIM2_ET TIM5_CH1 R TIM8_ETR - - - USART2_CT S UART4_ TX - SAI2_SD_B - - EVEN TOUT PA1 - TIM2_CH2 TIM5_CH2 - - - - USART2_RT S UART4_RX QUADSPI_ BK1_IO3 SAI2_MCK _B - - EVEN TOUT PA2 - TIM2_CH3 TIM5_CH3 TIM9_CH1 - - - USART2_TX SAI2_SCK_B - - - - EVEN TOUT PA3 - TIM2_CH4 TIM5_CH4 TIM9_CH2 - - - USART2_RX - - OTG_HS_U LPI_D0 - - EVEN TOUT PA4 - - - - - SPI1_NSS SPI3_NSS USART2_CK /I2S1_WS /I2S3_WS - - - - OTG_HS_ SOF EVEN TOUT PA5 - TIM2_CH1 /TIM2_ET R - TIM8_CH1 N - SPI1_SCK /I2S1_CK - - - - OTG_HS_U LPI_CK - - EVEN TOUT PA6 - TIM1_BKI N TIM3_CH1 TIM8_BKIN - SPI1_MIS O - - - TIM13_CH1 - - - EVEN TOUT PA7 - TIM1_CH1 TIM3_CH2 N TIM8_CH1 N - SPI1_MO SI/I2S1_S D - - - TIM14_CH1 - - FMC_SDN WE EVEN TOUT PA8 MCO1 TIM1_CH1 - TIM8_BKIN 2 I2C3_SCL - - USART1_CK - - OTG_FS_S OF - - EVEN TOUT PA9 - TIM1_CH2 - - I2C3_SMB A SPI2_SCK /I2S2_CK - USART1_TX - - - - - EVEN TOUT PA10 - TIM1_CH3 - - - - - USART1_RX - - OTG_FS_I D - - EVEN TOUT PA11 - TIM1_CH4 - - - - - USART1_CT S - CAN1_RX OTG_FS_D M - - EVEN TOUT 73/201 Pinouts and pin description PA0 STM32F730x8 Table 12. STM32F730x8 alternate function mapping AF0 AF1 AF2 AF3 AF4 I2C1/2/3/U SART1 Port AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS TIM1/2 TIM3/4/5 PA12 - TIM1_ETR - - - - - USART1_RT S SAI2_FS_B CAN1_TX OTG_FS_D P - - EVEN TOUT PA13 JTMSSWDIO - - - - - - - - - - - - EVEN TOUT PA14 JTCKSWCLK - - - - - - - - - - - - EVEN TOUT PA15 JTDI TIM2_CH1 /TIM2_ET R - - - - UART4_RTS - - - - EVEN TOUT PB0 - TIM1_CH2 TIM3_CH3 N TIM8_CH2 N - - - - UART4_CTS - OTG_HS_U LPI_D1 - - EVEN TOUT PB1 - TIM1_CH3 TIM3_CH4 N TIM8_CH3 N - - - - - - OTG_HS_U LPI_D2 - - EVEN TOUT PB2 - - - - - - SAI1_SD_ A SPI3_MOSI/I 2S3_SD - QUADSPI_ CLK - - - EVEN TOUT PB3 JTDO/TR ACESWO TIM2_CH2 - - - SPI1_SCK SPI3_SCK /I2S1_CK /I2S3_CK - - - SDMMC2_ D2 - - EVEN TOUT PB4 NJTRST - TIM3_CH1 - - SPI1_MIS O SPI3_MIS O SPI2_NSS/I2 S2_WS - - SDMMC2_ D3 - - EVEN TOUT PB5 - - TIM3_CH2 - I2C1_SMB A SPI1_MO SI/I2S1_S D SPI3_MO SI/I2S3_S D - - - OTG_HS_U LPI_D7 - FMC_SDC KE1 EVEN TOUT PB6 - - TIM4_CH1 - I2C1_SCL - - USART1_TX - - QUADSPI_ BK1_NCS - FMC_SDN E1 EVEN TOUT PB7 - - TIM4_CH2 - I2C1_SDA - - USART1_RX - - - - FMC_NL EVEN TOUT PB8 - - TIM4_CH3 TIM10_CH 1 I2C1_SCL - - - - CAN1_RX SDMMC2_ D4 - SDMMC1 _D4 EVEN TOUT SPI1_NSS SPI3_NSS /I2S1_WS /I2S3_WS DS12536 Rev 1 STM32F730x8 SYS TIM8/9/10/1 1/LPTIM1 Port A Port B AF5 Pinouts and pin description 74/201 Table 12. STM32F730x8 alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 TIM3/4/5 TIM8/9/10/1 1/LPTIM1 I2C1/2/3/U SART1 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS TIM4_CH4 TIM11_CH1 I2C1_SDA SPI2_NSS /I2S2_WS - - - CAN1_TX Port Port B AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS SDMMC2_ D5 - SDMMC1 _D5 EVEN TOUT DS12536 Rev 1 SYS TIM1/2 PB9 - - PB10 - TIM2_CH3 - - I2C2_SCL SPI2_SCK /I2S2_CK - USART3_TX - - OTG_HS_U LPI_D3 - - EVEN TOUT PB11 - TIM2_CH4 - - I2C2_SDA - - USART3_RX - - OTG_HS_U LPI_D4 - - EVEN TOUT PB12 - TIM1_BKI N - - I2C2_SMB A SPI2_NSS /I2S2_WS - USART3_CK - - OTG_HS_U LPI_D5 - OTG_HS_ ID EVEN TOUT PB13 - TIM1_CH1 N - - - SPI2_SCK /I2S2_CK - USART3_CT S - - OTG_HS_U LPI_D6 - - EVEN TOUT PB14 - TIM1_CH2 N - TIM8_CH2 N - SPI2_MIS O - USART3_RT S - TIM12_CH1 SDMMC2_ D0 - OTG_HS_ DM EVEN TOUT RTC_REF TIM1_CH3 IN N - TIM8_CH3 N - SPI2_MO SI/I2S2_S D - - - TIM12_CH2 SDMMC2_ D1 - OTG_HS_ DP EVEN TOUT PB15 - - - - - - - - SAI2_FS_B - OTG_HS_U LPI_STP - FMC_SDN WE EVEN TOUT PC1 TRACED0 - - - - SPI2_MO SI/I2S2_S D SAI1_SD_ A - - - - - - EVEN TOUT PC2 - - - - - SPI2_MIS O - - - - OTG_HS_U LPI_DIR - FMC_SDN E0 EVEN TOUT PC3 - - - - - SPI2_MO SI/I2S2_S D - - - - OTG_HS_U LPI_NXT - FMC_SDC KE0 EVEN TOUT Port C 75/201 Pinouts and pin description PC0 STM32F730x8 Table 12. STM32F730x8 alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 I2C1/2/3/U SART1 Port AF5 AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS DS12536 Rev 1 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1/LPTIM1 PC4 - - - - - I2S1_MCK - - - - - - FMC_SDN E0 EVEN TOUT PC5 - - - - - - - - - - - - FMC_SDC KE0 EVEN TOUT PC6 - - TIM3_CH1 TIM8_CH1 - I2S2_MCK - - USART6_TX - SDMMC2_ D6 - SDMMC1 _D6 EVEN TOUT PC7 - - TIM3_CH2 TIM8_CH2 - - I2S3_MCK - USART6_RX - SDMMC2_ D7 - SDMMC1 _D7 EVEN TOUT PC8 TRACED1 - TIM3_CH3 TIM8_CH3 - - - UART5_RTS USART6_CK - - - SDMMC1 _D0 EVEN TOUT PC9 MCO2 - TIM3_CH4 TIM8_CH4 I2C3_SDA I2S_CKIN - UART5_CTS - QUADSPI_ BK1_IO0 - - SDMMC1 _D1 EVEN TOUT PC10 - - - - - - SPI3_SCK /I2S3_CK USART3_TX UART4_TX QUADSPI_ BK1_IO1 - - SDMMC1 _D2 EVEN TOUT PC11 - - - - - - SPI3_MIS O USART3_RX UART4_RX QUADSPI_ BK2_NCS - - SDMMC1 _D3 EVEN TOUT PC12 TRACED3 - - - - - SPI3_MO SI/I2S3_S D USART3_CK UART5_TX - - - SDMMC1 _CK EVEN TOUT PC13 - - - - - - - - - - - - - EVEN TOUT PC14 - - - - - - - - - - - - - EVEN TOUT PC15 - - - - - - - - - - - - - EVEN TOUT Port C Pinouts and pin description 76/201 Table 12. STM32F730x8 alternate function mapping (continued) STM32F730x8 AF0 AF1 AF2 AF3 AF4 I2C1/2/3/U SART1 Port AF5 AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS DS12536 Rev 1 TIM1/2 TIM3/4/5 PD0 - - - - - - - - - CAN1_RX - - FMC_D2 EVEN TOUT PD1 - - - - - - - - - CAN1_TX - - FMC_D3 EVEN TOUT PD2 TRACED2 - TIM3_ETR - - - - - UART5_RX - - - SDMMC1 _CMD EVEN TOUT PD3 - - - - - SPI2_SCK /I2S2_CK - USART2_CT S - - - - FMC_CLK EVEN TOUT PD4 - - - - - - - USART2_RT S - - - - FMC_NO E EVEN TOUT PD5 - - - - - - - USART2_TX - - - - FMC_NW E EVEN TOUT PD6 - - - - - SPI3_MO SI/I2S3_S D SAI1_SD_ A USART2_RX - - - SDMMC2 _CK FMC_NW AIT EVEN TOUT PD7 - - - - - - - USART2_CK - - - SDMMC2 _CMD FMC_NE1 EVEN TOUT PD8 - - - - - - - USART3_TX - - - - FMC_D13 EVEN TOUT PD9 - - - - - - - USART3_RX - - - - FMC_D14 EVEN TOUT PD10 - - - - - - - USART3_CK - - - - FMC_D15 EVEN TOUT PD11 - - - - - - - USART3_CT S - QUADSPI_ BK1_IO0 SAI2_SD_A - FMC_A16/ FMC_CLE EVEN TOUT PD12 - - TIM4_CH1 LPTIM1_IN 1 - - - USART3_RT S - QUADSPI_ BK1_IO1 SAI2_FS_A - FMC_A17/ FMC_ALE EVEN TOUT PD13 - - TIM4_CH2 LPTIM1_O UT - - - - - QUADSPI_ BK1_IO3 SAI2_SCK_ A - FMC_A18 EVEN TOUT PD14 - - TIM4_CH3 - - - - - UART8_CTS - - - FMC_D0 EVEN TOUT PD15 - - TIM4_CH4 - - - - - UART8_RTS - - - FMC_D1 EVEN TOUT Port D Port D Pinouts and pin description 77/201 SYS TIM8/9/10/1 1/LPTIM1 STM32F730x8 Table 12. STM32F730x8 alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 I2C1/2/3/U SART1 Port AF5 AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS DS12536 Rev 1 TIM1/2 TIM3/4/5 PE0 - - TIM4_ETR LPTIM1_ET R - - - - UART8_Rx - SAI2_MCK _A - FMC_NBL 0 EVEN TOUT PE1 - - - LPTIM1_IN 2 - - - - UART8_Tx - - - FMC_NBL 1 EVEN TOUT PE2 TRACECL K - - - - SPI4_SCK SAI1_MCL K_A - - QUADSPI_ BK1_IO2 - - FMC_A23 EVEN TOUT PE3 TRACED0 - - - - - SAI1_SD_ B - - - - - FMC_A19 EVEN TOUT PE4 TRACED1 - - - - SPI4_NSS SAI1_FS_ A - - - - - FMC_A20 EVEN TOUT PE5 TRACED2 - - TIM9_CH1 - SPI4_MIS O SAI1_SCK _A - - - - - FMC_A21 EVEN TOUT PE6 TRACED3 TIM1_BKI N2 - TIM9_CH2 - SPI4_MO SI SAI1_SD_ A - - - SAI2_MCK _B - FMC_A22 EVEN TOUT PE7 - TIM1_ETR - - - - - - UART7_Rx - QUADSPI_ BK2_IO0 - FMC_D4 EVEN TOUT PE8 - TIM1_CH1 N - - - - - - UART7_Tx - QUADSPI_ BK2_IO1 - FMC_D5 EVEN TOUT PE9 - TIM1_CH1 - - - - - - UART7_RTS - QUADSPI_ BK2_IO2 - FMC_D6 EVEN TOUT PE10 - TIM1_CH2 N - - - - - - UART7_CTS - QUADSPI_ BK2_IO3 - FMC_D7 EVEN TOUT PE11 - TIM1_CH2 - - - SPI4_NSS - - - - SAI2_SD_B - FMC_D8 EVEN TOUT PE12 - TIM1_CH3 N - - - SPI4_SCK - - - - SAI2_SCK_ B - FMC_D9 EVEN TOUT PE13 - TIM1_CH3 - - - SPI4_MIS O - - - - SAI2_FS_B - FMC_D10 EVEN TOUT PE14 - TIM1_CH4 - - - SPI4_MO SI - - - - SAI2_MCK _B - FMC_D11 EVEN TOUT PE15 - TIM1_BKI N - - - - - - - - - - FMC_D12 EVEN TOUT Port E Port E STM32F730x8 SYS TIM8/9/10/1 1/LPTIM1 Pinouts and pin description 78/201 Table 12. STM32F730x8 alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 I2C1/2/3/U SART1 Port DS12536 Rev 1 Port F AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS 79/201 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1/LPTIM1 PF0 - - - - I2C2_SDA - - - - - - - FMC_A0 EVEN TOUT PF1 - - - - I2C2_SCL - - - - - - - FMC_A1 EVEN TOUT PF2 - - - - I2C2_SMB A - - - - - - - FMC_A2 EVEN TOUT PF3 - - - - - - - - - - - - FMC_A3 EVEN TOUT PF4 - - - - - - - - - - - - FMC_A4 EVEN TOUT PF5 - - - - - - - - - - - - FMC_A5 EVEN TOUT PF6 - - - TIM10_CH 1 - SPI5_NSS SAI1_SD_ B - UART7_Rx QUADSPI_ BK1_IO3 - - - EVEN TOUT PF7 - - - TIM11_CH1 - SPI5_SCK SAI1_MCL K_B - UART7_Tx QUADSPI_ BK1_IO2 - - - EVEN TOUT PF8 - - - - - SPI5_MIS O SAI1_SCK _B - UART7_RTS TIM13_CH1 QUADSPI_ BK1_IO0 - - EVEN TOUT PF9 - - - - - SPI5_MO SI SAI1_FS_ B - UART7_CTS TIM14_CH1 QUADSPI_ BK1_IO1 - - EVEN TOUT PF10 - - - - - - - - - - - - - EVEN TOUT PF11 - - - - - SPI5_MO SI - - - - SAI2_SD_B - FMC_SDN RAS EVEN TOUT PF12 - - - - - - - - - - - - FMC_A6 EVEN TOUT PF13 - - - - - - - - - - - - FMC_A7 EVEN TOUT PF14 - - - - - - - - - - - - FMC_A8 EVEN TOUT PF15 - - - - - - - - - - - - FMC_A9 EVEN TOUT Pinouts and pin description Port F AF5 STM32F730x8 Table 12. STM32F730x8 alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 I2C1/2/3/U SART1 Port DS12536 Rev 1 Port G AF5 AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1/LPTIM1 PG0 - - - - - - - - - - - - FMC_A10 EVEN TOUT PG1 - - - - - - - - - - - - FMC_A11 EVEN TOUT PG2 - - - - - - - - - - - - FMC_A12 EVEN TOUT PG3 - - - - - - - - - - - - FMC_A13 EVEN TOUT PG4 - - - - - - - - - - - - FMC_A14/ FMC_BA0 EVEN TOUT PG5 - - - - - - - - - - - - FMC_A15/ FMC_BA1 EVEN TOUT PG6 - - - - - - - - - - - - - EVEN TOUT PG7 - - - - - - - - USART6_CK - - - FMC_INT EVEN TOUT PG8 - - - - - - - - USART6_RT S - - - FMC_SDC LK EVEN TOUT PG9 - - - - - - - - USART6_RX QUADSPI_ BK2_IO2 SAI2_FS_B SDMMC2 _D0 FMC_NE2 /FMC_NC E EVEN TOUT PG10 - - - - - - - - - - SAI2_SD_B SDMMC2 _D1 FMC_NE3 EVEN TOUT Pinouts and pin description 80/201 Table 12. STM32F730x8 alternate function mapping (continued) STM32F730x8 AF0 AF1 AF2 AF3 AF4 I2C1/2/3/U SART1 Port Port G AF5 AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS DS12536 Rev 1 TIM1/2 TIM3/4/5 PG11 - - - - - - - - - - SDMMC2_ D2 - - EVEN TOUT PG12 - - - LPTIM1_IN 1 - - - - USART6_RT S - - SDMMC2 _D3 FMC_NE4 EVEN TOUT PG13 TRACED0 - - LPTIM1_O UT - - - - USART6_CT S - - - FMC_A24 EVEN TOUT PG14 TRACED1 - - LPTIM1_ET R - - - - USART6_TX QUADSPI_ BK2_IO3 - - FMC_A25 EVEN TOUT PG15 - - - - - - - - USART6_CT S - - - FMC_SDN CAS EVEN TOUT PH0 - - - - - - - - - - - - - EVEN TOUT PH1 - - - - - - - - - - - - - EVEN TOUT PH2 - - - LPTIM1_IN 2 - - - - - QUADSPI_ BK2_IO0 SAI2_SCK_ B - FMC_SDC KE0 EVEN TOUT PH3 - - - - - - - - - QUADSPI_ BK2_IO1 SAI2_MCK _B - FMC_SDN E0 EVEN TOUT PH4 - - - - I2C2_SCL - - - - - OTG_HS_U LPI_NXT - - EVEN TOUT PH5 - - - - I2C2_SDA SPI5_NSS - - - - - - FMC_SDN WE EVEN TOUT PH6 - - - - I2C2_SMB A SPI5_SCK - - - TIM12_CH1 - - FMC_SDN E1 EVEN TOUT PH7 - - - - I2C3_SCL SPI5_MIS O - - - - - - FMC_SDC KE1 EVEN TOUT Port H 81/201 Pinouts and pin description SYS TIM8/9/10/1 1/LPTIM1 STM32F730x8 Table 12. STM32F730x8 alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 I2C1/2/3/U SART1 Port AF5 AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS TIM1/2 TIM3/4/5 PH8 - - - - I2C3_SDA - - - - - - - FMC_D16 EVEN TOUT PH9 - - - - I2C3_SMB A - - - - TIM12_CH2 - - FMC_D17 EVEN TOUT PH10 - - TIM5_CH1 - - - - - - - - - FMC_D18 EVEN TOUT PH11 - - TIM5_CH2 - - - - - - - - - FMC_D19 EVEN TOUT PH12 - - TIM5_CH3 - - - - - - - - - FMC_D20 EVEN TOUT PH13 - - - TIM8_CH1 N - - - - UART4_TX CAN1_TX - - FMC_D21 EVEN TOUT PH14 - - - TIM8_CH2 N - - - - UART4_RX CAN1_RX - - FMC_D22 EVEN TOUT PH15 - - - TIM8_CH3 N - - - - - - - - FMC_D23 EVEN TOUT PI0 - - TIM5_CH4 - - SPI2_NSS /I2S2_WS - - - - - - FMC_D24 EVEN TOUT PI1 - - - TIM8_BKIN 2 - SPI2_SCK /I2S2_CK - - - - - - FMC_D25 EVEN TOUT PI2 - - - TIM8_CH4 - SPI2_MIS O - - - - - - FMC_D26 EVEN TOUT PI3 - - - TIM8_ETR - SPI2_MO SI/I2S2_S D - - - - - - FMC_D27 EVEN TOUT PI4 - - - TIM8_BKIN - - - - - - SAI2_MCK _A - FMC_NBL 2 EVEN TOUT PI5 - - - TIM8_CH1 - - - - - - SAI2_SCK_ A - FMC_NBL 3 EVEN TOUT PI6 - - - TIM8_CH2 - - - - - - SAI2_SD_A - FMC_D28 EVEN TOUT Port H DS12536 Rev 1 Port I STM32F730x8 SYS TIM8/9/10/1 1/LPTIM1 Pinouts and pin description 82/201 Table 12. STM32F730x8 alternate function mapping (continued) AF0 AF1 AF2 AF3 AF4 I2C1/2/3/U SART1 Port Port I AF5 AF6 AF7 AF8 AF9 AF10 SPI2/I2S2/ CAN1/TIM1 SAI2/QUAD SPI1/I2S1/ SPI2/I2S2/S SPI3/I2S3/ SAI2/USART 2/13/14/QU SPI/SDMM SPI2/I2S2/ PI3/I2S3/US SPI3/I2S3/ ADSPI/ 6/UART4/5/7/ C2/OTG2_ SPI3/I2S3/ ART1/2/3/UA SAI1/ 8/OTG1_FS FMC/ HS/OTG1_ SPI4/5 RT5 UART4 OTG2_HS FS AF11 AF12 AF15 SDMMC2 UART7/F MC/SDM MC1/ OTG2_FS SYS DS12536 Rev 1 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1/LPTIM1 PI7 - - - TIM8_CH3 - - - - - - SAI2_FS_A - FMC_D29 EVEN TOUT PI8 - - - - - - - - - - - - - EVEN TOUT PI9 - - - - - - - - UART4_RX CAN1_RX - - FMC_D30 EVEN TOUT PI10 - - - - - - - - - - - - FMC_D31 EVEN TOUT PI11 - - - - - - - - - - OTG_HS_U LPI_DIR - - EVEN TOUT PI12 - - - - - - - - - - - - - EVEN TOUT PI13 - - - - - - - - - - - - - EVEN TOUT PI14 - - - - - - - - - - - - - EVEN TOUT PI15 - - - - - - - - - - - - - EVEN TOUT STM32F730x8 Table 12. STM32F730x8 alternate function mapping (continued) Pinouts and pin description 83/201 Memory mapping 5 STM32F730x8 Memory mapping Refer to the product line reference manual for details on the memory mapping as well as the boundary addresses for all peripherals. 84/201 DS12536 Rev 1 STM32F730x8 6 6.1 Electrical characteristics Electrical characteristics Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 6.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3.3 V (for the 1.7 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 17. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 18. Figure 17. Pin loading conditions Figure 18. Pin input voltage MCU pin MCU pin C = 50 pF VIN MS19011V2 DS12536 Rev 1 MS19010V2 85/201 184 Electrical characteristics 6.1.6 STM32F730x8 Power supply scheme Figure 19. STM32F730x8 power supply scheme VBAT IN V DDSDMMC V DDSDMMC OUT PG[9..12], PD[6,7] IN 2 x 2.2 F VDD IO Logic IO Logic VCAP_1 VCAP_2 VDD 1/2/...11/12 12 x 100 nF + 1 x 4.7 F Level shifter GP I/Os Level shifter OUT 100 nF + 1 F Backup circuitry (OSC32K,RTC, Wakeup logic Backup registers, backup RAM) Power switch VBAT = 1.65 to 3.6V Voltage regulator VSS 1/2/...11/12 Flash memory BYPASS_REG VDDUSB VDDUSB 100 nF + 1 F PDR_ON VDD OTG FS PHY Reset controller VDDA VREF 100 nF + 1 F Kernel logic (CPU, digital & RAM) 100 nF + 1 F VREF+ VREF- ADC Analog: RCs, PLL, ... VSSA MSv42076V2 1. The two 2.2 F ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF. 2. The 4.7 F ceramic capacitor must be connected to one of the VDD pin. 3. VDDA=VDD and VSSA=VSS. 86/201 DS12536 Rev 1 STM32F730x8 Electrical characteristics Figure 20. STM32F730x8 power supply scheme VBAT Backup circuitry (OSC32K,RTC, Wakeup logic Backup registers, backup RAM) OUT GP I/Os IN V DDSDMMC Level shifter Power switch VBAT = 1.65 to 3.6V IO Logic OUT IN OUT PA[11,12], PB[14,15] VDDUSB IN VDDUSB Level shifter PG[9..12], PD[6,7] Level shifter VDDSDMMC 100 nF + 1 F IO Logic IO Logic 100 nF + 1 F OTG FS PHY Kernel logic (CPU, digital & RAM) V CAP_1 2 x 2.2 F V CAP_2 VDD V DD 1/2/...11/12 12 x 100 nF + 1 x 4.7 F Voltage regulator VSS 1/2/...11/12 Flash memory BYPASS_REG OTG HS PHY voltage regulator VDD12OTGHS 2.2 F 3 Kohm +/-1% PDR_ON VDD Reset controller VDDA VREF 100 nF + 1 F OTG HS PHY OTG_HS_REXT 100 nF + 1 F VREF+ VREF- ADC Analog: RCs, PLL, ... VSSA MSv42069V1 1. The VDDUSB allows supplying the PHY FS in PA11/PA12 and the PHY HS on PB14/PB15. DS12536 Rev 1 87/201 184 Electrical characteristics STM32F730x8 2. The two 2.2 F ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF. 3. The 4.7 F ceramic capacitor must be connected to one of the VDD pin. 4. VDDA=VDD and VSSA=VSS. Caution: Each power supply pair (VDD/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure good operation of the device. It is not recommended to remove filtering capacitors to reduce PCB size or cost. This might cause incorrect operation of the device. 6.1.7 Current consumption measurement Figure 21. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 13: Voltage characteristics, Table 14: Current characteristics, and Table 15: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. The device mission profile (application conditions) is compliant with JEDEC JESD47 Qualification Standard. Extended mission profiles are available on demand. Table 13. Voltage characteristics Symbol VDD-VSS VIN Ratings Min Max - 0.3 4.0 Input voltage on FT pins(2) VSS - 0.3 VDD+4.0 Input voltage on TTa pins VSS - 0.3 4.0 Input voltage on any other pin VSS - 0.3 4.0 VSS 9.0 External main supply voltage (including VDDA, VDD, VBAT, VDDUSB and VDDSDMMC) (1) Input voltage on BOOT pin 88/201 DS12536 Rev 1 Unit V STM32F730x8 Electrical characteristics Table 13. Voltage characteristics (continued) Symbol |VDDx| |VSSX -VSS| VESD(HBM) Ratings Min Max Variations between different VDD power pins - 50 Variations between all the different ground pins(3) - 50 Electrostatic discharge voltage (human body model) Unit mV see Section 6.3.18: Absolute maximum ratings (electrical sensitivity) - 1. All main power (VDD, VDDA, VDDSDMMC, VDDUSB) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum value must always be respected. Refer to Table 14 for the values of the maximum allowed injected current. 3. Include VREF- pin. Table 14. Current characteristics Symbol Ratings Max. IVDD Total current into sum of all VDD_x power lines (source)(1) IVSS (sink)(1) Total current out of sum of all VSS_x ground lines IVDDUSB IVDDSDMMC IVDDSDMMC 300 - 300 Total current into VDDUSB power line (source) 25 Total current into VDDSDMMC power line (source) Maximum current into each VDD_x power line IVDD 60 (source)(1) 100 Maximum current into VDDSDMMC power line (source): PG[12:9], PD[7:6] Maximum current out of each VSS_x ground line (sink)(1) IVSS 25 Total output current sunk by sum of all I/O and control pins (2) 120 Total output current sunk by sum of all USB I/Os 25 (2) Total output current sourced by sum of all I/Os and control pins IINJ(PIN) IINJ(PIN) (4) Injected current on FT, FTf, RST and B pins (3) mA - 25 Output current sourced by any I/Os and control pin IIO 100 - 100 Output current sunk by any I/O and control pin IIO Unit - 120 - 5/+0 Injected current on TTa pins(4) 5 Total injected current (sum of all I/O and control pins)(5) 25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages. 3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A positive injection is induced by VIN>VDDA while a negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer to Table 13: Voltage characteristics for the values of the maximum allowed input voltage. 5. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). DS12536 Rev 1 89/201 184 Electrical characteristics STM32F730x8 Table 15. Thermal characteristics Symbol Ratings TSTG Value - 65 to +150 Storage temperature range Maximum junction temperature TJ 6.3 Operating conditions 6.3.1 General operating conditions Unit C 125 Table 16. General operating conditions Symbol Conditions(1) Parameter Power Scale 3 (VOS[1:0] bits in PWR_CR register = 0x01), Regulator ON, over-drive OFF fHCLK Internal AHB clock frequency fPCLK1 Internal APB1 clock frequency fPCLK2 Internal APB2 clock frequency VDD VDDA(4)(5) VDDUSB VBAT Analog operating voltage (ADC limited to 1.2 M samples) Analog operating voltage (ADC limited to 2.4 M samples) USB supply voltage (supply voltage for PA11,PA12, PB14 and PB15 pins) Typ Max 0 - 144 - 168 - 180 - 180 - 216(2) 0 Over-drive OFF 0 - 45 Over-drive ON 0 - 54 Over-drive OFF 0 - 90 Over-drive ON 0 - 108 1.7(3) - 3.6 1.7(3) - 2.4 2.4 - 3.6 USB not used 1.7 3.3 3.6 USB used 3.0 - 3.6 - 1.65 - 3.6 It can be different from VDD 1.7 - 3.6 - Must be the same potential as VDD Backup operating voltage DS12536 Rev 1 Unit 0 Overdrive Power Scale 1 (VOS[1:0] bits in OFF PWR_CR register= 0x11), OverRegulator ON drive ON Standard operating voltage SDMMC2 supply voltage VDDSDMMC (supply voltage for PG[12:9] and PD6 pins) 90/201 Overdrive Power Scale 2 (VOS[1:0] bits in OFF PWR_CR register = 0x10), OverRegulator ON drive ON Min MHz (6) V STM32F730x8 Electrical characteristics Table 16. General operating conditions (continued) Symbol Min Typ Max Power Scale 3 ((VOS[1:0] bits in PWR_CR register = 0x01), 144 MHz HCLK max frequency 1.08 1.14 1.20 Power Scale 2 ((VOS[1:0] bits in PWR_CR register = 0x10), 168 MHz HCLK max frequency with over-drive OFF or 180 MHz with over-drive ON 1.20 1.26 1.32 Power Scale 1 ((VOS[1:0] bits in PWR_CR register = 0x11), 180 MHz HCLK max frequency with over-drive OFF or 216 MHz with over-drive ON 1.26 1.32 1.40 Regulator OFF: 1.2 V external voltage must be supplied from external regulator on VCAP_1/VCAP_2 pins(7) Max frequency 144 MHz 1.10 1.14 1.20 Max frequency 168MHz 1.20 1.26 1.32 Max frequency 180 MHz 1.26 1.32 1.38 Input voltage on RST and FT pins(8) 2 V VDD 3.6 V - 0.3 - 5.5 VDD 2 V - 0.3 - 5.2 Regulator ON: 1.2 V internal voltage on VCAP_1/VCAP_2 pins V12 VIN Conditions(1) Parameter - - 0.3 - VDDA+ 0.3 Input voltage on BOOT pin - 0 - 9 - - 881 - - 1117 - - 1587 - - 485 - 40 - 85 - 40 - 105 - 40 - 105 - 40 - 125 6 suffix version - 40 - 105 7 suffix version - 40 - 125 LQFP64 PD UFBGA176 Ambient temperature for 6 suffix version Maximum power dissipation Ambient temperature for 7 suffix version Maximum power dissipation TA TJ V Input voltage on TTa pins Power dissipation at TA = 85 C LQFP100 for suffix 6 or TA = 105 C for LQFP144 suffix 7(9) Junction temperature range Low power dissipation Low power dissipation (10) (10) Unit mW C C C 1. The over-drive mode is not supported at the voltage ranges from 1.7 to 2.1 V. 2. 216 MHz maximum frequency for 6 suffix version (200 MHz maximum frequency for 7 suffix version). 3. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.15.2: Internal reset OFF). 4. When the ADC is used, refer to Table 67: ADC characteristics. 5. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V. 6. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and power-down operation. 7. The over-drive mode is not supported when the internal regulator is OFF. 8. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled 9. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax. 10. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax. DS12536 Rev 1 91/201 184 Electrical characteristics STM32F730x8 Table 17. Limitations depending on the operating power supply range Maximum Flash Maximum HCLK memory access frequency vs Flash frequency with memory wait states no wait states (1)(2) (fFlashmax) Possible Flash memory operations Operating power supply range ADC operation VDD =1.7 to 2.1 V(3) Conversion time up to 1.2 Msps 20 MHz 180 MHz with 8 wait No I/O states and over-drive compensation OFF 8-bit erase and program operations only VDD = 2.1 to 2.4 V Conversion time up to 1.2 Msps 22 MHz 216 MHz with 9 wait No I/O states and over-drive compensation ON 16-bit erase and program operations VDD = 2.4 to 2.7 V Conversion time up to 2.4 Msps 24 MHz 216 MHz with 8 wait I/O compensation states and over-drive works ON 16-bit erase and program operations VDD = 2.7 to 3.6 V(4) Conversion time up to 2.4 Msps 30 MHz 216 MHz with 7 wait I/O compensation states and over-drive works ON 32-bit erase and program operations I/O operation 1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is required. 2. Thanks to the ART accelerator on ITCM interface and L1-cache on AXI interface, the number of wait states given here does not impact the execution speed from Flash memory since the ART accelerator or L1-cache allows to achieve a performance equivalent to 0-wait state program execution. 3. VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.15.2: Internal reset OFF). 4. The voltage range for USB full speed PHYs can drop down to 2.7 V. However the electrical characteristics of D- and D+ pins will be degraded between 2.7 and 3 V. 6.3.2 VCAP1/VCAP2 external capacitor Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to the VCAP1/VCAP2 pins. CEXT is specified in Table 18. Note: The VCAP2 pin is not available on the LQFP64 package. Figure 22. External capacitor CEXT C ESR R Leak MS19044V2 1. Legend: ESR is the equivalent series resistance. Table 18. VCAP1/VCAP2 operating conditions(1) 92/201 Symbol Parameter Conditions CEXT Capacitance of external capacitor 2.2 F ESR ESR of external capacitor <2 DS12536 Rev 1 STM32F730x8 Electrical characteristics 1. When bypassing the voltage regulator, the two 2.2 F VCAP capacitors are not required and should be replaced by two 100 nF decoupling capacitors. Table 19. VCAP1 operating conditions in the LQFP64 package(1) Symbol Parameter Conditions CEXT Capacitance of external capacitor 4.7 F ESR ESR of external capacitor between 0.1 and 0.2 1. When bypassing the voltage regulator, the 4.7 F VCAP capacitor is not required and should be replaced by two 100 nF decoupling capacitors. 6.3.3 Operating conditions at power-up / power-down (regulator ON) Subject to general operating conditions for TA. Table 20. Operating conditions at power-up / power-down (regulator ON) Symbol tVDD 6.3.4 Parameter Min Max VDD rise time rate 20 VDD fall time rate 20 Unit s/V Operating conditions at power-up / power-down (regulator OFF) Subject to general operating conditions for TA. Table 21. Operating conditions at power-up / power-down (regulator OFF)(1) Symbol tVDD tVCAP Parameter Conditions Min Max VDD rise time rate Power-up 20 VDD fall time rate Power-down 20 VCAP_1 and VCAP_2 rise time rate Power-up 20 VCAP_1 and VCAP_2 fall time rate Power-down 20 Unit s/V 1. To reset the internal logic at power-down, a reset must be applied on pin PA0 when VDD reach below 1.08 V. 6.3.5 Reset and power control block characteristics The parameters given in Table 22 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 16. DS12536 Rev 1 93/201 184 Electrical characteristics STM32F730x8 Table 22. reset and power control block characteristics Symbol VPVD Parameter Conditions Programmable voltage detector level selection VPVDhyst(1) PVD hysteresis VPOR/PDR Power-on/power-down reset threshold Min Typ Max Unit PLS[2:0]=000 (rising edge) 2.09 2.14 2.19 V PLS[2:0]=000 (falling edge) 1.98 2.04 2.08 V PLS[2:0]=001 (rising edge) 2.23 2.30 2.37 V PLS[2:0]=001 (falling edge) 2.13 2.19 2.25 V PLS[2:0]=010 (rising edge) 2.39 2.45 2.51 V PLS[2:0]=010 (falling edge) 2.29 2.35 2.39 V PLS[2:0]=011 (rising edge) 2.54 2.60 2.65 V PLS[2:0]=011 (falling edge) 2.44 2.51 2.56 V PLS[2:0]=100 (rising edge) 2.70 2.76 2.82 V PLS[2:0]=100 (falling edge) 2.59 2.66 2.71 V PLS[2:0]=101 (rising edge) 2.86 2.93 2.99 V PLS[2:0]=101 (falling edge) 2.65 2.84 2.92 V PLS[2:0]=110 (rising edge) 2.96 3.03 3.10 V PLS[2:0]=110 (falling edge) 2.85 2.93 2.99 V PLS[2:0]=111 (rising edge) 3.07 3.14 3.21 V PLS[2:0]=111 (falling edge) 2.95 3.03 3.09 V - 100 - mV Falling edge 1.60 1.68 1.76 V Rising edge 1.64 1.72 1.80 V - 40 - mV - VPDRhyst(1) PDR hysteresis 94/201 - VBOR1 Brownout level 1 threshold Falling edge 2.13 2.19 2.24 V Rising edge 2.23 2.29 2.33 V VBOR2 Brownout level 2 threshold Falling edge 2.44 2.50 2.56 V Rising edge 2.53 2.59 2.63 V VBOR3 Brownout level 3 threshold Falling edge 2.75 2.83 2.88 V Rising edge 2.85 2.92 2.97 V VBORhyst(1) BOR hysteresis - - 100 - mV TRSTTEMPO (1)(2) POR reset temporization - 0.5 1.5 3.0 ms IRUSH(1) InRush current on voltage regulator poweron (POR or wakeup from Standby) - - 160 250 mA ERUSH(1) InRush energy on voltage regulator power- VDD = 1.7 V, TA = 105 C, on (POR or wakeup IRUSH = 171 mA for 31 s from Standby) - - 5.4 C DS12536 Rev 1 STM32F730x8 Electrical characteristics 1. Guaranteed by design. 2. The reset temporization is measured from the power-on (POR reset or wakeup from VBAT) to the instant when first instruction is read by the user application code. 6.3.6 Over-drive switching characteristics When the over-drive mode switches from enabled to disabled or disabled to enabled, the system clock is stalled during the internal voltage set-up. The over-drive switching characteristics are given in Table 23. They are sbject to general operating conditions for TA. Table 23. Over-drive switching characteristics(1) Symbol Tod_swen Parameter Conditions Min Typ Max HSI - 45 - 45 - 100 - 40 - - 20 - 20 - 80 - 15 - HSE max for 4 MHz Over_drive switch and min for 26 MHz enable time External HSE 50 MHz HSI Tod_swdis HSE max for 4 MHz Over_drive switch and min for 26 MHz. disable time External HSE 50 MHz Unit s 1. Guaranteed by design. 6.3.7 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 21: Current consumption measurement scheme. All the run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark code. DS12536 Rev 1 95/201 184 Electrical characteristics STM32F730x8 Typical and maximum current consumption The MCU is placed under the following conditions: * All I/O pins are in input mode with a static value at VDD or VSS (no load). * All peripherals are disabled except if it is explicitly mentioned. * The Flash memory access time is adjusted both to fHCLK frequency and VDD range (see Table 17: Limitations depending on the operating power supply range). * When the regulator is ON, the voltage scaling and over-drive mode are adjusted to fHCLK frequency as follows: - Scale 3 for fHCLK 144 MHz - Scale 2 for 144 MHz < fHCLK 168 MHz - Scale 1 for 168 MHz < fHCLK 216 MHz. The over-drive is only ON at 216 MHz. * When the regulator is OFF, the V12 is provided externally as described in Table 16: General operating conditions: * The system clock is HCLK, fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2. * External clock frequency is 25 MHz and PLL is ON when fHCLK is higher than 25 MHz. * The typical current consumption values are obtained for 1.7 V VDD 3.6 V voltage range and for TA= 25 C unless otherwise specified. * The maximum values are obtained for 1.7 V VDD 3.6 V voltage range and a maximum ambient temperature (TA) unless otherwise specified. * For the voltage range 1.7 V VDD 3.6 V, the maximum frequency is 180 MHz. Table 24. Typical and maximum current consumption in Run mode, code with data processing running from ITCM RAM, regulator ON Max(1) Symbol Parameter Conditions All peripherals enabled(2)(3) IDD Supply current in RUN mode All peripherals disabled(3) fHCLK (MHz) Typ 216 156 170(4) 180(4) 200 200 144 154 164.6 183 143(4) 158(4) 127 168 113 119 127.4 141 144 86 96 112.6 126 60 41 44 52.8 65 25 22 24 33.5 45 216 99 110(4) 119.6(4) 138.5 200 92 102 113.1 132 180 81 90(4) 96.7(4) 125(4) 168 72 78 86.5 100.1 144 55 61 77.1 90.8 60 24 25 38.5 50.3 25 12 13 26.3 38.1 DS12536 Rev 1 134 (4) 180 1. Guaranteed by characterization results. 96/201 Unit TA = 25 C TA = 85 C TA = 105 C mA STM32F730x8 Electrical characteristics 2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered. 3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC for the analog part. 4. Guaranteed by test in production. Table 25. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART ON except prefetch / L1-cache ON) or SRAM on AXI (L1-cache ON), regulator ON Max(1) Symbol Parameter Conditions All peripherals enabled(2)(3) IDD Supply current in RUN mode All peripherals disabled(3) fHCLK (MHz) Typ Unit 216 155.3 164 175.8 185 200 144.7 153.6 165.2 176 180 127.3 135 143.5 154 168 113.1 119.1 127.8 138 144 86.9 91.6 99.5 110 60 41.2 43.6 53.1 64 25 21.7 24 33.6 43.8 216 90 106 120.4 130 200 84 99 113.8 124 180 74 86.6 97.3 107 168 66 76 87 97 144 51 59 68.2 78 60 23 27 38.8 49 25 11 13.6 26.4 36.8 TA = 25 C TA = 85 C TA = 105 C mA 1. Guaranteed by characterization results. 2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered. 3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC for the analog part. DS12536 Rev 1 97/201 184 Electrical characteristics STM32F730x8 Table 26. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory or SRAM on AXI (L1-cache disabled), regulator ON Max(1) Symbol Parameter Conditions All peripherals enabled(2)(3) IDD Supply current in RUN mode All peripherals disabled(3) fHCLK (MHz) Typ Unit 216 129.3 137.6 162.8 173 200 122 128 153.2 163.3 180 108 117 136.4 146 168 99 104.5 122.3 132 144 80 84.7 99.3 109.2 60 42 45 59.5 70 25 23 23.4 37.8 48 216 73.3 82.3 107.4 119 200 70 77 101.8 113.5 180 62 71 90.2 101 168 59 63.6 81.4 92.1 144 49 53.3 67.9 79 60 26 31 45.1 56 25 14 16 30.6 41.2 TA= 25 C TA=85 C TA=105 C mA 1. Guaranteed by characterization results. 2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered. 3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC for the analog part. 98/201 DS12536 Rev 1 STM32F730x8 Electrical characteristics Table 27. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory on ITCM interface (ART disabled), regulator ON Max(1) Symbol Parameter Conditions All peripherals enabled(2)(3) IDD Supply current in RUN mode All peripherals disabled(3) fHCLK (MHz) Typ Unit 216 138 151 174.7 184 200 133 141 164.3 174 180 110 131 149.2 159 168 99 117 134 144 144 79 98 111.7 121 60 49 53 64 75 25 27 30 38.3 48 216 82 96 119.5 131 200 81 89 113.1 124 180 65 85 103.1 114 168 58 76 93.2 104 144 48 67 80.4 91 60 33 36 49.7 60 25 18 21 31.1 41 TA= 25 C TA=85 C TA=105 C mA 1. Guaranteed by characterization results. 2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered. 3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC for the analog part. DS12536 Rev 1 99/201 184 Electrical characteristics STM32F730x8 Table 28. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART ON except prefetch / L1-cache ON) or SRAM on AXI (L1-cache ON), regulator OFF Max(1) Symbol Parameter IDD12/ IDD Supply current in RUN mode from V12 and VDD supply Conditions All Peripherals Enabled(2)(3) All Peripherals Disabled(3) Typ fHCLK (MHz) TA= 25 C TA= 85 C TA= 105 C IDD12 IDD IDD12 IDD IDD12 IDD IDD12 IDD 180 112 1.4 120 2 132.7 2 142 2 168 110 1.4 106.4 2 118.7 2 130 2 144 78 1.3 82.5 2 93.6 2 103 2 60 37 1.1 37.6 2 49.3 2 60 2 25 19 1.1 18.5 2 30.4 2 40 2 180 74 1.4 78 2 89.3 2 99 2 168 64 1.4 68 2 80.1 2 90 2 144 51 1.3 54 2 63.5 2 74 2 60 22 1.1 24 2 35.2 2 45 2 25 10 1.2 12 2 23.2 2 35 2 Unit mA 1. Guaranteed by characterization results. 2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered. 3. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC for the analog part. 100/201 DS12536 Rev 1 STM32F730x8 Electrical characteristics Table 29. Typical and maximum current consumption in Sleep mode, regulator ON Max(1) Symbol Parameter Conditions fHCLK (MHz) Typ 216 82 96(3) 109.3(3) 128.3 200 77 84 103.4 122.6 180 67 72(3) 88.3(3) 120(3) 168 60 64 78.9 92.7 144 46 49 61.8 73.6 60 24 26 37.2 49 25 14 16 27 38.8 42.9(3) 62.2 All peripherals enabled(2) Supply current in SLEEP mode IDD All peripherals disabled Unit TA= 25 C TA=85 C TA=105 C 28 (3) 216 24 200 22 26 41.9 61.2 180 19 21(3) 33.2(3) 48(3) 168 17 19 30.1 43.9 144 13 15 24.6 36.3 60 7 9 20.5 32.3 25 5 7 18.8 30.6 mA 1. Guaranteed by characterization results. 2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered. 3. Guaranteed by test in production. Table 30. Typical and maximum current consumption in Sleep mode, regulator OFF Max(1) Symbol IDD12/ IDD Parameter Supply current in RUN mode from V12 and VDD supply Conditions All Peripherals Enabled(2) All Peripherals Disabled Typ fHCLK (MHz) TA= 25 C TA= 85 C TA= 105 C IDD12 IDD IDD12 IDD IDD12 IDD IDD12 IDD 180 62 1.3 67.5 2 84.4 2 95 2 168 55 1.3 59.8 2 75.4 2 86 2 144 43 1.3 46.3 2 59.6 2 70 2 60 22 1 24 2 35.8 2 46 2 25 13 1 15 2 25.8 2 36 2 180 17 1.3 19 2 31.4 2 42 2 168 15 1.3 17 2 28.4 2 40 2 144 12 1.2 14 2 23.2 2 33 2 60 5 1 6 2 19.3 2 29 2 25 3 1 4 2 17.6 2 28 2 DS12536 Rev 1 Unit mA 101/201 184 Electrical characteristics STM32F730x8 1. Guaranteed by characterization results. 2. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered. Table 31. Typical and maximum current consumptions in Stop mode Max(1) Typ Symbol IDD_STOP_NM (normal mode) Parameter Flash memory in Stop mode, Supply current in Stop all oscillators OFF, no IWDG mode, main regulator in Flash memory in Deep power Run mode down mode, all oscillators OFF Flash memory in Stop mode, all Supply current in Stop oscillators OFF, no IWDG mode, main regulator in Flash memory in Deep power Low-power mode down mode, all oscillators OFF, no IWDG Regulator in Run mode, Flash memory in Deep power down Supply current in Stop mode, all oscillators OFF, no IDD_STOP_UDM mode, main regulator in IWDG (under-drive Low voltage and underRegulator in Low-power mode, mode) drive modes Flash memory in Deep power down mode, all oscillators OFF, no IWDG 1. Data based on characterization, tested in production. 102/201 VDD = 3.6 V Conditions DS12536 Rev 1 Unit TA = 25 C TA = 25 C TA = TA = 85 C 105 C 0.45 2 12 22 0.4 2 12 22 0.32 1.5 10 18 0.27 1.5 10 18 0.15 0.8 5 7 0.1 0.7 4 7 mA STM32F730x8 Electrical characteristics Table 32. Typical and maximum current consumptions in Standby mode Typ(1) Symbol Parameter Max(2) TA = 25 C TA = 25 C Conditions VDD = VDD= VDD = 1.7 V 2.4 V 3.3 V TA = 85 C TA = 105 C VDD = 3.3 V Backup SRAM OFF, RTC and LSE OFF 1.09 1.13 1.4 4 27 55 Backup SRAM ON, RTC and LSE OFF 1.85 1.88 2.17 5 30 60 Backup SRAM OFF, RTC ON and LSE in low drive mode 1.65 1.86 2.43 7 47 95.5 Backup SRAM OFF, RTC ON and LSE in medium low drive mode 1.67 1.88 2.46 7 47.5 97 1.8 2.01 2.61 7.5 50.5 102.5 1.92 2.13 2.73 8 53 107 Backup SRAM ON, RTC ON and LSE in low drive mode 2.39 2.6 3.23 9 62 127 Backup SRAM ON, RTC ON and LSE in Medium low drive mode 2.41 2.64 3.25 9 63 128 Backup SRAM ON, RTC ON and LSE in Medium high drive mode 2.67 2.89 2.53 10 68 139 Backup SRAM ON, RTC ON and LSE in High drive mode 2.68 2.9 3.51 10 68 138 Backup SRAM OFF, RTC ON and LSE in medium high drive Supply current mode IDD_STBY in Standby Backup SRAM OFF, RTC ON mode and LSE in high drive mode Unit A 1. PDR is OFF for VDD=1.7V. When the PDR is OFF (internal reset OFF), the typical current consumption is reduced by additional 1.2 A. 2. Guaranteed by characterization results. DS12536 Rev 1 103/201 184 Electrical characteristics STM32F730x8 Table 33. Typical and maximum current consumptions in VBAT mode Symbol Parameter Typ Max(2) TA =25 C TA =85 C TA =105 C VBAT = VBAT= VBAT= 1.7 V 2.4 V 3.3 V VBAT = 3.6 V Conditions(1) Backup SRAM OFF, RTC and LSE OFF 0.035 0.037 0.043 4 10 Backup SRAM ON, RTC and LSE OFF 0.69 0.71 0.73 9 20 Backup SRAM OFF, RTC ON and LSE in low drive mode 0.57 0.74 1.05 98 244 Backup SRAM OFF, RTC ON and LSE in medium low drive mode 0.59 0.76 1.08 101 251 0.69 0.86 1.19 111 277 0.8 0.98 1.31 122 305 Backup SRAM ON, RTC ON and LSE in low drive mode 1.22 1.41 1.74 162 405 Backup SRAM ON, RTC ON and LSE in Medium low drive mode 1.25 1.43 1.78 166 414 Backup SRAM ON, RTC ON and LSE in Medium high drive mode 1.46 1.65 2.01 187 468 Backup SRAM ON, RTC ON and LSE in High drive mode 1.46 1.65 2.01 187 468 Backup SRAM OFF, RTC ON Supply current and LSE in medium high drive IDD_VBAT in VBAT mode mode Backup SRAM OFF, RTC ON and LSE in high drive mode 1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values. 2. Guaranteed by characterization results. 104/201 DS12536 Rev 1 Unit A STM32F730x8 Electrical characteristics Figure 23. Typical VBAT current consumption (RTC ON/BKP SRAM OFF and LSE in low drive mode) 4 3.5 3 IDD_VBAT (uA) 1.65 V 1.7 V 2.5 1.8 V 2 2V 2.4 V 1.5 2.7 V 3V 1 3.3 V 3.6 V 0.5 0 0 20 40 60 80 100 120 Temperature C MS37585V1 Figure 24. Typical VBAT current consumption (RTC ON/BKP SRAM OFF and LSE in medium low drive mode) 4.5 4 IDD_VBAT (uA) 3.5 1.65 V 3 1.7 V 1.8 V 2.5 2V 2 2.4 V 2.7 V 1.5 3V 1 3.3 V 3.6 V 0.5 0 0 20 40 60 Temperature C DS12536 Rev 1 80 100 120 MS37586V1 105/201 184 Electrical characteristics STM32F730x8 Figure 25. Typical VBAT current consumption (RTC ON/BKP SRAM OFF and LSE in medium high drive mode) 4.5 4 3.5 1.65 V IDD_VBAT (uA) 3 1.7 V 1.8 V 2.5 2V 2 2.4 V 2.7 V 1.5 3V 1 3.3 V 3.6 V 0.5 0 0 20 40 60 80 100 120 Temperature C MS37587V1 Figure 26. Typical VBAT current consumption (RTC ON/BKP SRAM OFF and LSE in high drive mode) 4.5 4 3.5 IDD_VBAT (uA) 3 1.65 V 1.7 V 2.5 1.8 V 2V 2 2.4 V 1.5 2.7 V 3V 1 3.3 V 3.6 V 0.5 0 0 106/201 20 40 60 80 Temperature C DS12536 Rev 1 100 120 MS37588V1 STM32F730x8 Electrical characteristics Figure 27. Typical VBAT current consumption (RTC ON/BKP SRAM OFF and LSE in high medium drive mode) 9 8 IDD_VBAT (uA) 7 1.65 V 6 1.7 V 5 1.8 V 2V 4 2.4 V 2.7 V 3 3V 3.3 V 2 3.6 V 1 0 0 20 40 60 Temperature( C) 80 100 120 MS37589V1 I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 61: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption (see Table 35: Peripheral current consumption), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O DS12536 Rev 1 107/201 184 Electrical characteristics STM32F730x8 pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I SW = V DD x f SW x C Where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDD is the MCU supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. Table 34. Switching output I/O current consumption(1) I/O toggling Symbol Parameter Conditions frequency (fsw) MHz Typ Typ VDD = 3.3 V VDD = 1.8 V 2 0.1 0.1 8 0.4 0.2 25 1.1 0.7 50 2.4 1.3 60 3.1 1.6 84 4.3 2.4 90 4.9 2.6 100 5.4 2.8 108 5.6 - 2 0.2 0.1 8 0.6 0.3 25 1.8 1.1 50 3.1 2.3 60 4.6 3.4 84 9.7 3.6 90 10.12 5.2 100 14.92 5.4 108 18.11 - CEXT = 0 pF C = CINT + CS + CEXT IDDIO I/O switching Current CEXT = 10 pF C = CINT + CS + CEXT 108/201 DS12536 Rev 1 Unit mA STM32F730x8 Electrical characteristics Table 34. Switching output I/O current consumption(1) (continued) I/O toggling Symbol Parameter Conditions frequency (fsw) MHz Typ Typ VDD = 3.3 V VDD = 1.8 V 2 0.3 0.1 8 1.0 0.5 25 3.5 1.6 50 5.9 4.2 60 10.0 4.4 84 19.12 5.8 90 19.6 - 2 0.3 0.2 8 1.3 0.7 25 3.5 2.3 50 10.26 5.19 60 16.53 - CEXT = 22 pF C = CINT + CS + CEXT I/O switching Current IDDIO CEXT = 33 pF C = CINT + CS + CEXT Unit mA 1. CINT + CS, PCB board capacitance including the pad pin is estimated to15 pF. On-chip peripheral current consumption The MCU is placed under the following conditions: * At startup, all I/O pins are in analog input configuration. * All peripherals are disabled unless otherwise mentioned. * I/O compensation cell enabled. * The ART/L1-cache is ON. * Scale 1 mode selected, internal digital voltage V12 = 1.32 V. * HCLK is the system clock. fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2. The given value is calculated by measuring the difference of current consumption * - with all peripherals clocked off - with only one peripheral clocked on - fHCLK = 216 MHz (Scale 1 + over-drive ON), fHCLK = 168 MHz (Scale 2), fHCLK = 144 MHz (Scale 3) Ambient operating temperature is 25 C and VDD=3.3 V. DS12536 Rev 1 109/201 184 Electrical characteristics STM32F730x8 Table 35. Peripheral current consumption IDD(Typ)(1) Peripheral AHB1 (up to 216 MHz) AHB2 (up to 216 MHz) AHB3 (up to 216 MHz) Scale 2 Scale 3 GPIOA 3.6 3.4 2.9 GPIOB 3.7 3.6 3.1 GPIOC 3.7 3.4 3.0 GPIOD 3.7 3.6 3.0 GPIOE 3.6 3.4 2.9 GPIOF 3.5 3.4 2.9 GPIOG 3.5 3.3 2.8 GPIOH 3.5 3.4 2.9 GPIOI 3.5 3.3 2.9 CRC 1.2 1.1 0.9 BKPSRAM 0.8 0.7 0.6 DMA1 3.07 x N + 8.7 2.98 x N + 8.4 2.52 x N + 7.02 DMA2 3.01 x N + 7.98 2.95 x N + 7.95 2.48 x N + 6.69 OTG_HS+ULPI 54.4 53.2 44.6 RNG 1.9 1.8 1.6 USB_OTG_FS 28.7 27.9 23.5 AES - - - FMC 16.2 15.8 13.3 QSPI 16.9 16.3 13.8 15.8 12.8 8.5 A/MHz A/MHz A/MHz Bus matrix(2) 110/201 Unit Scale 1 DS12536 Rev 1 A/MHz STM32F730x8 Electrical characteristics Table 35. Peripheral current consumption (continued) IDD(Typ)(1) Peripheral Scale 2 Scale 3 TIM2 19.3 18.2 15.6 TIM3 15 14 12.2 TIM4 15.7 15.1 12.8 TIM5 18 16.9 14.4 TIM6 3.7 3.1 2.8 TIM7 3.5 2.9 2.5 TIM12 8.1 7.8 6.4 TIM13 6.1 5.1 4.7 TIM14 6.3 5.6 4.7 LPTIM1 9.4 9.8 8.3 WWDG APB1 (up to 54 MHz) Unit Scale 1 2.4 1.3 1.4 (3) SPI2/I2S2 6.7 6 5.3 SPI3/I2S3(3) 4.8 3.8 3.3 USART2 13.3 12 10.6 USART3 12.8 12 10.3 UART4 11.7 10.7 9.2 UART5 11.7 10.2 8.9 I2C1 10.6 9.6 8.3 I2C2 10.6 9.6 8.3 I2C3 10.7 9.8 8.3 CAN1 8.9 8 6.9 PWR 11.3 11.3 8.9 DAC 6.1 5.1 4.4 UART7 13.3 12 10.3 UART8 12.6 11.6 9.7 (4) DS12536 Rev 1 A/MHz 111/201 184 Electrical characteristics STM32F730x8 Table 35. Peripheral current consumption (continued) IDD(Typ)(1) Peripheral APB2 (up to 108 MHz) Unit Scale 1 Scale 2 Scale 3 TIM1 24.9 23.8 20 TIM8 24.5 23.7 20 USART1 12.4 11.6 10 USART6 12.3 11.7 10 ADC1(5) 6.3 5.8 4.9 ADC2 (5) 6.3 5.6 4.9 ADC3 (5) 6.4 5.8 5 SDMMC1 9.1 8.3 7.1 SDMMC2 7 7.2 6 3.2 3.2 2.6 SPI4 2.9 2.9 2.2 SYSCFG 1 1 0.7 TIM9 9.9 9.1 7.8 TIM10 7 6.4 5.6 TIM11 7.2 6.8 5.7 SPI5 4.8 4.1 3.6 SAI1 5.6 4.9 4.2 SAI2 5.4 4.7 4 USB PHY HS Controller 8.3 7.9 6.7 (3) SPI1/I2S1 A/MHz 1. When the I/O compensation cell is ON, IDD typical value increases by 0.22 mA. 2. The BusMatrix is automatically active when at least one master is ON. 3. To enable an I2S peripheral, first set the I2SMOD bit and then the I2SE bit in the SPI_I2SCFGR register. 4. When the DAC is ON and EN1/2 bits are set in DAC_CR register, add an additional power consumption of 0.75 mA per DAC channel for the analog part. 5. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.73 mA per ADC for the analog part. 112/201 DS12536 Rev 1 STM32F730x8 Electrical characteristics USB OTG HS and USB OTG HS PHY current consumption The MCU is placed under the following conditions: * STM32 MCU is enumerated as a HID device. * fHCLK = 216 MHz (Scale 1 + over-drive ON), fHCLK = 168 MHz (Scale 2), fHCLK = 144 MHz (Scale 3) The given value is calculated by measuring the difference of current consumption in case: * - USB is configured but no transfer is done. - USB is configured and there is a transmission on going. Ambient operating temperature is 25 C, VDD = VDDUSB = 3.3 V. Table 36. USB OTG HS and USB OTG PHY HS current consumption IDD (Typ) USB OTG HS and USB OTG HS PHY current consumption 6.3.8 Unit Scale 1 Scale 2 Scale 3 50.16 44.92 38.98 mA Wakeup time from low-power modes The wakeup times given in Table 37 are measured starting from the wakeup event trigger up to the first instruction executed by the CPU: * For Stop or Sleep modes: the wakeup event is WFE. * WKUP (PA0) pin is used to wakeup from Standby, Stop and Sleep modes. All timings are derived from tests performed under ambient temperature and VDD=3.3 V. Table 37. Low-power mode wakeup timings Symbol tWUSLEEP(2) Parameter Wakeup from Sleep Conditions Typ(1) Max(1) Unit - 13 13 CPU clock cycles 14 14.9 104.1 107.6 21.4 24.2 111.5 116.5 Main regulator is ON Main regulator is ON and Flash memory in Deep power down mode tWUSTOP(2) Wakeup from Stop mode with MR/LP regulator in normal mode Low power regulator is ON Low power regulator is ON and Flash memory in Deep power down mode DS12536 Rev 1 s 113/201 184 Electrical characteristics STM32F730x8 Table 37. Low-power mode wakeup timings (continued) Symbol Parameter Conditions Main regulator in under-drive mode (Flash memory in Deep power-down Wakeup from Stop mode mode) with MR/LP regulator in Low power regulator in under-drive Under-drive mode mode (Flash memory in Deep power-down mode) tWUSTOP(2) tWUSTDBY(2) Wakeup from Standby mode Typ(1) Max(1) 107.4 113.2 Unit s 112.7 120 Exit Standby mode on rising edge 308 313 Exit Standby mode on falling edge 307 313 s 1. Guaranteed by characterization results. 2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first 6.3.9 External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 61: I/O static characteristics. However, the recommended clock input waveform is shown in Figure 28. The characteristics given in Table 38 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 16. Table 38. High-speed external user clock characteristics Symbol Parameter Min Typ Max Unit 1 - 50 MHz 0.7VDD - VDD VSS - 0.3VDD fHSE_ext External user clock source frequency(1) VHSEH OSC_IN input pin high level voltage VHSEL OSC_IN input pin low level voltage tw(HSE) tw(HSE) OSC_IN high or low time(1) 5 - - tr(HSE) tf(HSE) OSC_IN rise or fall time(1) - - 10 - - 5 - pF - 45 - 55 % VSS VIN VDD - - 1 A Cin(HSE) IL - V ns OSC_IN input capacitance(1) DuCy(HSE) Duty cycle OSC_IN Input leakage current 1. Guaranteed by design. 114/201 Conditions DS12536 Rev 1 STM32F730x8 Electrical characteristics Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The external clock signal has to respect the Table 61: I/O static characteristics. However, the recommended clock input waveform is shown in Figure 29. The characteristics given in Table 39 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 16. Table 39. Low-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit - 32.768 1000 kHz 0.7VDD - VDD VSS - 0.3VDD fLSE_ext User External clock source frequency(1) VLSEH OSC32_IN input pin high level voltage VLSEL OSC32_IN input pin low level voltage tw(LSE) tf(LSE) OSC32_IN high or low time(1) 450 - - tr(LSE) tf(LSE) OSC32_IN rise or fall time(1) - - 50 Cin(LSE) DuCy(LSE) IL - V ns OSC32_IN input capacitance(1) - - 5 - pF Duty cycle - 30 - 70 % VSS VIN VDD - - 1 A OSC32_IN Input leakage current 1. Guaranteed by design. Figure 28. High-speed external clock source AC timing diagram VHSEH 90 % 10 % VHSEL tr(HSE) tf(HSE) tW(HSE) t tW(HSE) THSE External clock source fHSE_ext OSC_IN IL STM32F ai17528 DS12536 Rev 1 115/201 184 Electrical characteristics STM32F730x8 Figure 29. Low-speed external clock source AC timing diagram VLSEH 90% VLSEL 10% tr(LSE) tf(LSE) tW(LSE) OSC32_IN IL tW(LSE) t TLSE fLSE_ext External clock source STM32F ai17529 High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 40. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 40. HSE 4-26 MHz oscillator characteristics(1) Symbol fOSC_IN RF IDD ACCHSE(2) Parameter Conditions Min Typ Max Unit Oscillator frequency - 4 - 26 MHz Feedback resistor - - 200 - k VDD=3.3 V, ESR= 30 , CL=5 pF@25 MHz - 450 - VDD=3.3 V, ESR= 30 , CL=10 pF@25 MHz - 530 - - - 500 - 500 ppm Startup - - 1 mA/V VDD is stabilized - 2 - ms HSE current consumption HSE accuracy Gm_crit_max Maximum critical crystal gm tSU(HSE(3) Startup time A 1. Guaranteed by design. 2. This parameter depends on the crystal used in the application. The minimum and maximum values must be respected to comply with USB standard specifications. 3. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is based on characterization results. It is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. 116/201 DS12536 Rev 1 STM32F730x8 Electrical characteristics For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 30). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. Figure 30. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 8 MHz resonator CL2 fHSE OSC_IN REXT(1) RF Bias controlled gain OSC_OU T STM32F ai17530 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 41. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 41. LSE oscillator characteristics (fLSE = 32.768 kHz) (1) Symbol IDD Parameter LSE current consumption Conditions Min Typ Max LSEDRV[1:0]=00 Low drive capability - 250 - LSEDRV[1:0]=10 Medium low drive capability - 300 - LSEDRV[1:0]=01 Medium high drive capability - 370 - LSEDRV[1:0]=11 High drive capability - 480 - DS12536 Rev 1 Unit nA 117/201 184 Electrical characteristics STM32F730x8 Table 41. LSE oscillator characteristics (fLSE = 32.768 kHz) (1) (continued) Symbol Parameter Gm_crit_max Maximum critical crystal gm tSU(2) Conditions Min Typ Max LSEDRV[1:0]=00 Low drive capability - - 0.48 LSEDRV[1:0]=10 Medium low drive capability - - 0.75 LSEDRV[1:0]=01 Medium high drive capability - - 1.7 LSEDRV[1:0]=11 High drive capability - - 2.7 VDD is stabilized - 2 - start-up time Unit A/V s 1. Guaranteed by design. 2. Guaranteed by characterization results. tSU is the start-up time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST Microelectronics website www.st.com. Figure 31. Typical application with a 32.768 kHz crystal Resonator with integrated capacitors C L1 f LSE OSC32_ IN 32.768 kHz resonator RF OSC32_ OU T C L2 Bias controlled gain STM32F ai17531a 118/201 DS12536 Rev 1 STM32F730x8 Internal clock source characteristics The parameters given in Table 42 and Table 43 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 16. High-speed internal (HSI) RC oscillator Table 42. HSI oscillator characteristics (1) Symbol fHSI Parameter Conditions Min Typ Max Unit Frequency - - 16 - MHz HSI user trimming step(2) - - - 1 % -8 - 4.5 % (3) ACCHSI TA = -40 to 105 C tsu(HSI)(2) IDD(HSI) (2) C(3) -4 - 4 % C(4) -1 - 1 % HSI oscillator startup time - - 2.2 4 s HSI oscillator power consumption - - 60 80 A Accuracy of the HSI oscillator TA = -10 to 85 TA = 25 1. VDD = 3.3 V, TA = -40 to 105 C unless otherwise specified. 2. Guaranteed by design. 3. Guaranteed by characterization results. 4. Factory calibrated, parts not soldered. Figure 32. ACCHSI versus temperature 6 4 2 ACCHSI(%) 6.3.10 Electrical characteristics 0 -40 0 25 55 85 -2 105 125 TA ( C) -4 Min Max Typical -6 -8 MSv41055V1 1. Guaranteed by characterization results. DS12536 Rev 1 119/201 184 Electrical characteristics STM32F730x8 Low-speed internal (LSI) RC oscillator Table 43. LSI oscillator characteristics (1) Symbol Parameter fLSI(2) tsu(LSI) Frequency Min Typ Max Unit 17 32 47 kHz (3) LSI oscillator startup time - 15 40 s (3) LSI oscillator power consumption - 0.4 0.6 A IDD(LSI) 1. VDD = 3 V, TA = -40 to 105 C unless otherwise specified. 2. Guaranteed by characterization results. 3. Guaranteed by design. Figure 33. LSI deviation versus temperature 8.0% 6.0% Normalized deviation (%) 4.0% 2.0% Min 0.0% Max -40C 0C 25C 85C 105C 125C Typical -2.0% -4.0% -6.0% -8.0% Temperature (C) 6.3.11 MS37554V1 PLL characteristics The parameters given in Table 44 and Table 45 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 16. Table 44. Main PLL characteristics Symbol Conditions Min Typ Max fPLL_IN PLL input clock(1) - 0.95(2) 1 2.10 fPLL_OUT PLL multiplier output clock - 24 - 216 fPLL48_OUT 48 MHz PLL multiplier output clock - - 48 75 fVCO_OUT PLL VCO output - 100 - 432 120/201 Parameter DS12536 Rev 1 Unit MHz STM32F730x8 Electrical characteristics Table 44. Main PLL characteristics (continued) Symbol tLOCK Parameter PLL lock time Conditions Min Typ Max VCO freq = 100 MHz 75 - 200 VCO freq = 432 MHz 100 - 300 - 25 - - 150 - - 15 - - 200 - RMS Cycle-to-cycle jitter System clock 216 MHz peak to peak RMS peak to peak Period Jitter Jitter(3) Unit s ps Main clock output (MCO) for RMII Ethernet Cycle to cycle at 50 MHz on 1000 samples - 32 - Main clock output (MCO) for MII Ethernet Cycle to cycle at 25 MHz on 1000 samples - 40 - Bit Time CAN jitter Cycle to cycle at 1 MHz on 1000 samples - 330 - IDD(PLL)(4) PLL power consumption on VDD VCO freq = 100 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLL)(4) PLL power consumption on VDDA VCO freq = 100 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 mA 1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between PLL and PLLI2S. 2. Guaranteed by design. 3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%. 4. Guaranteed by characterization results. Table 45. PLLI2S characteristics Symbol Parameter Conditions Min Typ Max fPLLI2S_IN PLLI2S input clock(1) - 0.95(2) 1 2.10 fPLLI2SQ_OUT PLLI2S multiplier output clock for SAI - - - 216 fPLLI2SR_OUT PLLI2S multiplier output clock for I2S - - - 216 fVCO_OUT PLLI2S VCO output - 100 - 432 tLOCK PLLI2S lock time VCO freq = 100 MHz 75 - 200 VCO freq = 432 MHz 100 - 300 Unit MHz DS12536 Rev 1 s 121/201 184 Electrical characteristics STM32F730x8 Table 45. PLLI2S characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit RMS - 90 - ps peak to peak - 280 - ps Average frequency of 12.288 MHz N = 432, R = 5 on 1000 samples - 90 - ps WS I2S clock jitter Cycle to cycle at 48 KHz on 1000 samples - 400 - ps IDD(PLLI2S)(4) PLLI2S power consumption on VDD VCO freq = 100 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLLI2S)(4) PLLI2S power consumption on VDDA VCO freq = 100 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 mA Unit Cycle to cycle at 12.288 MHz on 48KHz period, N=432, R=5 Master I2S clock jitter (3) Jitter 1. Take care of using the appropriate division factor M to have the specified PLL input clock values. 2. Guaranteed by design. 3. Value given with main PLL running. 4. Guaranteed by characterization results. Table 46. PLLISAI characteristics Symbol Parameter Conditions Min Typ Max fPLLSAI_IN PLLSAI input clock(1) - 0.95(2) 1 2.10 fPLLSAIP_OUT PLLSAI multiplier output clock for 48 MHz - - 48 75 fPLLSAIQ_OUT PLLSAI multiplier output clock for SAI - - - 216 fVCO_OUT PLLSAI VCO output - 100 - 432 tLOCK PLLSAI lock time VCO freq = 100 MHz 75 - 200 VCO freq = 432 MHz 100 - 300 RMS - 90 - ps peak to peak - 280 - ps Average frequency of 12.288 MHz N = 432, R = 5 on 1000 samples - 90 - ps Cycle to cycle at 48 KHz on 1000 samples - 400 - ps MHz Cycle to cycle at 12.288 MHz on 48KHz period, N=432, R=5 Master SAI clock jitter (3) Jitter FS clock jitter 122/201 DS12536 Rev 1 s STM32F730x8 Electrical characteristics Table 46. PLLISAI characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit IDD(PLLSAI)(4) PLLSAI power consumption on VDD VCO freq = 100 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLLSAI)(4) PLLSAI power consumption on VDDA VCO freq = 100 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 mA 1. Take care of using the appropriate division factor M to have the specified PLL input clock values. 2. Guaranteed by design. 3. Value given with main PLL running. 4. Guaranteed by characterization results. 6.3.12 PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 57: EMI characteristics). It is available only on the main PLL. Table 47. SSCG parameters constraint Symbol Parameter Min Typ Max(1) Unit fMod Modulation frequency - - 10 KHz md Peak modulation depth 0.25 - 2 % MODEPER * INCSTEP - - - 215 -1 - 1. Guaranteed by design. Equation 1 The frequency modulation period (MODEPER) is given by the equation below: MODEPER = round [ f PLL_IN ( 4 x f Mod ) ] fPLL_IN and fMod must be expressed in Hz. As an example: If fPLL_IN = 1 MHz, and fMOD = 1 kHz, the modulation depth (MODEPER) is given by equation 1: 6 3 MODEPER = round [ 10 ( 4 x 10 ) ] = 250 Equation 2 Equation 2 allows to calculate the increment step (INCSTEP): INCSTEP = round [ ( ( 2 15 - 1 ) x md x PLLN ) ( 100 x 5 x MODEPER ) ] fVCO_OUT must be expressed in MHz. With a modulation depth (md) = 2 % (4 % peak to peak), and PLLN = 240 (in MHz): INCSTEP = round [ ( ( 2 15 - 1 ) x 2 x 240 ) ( 100 x 5 x 250 ) ] = 126md(quantitazed)% DS12536 Rev 1 123/201 184 Electrical characteristics STM32F730x8 An amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of MODPER and INCSTEP. As a result, the achieved modulation depth is quantized. The percentage quantized modulation depth is given by the following formula: md quantized % = ( MODEPER x INCSTEP x 100 x 5 ) ( ( 2 15 - 1 ) x PLLN ) As a result: md quantized % = ( 250 x 126 x 100 x 5 ) ( ( 2 15 - 1 ) x 240 ) = 2.002%(peak) Figure 34 and Figure 35 show the main PLL output clock waveforms in center spread and down spread modes, where: F0 is fPLL_OUT nominal. Tmode is the modulation period. md is the modulation depth. Figure 34. PLL output clock waveforms in center spread mode Frequency (PLL_OUT) md F0 md tmode Time 2xtmode ai17291 Figure 35. PLL output clock waveforms in down spread mode Frequency (PLL_OUT) F0 2xmd tmode 2xtmode Time ai17292b 124/201 DS12536 Rev 1 STM32F730x8 6.3.13 Electrical characteristics USB OTG HS PHY PLLs characteristics The parameters given in Table 48 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 16. Table 48. USB OTG HS PLL1 characteristics(1) Symbol fPLL1_IN Parameter Conditions PLL1 input clock (2) Min Typ Max 12, 12.5, 16, 24, 25 fPLL1_OUT PLL1 output clock - - 60 - fVCO_OUT PLL1 VCO output - 600 - 720 (2) - - - 22 IDD(PLL1) PLL1 digital power consumption - - - 1.8 IDDA(PLL1) PLL1 analog power consumption - - - 2.75 tLOCK PLL1 lock time Unit MHz s mA 1. Guaranteed by design. 2. Based on test during characterization. Table 49. USB OTG HS PLL2 characteristics(1) Symbol fPLL2_IN Parameter Conditions Min Typ Max - - 60 - - - 480 - PLL2 input clock clock(2) fPLL2_OUT PLL2 output fVCO_OUT PLL2 VCO output - - 480 - tLOCK PLL2 lock time(2) - - - 91 IDD(PLL2) PLL2 digital power consumption - - - 2.1 IDDA(PLL2) PLL2 analog power consumption - - - 1.5 Unit MHz s mA 1. Guaranteed by design. 2. Based on test during characterization. 6.3.14 USB OTG HS PHY regulator characteristics The parameters given in Table 50 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 16. Table 50. USB OTG HS PHY regulator characteristics(1) Symbol Parameter Conditions Min Typ Max Unit VDD12OTGHS 1.2 V internal voltage on VDD12OTGHS - 1.18 1.2 1.24 V CEXT External capacitor on VDD12OTGHS - 1.1 2.2 3.3 F IDDPHYHSREG Regulator power consumption - 100 120 125 A 1. Based on test during characterization. DS12536 Rev 1 125/201 184 Electrical characteristics 6.3.15 STM32F730x8 USB HS PHY external resistor characteristics Table 51. USB HS PHY external resistor characteristics Symbol REXT 6.3.16 Parameter Conditions External calibration resistor connected Required if using (to GND) from OTG_HS_REXT USB HS PHY Min Typ Max Unit 2.97 3.00 3.03 k Memory characteristics Flash memory The characteristics are given at TA = -40 to 105 C unless otherwise specified. The devices are shipped to customers with the Flash memory erased. Table 52. Flash memory characteristics Symbol IDD Parameter Supply current Conditions Min Typ Max Write / Erase 8-bit mode, VDD = 1.7 V - 6.7 - Write / Erase 16-bit mode, VDD = 2.1 V - 9.2 - Write / Erase 32-bit mode, VDD = 3.3 V - 12.6 - Unit mA Table 53. Flash memory programming Symbol tprog Parameter Word programming time tERASE16KB Sector (16 KB) erase time tERASE128KB Sector (128 KB) erase time tERASE64KB Sector (64 KB) erase time 126/201 Conditions Min(1) Typ Max(1) Unit Program/erase parallelism (PSIZE) = x 8/16/32 - 16 100(2) Program/erase parallelism (PSIZE) = x 8 - 346 418 Program/erase parallelism (PSIZE) = x 16 - 252 312 Program/erase parallelism (PSIZE) = x 32 - 208 265 Program/erase parallelism (PSIZE) = x 8 - 1953 2500 Program/erase parallelism (PSIZE) = x 16 - 1252 1639 Program/erase parallelism (PSIZE) = x 32 - 927 1322 Program/erase parallelism (PSIZE) = x 8 - 1027 1298 Program/erase parallelism (PSIZE) = x 16 - 675 840 Program/erase parallelism (PSIZE) = x 32 - 505 682 DS12536 Rev 1 s ms ms ms STM32F730x8 Electrical characteristics Table 53. Flash memory programming (continued) Symbol Parameter tME Mass erase time Vprog Programming voltage Conditions Min(1) Typ Max(1) Unit Program/erase parallelism (PSIZE) = x 8 - 7718 9883 Program/erase parallelism (PSIZE) = x 16 - 4869 6379 Program/erase parallelism (PSIZE) = x 32 - 3503 5180 32-bit program operation 2.7 - 3 V 16-bit program operation 2.1 - 3.6 V 8-bit program operation 1.7 - 3.6 V ms 1. Guaranteed by characterization results. 2. The maximum programming time is measured after 10 K erase operations. Table 54. Flash memory programming with VPP Symbol Parameter Conditions tprog Double word programming tERASE16KB Sector (16 KB) erase time tERASE128KB Sector (128 KB) erase time tERASE64KB tME Sector (64 KB) erase time Min(1) Typ Max(1) Unit - 16 100(2) s - 180 - - 900 - - 450 - - 6.9 - s TA = 0 to +40 C VDD = 3.3 V VPP = 8.5 V Mass erase time ms Vprog Programming voltage - 2.7 - 3.6 V VPP VPP voltage range - 7 - 9 V IPP Minimum current sunk on the VPP pin - 10 - - mA Cumulative time during which VPP is applied - - - 1 hour tVPP(3) 1. Guaranteed by design. 2. The maximum programming time is measured after 10 K erase operations. 3. VPP should only be connected during programming/erasing. Table 55. Flash memory endurance and data retention Symbol NEND tRET Parameter Endurance Data retention Conditions(1) Value Min(2) TA = -40 to +85 C (6 suffix versions) TA = -40 to +105 C (7 suffix versions) 10 1 kcycle(3) at TA = 85 C 30 1 kcycle(3) at TA = 105 C 10 10 kcycles(3) at TA = 55 C 20 DS12536 Rev 1 Unit kcycles Years 127/201 184 Electrical characteristics STM32F730x8 1. Tj can not go above 125C (current consumption limitation). 2. Guaranteed by characterization results. 3. Cycling performed over the whole temperature range. 6.3.17 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: * Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. * FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 56. They are based on the EMS levels and classes defined in application note AN1709. Table 56. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD = 3.3 V, TA = +25 C, fHCLK = 216 MHz, conforms to IEC 61000-4-2 2B VEFTB VDD = 3.3 V, TA =+25 C, Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS fHCLK = 216 MHz, pins to induce a functional disturbance conforms to IEC 61000-4-2 5A As a consequence, it is recommended to add a serial resistor (1 k) located as close as possible to the MCU to the pins exposed to noise (connected to tracks longer than 50 mm on PCB). Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations 128/201 DS12536 Rev 1 STM32F730x8 Electrical characteristics The software flowchart must include the management of runaway conditions such as: * Corrupted program counter * Unexpected reset * Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading. Table 57. EMI characteristics Symbol Parameter Conditions Monitored frequency band Max vs. [fHSE/fCPU] Unit 25/200 MHz SEMI 6.3.18 VDD = 3.6 V, TA = 25 C, conforming to IEC61967-2 ART/L1-cache OFF, over-drive ON, Peak level all peripheral clocks enabled, clock dithering disabled. 0.1 MHz to 30 MHz 23 30 MHz to 130 MHz 20 130 MHz to 1 GHz 34 1 GHz to 2 GHz 24 EMI Level 4 dBV - Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts x (n+1) supply pins). This test conforms to the ANSI/ESDA/JEDEC JS-001-2012 and ANSI/ESD S5.3.1-2009 standards. DS12536 Rev 1 129/201 184 Electrical characteristics STM32F730x8 Table 58. ESD absolute maximum ratings Symbol Ratings Conditions TA = +25 C conforming to ANSI/ESDA/JEDEC JS-001-2012 VESD(HBM) Electrostatic discharge voltage (human body model) VESD(CDM) TA = +25 C conforming to ANSI/ESD Electrostatic discharge STM5.3.1-2009, all the packages voltage (charge device model) excepted WLCSP100 Class Maximum value(1) 2 2000 3 250 Unit V 1. Guaranteed by characterization results. Static latchup Two complementary static tests are required on six parts to assess the latchup performance: * A supply overvoltage is applied to each power supply pin * A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latchup standard. Table 59. Electrical sensitivities Symbol LU 6.3.19 Parameter Static latch-up class Conditions TA = +105 C conforming to JESD78A Class II level A I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibilty to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of - 5 A/+0 A range), or other functional failure (for example reset, oscillator frequency deviation). Negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection. The test results are given in Table 60. 130/201 DS12536 Rev 1 STM32F730x8 Electrical characteristics Table 60. I/O current injection susceptibility Functional susceptibility Symbol IINJ Description Negative injection Positive injection Injected current on BOOT0, PDR_ON, BYPASS_REG, OTG_HS_REXT -0 0 Injected current on NRST -0 NA(1) Injected current on PF9, PF10, PH0_OSCIN, PH1_OSCOUT, PC0, PC1, PC2, PC3, PB14(2), PB15(2) -0 NA(1) Injected current on any other FT or FTf pins -5 NA(1) Injected current on any other pins -5 +5 Unit mA 1. Injection is not possible. 2. PB14 and PB15 in the STM32F730x8 devices. Note: It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. 6.3.20 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 61: I/O static characteristics are derived from tests performed under the conditions summarized in Table 16. All I/Os are CMOS and TTL compliant. Table 61. I/O static characteristics Symbol Parameter FT, TTa and NRST I/O input low level voltage VIL BOOT I/O input low level voltage FT, TTa and NRST I/O input high level voltage(5) VIH BOOT I/O input high level voltage Conditions Min Typ 1.7 VVDD3.6 V - - 1.75 VVDD 3.6 V, - 40 CTA 105 C - - 1.7 VVDD 3.6 V, 0 CTA 105 C - 1.7 VVDD3.6 V 1.75 VVDD 3.6 V, - 40 CTA 105 C 1.7 VVDD 3.6 V, 0 CTA 105 C DS12536 Rev 1 Max Unit 0.35VDD -0.04(1) 0.3VDD(2) V 0.1VDD+0.1(1) 0.45VDD+0.3(1) 0.7VDD(2) - V 0.17VDD+0.7(1) - - 131/201 184 Electrical characteristics STM32F730x8 Table 61. I/O static characteristics (continued) Symbol Parameter Conditions Min Typ Max 1.7 VVDD3.6 V 10%VDD(3) - - 0.1 - - VSS VIN VDD - - 1 VIN = 5 V - - 3 30 40 50 PA10/PB12 (OTG_FS_ID ,OTG_HS_ID ) 7 10 14 All pins except for PA10/PB12 (OTG_FS_ID ,OTG_HS_ID ) 30 40 50 7 10 14 - 5 - FT, TTa and NRST I/O input hysteresis VHYS BOOT I/O input hysteresis Ilkg RPU RPD CIO(8) I/O input leakage current (4) I/O FT input leakage current (5) Weak pull-up equivalent resistor(6) Weak pulldown equivalent resistor(7) All pins except for PA10/PB12 (OTG_FS_ID ,OTG_HS_ID ) 1.75 VVDD 3.6 V, - 40 CTA 105 C 1.7 VVDD 3.6 V, 0 CTA 105 C V k VIN = VDD - 1. Guaranteed by design. 2. Tested in production. 3. With a minimum of 200 mV. 4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 60: I/O current injection susceptibility 5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 60: I/O current injection susceptibility 6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimum (~10% order). 7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the series resistance is minimum (~10% order). 8. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results. All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements for FT I/Os is shown in Figure 36. 132/201 A VIN = VSS PA10/PB12 (OTG_FS_ID ,OTG_HS_ID ) I/O pin capacitance Unit DS12536 Rev 1 pF STM32F730x8 Electrical characteristics Figure 36. FT I/O input characteristics VIL/VIH (V) 2.52 in = DD 7V 0. Hm I tV en m ire 2.0 1.92 TTL requirement VIHmin = 2V .3 +0 DD V .45 r M d e st in on , ns tio ign 0 in= pr Te ed n -C io ct u od 1.7 1.22 1.19 OS u eq la mu m VIH si s De Area not determined s Ba 1.065 0.8 sign n De o ased s B 0.55 0.51 a ILm ns, V atio imul 4 -0.0 VDD .35 x= 0 TTL requirement VILmax = 0.8V Tested in production - CMOS requirement VILmax = 0.3VDD VDD (V) 1.7 2.0 2.4 2.7 3.3 3.6 MS33746V2 Output driving current The GPIOs (general purpose input/outputs) can sink or source up to 8 mA, and sink or source up to 20 mA (with a relaxed VOL/VOH) except PC13, PC14, PC15 and PI8 which can sink or source up to 3mA. When using the PC13 to PC15 and PI8 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF. In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2. In particular: * The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 14). * The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 14). Output voltage levels Unless otherwise specified, the parameters given in Table 62 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 16. All I/Os are CMOS and TTL compliant. DS12536 Rev 1 133/201 184 Electrical characteristics STM32F730x8 Table 62. Output voltage characteristics Symbol Parameter Conditions Min Max CMOS port(2) IIO = +8 mA 2.7 V VDD 3.6 V - 0.4 VDD - 0.4 - VDD - 0.4 - Output low level voltage for an I/O pin TTL port(2) IIO =+8mA 2.7 V VDD 3.6 V - 0.4 VOH (3) Output high level voltage for an I/O pin except PC14 TTL port(2) IIO =-8mA 2.7 V VDD 3.6 V 2.4 - VOL(1) Output low level voltage for an I/O pin IIO = +20 mA 2.7 V VDD 3.6 V - 1.3(4) VOH(3) Output high level voltage for an I/O pin except PC14 IIO = -20 mA VDD -1.3(4) 2.7 V VDD 3.6 V VOL(1) Output low level voltage for an I/O pin IIO = +6 mA 1.8 V VDD 3.6 V VOH(3) Output high level voltage for an I/O pin except PC14 IIO = -6 mA 1.8 V VDD 3.6 V VOL(1) Output low level voltage for an I/O pin IIO = +4 mA 1.7 V VDD 3.6V - 0.4(5) VOH(3) Output high level voltage for an I/O pin except PC14 IIO = -4 mA 1.7 V VDD 3.6V VDD -0.4(5) - VOH(3) Output high level voltage for PC14 IIO = -1 mA 1.7 V VDD 3.6V VDD -0.4(5) - VOL(1) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin except PC14 Unit CMOS port(2) IIO = -8 mA 2.7 V VDD 3.6 V V CMOS port(2) VOH(3) VOL (1) Output high level voltage for PC14 IIO = -2 mA 2.7 V VDD 3.6 V V - V 0.4(4) V VDD -0.4(4) - V 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 14. and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 14 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 4. Based on characterization data. 5. Guaranteed by design. Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 37 and Table 63, respectively. 134/201 DS12536 Rev 1 STM32F730x8 Electrical characteristics Unless otherwise specified, the parameters given in Table 63 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 16. Table 63. I/O AC characteristics(1)(2) OSPEEDRy [1:0] bit value(1) Symbol fmax(IO)out Parameter Maximum frequency Conditions (3) 00 tf(IO)out/ tr(IO)out fmax(IO)out Output high to low level fall time and output low to high level rise time Maximum frequency(3) 01 tf(IO)out/ tr(IO)out fmax(IO)out Output high to low level fall time and output low to high level rise time Maximum frequency(3) 10 tf(IO)out/ tr(IO)out Output high to low level fall time and output low to high level rise time Min Typ Max CL = 50 pF, VDD 2.7 V - - 4 CL = 50 pF, VDD 1.7 V - - 2 CL = 10 pF, VDD 2.7 V - - 8 CL = 10 pF, VDD 1.8 V - - 4 CL = 10 pF, VDD 1.7 V - - 3 CL = 50 pF, VDD = 1.7 V to 3.6 V - - 100 CL = 50 pF, VDD 2.7 V - - 25 CL = 50 pF, VDD 1.8 V - - 12.5 CL = 50 pF, VDD 1.7 V - - 10 CL = 10 pF, VDD 2.7 V - - 50 CL = 10 pF, VDD 1.8 V - - 20 CL = 10 pF, VDD 1.7 V - - 12.5 CL = 50 pF, VDD 2.7 V - - 10 CL = 10 pF, VDD 2.7 V - - 6 CL = 50 pF, VDD 1.7 V - - 20 CL = 10 pF, VDD 1.7 V - - 10 CL = 40 pF, VDD 2.7 V - - 50(4) CL = 10 pF, VDD 2.7 V - - 100(4) CL = 40 pF, VDD 1.7 V - - 25 CL = 10 pF, VDD 1.8 V - - 50 CL = 10 pF, VDD 1.7 V - - 42.5 CL = 40 pF, VDD 2.7 V - - 6 CL = 10 pF, VDD 2.7 V - - 4 CL = 40 pF, VDD 1.7 V - - 10 CL = 10 pF, VDD 1.7 V - - 6 DS12536 Rev 1 Unit MHz ns MHz ns MHz ns 135/201 184 Electrical characteristics STM32F730x8 Table 63. I/O AC characteristics(1)(2) (continued) OSPEEDRy [1:0] bit value(1) Symbol fmax(IO)out Parameter Conditions Maximum frequency(3) 11 tf(IO)out/ tr(IO)out - tEXTIpw Output high to low level fall time and output low to high level rise time Min Typ Max CL = 30 pF, VDD 2.7 V - - 100(4) CL = 30 pF, VDD 1.8 V - - 50 CL = 30 pF, VDD 1.7 V - - 42.5 CL = 10 pF, VDD 2.7 V - - 180(4) CL = 10 pF, VDD 1.8 V - - 100 CL = 10 pF, VDD 1.7 V - - 72.5 CL = 30 pF, VDD 2.7 V - - 4 CL = 30 pF, VDD 1.8 V - - 6 CL = 30 pF, VDD 1.7 V - - 7 CL = 10 pF, VDD 2.7 V - - 2.5 CL = 10 pF, VDD 1.8 V - - 3.5 CL = 10 pF, VDD 1.7 V - - 4 10 - - Pulse width of external signals detected by the EXTI controller - Unit MHz ns ns 1. Guaranteed by design. 2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F72xxx and STM32F73xxx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register. 3. The maximum frequency is defined in Figure 37. 4. For maximum frequencies above 50 MHz and VDD > 2.4 V, the compensation cell should be used. Figure 37. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% EXTERNAL OUTPUT ON CL tr(IO)out tf(IO)out T Maximum frequency is achieved if (tr + tf) (2/3)T and if the duty cycle is (45-55%) when loaded by CL specified in the table " I/O AC characteristics". ai14131d 136/201 DS12536 Rev 1 STM32F730x8 6.3.21 Electrical characteristics NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 61: I/O static characteristics). Unless otherwise specified, the parameters given in Table 64 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 16. Table 64. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit RPU Weak pull-up equivalent resistor(1) VIN = VSS 30 40 50 k - - - 100 ns VDD > 2.7 V 300 - - ns Internal Reset source 20 - - s VF(NRST) (2) NRST Input filtered pulse VNF(NRST)(2) NRST Input not filtered pulse TNRST_OUT Generated reset pulse duration 1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). 2. Guaranteed by design. Figure 38. Recommended NRST pin protection VDD External reset circuit (1) NRST (2) RPU Internal Reset Filter 0.1 F STM32F ai14132c 1. The reset network protects the device against parasitic resets. 0.1 uF capacitor must be placed as close as possible to the chip. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 64. Otherwise the reset is not taken into account by the device. DS12536 Rev 1 137/201 184 Electrical characteristics 6.3.22 STM32F730x8 TIM timer characteristics The parameters given in Table 65 are guaranteed by design. Refer to Section 6.3.20: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 65. TIMx characteristics(1)(2) Conditions(3) Min Max Unit AHB/APBx prescaler=1 or 2 or 4, fTIMxCLK = 216 MHz 1 - tTIMxCLK AHB/APBx prescaler>4, fTIMxCLK = 108 MHz 1 - tTIMxCLK Timer external clock frequency on CH1 to CH4 f TIMxCLK = 216 MHz 0 fTIMxCLK/2 MHz Timer resolution - 16/32 bit - 65536 x 65536 tTIMxCLK Symbol tres(TIM) fEXT ResTIM tMAX_COUNT Parameter Timer resolution time Maximum possible count with 32-bit counter - 1. TIMx is used as a general term to refer to the TIM1 to TIM12 timers. 2. Guaranteed by design. 3. The maximum timer frequency on APB1 or APB2 is up to 216 MHz, by setting the TIMPRE bit in the RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCLK, otherwise TIMxCLK = 4x PCLKx. 6.3.23 RTC characteristics Table 66. RTC characteristics 6.3.24 Symbol Parameter Conditions - fPCLK1/RTCCLK frequency ratio Any read/write operation from/to an RTC register Min Max 4 - 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 67 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 16. Table 67. ADC characteristics Symbol VDDA Parameter Power supply VREF+ Positive reference voltage VREF- Negative reference voltage 138/201 Conditions VDDA -VREF+ < 1.2 V - DS12536 Rev 1 Min Typ Max Unit 1.7(1) - 3.6 V 1.7(1) - VDDA V - 0 - V STM32F730x8 Electrical characteristics Table 67. ADC characteristics (continued) Symbol fADC fTRIG(2) VAIN RAIN(2) Parameter ADC clock frequency External trigger frequency Conversion voltage range(3) External input impedance RADC(2)(4) Sampling switch resistance CADC(2) Internal sample and hold capacitor Conditions Min Typ Max Unit VDDA = 1.7(1) to 2.4 V 0.6 15 18 MHz VDDA = 2.4 to 3.6 V 0.6 30 36 MHz fADC = 30 MHz, 12-bit resolution - - 1764 kHz - - - 17 1/fADC - 0 (VSSA or VREFtied to ground) - VREF+ V See Equation 1 for details - - 50 k - 1.5 - 6 k - - 4 7 pF tlat(2) Injection trigger conversion latency fADC = 30 MHz - - 0.100 s - - - 3(5) 1/fADC tlatr(2) Regular trigger conversion latency fADC = 30 MHz - - 0.067 s 1/fADC tS(2) Sampling time tSTAB(2) Power-up time tCONV(2) Total conversion time (including sampling time) - - - 2(5) fADC = 30 MHz 0.100 - 16 s - 3 - 480 1/fADC - 2 3 s fADC = 30 MHz 12-bit resolution 0.50 - 16.40 s fADC = 30 MHz 10-bit resolution 0.43 - 16.34 s fADC = 30 MHz 8-bit resolution 0.37 - 16.27 s fADC = 30 MHz 6-bit resolution 0.30 - 16.20 s - 9 to 492 (tS for sampling +n-bit resolution for successive approximation) Sampling rate fS(2) (fADC = 36 MHz, and tS = 3 ADC cycles) 1/fADC 12-bit resolution Single ADC - - 2.4 Msps 12-bit resolution Interleave Dual ADC mode - - 4.5 Msps 12-bit resolution Interleave Triple ADC mode - - 7.2 Msps DS12536 Rev 1 139/201 184 Electrical characteristics STM32F730x8 Table 67. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit IVREF+(2) ADC VREF DC current consumption in conversion mode - - 300 500 A IVDDA(2) ADC VDDA DC current consumption in conversion mode - - 1.6 1.8 mA 1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.15.2: Internal reset OFF). 2. Guaranteed by characterization results. 3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. 4. RADC maximum value is given for VDD=1.7 V, and minimum value for VDD=3.3 V. 5. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 67. Equation 1: RAIN max formula R AIN ( k - 0.5 ) - - R ADC = --------------------------------------------------------------N+2 f ADC x C ADC x ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. Table 68. ADC static accuracy at fADC = 18 MHz Symbol ET Parameter Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fADC =18 MHz VDDA = 1.7 to 3.6 V VREF = 1.7 to 3.6 V VDDA -VREF < 1.2 V Typ Max(1) 3 4 2 3 1 3 1 2 2 3 Unit LSB 1. Guaranteed by characterization results. Table 69. ADC static accuracy at fADC = 30 MHz Symbol ET Parameter Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fADC = 30 MHz, RAIN < 10 k, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V, VDDA -VREF < 1.2 V 1. Guaranteed by characterization results. 140/201 DS12536 Rev 1 Typ Max(1) 2 5 1.5 2.5 1.5 4 1 2 1.5 3 Unit LSB STM32F730x8 Electrical characteristics Table 70. ADC static accuracy at fADC = 36 MHz Symbol Parameter ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Test conditions Typ Max(1) 4 7 2 3 3 6 2 3 3 6 fADC =36 MHz, VDDA = 2.4 to 3.6 V, VREF = 1.7 to 3.6 V VDDA -VREF < 1.2 V Unit LSB 1. Guaranteed by characterization results. Table 71. ADC dynamic accuracy at fADC = 18 MHz - limited test conditions(1) Symbol Parameter Test conditions ENOB Effective number of bits SINAD Signal-to-noise and distortion ratio SNR Signal-to-noise ratio THD Total harmonic distortion fADC =18 MHz VDDA = VREF+= 1.7 V Input Frequency = 20 KHz Temperature = 25 C Min Typ Max Unit 10.3 10.4 - bits 64 64.2 - 64 65 - - 67 - 72 - dB 1. Guaranteed by characterization results. Table 72. ADC dynamic accuracy at fADC = 36 MHz - limited test conditions(1) Symbol Parameter Test conditions ENOB Effective number of bits SINAD Signal-to noise and distortion ratio SNR Signal-to noise ratio THD Total harmonic distortion fADC =36 MHz VDDA = VREF+ = 3.3 V Input Frequency = 20 KHz Temperature = 25 C Min Typ Max Unit 10.6 10.8 - bits 66 67 - 64 68 - - 70 - 72 - dB 1. Guaranteed by characterization results. Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 6.3.20 does not affect the ADC accuracy. DS12536 Rev 1 141/201 184 Electrical characteristics STM32F730x8 Figure 39. ADC accuracy characteristics [1LSB IDEAL = V REF+ 4096 (or V DDA 4096 depending on package)] EG 4095 4094 4093 (2) ET (3) 7 (1) 6 5 EO 4 EL 3 ED 2 1L SBIDEAL 1 0 1 2 3 456 7 V SSA 4093 4094 4095 4096 VDDA ai14395c 1. See also Table 69. 2. Example of an actual transfer curve. 3. Ideal transfer curve. 4. End point correlation line. 5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one. EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. Figure 40. Typical connection diagram using the ADC STM32F VDD RAIN(1) AINx VAIN Cparasitic Sample and hold ADC converter VT 0.6 V RADC(1) VT 0.6 V IL1 A 12-bit converter C ADC(1) ai17534 1. Refer to Table 67 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced. 142/201 DS12536 Rev 1 STM32F730x8 Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in Figure 41 or Figure 42, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 41. Power supply and reference decoupling (VREF+ not connected to VDDA) STM32 VREF+ (1) 1 F // 10 nF VDDA 1 F // 10 nF VSSA/VREF+ (1) ai17535c 1. VREF+ input is available on all the packages except LQFP64, whereas the VREF- is available only on UFBGA176. When VREF- is not available, it is internally connected to VSSA. Figure 42. Power supply and reference decoupling (VREF+ connected to VDDA) STM32F VREF+/VDDA (1) 1 F // 10 nF VREF-/VSSA (1) ai17536c 1. VREF+ input is available on all the packages except LQFP64, whereas the VREF- is available only on UFBGA176. When VREF- is not available, it is internally connected to VSSA. DS12536 Rev 1 143/201 184 Electrical characteristics 6.3.25 STM32F730x8 Temperature sensor characteristics Table 73. Temperature sensor characteristics Symbol Parameter Min Typ Max Unit VSENSE linearity with temperature - 1 2 C Average slope - 2.5 - mV/C Voltage at 25 C - 0.76 - V tSTART(2) Startup time - 6 10 s TS_temp(2) ADC sampling time when reading the temperature (1 C accuracy) 10 - - s TL(1) Avg_Slope (1) V25(1) 1. Guaranteed by characterization results. 2. Guaranteed by design. Table 74. Temperature sensor calibration values Symbol Parameter Memory address TS_CAL1 TS ADC raw data acquired at temperature of 30 C, VDDA= 3.3 V 0x1FF0 7A2C - 0x1FF0 7A2D TS_CAL2 TS ADC raw data acquired at temperature of 110 C, VDDA= 3.3 V 0x1FF0 7A2E - 0x1FF0 7A2F 6.3.26 VBAT monitoring characteristics Table 75. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 50 - K Q Ratio on VBAT measurement - 4 - - Error on Q -1 - +1 % ADC sampling time when reading the VBAT 1 mV accuracy 5 - - s Er(1) TS_vbat(2)(2) 1. Guaranteed by design. 2. Shortest sampling time can be determined in the application by multiple iterations. 6.3.27 Reference voltage The parameters given in Table 76 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 16. Table 76. internal reference voltage Symbol VREFINT TS_vrefint(1) VRERINT_s(2) 144/201 Parameter Internal reference voltage Conditions Min Typ Max Unit -40 C < TA < +105 C 1.18 1.21 1.24 V - 10 - - s VDD = 3V 10mV - 3 5 mV ADC sampling time when reading the internal reference voltage Internal reference voltage spread over the temperature range DS12536 Rev 1 STM32F730x8 Electrical characteristics Table 76. internal reference voltage (continued) Symbol Parameter Conditions Min Typ Max Unit TCoeff(2) Temperature coefficient - - 30 50 ppm/C tSTART(2) Startup time - - 6 10 s 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design. Table 77. Internal reference voltage calibration values Symbol Parameter VREFIN_CAL 6.3.28 Memory address Raw data acquired at temperature of 30 C VDDA = 3.3 V 0x1FF0 7A2A - 0x1FF0 7A2B DAC electrical characteristics Table 78. DAC characteristics Symbol Parameter Min Typ Max Unit Comments - VDDA Analog supply voltage 1.7(1) - 3.6 V VREF+ Reference supply voltage 1.7(1) - 3.6 V VSSA Ground 0 - 0 V - 5 - - k - 25 - - k - Impedance output with buffer OFF - - 15 When the buffer is OFF, the Minimum k resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 M Capacitive load - - 50 pF DAC_OUT Lower DAC_OUT voltage with buffer ON min(2) 0.2 - - V DAC_OUT Higher DAC_OUT voltage max(2) with buffer ON - - VDDA - 0.2 V DAC_OUT Lower DAC_OUT voltage with buffer OFF min(2) - 0.5 - mV - VREF+ - 1LSB V RLOAD (2) RO(2) CLOAD(2) Connected to Resistive load VSSA with buffer ON Connected to VDDA DAC_OUT Higher DAC_OUT voltage with buffer OFF max(2) - DS12536 Rev 1 VREF+ VDDA Maximum capacitive load at DAC_OUT pin (when the buffer is ON). It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x1C7) to (0xE38) at VREF+ = 1.7 V It gives the maximum output excursion of the DAC. 145/201 184 Electrical characteristics STM32F730x8 Table 78. DAC characteristics (continued) Symbol IVREF+(4) Parameter DAC DC VREF current consumption in quiescent mode (Standby mode) Min Typ Max - 170 240 Unit A Comments With no load, worst code (0x800) at VREF+ = 3.6 V in terms of DC consumption on the inputs With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs - 50 75 - 280 380 A With no load, middle code (0x800) on the inputs - 475 625 A With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs Differential non linearity Difference between two consecutive code-1LSB) - - 0.5 LSB Given for the DAC in 10-bit configuration. - - 2 LSB Given for the DAC in 12-bit configuration. - - 1 LSB Given for the DAC in 10-bit configuration. INL(4) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) - - 4 LSB Given for the DAC in 12-bit configuration. - - 10 mV Given for the DAC in 12-bit configuration Offset(4) Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) - - 3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V - - 12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V - - 0.5 % Given for the DAC in 12-bit configuration - 3 6 s CLOAD 50 pF, RLOAD 5 k IDDA(4) DNL(4) Gain error(4) DAC DC VDDA current consumption in quiescent mode(3) Gain error Settling time (full scale: for a 10-bit input code transition between the lowest and the (4) tSETTLING highest input codes when DAC_OUT reaches final value 4LSB THD(4) Total Harmonic Distortion Buffer ON - - - dB CLOAD 50 pF, RLOAD 5 k Update rate(2) Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) - - 1 MS/s CLOAD 50 pF, RLOAD 5 k 146/201 DS12536 Rev 1 STM32F730x8 Electrical characteristics Table 78. DAC characteristics (continued) Symbol Parameter Min Typ Max Unit Comments Wakeup time from off state tWAKEUP(4) (Setting the ENx bit in the DAC Control register) - 6.5 10 s CLOAD 50 pF, RLOAD 5 k input code between lowest and highest possible ones. Power supply rejection ratio PSRR+ (2) (to VDDA) (static DC measurement) - -67 -40 dB No RLOAD, CLOAD = 50 pF 1. VDDA minimum value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 3.15.2: Internal reset OFF). 2. Guaranteed by design. 3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs. 4. Guaranteed by characterization results. Figure 43. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC Buffer(1) RL DAC_OUTx 12-bit digital to analog converter CL ai17157V3 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 6.3.29 Communications interfaces I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev. 03 for: * Standard-mode (Sm): with a bit rate up to 100 kbit/s * Fast-mode (Fm): with a bit rate up to 400 kbit/s. * Fast-mode Plus (Fm+): with a bit rate up to 1Mbit/s. The I2C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to RM0431 reference manual) and when the I2CCLK frequency is greater than the minimum shown in the table below: DS12536 Rev 1 147/201 184 Electrical characteristics STM32F730x8 Table 79. Minimum I2CCLK frequency in all I2C modes Symbol Parameter Condition Standard-mode Fast-mode f(I2CCLK) I2CCLK frequency Fast-mode Plus Min - 2 Analog Filter ON DNF=0 10 Analog Filter OFF DNF=1 9 Analog Filter ON DNF=0 22.5 Analog Filter OFF DNF=1 16 Unit MHz The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are not "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The 20mA output drive requirement in Fast-mode Plus is not supported. This limits the maximum load Cload supported in Fm+, which is given by these formulas: * Tr(SDA/SCL)=0.8473xRpxCload * Rp(min)= (VDD-VOL(max))/IOL(max) Where Rp is the I2C lines pull-up. Refer to Section 6.3.20: I/O port characteristics for the I2C I/Os characteristics. All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog filter characteristics: Table 80. I2C analog filter characteristics(1) Symbol Parameter Min Max Unit tAF Maximum pulse width of spikes that are suppressed by the analog filter 50(2) 260(3) ns 1. Guaranteed by characterization results. 2. Spikes with widths below tAF(min) are filtered. 3. Spikes with widths above tAF(max) are not filtered 148/201 DS12536 Rev 1 STM32F730x8 Electrical characteristics SPI interface characteristics Unless otherwise specified, the parameters given in Table 81 for the SPI interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 16, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Capacitive load C = 30 pF * Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI). Table 81. SPI dynamic characteristics(1) Symbol fSCK 1/tc(SCK) Parameter SPI clock frequency Conditions Min Typ Max Master mode SPI1,4,5 2.7VDD3.6 - - 54(2) Master mode SPI1,4,5 1.71VDD3.6 - - 27 Master transmitter mode SPI1,4,5 1.71VDD3.6 - - 54 Slave receiver mode SPI1,4,5 1.71VDD3.6 - - 54 Slave mode transmitter/full duplex SPI1,4,5 2.7VDD3.6 - - 50(3) Slave mode transmitter/full duplex SPI1,4,5 1.71VDD3.6 - - 37(3) Master & Slave mode SPI2,3 1.71VDD3.6 - - 27 tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4xTpclk - - th(NSS) NSS hold time Slave mode, SPI presc = 2 2xTpclk - - tw(SCKH) tw(SCKL) SCK high and low time Master mode Tpclk-1 Tpclk Tpclk+1 DS12536 Rev 1 Unit MHz ns 149/201 184 Electrical characteristics STM32F730x8 Table 81. SPI dynamic characteristics(1) (continued) Symbol tsu(MI) tsu(SI) th(MI) th(SI) Parameter Data input setup time Data input hold time Conditions Min Typ Max Master mode 4 - - Slave mode 3.5 - - Master mode 3 - - Slave mode 1 - - ta(SO) Data output access time Slave mode 7 9 21 tdis(SO) Data output disable time Slave mode 5 7 12 Slave mode 2.7VDD3.6V - 6.5 10 Slave mode 1.71VDD3.6V - 6.5 13.5 Master mode - 2 3 Slave mode 1.71VDD3.6V 4.5 - - Master mode 0 - - tv(SO) Data output valid time tv(MO) th(SO) Data output hold time th(MO) Unit ns 1. Guaranteed by characterization results. 2. Excepting SPI1 with SCK IO=PA5. In this configuration, the maximum achievable frequency is 40 MHz. 3. Maximum frequency of the slave transmitter is determined by sum of Tv(SO) and Tsu(MI) intervals which has to fit into SCK level phase preceding the SCK sampling edge.This value can be achieved when it communicates with a Master having Tsu(MI)=0 while signal Duty(SCK)=50%. Figure 44. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) tsu(NSS) th(NSS) tw(SCKH) tr(SCK) SCK input CPHA=0 CPOL=0 CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) First bit OUT MISO output th(SO) Next bits OUT tf(SCK) tdis(SO) Last bit OUT th(SI) tsu(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V1 150/201 DS12536 Rev 1 STM32F730x8 Electrical characteristics Figure 45. SPI timing diagram - slave mode and CPHA = 1 NSS input tsu(NSS) tw(SCKH) ta(SO) tw(SCKL) tf(SCK) th(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tv(SO) th(SO) First bit OUT MISO output tsu(SI) tr(SCK) Next bits OUT tdis(SO) Last bit OUT th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41659V1 Figure 46. SPI timing diagram - master mode High NSS input SCK Output tc(SCK) CPHA= 0 CPOL=0 SCK Output SCK input tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) MSB IN tr(SCK) tf(SCK) BIT6 IN LSB IN th(MI) MOSI OUTPUT MSB OUT tv(MO) B I T1 OUT LSB OUT th(MO) ai14136c DS12536 Rev 1 151/201 184 Electrical characteristics STM32F730x8 I2S interface characteristics Unless otherwise specified, the parameters given in Table 82 for the I2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 16, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load C = 30 pF * Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate function characteristics (CK, SD, WS). Table 82. I2S dynamic characteristics(1) Symbol Parameter Conditions Min Max Unit fMCK I2S Main clock output - 256 x 8K 256xFs(2) MHz fCK I2S clock frequency Master data: 32 bits - 64xFs Slave data: 32 bits - 64xFs 30 70 DCK I2S clock frequency duty cycle Slave receiver tv(WS) WS valid time Master mode - 3 th(WS) WS hold time Master mode 0 - tsu(WS) WS setup time Slave mode 5 - th(WS) WS hold time Slave mode 2 - Master receiver 2.5 - Slave receiver 2.5 - Master receiver 3.5 - Slave receiver 2 - Slave transmitter (after enable edge) - 12 Master transmitter (after enable edge) - 3 Slave transmitter (after enable edge) 5 - Master transmitter (after enable edge) 0 - tsu(SD_MR) tsu(SD_SR) th(SD_MR) th(SD_SR) tv(SD_ST) tv(SD_MT) th(SD_ST) th(SD_MT) Data input setup time Data input hold time Data output valid time Data output hold time MHz % ns 1. Guaranteed by characterization results. 2. 256xFs maximum is 49.152 MHz (APB1 Maximum frequency). Note: Refer to RM0431 reference manual I2S section for more details on the sampling frequency (FS). fMCK, fCK, and DCK values reflect only the digital peripheral behavior. The values of these parameters might be slightly impacted by the source clock precision. DCK depends mainly on the value of ODD bit. The digital contribution leads to a minimum value of (I2SDIV/(2*I2SDIV+ODD) and a maximum value of (I2SDIV+ODD)/(2*I2SDIV+ODD). FS maximum value is supported for each mode/condition. 152/201 DS12536 Rev 1 STM32F730x8 Electrical characteristics Figure 47. I2S slave timing diagram (Philips protocol)(1) CK Input tc(CK) CPOL = 0 CPOL = 1 tw(CKH) th(WS) tw(CKL) WS input tv(SD_ST) tsu(WS) SDtransmit LSB transmit(1) MSB transmit Bitn transmit tsu(SD_SR) LSB receive(1) SDreceive th(SD_ST) LSB transmit th(SD_SR) MSB receive Bitn receive LSB receive MS46528V1 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 48. I2S master timing diagram (Philips protocol)(1) tf(CK) tr(CK) CK output tc(CK) CPOL = 0 tw(CKH) CPOL = 1 tv(WS) th(WS) tw(CKL) WS output tv(SD_MT) SDtransmit LSB transmit(1) MSB transmit LSB receive(1) LSB transmit th(SD_MR) tsu(SD_MR) SDreceive Bitn transmit th(SD_MT) MSB receive Bitn receive LSB receive MS46529V1 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. DS12536 Rev 1 153/201 184 Electrical characteristics STM32F730x8 SAI characteristics Unless otherwise specified, the parameters given in Table 83 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 16, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 10 * Capacitive load C=30 pF * Measurement points are performed at CMOS levels: 0.5VDD Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate function characteristics (SCK,SD,WS). Table 83. SAI characteristics(1) Symbol Parameter Conditions Min Max fMCKL SAI Main clock output - 256x8K 256xFs FCK SAI clock frequency(2) Master data: 32 bits - 128xFs(3) Slave data: 32 bits - 128xFs(3) Master mode 2.7VDD3.6V - 18 Master mode 1.71VDD3.6V - 20 Slave mode 1 - Master mode 7 - Slave mode 0.5 - Master receiver 1 - Slave receiver 2.5 - Master receiver 3.5 - Slave receiver 0.5 - Slave transmitter (after enable edge) 2.7VDD3.6V - 11 Slave transmitter (after enable edge) 1.71VDD3.6V - 18 Slave transmitter (after enable edge) 5 - Master transmitter (after enable edge) 2.7VDD3.6V - 16 Master transmitter (after enable edge) 1.71VDD3.6V - 18.5 Master transmitter (after enable edge) 7.5 - tv(FS) FS valid time tsu(FS) FS setup time th(FS) FS hold time tsu(SD_A_MR) tsu(SD_B_SR) th(SD_A_MR) th(SD_B_SR) tv(SD_B_MT) th(SD_B_ST) tv(SD_A_MT) th(SD_A_MT) Data input setup time Data input hold time Data output valid time Data output hold time Data output valid time Data output hold time 1. Guaranteed by characterization results. 2. APB clock frequency must be at least twice SAI clock frequency. 3. With Fs = 192 KHz. 154/201 DS12536 Rev 1 Unit MHz ns STM32F730x8 Electrical characteristics Figure 49. SAI master timing waveforms 1/fSCK SAI_SCK_X th(FS) SAI_FS_X (output) tv(FS) th(SD_MT) tv(SD_MT) SAI_SD_X (transmit) Slot n tsu(SD_MR) SAI_SD_X (receive) Slot n+2 th(SD_MR) Slot n MS32771V1 Figure 50. SAI slave timing waveforms 1/fSCK SAI_SCK_X tw(CKH_X) SAI_FS_X (input) tw(CKL_X) tsu(FS) th(FS) th(SD_ST) tv(SD_ST) SAI_SD_X (transmit) Slot n tsu(SD_SR) SAI_SD_X (receive) Slot n+2 th(SD_SR) Slot n MS32772V1 DS12536 Rev 1 155/201 184 Electrical characteristics STM32F730x8 USB OTG full speed (FS) characteristics This interface is present in both the USB OTG HS and USB OTG FS controllers. Table 84. USB OTG full speed startup time Symbol tSTARTUP(1) Parameter Max Unit USB OTG full speed transceiver startup time 1 s 1. Guaranteed by design. Table 85. USB OTG full speed DC electrical characteristics Symbol Parameter Conditions USB OTG full speed VDDUSB transceiver operating voltage Input levels Min. (1) Typ. - 3.0(2) Max.( 1) Unit - 3.6 V VDI(3) Differential input sensitivity I(USB_FS_DP/DM, USB_HS_DP/DM) 0.2 - - VCM(3) Differential common mode range Includes VDI range 0.8 - 2.5 VSE(3) Single ended receiver threshold - 1.3 - 2.0 VOL Static output level low RL of 1.5 k to 3.6 V(4) - - 0.3 2.8 - 3.6 14.25 - 24.8 2.4 5.2 8 Output levels VOH Static output level high RL of 15 k to PA11, PA12 (USB_FS_DP/DM) RPD RPU VIN = VDD PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) PA12 (USB_FS_DP) VSS(4) VIN = VDD V V k VIN = VSS, during idle 0.9 1.25 1.575 VIN = VSS, during reception 0.55 0.95 PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) 1.35 1. All the voltages are measured from the local ground potential. 2. The USB OTG full speed transceiver functionality is ensured down to 2.7 V but not the full USB full speed electrical characteristics which are degraded in the 2.7-to-3.0 V VDDUSB voltage range. 3. Guaranteed by design. 4. RL is the load connected on the USB OTG full speed drivers. Note: 156/201 When VBUS sensing feature is enabled, PA9 and PB13 should be left at their default state (floating input), not as alternate function. A typical 200 A current consumption of the sensing block (current to voltage conversion to determine the different sessions) can be observed on PA9 and PB13 when the feature is enabled. DS12536 Rev 1 STM32F730x8 Electrical characteristics Figure 51. USB OTG full speed timings: definition of data signal rise and fall time Cross over points Differential data lines VCRS VSS tf tr ai14137b Table 86. USB OTG full speed electrical characteristics(1) Driver characteristics Symbol tr tf trfm Parameter Rise time(2) Fall time(2) Conditions Min Max Unit CL = 50 pF 4 20 ns CL = 50 pF 4 20 ns tr/tf 90 111 % - 1.3 2.0 V Driving high or low 28 44 Rise/ fall time matching VCRS Output signal crossover voltage ZDRV Output driver impedance(3) 1. Guaranteed by design. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). 3. No external termination series resistors are required on DP (D+) and DM (D-) pins since the matching impedance is included in the embedded driver. USB high speed (HS) characteristics (through ULPI) Unless otherwise specified, the parameters given in Table 89 for ULPI are derived from tests performed under the ambient temperature, fHCLK frequency summarized in Table 88 and VDD supply voltage conditions summarized in Table 87, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11, unless otherwise specified * Capacitive load C = 20 pF, unless otherwise specified * Measurement points are done at CMOS levels: 0.5VDD. Refer to Section 6.3.20: I/O port characteristics for more details on the input/output characteristics. Table 87. USB HS DC electrical characteristics Symbol Input level Parameter VDD USB OTG HS operating voltage Min.(1) Max.(1) Unit 1.7 3.6 V 1. All the voltages are measured from the local ground potential. DS12536 Rev 1 157/201 184 Electrical characteristics STM32F730x8 Table 88. USB HS clock timing parameters(1) Symbol Parameter Min Typ Max Unit - fHCLK value to guarantee proper operation of USB HS interface 30 - - MHz FSTART_8BIT Frequency (first transition) 54 60 66 MHz FSTEADY Frequency (steady state) 500 ppm 59.97 60 60.03 MHz DSTART_8BIT Duty cycle (first transition) 40 50 60 % DSTEADY Duty cycle (steady state) 500 ppm 49.975 50 50.025 % tSTEADY Time to reach the steady state frequency and duty cycle after the first transition - - 1.4 ms Peripheral - - 5.6 Host - - - - - - tSTART_DEV tSTART_HOST Clock startup time after the de-assertion of SuspendM 8-bit 10% 8-bit 10% PHY preparation time after the first transition of the input clock tPREP ms s 1. Guaranteed by design. Figure 52. ULPI timing diagram Clock Control In (ULPI_DIR, ULPI_NXT) tSC tHC tSD tHD data In (8-bit) tDC Control out (ULPI_STP) tDC tDD data out (8-bit) ai17361c 158/201 DS12536 Rev 1 STM32F730x8 Electrical characteristics Table 89. Dynamic characteristics: USB ULPI(1) Symbol Parameter Conditions Min. Typ. Max. tSC Control in (ULPI_DIR, ULPI_NXT) setup time - 1.5 - - tHC Control in (ULPI_DIR, ULPI_NXT) hold time - 1 - - tSD Data in setup time - 1.5 - - tHD Data in hold time - 1 - - 2.7 V < VDD < 3.6 V, CL = 20 pF and OSPEEDRy[1:0] = 11 - 6 7.5 - 9.5 11 tDC/tDD Data/control output delay 1.7 V < VDD < 3.6 V, CL = 15 pF and OSPEEDRy[1:0] = 11 - Unit ns 1. Guaranteed by characterization results. USB high speed (HS) characteristics (embedded PHY High speed on STM32F730x8 devices) Table 90. USB OTG high speed DC electrical characteristics Symbol Parameter Conditions Min Typ Max Unit Vhssq High speed squelch detection threshold - 100 - 150 mV Vhsdsc High speed disconnect detection threshold - 525 - 625 mV Vhsdif High speed differential detection threshold - 100 - - mV Vhscm High speed data signalling common mode voltage range - -50 - 500 mV Vhsoi High speed idle level - -10 - 10 mV Vhsoh High speed data signaling high - 360 - 440 mV Vhsol High speed data signaling low - -10 - 10 mV Vchirpj Chirp J level - 700 - 1100 mV Vchirpk Chirp K level - -900 - -500 mV Min Typ Max Unit Table 91. USB OTG high speed electrical characteristics Parameter Comments Conditions tlr Rise time - 0.5 - - ns tlf Fall time - 0.5 - - ns tlrfm Setup time from INHSDRIVERENABLE=1 to the transition on INHSDATAP/INHSDATAN - 10 - - ns Zdrv Driver output impedance - 40.5 - 49.5 DS12536 Rev 1 159/201 184 Electrical characteristics STM32F730x8 Table 92. USB FS PHY BCD electrical characteristics Symbol Parameter Conditions Min Typ Max Unit Primary detection mode consumption - - - 300 Secondary detection mode consumption - - - 300 RDAT_LKG Data line leakage resistance - 300 - - k VDAT_LKG Data line leakage voltage - 0.0 - 3.6 V RDCP_DAT Dedicated charging port resistance across D+/D- - - - 200 VLGC_HI Logic high - 2.0 - 3.6 VLGC_LOW Logic low - - - 0.8 Logic threshold - 0.8 - 2.0 VDAT_REF Data detect voltage - 0.25 - 3.6 VDP_SRC D+ source voltage - 0.5 - 3.6 VDM_SRC D- source voltage - 0.5 - 3.6 IDM_SINK D- sink current - 25 - 175 IDP_SINK D+ sink current - 25 - 175 IDP_SRC Data contact detect current source - 7 - 30 IDDUSB VLGC A V A CAN (controller area network) interface Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate function characteristics (CANx_TX and CANx_RX). 6.3.30 FMC characteristics Unless otherwise specified, the parameters given in Table 93 to Table 106 for the FMC interface are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 16, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.20: I/O port characteristics for more details on the input/output characteristics. Asynchronous waveforms and timings Figure 53 through Figure 56 represent asynchronous waveforms and Table 93 through Table 100 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: * AddressSetupTime = 0x1 * AddressHoldTime = 0x1 * DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5) * BusTurnAroundDuration = 0x0 * Capcitive load CL = 30 pF In all timing tables, the THCLK is the HCLK clock period 160/201 DS12536 Rev 1 STM32F730x8 Electrical characteristics Figure 53. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms tw(NE) FMC_NE tv(NOE_NE) t w(NOE) t h(NE_NOE) FMC_NOE FMC_NWE tv(A_NE) FMC_A[25:0] t h(A_NOE) Address tv(BL_NE) t h(BL_NOE) FMC_NBL[1:0] t h(Data_NE) t su(Data_NOE) th(Data_NOE) t su(Data_NE) Data FMC_D[15:0] t v(NADV_NE) tw(NADV) FMC_NADV (1) FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) MS32753V1 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. DS12536 Rev 1 161/201 184 Electrical characteristics STM32F730x8 Table 93. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) Symbol Min Max 2Thclk -1 2Thclk +1 0 0.5 2Thclk -1 2Thclk +1 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 0.5 th(A_NOE) Address hold time after FMC_NOE high 0 - tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5 th(BL_NOE) FMC_BL hold time after FMC_NOE high 0 - tsu(Data_NE) Data to FMC_NEx high setup time Thclk -1.5 - tsu(Data_NOE) Data to FMC_NOEx high setup time Thclk -1.5 - th(Data_NOE) Data hold time after FMC_NOE high 0 - th(Data_NE) Data hold time after FMC_NEx high 0 - tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0 FMC_NADV low time - Thclk -0.5 tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) tw(NADV) Parameter FMC_NE low time FMC_NEx low to FMC_NOE low FMC_NOE low time Unit ns 1. CL = 30 pF. Table 94. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings(1) Symbol tw(NE) tw(NOE) tw(NWAIT) Parameter Min Max FMC_NE low time 7Thclk +1 7Thclk +1 FMC_NWE low time 5Thclk -1 5Thclk +1 FMC_NWAIT low time Thclk -0.5 - 5Thclk +1.5 - 4Thclk +1 - tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 1. Guaranteed by characterization results. 162/201 DS12536 Rev 1 Unit ns STM32F730x8 Electrical characteristics Figure 54. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms tw(NE) FMC_NEx FMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FMC_NWE tv(A_NE) FMC_A[25:0] th(A_NWE) Address tv(BL_NE) FMC_NBL[1:0] th(BL_NWE) NBL tv(Data_NE) th(Data_NWE) Data FMC_D[15:0] t v(NADV_NE) FMC_NADV (1) tw(NADV) FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) MS32754V1 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. Table 95. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1) Symbol tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) Parameter Min Max FMC_NE low time 3Thclk +1 3Thclk +1 FMC_NEx low to FMC_NWE low Thclk - 0.5 Thclk +0.5 FMC_NWE low time Thclk - 1.5 Thclk +0.5 Thclk - - 0 Thclk - 0.5 - - 0.5 Thclk - 0.5 - FMC_NWE high to FMC_NE high hold time FMC_NEx low to FMC_A valid th(A_NWE) Address hold time after FMC_NWE high tv(BL_NE) FMC_NEx low to FMC_BL valid Unit ns th(BL_NWE) FMC_BL hold time after FMC_NWE high tv(Data_NE) Data to FMC_NEx low to Data valid - Thclk +1.5 th(Data_NWE) Data hold time after FMC_NWE high Thclk +0.5 - tv(NADV_NE) FMC_NEx low to FMC_NADV low - 0 FMC_NADV low time - Thclk - 0.5 tw(NADV) 1. Guaranteed by characterization results. DS12536 Rev 1 163/201 184 Electrical characteristics STM32F730x8 Table 96. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings(1) Symbol Parameter FMC_NE low time tw(NE) tw(NWE) FMC_NWE low time Min Max 8Thclk -1 8Thclk +1 6Thclk -1.5 6Thclk +0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6Thclk -1 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4Thclk + 2 - Unit ns 1. Guaranteed by characterization results. Figure 55. Asynchronous multiplexed PSRAM/NOR read waveforms tw(NE) FMC_ NE tv(NOE_NE) t h(NE_NOE) FMC_NOE t w(NOE) FMC_NWE th(A_NOE) tv(A_NE) FMC_ A[25:16] Address tv(BL_NE) th(BL_NOE) FMC_ NBL[1:0] NBL th(Data_NE) tsu(Data_NE) t v(A_NE) FMC_ AD[15:0] tsu(Data_NOE) th(Data_NOE) Data Address th(AD_NADV) t v(NADV_NE) tw(NADV) FMC_NADV FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) MS32755V1 164/201 DS12536 Rev 1 STM32F730x8 Electrical characteristics Table 97. Asynchronous multiplexed PSRAM/NOR read timings(1) Symbol Min Max 3Thclk -1 3Thclk +1 2Thclk 2Thclk +0.5 Thclk -1 Thclk +1 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 0.5 FMC_NEx low to FMC_NADV low 0 0.5 FMC_NADV low time Thclk -0.5 Thclk +1 th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high) Thclk +0.5 - th(A_NOE) Address hold time after FMC_NOE high Thclk -0.5 - th(BL_NOE) FMC_BL time after FMC_NOE high 0 - FMC_NEx low to FMC_BL valid - 0.5 tw(NE) tv(NOE_NE) ttw(NOE) th(NE_NOE) tv(A_NE) tv(NADV_NE) tw(NADV) tv(BL_NE) Parameter FMC_NE low time FMC_NEx low to FMC_NOE low FMC_NOE low time tsu(Data_NE) Data to FMC_NEx high setup time Thclk -1.5 - tsu(Data_NOE) Data to FMC_NOE high setup time Thclk -1.5 - th(Data_NE) Data hold time after FMC_NEx high 0 - th(Data_NOE) Data hold time after FMC_NOE high 0 - Unit ns 1. Guaranteed by characterization results. Table 98. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1) Symbol Min Max 8Thclk -1 8Thclk +1 FMC_NWE low time 5Thclk -1.5 8Thclk +0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5Thclk +1.5 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4Thclk +1 - tw(NE) tw(NOE) Parameter FMC_NE low time Unit ns 1. Guaranteed by characterization results. DS12536 Rev 1 165/201 184 Electrical characteristics STM32F730x8 Figure 56. Asynchronous multiplexed PSRAM/NOR write waveforms tw(NE) FMC_ NEx FMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FMC_NWE th(A_NWE) tv(A_NE) FMC_ A[25:16] Address tv(BL_NE) th(BL_NWE) FMC_ NBL[1:0] NBL t v(A_NE) FMC_ AD[15:0] t v(Data_NADV) Address th(Data_NWE) Data th(AD_NADV) t v(NADV_NE) tw(NADV) FMC_NADV FMC_NWAIT th(NE_NWAIT) tsu(NWAIT_NE) MS32756V1 Table 99. Asynchronous multiplexed PSRAM/NOR write timings(1) Symbol Min Max FMC_NE low time 4Thclk -1 4Thclk +1 FMC_NEx low to FMC_NWE low Thclk -0.5 Thclk +0.5 FMC_NWE low time 2Thclk -0.5 2Thclk +0.5 FMC_NWE high to FMC_NE high hold time Thclk -0.5 - FMC_NEx low to FMC_A valid - 0 FMC_NEx low to FMC_NADV low 0 0.5 Thclk Thclk +1 FMC_AD(adress) valid hold time after FMC_NADV high) Thclk +0.5 - th(A_NWE) Address hold time after FMC_NWE high Thclk +0.5 - th(BL_NWE) FMC_BL hold time after FMC_NWE high Thclk -0.5 - tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) tv(NADV_NE) tw(NADV) th(AD_NADV) 166/201 Parameter FMC_NADV low time tv(BL_NE) FMC_NEx low to FMC_BL valid - 0.5 tv(Data_NADV) FMC_NADV high to Data valid - Thclk +1.5 th(Data_NWE) Data hold time after FMC_NWE high Thclk +0.5 - DS12536 Rev 1 Unit ns STM32F730x8 Electrical characteristics 1. Guaranteed by characterization results. Table 100. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1) Symbol Min Max FMC_NE low time 9Thclk - 1 9Thclk + 1 FMC_NWE low time 7Thclk -0.5 7Thclk + 0.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 6Thclk + 2 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4Thclk - 1 - tw(NE) tw(NWE) Parameter Unit ns 1. Guaranteed by characterization results. Synchronous waveforms and timings Figure 57 through Figure 60 represent synchronous waveforms and Table 101 through Table 104 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: * BurstAccessMode = FMC_BurstAccessMode_Enable; * MemoryType = FMC_MemoryType_CRAM; * WriteBurst = FMC_WriteBurst_Enable; * CLKDivision = 1; * DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM * CL = 30 pF on data and address lines. CL = 10 pF on FMC_CLK unless otherwise specified. In all timing tables, the THCLK is the HCLK clock period. - For 2.7 VVDD3.6 V, maximum FMC_CLK = 108 MHz at CL=20 pF or 90 MHz at CL=30 pF (on FMC_CLK). - For 1.71 VVDD<2.7 V, maximum FMC_CLK = 70 MHz at CL=10 pF (on FMC_CLK). DS12536 Rev 1 167/201 184 Electrical characteristics STM32F730x8 Figure 57. Synchronous multiplexed NOR/PSRAM read timings BUSTURN = 0 tw(CLK) tw(CLK) FMC_CLK Data latency = 0 td(CLKL-NExL) FMC_NEx t d(CLKL-NADVL) td(CLKH-NExH) td(CLKL-NADVH) FMC_NADV td(CLKL-AV) td(CLKH-AIV) FMC_A[25:16] td(CLKL-NOEL) td(CLKH-NOEH) FMC_NOE t d(CLKL-ADV) FMC_AD[15:0] td(CLKL-ADIV) tsu(ADV-CLKH) AD[15:0] th(CLKH-ADV) tsu(ADV-CLKH) D1 tsu(NWAITV-CLKH) FMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) tsu(NWAITV-CLKH) th(CLKH-ADV) D2 th(CLKH-NWAITV) th(CLKH-NWAITV) th(CLKH-NWAITV) MS32757V1 168/201 DS12536 Rev 1 STM32F730x8 Electrical characteristics Table 101. Synchronous multiplexed NOR/PSRAM read timings(1) Symbol tw(CLK) Parameter FMC_CLK period Min Max 2Thclk - 0.5 - - 2 Thclk + 0.5 - td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0...2) td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) - 3 td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) Thclk - - 2 Thclk - 0.5 - td(CLKL-NOEL) FMC_CLK low to FMC_NOE low td(CLKH-NOEH) FMC_CLK high to FMC_NOE high td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 2 td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 - tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 0.5 - th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 4 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 3 - Unit ns 1. Guaranteed by characterization results. DS12536 Rev 1 169/201 184 Electrical characteristics STM32F730x8 Figure 58. Synchronous multiplexed PSRAM write timings BUSTURN = 0 tw(CLK) tw(CLK) FMC_CLK Data latency = 0 td(CLKL-NExL) td(CLKH-NExH) FMC_NEx td(CLKL-NADVL) td(CLKL-NADVH) FMC_NADV td(CLKH-AIV) td(CLKL-AV) FMC_A[25:16] td(CLKH-NWEH) td(CLKL-NWEL) FMC_NWE td(CLKL-ADIV) td(CLKL-ADV) FMC_AD[15:0] td(CLKL-Data) td(CLKL-Data) AD[15:0] D1 D2 FMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) th(CLKH-NWAITV) td(CLKH-NBLH) FMC_NBL MS32758V1 170/201 DS12536 Rev 1 STM32F730x8 Electrical characteristics Table 102. Synchronous multiplexed PSRAM write timings(1) Symbol Min Max 2Thclk - 0.5 - - 2 Thclk +0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 1 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - - 3 Thclk - - 1.5 Thclk +0.5 - tw(CLK) Parameter FMC_CLK period td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0...2) td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) td(CLKL-NWEL) FMC_CLK low to FMC_NWE low t(CLKH-NWEH) FMC_CLK high to FMC_NWE high td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 3 td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 - td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low - 3 td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2 td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Thclk +0.5 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 3 - Unit ns 1. Guaranteed by characterization results. DS12536 Rev 1 171/201 184 Electrical characteristics STM32F730x8 Figure 59. Synchronous non-multiplexed NOR/PSRAM read timings tw(CLK) tw(CLK) FMC_CLK td(CLKL-NExL) td(CLKH-NExH) Data latency = 0 FMC_NEx td(CLKL-NADVL) td(CLKL-NADVH) FMC_NADV td(CLKH-AIV) td(CLKL-AV) FMC_A[25:0] td(CLKL-NOEL) td(CLKH-NOEH) FMC_NOE tsu(DV-CLKH) th(CLKH-DV) tsu(DV-CLKH) FMC_D[15:0] th(CLKH-DV) D1 tsu(NWAITV-CLKH) FMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) D2 th(CLKH-NWAITV) tsu(NWAITV-CLKH) FMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) t h(CLKH-NWAITV) th(CLKH-NWAITV) MS32759V1 Table 103. Synchronous non-multiplexed NOR/PSRAM read timings(1) Symbol Min Max 2Thclk - 0.5 - - 2 Thclk +0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - - 3 Thclk - - 2 Thclk -0.5 - 0.5 - tw(CLK) t(CLKL-NExL) td(CLKH-NExH) Parameter FMC_CLK period FMC_CLK low to FMC_NEx low (x=0..2) FMC_CLK high to FMC_NEx high (x= 0...2) td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) td(CLKL-NOEL) FMC_CLK low to FMC_NOE low td(CLKH-NOEH) FMC_CLK high to FMC_NOE high tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high th(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high 4 - FMC_NWAIT valid before FMC_CLK high 2 - 3 - t(NWAIT-CLKH) th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 172/201 DS12536 Rev 1 Unit ns STM32F730x8 Electrical characteristics 1. Guaranteed by characterization results. Figure 60. Synchronous non-multiplexed PSRAM write timings tw(CLK) tw(CLK) FMC_CLK td(CLKL-NExL) td(CLKH-NExH) Data latency = 0 FMC_NEx td(CLKL-NADVL) td(CLKL-NADVH) FMC_NADV td(CLKH-AIV) td(CLKL-AV) FMC_A[25:0] td(CLKL-NWEL) td(CLKH-NWEH) FMC_NWE td(CLKL-Data) td(CLKL-Data) D1 FMC_D[15:0] D2 FMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tsu(NWAITV-CLKH) td(CLKH-NBLH) th(CLKH-NWAITV) FMC_NBL MS32760V1 DS12536 Rev 1 173/201 184 Electrical characteristics STM32F730x8 Table 104. Synchronous non-multiplexed PSRAM write timings(1) Symbol Min Max 2Thclk - 0.5 - - 2 Thclk +0.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 0.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - - 3 Thclk - - 1.5 Thclk +1 - t(CLK) Parameter FMC_CLK period td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) t(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0...2) td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) td(CLKL-NWEL) FMC_CLK low to FMC_NWE low td(CLKH-NWEH) FMC_CLK high to FMC_NWE high td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 3 td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 2 td(CLKH-NBLH) FMC_CLK high to FMC_NBL high Thclk +1 - 2 - 3.5 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high Unit ns 1. Guaranteed by characterization results. NAND controller waveforms and timings Figure 61 through Figure 64 represent synchronous waveforms, and Table 105 and Table 106 provide the corresponding timings. The results shown in this table are obtained with the following FMC configuration: * COM.FMC_SetupTime = 0x01; * COM.FMC_WaitSetupTime = 0x03; * COM.FMC_HoldSetupTime = 0x02; * COM.FMC_HiZSetupTime = 0x01; * ATT.FMC_SetupTime = 0x01; * ATT.FMC_WaitSetupTime = 0x03; * ATT.FMC_HoldSetupTime = 0x02; * ATT.FMC_HiZSetupTime = 0x01; * Bank = FMC_Bank_NAND; * MemoryDataWidth = FMC_MemoryDataWidth_16b; * ECC = FMC_ECC_Enable; * ECCPageSize = FMC_ECCPageSize_512Bytes; * TCLRSetupTime = 0; * TARSetupTime = 0. In all timing tables, the THCLK is the HCLK clock period. 174/201 DS12536 Rev 1 STM32F730x8 Electrical characteristics Figure 61. NAND controller waveforms for read access FMC_NCEx ALE (FMC_A17) CLE (FMC_A16) FMC_NWE td(ALE-NOE) th(NOE-ALE) FMC_NOE (NRE) tsu(D-NOE) th(NOE-D) FMC_D[15:0] MS32767V1 Figure 62. NAND controller waveforms for write access FMC_NCEx ALE (FMC_A17) CLE (FMC_A16) th(NWE-ALE) td(ALE-NWE) FMC_NWE FMC_NOE (NRE) th(NWE-D) tv(NWE-D) FMC_D[15:0] MS32768V1 Figure 63. NAND controller waveforms for common memory read access FMC_NCEx ALE (FMC_A17) CLE (FMC_A16) th(NOE-ALE) td(ALE-NOE) FMC_NWE tw(NOE) FMC_NOE tsu(D-NOE) th(NOE-D) FMC_D[15:0] MS32769V1 DS12536 Rev 1 175/201 184 Electrical characteristics STM32F730x8 Figure 64. NAND controller waveforms for common memory write access FMC_NCEx ALE (FMC_A17) CLE (FMC_A16) td(ALE-NOE) tw(NWE) th(NOE-ALE) FMC_NWE FMC_N OE td(D-NWE) tv(NWE-D) th(NWE-D) FMC_D[15:0] MS32770V1 Table 105. Switching characteristics for NAND Flash read cycles(1) Symbol tw(N0E) Parameter FMC_NOE low width Min Max 4Thclk -0.5 4Thclk +0.5 tsu(D-NOE) FMC_D[15-0] valid data before FMC_NOE high 11 - th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high 0 - td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 3Thclk +1.5 th(NOE-ALE) FMC_NWE high to FMC_ALE invalid 4Thclk - 2 - Unit ns 1. Guaranteed by characterization results. Table 106. Switching characteristics for NAND Flash write cycles(1) Symbol tw(NWE) Parameter FMC_NWE low width Max 4Thclk -0.5 4Thclk +0.5 0 - tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 2Thclk - 1 - td(D-NWE) FMC_D[15-0] valid before FMC_NWE high 5Thclk - 1 - - 3Thclk +1.5 2Thclk - 2 - td(ALE-NWE) FMC_ALE valid before FMC_NWE low th(NWE-ALE) FMC_NWE high to FMC_ALE invalid 1. Guaranteed by characterization results. 176/201 Min DS12536 Rev 1 Unit ns STM32F730x8 Electrical characteristics SDRAM waveforms and timings * CL = 30 pF on data and address lines. CL = 10 pF on FMC_SDCLK unless otherwise specified. In all timing tables, the THCLK is the HCLK clock period. - For 3.0 VVDD3.6 V, maximum FMC_SDCLK= 100 MHz at CL=20 pF (on FMC_SDCLK). - For 2.7 VVDD3.6 V, maximum FMC_SDCLK = 90 MHz at CL=30 pF (on FMC_SDCLK). - For 1.71 VVDD<1.9 V, maximum FMC_SDCLK = 70 MHz at CL=10 pF (on FMC_SDCLK). Figure 65. SDRAM read access waveforms (CL = 1) FMC_SDCLK td(SDCLKL_AddC) th(SDCLKL_AddR) td(SDCLKL_AddR) FMC_A[12:0] Row n Col1 Col2 Coli Coln th(SDCLKL_AddC) th(SDCLKL_SNDE) td(SDCLKL_SNDE) FMC_SDNE[1:0] td(SDCLKL_NRAS) th(SDCLKL_NRAS) FMC_SDNRAS th(SDCLKL_NCAS) td(SDCLKL_NCAS) FMC_SDNCAS FMC_SDNWE tsu(SDCLKH_Data) FMC_D[31:0] th(SDCLKH_Data) Data1 Data2 Datai Datan MS32751V2 DS12536 Rev 1 177/201 184 Electrical characteristics STM32F730x8 Table 107. SDRAM read timings(1) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2Thclk -0.5 2Thclk +0.5 tsu(SDCLKH _Data) Data input setup time 1.5 - th(SDCLKH_Data) Data input hold time 2 - td(SDCLKL_Add) Address valid time - 1.5 td(SDCLKL- SDNE) Chip select valid time - 1.5 th(SDCLKL_SDNE) Chip select hold time 0.5 - td(SDCLKL_SDNRAS) SDNRAS valid time - 1 th(SDCLKL_SDNRAS) SDNRAS hold time 0.5 - td(SDCLKL_SDNCAS) SDNCAS valid time - 1.5 th(SDCLKL_SDNCAS) SDNCAS hold time 0 - Unit ns 1. Guaranteed by characterization results. Table 108. LPSDR SDRAM read timings(1) Symbol Parameter Min Max tW(SDCLK) FMC_SDCLK period 2Thclk -0.5 2Thclk +0.5 tsu(SDCLKH_Data) Data input setup time 0 - th(SDCLKH_Data) Data input hold time 4.5 - td(SDCLKL_Add) Address valid time - 1.5 td(SDCLKL_SDNE) Chip select valid time - 1.5 th(SDCLKL_SDNE) Chip select hold time 0 - td(SDCLKL_SDNRAS SDNRAS valid time - 0.5 th(SDCLKL_SDNRAS) SDNRAS hold time 0 - td(SDCLKL_SDNCAS) SDNCAS valid time - 1.5 th(SDCLKL_SDNCAS) SDNCAS hold time 0 - 1. Guaranteed by characterization results. 178/201 DS12536 Rev 1 Unit ns STM32F730x8 Electrical characteristics Figure 66. SDRAM write access waveforms FMC_SDCLK td(SDCLKL_AddC) th(SDCLKL_AddR) td(SDCLKL_AddR) FMC_A[12:0] Row n Col1 Col2 Coli Coln th(SDCLKL_AddC) th(SDCLKL_SNDE) td(SDCLKL_SNDE) FMC_SDNE[1:0] th(SDCLKL_NRAS) td(SDCLKL_NRAS) FMC_SDNRAS td(SDCLKL_NCAS) th(SDCLKL_NCAS) td(SDCLKL_NWE) th(SDCLKL_NWE) FMC_SDNCAS FMC_SDNWE td(SDCLKL_Data) Data1 FMC_D[31:0] Data2 Datai Datan th(SDCLKL_Data) td(SDCLKL_NBL) FMC_NBL[3:0] MS32752V2 Table 109. SDRAM write timings(1) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2Thclk -0.5 2Thclk +0.5 td(SDCLKL _Data) Data output valid time - 1.5 th(SDCLKL _Data) Data output hold time 0 - td(SDCLKL_Add) Address valid time - 1.5 td(SDCLKL_SDNWE) SDNWE valid time - 1.5 th(SDCLKL_SDNWE) SDNWE hold time 0.5 - td(SDCLKL_ SDNE) Chip select valid time - 1.5 th(SDCLKL-_SDNE) Chip select hold time 0.5 - td(SDCLKL_SDNRAS) SDNRAS valid time - 1 th(SDCLKL_SDNRAS) SDNRAS hold time 0.5 - td(SDCLKL_SDNCAS) SDNCAS valid time - 1.5 td(SDCLKL_SDNCAS) SDNCAS hold time 0.5 - Unit ns 1. Guaranteed by characterization results. DS12536 Rev 1 179/201 184 Electrical characteristics STM32F730x8 Table 110. LPSDR SDRAM write timings(1) Symbol Parameter Min Max tw(SDCLK) FMC_SDCLK period 2Thclk -0.5 2Thclk +0.5 td(SDCLKL _Data) Data output valid time - 2 th(SDCLKL _Data) Data output hold time 0 - td(SDCLKL_Add) Address valid time - 1.5 td(SDCLKL-SDNWE) SDNWE valid time - 1.5 th(SDCLKL-SDNWE) SDNWE hold time 0 - td(SDCLKL- SDNE) Chip select valid time - 0.5 th(SDCLKL- SDNE) Chip select hold time 0. - td(SDCLKL-SDNRAS) SDNRAS valid time - 2 th(SDCLKL-SDNRAS) SDNRAS hold time 0 - td(SDCLKL-SDNCAS) SDNCAS valid time - 2 td(SDCLKL-SDNCAS) SDNCAS hold time 0 - Unit ns 1. Guaranteed by characterization results. 6.3.31 Quad-SPI interface characteristics Unless otherwise specified, the parameters given in Table 111 and Table 112 for Quad-SPI are derived from tests performed under the ambient temperature, fAHB frequency and VDD supply voltage conditions summarized in Table 16: General operating conditions, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Capacitive load C = 20 pF * Measurement points are done at CMOS levels: 0.5 VDD Refer to Section 6.3.20: I/O port characteristics for more details on the input/output alternate function characteristics. Table 111. Quad-SPI characteristics in SDR mode(1) Symbol Fck1/t(CK) 180/201 Parameter Quad-SPI clock frequency Conditions Min Typ Max 2.7 VVDD<3.6 V CL=20 pF - - 108 1.71 V<VDD<3.6 V CL=15 pF - DS12536 Rev 1 Unit MHz - 100 STM32F730x8 Electrical characteristics Table 111. Quad-SPI characteristics (continued)in SDR mode(1) (continued) Symbol Parameter Conditions Min Typ Max tw(CKH) tw(CKL) Quad-SPI clock high and low time - ts(IN) Data input setup time t(CK)/2 - 0.5 - t(CK)/2 + 0.5 t(CK)/2 - 0.5 - t(CK)/2 + 0.5 3 - - th(IN) Data input hold time 1 - - tv(OUT) Data output valid time 2.7 V<VDD<3.6 V - 1.5 3 1.71 V<VDD<3.6 V - 1.5 2.5 th(OUT) Data output hold time - 0.5 - - - Unit ns 1. Guaranteed by characterization results. Table 112. Quad-SPI characteristics in DDR mode(1) Symbol Parameter Fck1/t(CK) Quad-SPI clock frequency tw(CKH) tw(CKL) Quad-SPI clock high and low time ts(IN), tsf(IN) Data input setup time thr(IN), thf(IN) Data input hold time tvr(OUT), tvf(OUT) thr(OUT), thf(OUT) Data output valid time Data output hold time Conditions Min Typ Max 2.7 V<VDD<3.6 V CL=20 pF - - 80 1.8 V<VDD<3.6 V CL=15 pF - - 80 1.71 V<VDD<3.6 V CL=10 pF - - 80 t(CK)/2 0.5 - t(CK)/2 + 0.5 t(CK)/2 0.5 - t(CK)/2 + 0.5 2.7 V<VDD<3.6 V 1 - - 1.71 V<VDD<2 V 0.5 - - 2.7 V<VDD<3.6 V 2.25 - - 1.71 V<VDD<2 V 2.75 - - 2.7 V<VDD<3.6 V - 9.5 11.5 1.71 V<VDD<3.6 V DHHC=0 - 9.5 12.25 DHHC=1 Pres=1, 2... - Thclk/2 +2 Thclk/2 +2.5 DHHC=0 5.5 - - DHHC=1 Pres=1, 2... Thclk/2 +0.75 - - - Unit MHz ns 1. Guaranteed by characterization results. DS12536 Rev 1 181/201 184 Electrical characteristics STM32F730x8 Figure 67. Quad-SPI timing diagram - SDR mode tr(CK) t(CK) tw(CKH) tw(CKL) tf(CK) Clock tv(OUT) th(OUT) Data output D1 D0 ts(IN) Data input D0 D2 th(IN) D1 D2 MSv36878V1 Figure 68. Quad-SPI timing diagram - DDR mode tr(CK) t(CK) tw(CKH) tw(CKL) tf(CK) Clock tvf(OUT) Data output thr(OUT) D0 tvr(OUT) D1 D2 thf(OUT) D3 tsf(IN) thf(IN) Data input D0 D1 D4 D5 tsr(IN) thr(IN) D2 D3 D4 D5 MSv36879V1 6.3.32 SD/SDIO MMC card host interface (SDMMC) characteristics Unless otherwise specified, the parameters given in Table 113 for the SDIO/MMC interface are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDD supply voltage conditions summarized in Table 16, with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Capacitive load C = 30 pF * Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.20: I/O port characteristics for more details on the input/output characteristics. 182/201 DS12536 Rev 1 STM32F730x8 Electrical characteristics Figure 69. SDIO high-speed mode Figure 70. SD default mode CK tOVD tOHD D, CMD (output) ai14888 Table 113. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V(1) Symbol Parameter Conditions Min Typ Max Unit fPP Clock frequency in data transfer mode - 0 - 50 MHz - SDMMC_CK/fPCLK2 frequency ratio - - - 8/3 - tW(CKL) Clock low time fpp =50 MHz 9 10 - tW(CKH) Clock high time fpp =50 MHz 9 10 - ns CMD, D inputs (referenced to CK) in MMC and SD HS mode tISU Input setup time HS fpp =50 MHz 1 - - tIH Input hold time HS fpp =50 MHz 3 - - ns CMD, D outputs (referenced to CK) in MMC and SD HS mode tOV Output valid time HS fpp =50 MHz - 11 12 tOH Output hold time HS fpp =50 MHz 9 - - DS12536 Rev 1 ns 183/201 184 Electrical characteristics STM32F730x8 Table 113. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V(1) (continued) Symbol Parameter Conditions Min Typ Max Unit CMD, D inputs (referenced to CK) in SD default mode tISUD Input setup time SD fpp =25 MHz 1 - - tIHD Input hold time SD fpp =25 MHz 3 - - ns CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time SD fpp =25 MHz - 2 2.5 tOHD Output hold default time SD fpp =25 MHz 0.5 - - ns 1. Guaranteed by characterization results,. Table 114. Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V(1)(2) Symbol Parameter Conditions Min Typ Max Unit fPP Clock frequency in data transfer mode - 0 - 50 MHz - SDMMC_CK/fPCLK2 frequency ratio - - - 8/3 - tW(CKL) Clock low time fpp =50 MHz 9.5 10.5 - tW(CKH) Clock high time fpp =50 MHz 8.5 9.5 - ns CMD, D inputs (referenced to CK) in eMMC mode tISU Input setup time HS fpp =50 MHz 0 - - tIH Input hold time HS fpp =50 MHz 4.5 - - ns CMD, D outputs (referenced to CK) in eMMC mode tOV Output valid time HS fpp =50 MHz - 12 14 tOH Output hold time HS fpp =50 MHz 10.5 - - 1. Guaranteed by characterization results. 2. Cload = 20 pF. 184/201 DS12536 Rev 1 ns STM32F730x8 7 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. LQFP64 - 10 x 10 mm, low-profile quad flat package information Figure 71. LQFP64 - 10 x 10 mm, low-profile quad flat package outline 0.25 mm GAUGE PLANE c A1 A SEATING PLANE C A2 A1 ccc C D D1 D3 K L L1 33 48 32 49 64 E E1 b E3 7.1 17 16 1 PIN 1 IDENTIFICATION e 5W_ME_V3 1. Drawing is not to scale. Table 115. LQFP64 - 10 x 10 mm, low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.60 - - 0.0630 A1 0.05 - 0.15 0.0020 - 0.0059 A2 1.350 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 DS12536 Rev 1 185/201 197 Package information STM32F730x8 Table 115. LQFP64 - 10 x 10 mm, low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max c 0.09 - 0.20 0.0035 - 0.0079 D - 12.00 - - 0.4724 - D1 - 10.00 - - 0.3937 - D3 - 7.50 - - 0.2953 - E - 12.00 - - 0.4724 - E1 - 10.00 - - 0.3937 - E3 - 7.50 - - 0.2953 - e - 0.50 - - 0.0197 - K 0 3.5 7 0 3.5 7 L 0.45 0.60 0.75 0.0177 0.0236 0.0295 L1 - 1.00 - - 0.0394 - ccc - - 0.08 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 72. LQFP64 - 10 x 10 mm, low-profile quad flat package recommended footprint 48 33 0.3 0.5 49 32 12.7 10.3 10.3 17 64 1.2 16 1 7.8 12.7 ai14909c 1. Dimensions are in millimeters. 186/201 DS12536 Rev 1 STM32F730x8 Package information LQFP64 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 73. LQFP64 - 10 x 10 mm, low-profile quad flat package top view example Revision code Product identification(1) R STM32F730 R8T6 Date code Y WW Pin 1 indentifier MSv50811V1 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS12536 Rev 1 187/201 197 Package information 7.2 STM32F730x8 LQFP100, 14 x 14 mm low-profile quad flat package information Figure 74. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline 0.25 mm c A1 A A2 SEATING PLANE C GAUGE PLANE D L D1 A1 K ccc C L1 D3 51 75 50 100 E E3 E1 b 76 26 PIN 1 1 IDENTIFICATION 25 e 1L_ME_V5 1. Drawing is not to scale. Table 116. LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol 188/201 Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.6220 0.6299 0.6378 DS12536 Rev 1 STM32F730x8 Package information Table 116. LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0 3.5 7 0 3.5 7 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 75. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package recommended footprint 75 76 51 50 0.5 0.3 16.7 14.3 100 26 1.2 1 25 12.3 16.7 ai14906c 1. Dimensions are expressed in millimeters. DS12536 Rev 1 189/201 197 Package information STM32F730x8 LQFP100 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 76. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package top view example Product identification (1) STM32F730 V8T6 Revision code R Date code Y WW Pin 1 identifier MS50812V1 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 190/201 DS12536 Rev 1 STM32F730x8 LQFP144, 20 x 20 mm low-profile quad flat package information Figure 77. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline c A1 A SEATING PLANE C A2 0.25 mm ccc C D L D1 K A1 GAUGE PLANE L1 D3 108 73 109 72 E E3 E1 b 7.3 Package information 37 144 1 PIN 1 IDENTIFICATION 36 e 1A_ME_V3 1. Drawing is not to scale. Table 117. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.874 DS12536 Rev 1 191/201 197 Package information STM32F730x8 Table 117. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.500 - - 0.689 - E 21.800 22.000 22.200 0.8583 0.8661 0.8740 E1 19.800 20.000 20.200 0.7795 0.7874 0.7953 E3 - 17.500 - - 0.6890 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0 3.5 7 0 3.5 7 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 78. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package recommended footprint 108 109 73 1.35 72 0.35 0.5 19.9 17.85 22.6 144 37 1 36 19.9 22.6 ai14905e 1. Dimensions are expressed in millimeters. 192/201 DS12536 Rev 1 STM32F730x8 Package information LQP144 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 79. LQFP144, 20 x 20mm, 144-pin low-profile quad flat package top view example Revision code Product identification(1) R STM32F730Z8T6 Y WW Pin 1 identifier Date code MS50813V1 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS12536 Rev 1 193/201 197 Package information 7.4 STM32F730x8 UFBGA176+25, 10 x 10, 0.65 mm ultra thin-pitch ball grid array package information Figure 80. UFBGA176+25, 10 x 10 x 0.65 mm ultra thin fine-pitch ball grid array package outline C Seating plane A2 A4 ddd C A1 b A A1 ball identifier e A1 ball index area A E F A F D e B R 15 1 BOTTOM VIEW Ob (176 + 25 balls) TOP VIEW O eee M C A B O fff M C A0E7_ME_V6 1. Drawing is not to scale. Table 118. UFBGA176+25, 10 x 10 x 0.65 mm ultra thin fine-pitch ball grid array package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.002 0.0031 0.0043 A2 0.400 0.450 0.500 0.0157 0.0177 0.0197 b 0.230 0.280 0.330 0.0091 0.0110 0.0130 D 9.950 10.000 10.050 0.3917 0.3937 0.3957 E 9.950 10.000 10.050 0.3917 0.3937 0.3957 e - 0.650 - - 0.0256 - F 0.400 0.450 0.500 0.0157 0.0177 0.0197 ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 194/201 DS12536 Rev 1 STM32F730x8 Package information Figure 81. UFBGA176+25, 10 x 10 mm x 0.65 mm, ultra fine-pitch ball grid array package recommended footprint Dpad Dsm A0E7_FP_V1 Table 119. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) Dimension Recommended values Pitch 0.65 mm Dpad 0.300 mm Dsm 0.400 mm typ. (depends on the soldermask registration tolerance) Stencil opening 0.300 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.100 mm DS12536 Rev 1 195/201 197 Package information STM32F730x8 UFBGA176+25 device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 82. UFBGA176+25, 10 x 10 x 0.6 mm ultra thin fine-pitch ball grid array package top view example Revision code Product identification(1) R STM32F730 I8K6 Date code Ball A1 indentifier Y WW MS50810V1 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 196/201 DS12536 Rev 1 STM32F730x8 7.5 Package information Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x JA) Where: * TA max is the maximum ambient temperature in C, * JA is the package junction-to-ambient thermal resistance, in C/W, * PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), * PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = (VOL x IOL) + ((VDD - VOH) x IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 120. Package thermal characteristics Symbol JA Parameter Value Thermal resistance junction-ambient LQFP64 - 10 x 10 mm / 0.5 mm pitch 48.5 Thermal resistance junction-ambient LQFP100 - 14x 14 mm / 0.5 mm pitch 47.1 Thermal resistance junction-ambient LQFP144 - 20 x 20 mm / 0.5 mm pitch 45.6 Thermal resistance junction-ambient UFBGA176 - 10x 10 mm / 0.65 mm pitch 41.2 Unit C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. DS12536 Rev 1 197/201 197 Ordering information 8 STM32F730x8 Ordering information Table 121. Ordering information scheme Example: STM32 F 730 V 8 T 6 xxx Device family STM32 = Arm-based 32-bit microcontroller Product type F = general-purpose Device subfamily 730 = STM32F730x8, with and without OTG PHY HS Pin count R = 64 pins V = 100 pins Z = 144 pins I = 176 pins Flash memory size 8 = 64 Kbytes of Flash memory Package T = LQFP K = UFBGA (10 x 10 mm) Temperature range 6 = Industrial temperature range, -40 to 85 C. 7 = Industrial temperature range, -40 to 105 C. Options xxx = programmed parts TR = tape and reel For a list of available options (speed, package, etc.) or for further information on any aspect of this device, contact the nearest ST sales office. 198/201 DS12536 Rev 1 STM32F730x8 Recommendations when using internal reset OFF Appendix A Recommendations when using internal reset OFF When the internal reset is OFF, the following integrated features are no longer supported: A.1 * The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled. * The brownout reset (BOR) circuitry must be disabled. * The embedded programmable voltage detector (PVD) is disabled. * VBAT functionality is no more available and VBAT pin should be connected to VDD. * The over-drive mode is not supported. Operating conditions Table 122. Limitations depending on the operating power supply range Operating power supply range ADC operation Maximum Flash memory access frequency with no wait states (fFlashmax) VDD =1.7 to 2.1 V(3) Conversion time up to 1.2 Msps 20 MHz Maximum Flash memory access frequency with wait states (1)(2) 180 MHz with 8 wait states and over-drive OFF I/O operation Possible Flash memory operations 8-bit erase and - No I/O program compensation operations only 1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is required. 2. Thanks to the ART accelerator on ITCM interface and L1-cache on AXI interface, the number of wait states given here does not impact the execution speed from the Flash memory since the ART accelerator or L1cache allows to achieve a performance equivalent to 0-wait state program execution. 3. VDD/VDDA minimum value of 1.7 V, with the use of an external power supply supervisor (refer to Section 3.15.1: Internal reset ON). DS12536 Rev 1 199/201 200 Revision history STM32F730x8 Revision history Table 123. Document revision history 200/201 Date Revision 27-Jun-2018 1 Changes Initial release. DS12536 Rev 1 STM32F730x8 IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2018 STMicroelectronics - All rights reserved DS12536 Rev 1 201/201 201