512Mb: x4, x8, x16 DDR2 SDRAM
Features
PDF: 09005aef8117c18e/Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_1.fm - Rev. K 3/06 EN 1©2004 Micron Technology, Inc. All rights reserved.
DDR2 SDRAM
MT47H128M4 – 32 Meg x 4 x 4 banks
MT47H64M8 – 16 Meg x 8 x 4 banks
MT47H32M16 – 8 Meg x 16 x 4 banks
For the latest data sheet, refer to Micron’s Web site: http://www.micron.com/ddr2
Features
•RoHS compliant
•V
DD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V
• JEDEC standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• 4-bit prefetch architecture
• Duplicate output strobe (RDQS) option for x8
• DLL to align DQ and DQS transitions with CK
• 4 internal banks for concurrent operation
• Programmable CAS latency (CL)
• Posted CAS additive latency (AL)
• WRITE latency = READ latency – 1 tCK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
• Industrial temperature (IT) option
• Supports JEDEC clock jitter specification
Options Marking
• Configuration
128 Meg x 4 (32 Meg x 4 x 4 banks) 128M4
64 Meg x 8 (16 Meg x 8 x 4 banks) 64M8
32 Meg x 16 (8 Meg x 16 x 4 banks) 32M16
• FBGA package (lead-free)
84-ball FBGA (12mm x 12.5mm) (:B)
(10mm x 12.5mm) (:D)
CC
BN
60-ball FBGA (12mm x 10mm) (:B)
(10mm x 10mm) (:D)
CB
B6
• Timing – cycle time
5.0ns @ CL = 3 (DDR2-400) -5E
3.75ns @ CL = 4 (DDR2-533) -37E
3.0ns @ CL = 5 (DDR2-667) -3
3.0ns @ CL = 4 (DDR2-667) -3E
2.5ns @ CL = 6 (DDR2-800) -25
2.5ns @ CL = 5 (DDR2-800) -25E
• Self refresh
Standard None
Low-power L
• Operating temperature
Commercial
(0°C
≤
T
C
≤
85°C)
None
Industrial
(–40°C
≤
T
C
≤
95°C; –40°C
≤
T
A
≤
85°C)
IT
• Revision :A/:B/:D
Table 1: Configuration Addressing
Architecture
128 Meg x 4 64 Meg x 8
32 Meg x 16
Configuration 32 Meg x 4 x 4
banks
16 Meg x 8 x
4 banks
8 Meg x 16 x
4 banks
Refresh Count 8K 8K 8K
Row Addr. 16K (A0–A13)
16K (A0–A13)
8K (A0–A12)
Bank Addr. 4 (BA0–BA1) 4 (BA0–BA1) 4 (BA0–BA1)
Column Addr.
2K (A0–A9, A11)
1K (A0–A9) 1K (A0–A9)
Note: CL = CAS latency.
Table 2: Key Timing Parameters
Speed
Grade
Data Rate (MHz) tRCD
(ns)
tRP
(ns)
tRC
(ns)CL = 3 CL = 4 CL = 5 CL = 6
-5E 400 400 N/A N/A 15 15 55
-37E 400 533 N/A N/A 15 15 55
-3 400 533 667 N/A 15 15 55
-3E N/A667667N/A121254
-25 N/A N/A 667 800 15 15 55
-25E N/A 533 800 N/A 12.5 12.5 55
PDF: 09005aef8117c18e/Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2TOC.fm - Rev. K 3/06 EN 2©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Table of Contents
Table of Contents
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
FBGA Part Marking Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Industrial Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
General Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Ball Assignment and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Mode Register (MR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
DLL RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Write Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Extended Mode Register (EMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
DLL Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Output Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
DQS# Enable/Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
RDQS Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Output Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
On-Die Termination (ODT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Off-Chip Driver (OCD) Impedance Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Posted CAS Additive Latency (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Extended Mode Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Extended Mode Register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Command Truth Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
DESELECT, NOP, and LM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
LOAD MODE (LM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Bank/Row Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
ACTIVE Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
ACTIVE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
PRECHARGE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
SELF REFRESH Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
REFRESH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
REFRESH Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Power-Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Precharge Power-Down Clock Frequency Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
PDF: 09005aef8117c18e/Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2TOC.fm - Rev. K 3/06 EN 3©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Table of Contents
RESET Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
(CKE LOW Anytime) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
ODT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
MRS Command to ODT Update Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Temperature and Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
AC and DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Input Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Input Slew Rate Derating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Power and Ground Clamp Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
AC Overshoot/Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Output Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Full Strength Pull-Down Driver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Full Strength Pull-Up Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Reduced Strength Pull-Down Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Reduced Strength Pull-Up Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
FBGA Package Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
IDD7 Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
AC Operating Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
PDF: 09005aef8117c18e/Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2LOF.fm - Rev. K 3/06 EN 4©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
List of Figures
List of Figures
Figure 1: 512Mb DDR2 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 2: 84-Ball FBGA (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 3: 60-Ball FBGA (x4, x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 4: Functional Block Diagram – 32 Meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 5: Functional Block Diagram – 64 Meg x 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 6: Functional Block Diagram – 128 Meg x 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 7: DDR2 Power-up and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 8: Mode Register (MR) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 9: CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 10: Extended Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 11: READ Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 12: WRITE Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Figure 13: Extended Mode Register 2 (EMR2) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Figure 14: Extended Mode Register 3 (EMR3) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 15: ACTIVE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Figure 16: READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 17: Example: Meeting tRRD (MIN) and tRCD (MIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 18: READ Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Figure 19: Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 20: Nonconsecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Figure 21: READ Interrupted by READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Figure 22: READ-to-PRECHARGE – BL = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Figure 23: READ-to-PRECHARGE – BL = 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Figure 24: READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Figure 25: Bank Read – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Figure 26: Bank Read – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Figure 27: x4, x8 Data Output Timing – tDQSQ, tQH, and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Figure 28: x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Figure 29: Data Output Timing – tAC and tDQSCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Figure 30: WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Figure 31: WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Figure 32: Consecutive WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Figure 33: Nonconsecutive WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Figure 34: Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Figure 35: WRITE Interrupted by WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Figure 36: WRITE-to-READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Figure 37: WRITE-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Figure 38: Bank Write – without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Figure 39: Bank Write – with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Figure 40: WRITE – DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Figure 41: Data Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Figure 42: PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Figure 43: Self Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Figure 44: Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Figure 45: Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Figure 46: READ to Power-Down or Self Refresh Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Figure 47: READ with Auto Precharge to Power-Down or Self Refresh Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Figure 48: WRITE to Power-Down or Self-Refresh Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Figure 49: WRITE with Auto Precharge to Power-Down or Self Refresh Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Figure 50: REFRESH Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Figure 51: ACTIVE Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Figure 52: PRECHARGE Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Figure 53: LOAD MODE Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Figure 54: Input Clock Frequency Change During Precharge Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . .71
Figure 55: RESET Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Figure 56: ODT Timing for Entering and Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
PDF: 09005aef8117c18e/Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2LOF.fm - Rev. K 3/06 EN 5©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
List of Figures
Figure 57: Timing for MRS Command to ODT Update Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Figure 58: ODT Timing for Active or Fast-Exit Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Figure 59: ODT Timing for Slow-Exit or Precharge Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Figure 60: ODT Turn-off Timings when Entering Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Figure 61: ODT Turn-On Timing when Entering Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Figure 62: ODT Turn-Off Timing when Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Figure 63: ODT Turn-on Timing when Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Figure 64: Example Temperature Test Point Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Figure 65: Single-Ended Input Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Figure 66: Differential Input Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Figure 67: Nominal Slew Rate for tIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Figure 68: Tangent Line for tIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Figure 69: Nominal Slew Rate for tIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Figure 70: Tangent Line for tIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Figure 71: Nominal Slew Rate for tDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Figure 72: Tangent Line for tDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Figure 73: Nominal Slew Rate for tDH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 74: Tangent Line for tDH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 75: AC Input Test Signal Waveform Command/Address Balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 76: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential) . . . . . . . . . . . . . . . . . . . . . 102
Figure 77: AC Input Test Signal Waveform for Data with DQS (single-ended) . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 78: AC Input Test Signal Waveform (differential) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 79: Input Clamp Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 80: Overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 81: Undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 82: Differential Output Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 83: Output Slew Rate Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 84: Full Strength Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 85: Full Strength Pull-up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 86: Reduced Strength Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 87: Reduced Strength Pull-up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 88: 84-Ball FBGA Package – 12mm x 12.5mm (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 89: 84-Ball FBGA Package – 10mm x 12.5mm (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 90: 60-Ball FBGA Package – 12mm x 10mm (x4, x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 91: 60-Ball FBGA Package – 10mm x 10mm (x4, x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
PDF: 09005aef8117c18e/Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2LOT.fm - Rev. K 3/06 EN 6©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
List of Tables
List of Tables
Table 1: Configuration Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table 2: Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table 3: FBGA 84-/60-Ball Descriptions – 128 Meg x 4, 64 Meg x 8, 32 Meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 4: Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 5: Truth Table – DDR2 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 6: Truth Table – Current State Bank n - Command to Bank n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 7: Truth Table – Current State Bank n - Command to Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 8: Minimum Delay with Auto Precharge Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 9: READ Using Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 10: WRITE Using Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Table 11: CKE Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Table 12: DDR2-400/533 ODT Timing for Active and Fast-Exit Power-Down Modes . . . . . . . . . . . . . . . . . . . . .76
Table 13: DDR2-400/533 ODT Timing for Slow-Exit and Precharge Power-Down Modes . . . . . . . . . . . . . . . . .77
Table 14: DDR2-400/533 ODT Turn-off Timings when Entering Power-Down Mode . . . . . . . . . . . . . . . . . . . . .78
Table 15: DDR2-400/533 ODT Turn-on Timing when Entering Power-Down Mode . . . . . . . . . . . . . . . . . . . . . .79
Table 16: DDR2-400/533 ODT Turn-off Timing when Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . .80
Table 17: DDR2-400/533 ODT Turn-On Timing when Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . .81
Table 17: Absolute Maximum DC Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Table 18: Temperature Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Table 19: Thermal Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Table 20: Recommended DC Operating Conditions (SSTL_18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Table 21: ODT DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Table 22: Input DC Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Table 23: Input AC Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Table 24: Differential Input Logic Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Table 25: AC Input Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Table 26: DDR2-400/533 Setup and Hold Time Derating Values (tIS and tIH). . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Table 27: DDR2-667 Setup and Hold Time Derating Values (tIS and tIH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Table 28: DDR2-400/533 tDS, tDH Derating Values with Differential Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Table 29: DDR2-667 tDS, tDH Derating Values with Differential Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Table 30: Single-Ended DQS Slew Rate Derating Values Using tDSb and tDHb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Table 31: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-667 . . . . . . . . . . . . . . . . . . .96
Table 32: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-533 . . . . . . . . . . . . . . . . . . .97
Table 33: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-400 . . . . . . . . . . . . . . . . . . .97
Table 34: Input Clamp Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 35: Address and Control Balls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 36: Clock, Data, Strobe, and Mask Balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 37: Differential AC Output Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 38: Output DC Current Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 39: Output Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 40: Full Strength Pull-Down Current (mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 41: Full Strength Pull-Up Current (mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 42: Reduced Strength Pull-Down Current (mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 43: Reduced Strength Pull-Up Current (mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 44: Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 45: DDR2 IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 46: General IDD Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 47: IDD7 Timing Patterns (4-bank) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 48: AC Operating Conditions for -3E, -3, -37E, and -5E Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 49: AC Operating Conditions for -25E and -25 Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 7©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Part Numbers
Part Numbers
Figure 1: 512Mb DDR2 Part Numbers
Note: Not all speeds and configurations are available. Contact Micron sales for current revision.
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part
marking that is different from the part number. Micron’s FBGA Part Marking Decoder is
available at www.micron.com/decoder.
General Description
The 512Mb DDR2 SDRAM is a high-speed CMOS, dynamic random access memory
containing 536,870,912 bits. It is internally configured as a 4-bank DRAM. The functional
block diagrams of the all device configurations are shown in “Functional Description”
on page 14. Ball assignments and signal descriptions are shown in “Ball Assignment and
Description” on page 9.
The 512Mb DDR2 SDRAM uses a double data rate architecture to achieve high-speed
operation. The double data rate architecture is essentially a 4n-prefetch architecture,
with an interface designed to transfer two data words per clock cycle at the I/O balls. A
single read or write access for the 512Mb DDR2 SDRAM effectively consists of a single
4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corre-
sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls.
A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM
during READs and by the memory controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for WRITEs. The x16 offering has two data
strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS,
UDQS#).
Package
84-Ball 12 x 12.5 FBGA
84-Ball 10 x 12.5 FBGA
60-Ball 12 x 10 FBGA
60-Ball 10 x 10 FBGA
CC
BN
CB
B6
Example Part Number: MT47H64M8BT-37E :A
Configuration
128 Meg x 4
64 Meg x 8
32 Meg x 16
128M4
64M8
32M16
Speed Grade
tCK = 5ns, CL = 3
tCK = 3.75ns, CL = 4
tCK = 3ns, CL = 5
tCK = 3ns, CL = 4
tCK = 2.5ns, CL = 6
tCK = 2.5ns, CL = 5
-5E
-37E
-3
-3E
-25
-25E
-
Configuration
MT47H PackageSpeed
Revision
Revision
:A/:B/:D
:
Low-Power
Industrial Temperature
L
IT
{
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 8©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
General Description
The 512Mb DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing
of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is referenced to both
edges of DQS as well as to both edges of CK.
Read and write accesses to the DDR2 SDRAM are burst-oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed. The address bits
registered coincident with the READ or WRITE command are used to select the bank and
the starting column location for the burst access.
The DDR2 SDRAM provides for programmable read or write burst lengths of four or
eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another
read or a burst write of eight with another write. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
access.
As with standard DDR SDRAMs, the pipelined, multibank architecture of DDR2 SDRAMs
allows for concurrent operation, thereby providing high, effective bandwidth by hiding
row precharge and activation time.
A self refresh mode is provided, along with a power-saving, power-down mode.
All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength
outputs are SSTL_18-compatible.
Industrial Temperature
The industrial temperature (IT) device has two simultaneous requirements: ambient
temperature surrounding the device cannot exceed –40°C or +85°C, and the case
temperature cannot exceed –40°C or 95°C. JEDEC specifications require the refresh rate
to double when TC exceeds 85°C; this also requires use of the high-temperature self
refresh option. Additionally, ODT resistance and the input/output impedance must be
derated when the TC is < 0°C or > 85°C.
General Notes
• The functionality and the timing specifications discussed in this data sheet are for the
DLL-enabled mode of operation.
• Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ
term is to be interpreted as any and all DQ collectively, unless specifically stated
otherwise. Additionally, the x16 is divided into 2 bytes, the lower byte and upper byte.
For the lower byte (DQ0–DQ7), DM refers to LDM and DQS refers to LDQS. For the
upper byte (DQ8–DQ15), DM refers to UDM and DQS refers to UDQS.
• Complete functionality is described throughout the document, and any page or
diagram may have been simplified to convey a topic and may not be inclusive of all
requirements.
• Any specific requirement takes precedence over a general statement.
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 9©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Ball Assignment and Description
Ball Assignment and Description
Figure 2: 84-Ball FBGA (x16)
12mm x 12.5mm and 10mm x 12.5mm (top view)
1234 67895
VDD
DQ14
VDDQ
DQ12
VDD
DQ6
VDDQ
DQ4
VDDL
RFU
VSS
VDD
NC
VSSQ
DQ9
VSSQ
NC
VSSQ
DQ1
VSSQ
VREF
CKE
BA0
A10
A3
A7
A12
VSS
UDM
VDDQ
DQ11
VSS
LDM
VDDQ
DQ3
VSS
WE#
BA1
A1
A5
A9
RFU
VSSQ
UDQS
VDDQ
DQ10
VSSQ
LDQS
VDDQ
DQ2
VSSDL
RAS#
CAS#
A2
A6
A11
RFU
VDDQ
DQ15
VDDQ
DQ13
VDDQ
DQ7
VDDQ
DQ5
VDD
ODT
VDD
VSS
UDQS#/NU
VSSQ
DQ8
VSSQ
LDQS#/NU
VSSQ
DQ0
VSSQ
CK
CK#
CS#
A0
A4
A8
RFU
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 10 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Ball Assignment and Description
Figure 3: 60-Ball FBGA (x4, x8)
12mm x 10mm and 10mm x 10mm (top view)
1234 67895
VDD
NF, DQ6
VDDQ
NF, DQ4
VDDL
RFU
VSS
VDD
NF, RDQS#/NU
VSSQ
DQ1
VSSQ
VREF
CKE
BA0
A10
A3
A7
A12
VSS
DM, DM/RDQS
VDDQ
DQ3
VSS
WE#
BA1
A1
A5
A9
RFU
VSSQ
DQS
VDDQ
DQ2
VSSDL
RAS#
CAS#
A2
A6
A11
RFU
VDDQ
NF, DQ7
VDDQ
NF, DQ5
VDD
ODT
VDD
VSS
DQS#/NU
VSSQ
DQ0
VSSQ
CK
CK#
CS#
A0
A4
A8
A13
A
B
C
D
E
F
G
H
J
K
L
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 11 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Ball Assignment and Description
Table 3: FBGA 84-/60-Ball Descriptions – 128 Meg x 4, 64 Meg x 8, 32 Meg x 16
x16 FBGA Ball
Number
x4, x8 FBGA
Ball Number Symbol Type Description
K9 F9 ODT Input On-die termination: ODT (registered HIGH) enables termination
resistance internal to the DDR2 SDRAM. When enabled, ODT is only
applied to each of the following balls: DQ0–DQ15, LDM, UDM,
LDQS, LDQS#, UDQS, and UDQS# for the x16; DQ0–DQ7, DQS,
DQS#, RDQS, RDQS#, and DM for the x8; DQ0–DQ3, DQS, DQS#,
and DM for the x4. The ODT input will be ignored if disabled via
the LOAD MODE command.
J8, K8 E8, F8 CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and DQS/
DQS#) is referenced to the crossings of CK and CK#.
K2 F2 CKE Input Clock enable: CKE (registered HIGH) activates and CKE (registered
LOW) deactivates clocking circuitry on the DDR2 SDRAM. The
specific circuitry that is enabled/disabled is dependent on the DDR2
SDRAM configuration and operating mode. CKE LOW provides
precharge power-down mode and SELF REFRESH operation (all
banks idle), or active power-down (row active in any bank). CKE is
synchronous for power-down entry, power-down exit, output
disable, and for self refresh entry. CKE is asynchronous for SELF
REFRESH exit. Input buffers (excluding CK, CK#, CKE, and ODT) are
disabled during power-down. Input buffers (excluding CKE) are
disabled during self refresh. CKE is an SSTL_18 input but will detect
a LVCMOS LOW level once VDD is applied during first power-up.
After VREF has become stable during the power on and
initialization sequence, it must be maintained for proper operation
of the CKE receiver. For proper SELF REFRESH operation, VREF must
be maintained.
L8 G8 CS# Input Chip select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS#
is registered HIGH. CS# provides for external bank selection on
systems with multiple ranks. CS# is considered part of the command
code.
K7, L7,
K3
F7, G7,
F3
RAS#, CAS#,
WE#
Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.
F3, B3
B3
LDM, UDM
(DM)
Input Input data mask: DM is an input mask signal for write data. Input
data is masked when DM is concurrently sampled HIGH during a
WRITE access. DM is sampled on both edges of DQS. Although DM
balls are input-only, the DM loading is designed to match that of
DQ and DQS balls. LDM is DM for lower byte DQ0–DQ7 and UDM is
DM for upper byte DQ8–DQ15.
L2, L3 G2, G3 BA0–BA1 Input Bank address inputs: BA0–BA1 define to which bank an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied. BA0–
BA1define which mode register including MR, EMR, EMR(2), and
EMR(3) is loaded during the LOAD MODE command.
M8, M3, M7, N2,
N8, N3, N7, P2,
P8, P3, M2, P7,
R2
–A0–A3
A4–A7
A8–A11
A12
Input Address inputs: Provide the row address for ACTIVE commands, and
the column address and auto precharge bit (A10) for READ/WRITE
commands, to select one location out of the memory array in the
respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10
LOW, bank selected by BA1–BA0) or all banks (A10 HIGH). The
address inputs also provide the op-code during a LOAD MODE
command.
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 12 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Ball Assignment and Description
– H8, H3, H7, J2,
J8, J3, J7, K2,
K8, K3, H2, K7,
L2, L8
A0–A3
A4–A7
A8–A11
A12–A13
Input Address inputs: Provide the row address for ACTIVE commands and
the column address and auto precharge bit (A10) for READ/WRITE
commands to select one location out of the memory array in the
respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10
LOW, bank selected by BA1–BA0) or all banks (A10 HIGH). The
address inputs also provide the op-code during a LOAD MODE
command.
G8, G2, H7, H3,
H1, H9, F1, F9,
C8, C2, D7, D3,
D1, D9, B1, B9
–DQ0–DQ3
DQ4–DQ7
DQ8–DQ11
DQ12–DQ15
I/O Data input/output: Bidirectional data bus for 32 Meg x 16.
– C8, C2, D7, D3,
D1, D9, B1, B9
DQ0–DQ3
DQ4–DQ7
I/O Data input/output: Bidirectional data bus for 64 Meg x 8.
– C8,C2,D7,D3 DQ0–DQ3 I/O Data input/output: Bidirectional data bus for 128 Meg x 4.
B7
A8
– UDQS,
UDQS#
I/O Data strobe for upper byte: Output with read data, input with
write data for source synchronous operation. Edge-aligned with
read data, center-aligned with write data. UDQS# is only used
when differential data strobe mode is enabled via the LOAD MODE
command.
F7
E8
– LDQS,
LDQS#
I/O Data strobe for lower byte: Output with read data, input with write
data for source synchronous operation. Edge-aligned with read
data, center-aligned with write data. LDQS# is only used when
differential data strobe mode is enabled via the LOAD MODE
command.
– B7, A8 DQS, DQS# I/O Data strobe: Output with read data, input with write data for
source synchronous operation. Edge-aligned with read data, center
aligned with write data. DQS# is only used when differential data
strobe mode is enabled via the LOAD MODE command.
–B3
A2
RDQS,
RDQS#
Output Redundant data strobe for 64 Meg x 8 only. RDQS is enabled/
disabled via the LOAD MODE command to the extended mode
register (EMR). When RDQS is enabled, RDQS is output with read
data only and is ignored during write data. When RDQS is disabled,
ball B3 becomes data mask (see DM ball). RDQS# is only used when
RDQS is enabled and differential data strobe mode is enabled.
A1, E1, M9, J9, R1
A1, E9, H9, L1 VDD Supply Power supply: 1.8V ±0.1V.
J1 E1 VDDL Supply DLL power supply: 1.8V ±0.1V.
A9, C1, C3, C7,
C9, E9, G1, G3,
G7, G9
A9, C1,
C3, C7, C9
VDDQ Supply DQ power supply: 1.8V ±0.1V. Isolated on the device for improved
noise immunity.
J2 E2 VREF Supply SSTL_18 reference voltage.
A3, E3, J3, N1,
P9
A3, E3, J1, K9 VSS Supply Ground.
J7 E7 VSSDL Supply DLL ground. Isolated on the device from VSS and VSSQ.
A7, B2, B8, D2,
D8, E7, F2, F8,
H2, H8
A7, B2,
B8, D2, D8
VSSQ Supply DQ ground. Isolated on the device for improved noise immunity.
A2, E2 – NC – No connect: These balls should be left unconnected.
– B1, D1, D9, B9 NF – No function: These balls are used as DQ4–DQ7 on the 64 Meg x 8,
but are NF (no function) on the 128 Meg x 4 configuration.
Table 3: FBGA 84-/60-Ball Descriptions – 128 Meg x 4, 64 Meg x 8, 32 Meg x 16 (continued)
x16 FBGA Ball
Number
x4, x8 FBGA
Ball Number Symbol Type Description
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 13 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Ball Assignment and Description
A8, E8 – NU – Not used: Not used only on x16. If EMR[E10] = 0, A8 and E8 are
UDQS# and LDQS#. If EMR[E10] = 1, then A8 and E8 are not used.
– A2, A8 NU – Not used: Not used only on x8. If EMR[E10] = 0, A2 and A8 are
RDQS# and DQS#.
If EMR[E10] = 1, then A2 and A8 are not used.
L1, R3, R7, R8 – RFU – Reserved for future use (x16 only): Row address bits A13 (R8), A14
(R3), and A15 (R7) are reserved for 2Gb and 4Gb densities. BA2 (L1)
is reserved for 1Gb device.
–G1, L3, L7 RFU – Reserved for future use (x4, x8 only): Row address bits A14 (L3) and
A15 (L7) are reserved for 2Gb and 4Gb densities. BA2 (G1) is
reserved for 1Gb device.
Table 3: FBGA 84-/60-Ball Descriptions – 128 Meg x 4, 64 Meg x 8, 32 Meg x 16 (continued)
x16 FBGA Ball
Number
x4, x8 FBGA
Ball Number Symbol Type Description
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 14 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Functional Description
Functional Description
The 512Mb DDR2 SDRAM is a high-speed CMOS dynamic random access memory
containing 536,870,912 bits. The 512Mb DDR2 SDRAM is internally configured as a 4-
bank DRAM.
The 512Mb DDR2 SDRAM uses a double data rate architecture to achieve high-speed
operation. The DDR2 architecture is essentially a 4n-prefetch architecture, with an inter-
face designed to transfer two data words per clock cycle at the I/O balls. A single read or
write access for the 512Mb DDR2 SDRAM consists of a single 4n-bit-wide, one-clock-
cycle data transfer at the internal DRAM core and four corresponding n-bit- wide, one-
half-clock-cycle data transfers at the I/O balls.
Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections
provide detailed information covering device initialization, register definition,
command descriptions, and device operation.
Figure 4: Functional Block Diagram – 32 Meg x 16
13
ROW-
ADDRESS
MUX
CONTROL
LOGIC
COLUMN-
ADDRESS
COUNTER/
LATCH
MODE
REGISTERS
10
A0–A12,
BA0, BA1
13
ADDRESS
REGISTER
15
256
(x64)
16,384
I/O GATING
DM MASK LOGIC
COLUMN
DECODER
BANK 0
MEMORY
ARRAY
(8,192 x 128 x 64)
BANK 0
ROW-
ADDRESS
LATCH&
DECODER
8,192
SENSE AMPLIFIERS
BANK
CONTROL
LOGIC
15
BANK 1
BANK 2
BANK 3
13
8
2
2
REFRESH
COUNTER
16
16
16
4
64
64
64
CK OUT
DATA
UDQS, UDQS#
LDQS, LDQS#
Internal
CK, CK#
CK, CK#
COL0, COL1
COL0, COL1
CK IN
DLL
MUX
DQS
GENERATOR
16
16
16
16
16
UDQS, UDQS#
LDQS, LDQS#
4
READ
LATCH
WRITE
FIFO
&
DRIVERS
DATA
16
16
16
16
64
2
2
2
2
MASK
2
2
2
2
2
8
16
16
2
BANK 1
BANK 2
BANK 3
INPUT
REGISTERS
UDM, LDM
DQ0–DQ15
RAS#
CAS#
CK
CS#
WE#
CK#
COMMAND
DECODE
CKE
ODT
DRVRS
RCVRS
VDDQ
R1
R1
R2
R2
sw1 sw2
VssQ
sw1 sw2
ODT CONTROL
sw3
R3
R3
sw3
R1
R1
R2
R2
sw1 sw2
R3
R3
sw3
R1
R1
R2
R2
sw1 sw2
R3
R3
sw3
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 15 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Functional Description
Figure 5: Functional Block Diagram – 64 Meg x 8
Figure 6: Functional Block Diagram – 128 Meg x 4
14
ROW-
ADDRESS
MUX
CONTROL
LOGIC
COLUMN-
ADDRESS
COUNTER/
LATCH
MODE
REGISTERS
10
COMMAND
DECODE
A0–A13,
BA0, BA1
14
ADDRESS
REGISTER
16
256
(x32)
8,192
I/O GATING
DM MASK LOGIC
COLUMN
DECODER
BANK 0
MEMORY
ARRAY
(16,384 x 256 x 32)
BANK 0
ROW-
ADDRESS
LATCH &
DECODER
16,384
SENSE AMPLIFIERS
BANK
CONTROL
LOGIC
16
BANK 1
BANK 2
BANK 3
14
8
2
2
REFRESH
COUNTER
8
88
2
RCVRS
32
32
32
CK OUT
DATA
DQS, DQS#
internal
CK, CK#
CK, CK#
COL0, COL1
COL0, COL1
CK IN
DRVRS
DLL
MUX
DQS
GENERATOR
8
8
8
8
8
DQ0–DQ7
DQS, DQS#
2
READ
LATCH
WRITE
FIFO
&
DRIVERS
DATA
8
8
8
8
32
1
1
1
1
MASK
1
1
1
11
4
8
8
2
BANK 1
BANK 2
BANK 3
INPUT
REGISTERS
DM
RDQS#
RAS#
CAS#
CK
CS#
WE#
CK#
CKE
ODT
RDQS
V
DD
Q
R1
R1
R2
R2
sw1 sw2
VssQ
sw1 sw2
ODT CONTROL
sw3
R3
R3
sw3
R1
R1
R2
R2
sw1 sw2
R3
R3
sw3
R1
R1
R2
R2
sw1 sw2
R3
R3
sw3
14
ROW-
ADDRESS
MUX
CONTROL
LOGIC
COLUMN-
ADDRESS
COUNTER/
LATCH
MODE
REGISTERS
11
COMMAND
DECODE
A0–A13,
BA0, BA1
14
ADDRESS
REGISTER
16
512
(x16)
8,192
I/O GATING
DM MASK LOGIC
COLUMN
DECODER
BANK0
MEMORY
ARRAY
(16,384 x 512 x 16)
BANK0
ROW-
ADDRESS
LATCH &
DECODER
16,384
SENSE AMPLIFIERS
BANK
CONTROL
LOGIC
16
BANK1
BANK2
BANK3
14
9
2
2
REFRESH
COUNTER
4
44
2
RCVRS
16
16
16
CK OUT
DATA
DQS, DQS#
internal
CK, CK#
CK, CK#
COL0, COL1
COL0, COL1
CK IN
DRVRS
DLL
MUX
DQS
GENERATOR
4
4
4
4
4
DQ0–DQ3
DQS, DQS#
2
READ
LATCH
WRITE
FIFO
&
DRIVERS
DATA
4
4
4
4
16
1
1
1
1
MASK
1
1
1
11
4
4
4
2
BANK1
BANK2
BANK3
INPUT
REGISTERS
DM
RAS#
CAS#
CK
CS#
WE#
CK#
CKE
ODT
V
DD
Q
R1
R1
R2
R2
sw1 sw2
VssQ
sw1 sw2
ODT CONTROL
sw3
R3
R3
sw3
R1
R1
R2
R2
sw1 sw2
R3
R3
sw3
R1
R1
R2
R2
sw1 sw2
R3
R3
sw3
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 16 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Initialization
Initialization
DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than
those specified may result in undefined operation. Figure 7 illustrates the sequence required for power-up and
initialization.
Figure 7: DDR2 Power-up and Initialization
Notes appear on page 17
LVCMOS
LOW LEVEL2
t
VTD
1
CKE
R
TT
Power-up:
V
DD
and stable
clock (CK, CK#)
T = 200µs (MIN)
High-Z
DM
4
DQS
4
High-Z
ADDRESS
3
CK
CK#
tCL
VTT
1
VREF
VDDQ
COMMAND
3
NOP5
PRE
T0 Ta0
DON’T CARE
tCL
tCK
VDD
ODT
DQ
4
High-Z
T = 400ns
(MIN)
6
Tb0
200 cycles of CK are required before a READ command can be issued.
MR with
DLL RESET
tRFC
LM
10
PRE
11
LM
9
REF
12
REF LM
13
Tg0 Th0 Ti0 Tj0
MR without
DLL RESET
EMR with
OCD Default
Tk0 Tl0 Tm0
Te0 Tf0
EMR(2) EMR(3)
tMRD
LM
8
LM
7
A10 = 1
tRPA
Tc0Td0
SSTL_18
LOW LEVEL
2
VALID
16
VALID
Indicates a break in
time scale
LM
14
EMR with
OCD Exit
LM
15
Normal
Operation
See note 12
CODE CODE
A10 = 1
CODE CODE
CODE CODE CODE
tMRD tMRD tMRD tMRD
tRPA tRFC
VDDL
tMRD tMRD
EMR
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 17 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Initialization
Notes: 1.
Applying power; if CKE is maintained below 0.2 x V
DD
Q,
outputs remain disabled. To guaran-
tee RTT (ODT resistance) is off, VREF must be valid and a low level must be applied to the
ODT ball (all other inputs may be undefined; I/Os and outputs must be less than VDDQ dur-
ing voltage ramp time to avoid DDR2 SDRAM device latch-up). VTT is not applied directly to
the device; however, tVTT should be ≥0 to avoid device latch-up. At least one of the follow-
ing two sets of conditions (A or B) must be met to obtain a stable supply state (stable supply
defined as VDD, VDDL, VDDQ, VREF, and VTT are between their minimum and maximum val-
ues as stated in Table 20 on page 84):
A. Single power source: The VDD voltage ramp from 300mV to VDD (MIN) must take no
longer than 200ms; during the VDD voltage ramp, |VDD - VDDQ| ≤ 0.3V. Once supply voltage
ramping is complete (when VDDQ crosses VDD [MIN]), Table 20 specifications apply.
• VDD, VDDL, and VDDQ are driven from a single power converter output
• VTT is limited to 0.95V MAX
• VREF tracks VDDQ/2; VREF must be within ±0.3V with respect to VDDQ/2 during sup-
ply ramp time
• VDDQ ≥ VREF at all times
B. Multiple power sources: VDD ≥ VDDL ≥ VDDQ must be maintained during supply volt-
age ramping, for both AC and DC levels, until supply voltage ramping completes (VDDQ
crosses VDD [MIN]). Once supply voltage ramping is complete, Table 20 specifications apply.
• Apply VDD and VDDL before or at the same time as VDDQ; VDD/VDDL voltage ramp
time must be ≤200ms from when VDD ramps from 300mV to VDD (MIN)
• Apply VDDQ before or at the same time as VTT; the VDDQ voltage ramp time from
when VDD (MIN) is achieved to when VDDQ (MIN) is achieved must be ≤500ms; while
VDD is ramping, current can be supplied from VDD through the device to VDDQ
• VREF must track VDDQ/2; VREF must be within ±0.3V with respect to VDDQ/2 during
supply ramp time; VDDQ ≥ VREF must be met at all times
• Apply VTT; the VTT voltage ramp time from when VDDQ (MIN) is achieved to when
VTT (MIN) is achieved must be no greater than 500ms
2. CKE uses LVCMOS input levels prior to state T0 to ensure DQs are High-Z during device
power-up prior to VREF being stable. After state T0, CKE is required to have SSTL_18 input
levels. Once CKE transitions to a high level, it must stay HIGH for the duration of the initial-
ization sequence.
3. PRE = PRECHARGE command, LM = LOAD MODE command, MR = Mode Register, EMR =
extended mode register, EMR2 = extended mode register 2, EMR3 = extended mode regis-
ter 3, REF = REFRESH command, ACT = ACTIVE command, A10 = PRECHARGE ALL, CODE =
desired values for mode registers (bank addresses are required to be decoded), VALID - any
valid command/address, RA = row address, bank address.
4. DM represents DM for x4, x8 configurations and UDM, LDM for x16 configuration; DQS rep-
resents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, RDQS# for the appropriate configu-
ration (x4, x8, x16); DQ represents DQ0–DQ3 for x4, DQ–DQ7 for x8, and DQ0–DQ15 for x16.
5. For a minimum of 200µs after stable power and clock (CK, CK#), apply NOP or DESELECT
commands, then take CKE HIGH.
6. Wait a minimum of 400ns, then issue a PRECHARGE ALL command.
7. Issue a LOAD MODE command to the EMR(2). (To issue an EMR(2) command, provide LOW
to BA0, and provide HIGH to BA1.) Set register E7 to “0” or “1;” all others must be “0.”
8. Issue a LOAD MODE command to the EMR(3). (To issue an EMR(3) command, provide HIGH
to BA0 and BA1.) Set all registers to “0.”
9. Issue a LOAD MODE command to the EMR to enable DLL. To issue a DLL ENABLE command,
provide LOW to BA1 and A0; provide HIGH to BA0. Bits E7, E8, and E9 can be set to “0” or
“1;” Micron recommends setting them to “0.”
10. Issue a LOAD MODE command for DLL RESET. 200 cycles of clock input is required to lock
the DLL. (To issue a DLL RESET, provide HIGH to A8 and provide LOW to BA1 and BA0.) CKE
must be HIGH the entire time.
11. Issue PRECHARGE ALL command.
12. Issue two or more REFRESH commands.
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 18 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Initialization
13. Issue a LOAD MODE command with LOW to A8 to initialize device operation (i.e., to pro-
gram operating parameters without resetting the DLL). To access the mode registers, BA1
=1, BA0 = 0.
14. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits E7, E8, and
E9 to “1,” and then setting all other desired parameters. To access the extended mode reg-
ister, BA1 = 0, BA0 = 1.
15. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7, E8, and E9
to “0,” and then setting all other desired parameters. To access the extended mode regis-
ters, BA1 = 0, BA0 = 1.
16. The DDR2 SDRAM is now initialized and ready for normal operation 200 clock cycles after
the DLL RESET at Tf0. It is also suggested to include a single dummy WRITE command fol-
lowed by tWR anytime after the REFRESH commands, but before the first true WRITE com-
mand to the DRAM.
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 19 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Mode Register (MR)
Mode Register (MR)
The mode register is used to define the specific mode of operation of the DDR2 SDRAM.
This definition includes the selection of a burst length, burst type, CAS latency, oper-
ating mode, DLL RESET, write recovery, and power-down mode, as shown in Figure 8 on
page 20. Contents of the mode register can be altered by re-executing the LOAD MODE
(LM) command. If the user chooses to modify only a subset of the MR variables, all vari-
ables (M0–M13 for x4 and x8 or M0–M12 for x16) must be programmed when the
command is issued.
The MR is programmed via the LM command (bits BA1–BA0 = 0, 0) and other bits (M13–
M0 for x4 and x8, M12–M0 for x16) will retain the stored information until it is
programmed again or the device loses power (except for bit M8, which is self-clearing).
Reprogramming the mode register will not alter the contents of the memory array,
provided it is performed correctly.
The LM command can only be issued (or reissued) when all banks are in the precharged
state (idle state) and no bursts are in progress. The controller must wait the specified
time tMRD before initiating any subsequent operations such as an ACTIVE command.
Violating either of these requirements will result in unspecified operation.
Burst Length
Burst length is defined by bits M0–M3, as shown in Figure 8 on page 20. Read and write
accesses to the DDR2 SDRAM are burst-oriented, with the burst length being program-
mable to either four or eight. The burst length determines the maximum number of
column locations that can be accessed for a given READ or WRITE command.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A2–Ai when BL = 4 and by A3–Ai when BL = 8 (where Ai is the most
significant column address bit for a given configuration). The remaining (least signifi-
cant) address bit(s) is (are) used to select the starting location within the block. The
programmed burst length applies to both READ and WRITE bursts.
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 20 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Mode Register (MR)
Figure 8: Mode Register (MR) Definition
Notes: 1. M13 (A13) is reserved for future use and must be programmed to “0.” A13 is not used in
x16 configuration.
2. Not all listed CL options are supported in any individual speed grade.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved.
The burst type is selected via bit M3, as shown in Figure 8. The ordering of accesses
within a burst is determined by the burst length, the burst type, and the starting column
address, as shown in Table 4 on page 21. DDR2 SDRAM supports 4-bit burst mode and 8-
bit burst mode only. For 8-bit burst mode, full, interleaved address ordering is
supported; however, sequential address ordering is nibble-based.
Burst Length
CAS#
BTPD
A9 A7 A6 A5 A4 A3A8 A2 A1 A0
Mode Register (Mx)
Address Bus
9765438210
A10A12 A11BA0
BA1
10111213
01
14
Burst Length
Reserved
Reserved
4
8
Reserved
Reserved
Reserved
Reserved
M0
0
1
0
1
0
1
0
1
M1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
0
1
Burst Type
Sequential
Interleaved
M3
CAS Latency (CL)
Reserved
Reserved
Reserved
3
4
5
6
Reserved
M4
0
1
0
1
0
1
0
1
M5
0
0
1
1
0
0
1
1
M6
0
0
0
0
1
1
1
1
0
1
Mode
Normal
Test
M7
15
DLL TM
0
1
DLL Reset
No
Yes
M8
WRITE RECOVERY
Reserved
2
3
4
5
6
Reserved
Reserved
M9
0
1
0
1
0
1
0
1
M10
0
0
1
1
0
0
1
1
M11
0
0
0
0
1
1
1
1
WR
A13
MR
0
1
0
1
Mode Register Definition
Mode Register (MR)
Extended Mode Register (EMR)
Extended Mode Register (EMR2)
Extended Mode Register (EMR3)
M15
0
0
1
1
M12
0
1
PD mode
Fast Exit
(Normal)
Slow Exit
(Low Power)
M14
Latency
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 21 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Mode Register (MR)
Operating Mode
The normal operating mode is selected by issuing a command with bit M7 set to “0,” and
all other bits set to the desired values, as shown in Figure 8 on page 20. When bit M7 is
“1,” no other bits of the mode register are programmed. Programming bit M7 to “1”
places the DDR2 SDRAM into a test mode that is only used by the manufacturer and
should not be used. No operation or functionality is guaranteed if M7 bit is “1.”
DLL RESET
DLL RESET is defined by bit M8, as shown in Figure 8 on page 20. Programming bit M8
to “1” will activate the DLL RESET function. Bit M8 is self-clearing, meaning it returns
back to a value of “0” after the DLL RESET function has been issued.
Anytime the DLL RESET function is used, 200 clock cycles must occur before a READ
command can be issued to allow time for the internal clock to be synchronized with the
external clock. Failing to wait for synchronization to occur may result in a violation of
the tAC or tDQSCK parameters.
Write Recovery
Write recovery (WR) time is defined by bits M9–M11, as shown in Figure 8 on page 20.
The WR register is used by the DDR2 SDRAM during WRITE with auto precharge opera-
tion. During WRITE with auto precharge operation, the DDR2 SDRAM delays the
internal auto precharge operation by WR clocks (programmed in bits M9–M11) from the
last data burst. An example of WRITE with auto precharge is shown in Figure 39 on
page 57.
WR values of 2, 3, 4, 5, or 6 clocks may be used for programming bits M9–M11. The user
is required to program the value of WR, which is calculated by dividing tWR (in nanosec-
onds) by tCK (in nanoseconds) and rounding up a noninteger value to the next integer;
WR [cycles] = tWR [ns] / tCK [ns]. Reserved states should not be used as unknown opera-
tion or incompatibility with future versions may result.
Table 4: Burst Definition
Burst Length
Starting Column
Address
(A2, A1, A0)
Order of Accesses Within a Burst
Burst Type = Sequential Burst Type = Interleaved
4 0 0 0, 1, 2, 3 0, 1, 2, 3
0 1 1, 2, 3, 0 1, 0, 3, 2
1 0 2, 3, 0, 1 2, 3, 0, 1
1 1 3, 0, 1, 2 3, 2, 1, 0
8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7
0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6
0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5
0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4
1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3
1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2
1 1 0 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1
1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 22 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Mode Register (MR)
Power-Down Mode
Active power-down (PD) mode is defined by bit M12, as shown in Figure 8 on page 20.
PD mode allows the user to determine the active power-down mode, which determines
performance versus power savings. PD mode bit M12 does not apply to precharge PD
mode.
When bit M12 = 0, standard active PD mode, or “fast-exit” active PD mode, is enabled.
The tXARD parameter is used for fast-exit active PD exit timing. The DLL is expected to
be enabled and running during this mode.
When bit M12 = 1, a lower-power active PD mode, or “slow-exit” active PD mode, is
enabled. The tXARDS parameter is used for slow-exit active PD exit timing. The DLL can
be enabled but “frozen” during active PD mode since the exit-to-READ command timing
is relaxed. The power difference expected between PD normal and PD low-power mode
is defined in the IDD table.
CAS Latency (CL)
The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 8 on page 20. CL is
the delay, in clock cycles, between the registration of a READ command and the avail-
ability of the first bit of output data. The CL can be set to 3, 4, 5, or 6 clocks, depending
on the speed grade option being used.
DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be
used as unknown operation or incompatibility with future versions may result.
DDR2 SDRAM also supports a feature called posted CAS additive latency (AL). This
feature allows the READ command to be issued prior to tRCD (MIN) by delaying the
internal command to the DDR2 SDRAM by AL clocks. The AL feature is described in
more detail in “Posted CAS Additive Latency (AL)” on page 26.
Examples of CL = 3 and CL = 4 are shown in Figure 9 on page 23; both assume AL = 0. If a
READ command is registered at clock edge n, and the CL is m clocks, the data will be
available nominally coincident with clock edge n + m (this assumes AL = 0).
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 23 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Extended Mode Register (EMR)
Figure 9: CAS Latency (CL)
Notes: 1. BL = 4.
2. Posted CAS# additive latency (AL) = 0.
3. Shown with nominal tAC, tDQSCK, and tDQSQ.
Extended Mode Register (EMR)
The extended mode register controls functions beyond those controlled by the mode
register; these additional functions are DLL enable/disable, output drive strength, on-
die termination (ODT) (RTT), posted AL, off-chip driver impedance calibration (OCD),
DQS# enable/disable, RDQS/RDQS# enable/disable, and output disable/enable. These
functions are controlled via the bits shown in Figure 10 on page 24. The EMR is
programmed via the LM command and will retain the stored information until it is
programmed again or the device loses power. Reprogramming the EMR will not alter the
contents of the memory array, provided it is performed correctly.
The EMR must be loaded when all banks are idle and no bursts are in progress, and the
controller must wait the specified time tMRD before initiating any subsequent opera-
tion. Violating either of these requirements could result in unspecified operation.
D
OUT
n + 3
D
OUT
n + 2
D
OUT
n + 1
CK
CK#
COMMAND
DQ
DQS, DQS#
CL = 3 (AL = 0)
READ
T0 T1 T2
DON’T CARETRANSITIONING DATA
NOP NOP NOP
D
OUT
n
T3 T4 T5
NOP NOP
T6
NOP
D
OUT
n + 3
D
OUT
n + 2
D
OUT
n + 1
CK
CK#
COMMAND
DQ
DQS, DQS#
CL = 4 (AL = 0)
READ
T0 T1 T2
NOP NOP NOP
D
OUT
n
T3 T4 T5
NOP NOP
T6
NOP
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 24 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
DLL Enable/Disable
Figure 10: Extended Mode Register Definition
Notes: 1. During initialization, all three bits must be set to “1” for OCD default state, then must be
set to “0” before initialization is finished, as detailed in the notes on pages 17–18.
2. E13 (A13) is not used on the x16 configuration.
DLL Enable/Disable
The DLL may be enabled or disabled by programming bit E0 during the LM command,
as shown in Figure 10. The DLL must be enabled for normal operation. DLL enable is
required during power-up initialization and upon returning to normal operation after
having disabled the DLL for the purpose of debugging or evaluation. Enabling the DLL
should always be followed by resetting the DLL using the LM command.
The DLL is automatically disabled when entering SELF REFRESH operation and is auto-
matically re-enabled and reset upon exit of SELF REFRESH operation.
Anytime the DLL is enabled (and subsequently reset), 200 clock cycles must occur before
a READ command can be issued, to allow time for the internal clock to synchronize with
the external clock. Failing to wait for synchronization to occur may result in a violation
of the tAC or tDQSCK parameters.
DLLPosted CAS#out
A9 A7 A6 A5 A4 A3A8 A2 A1 A0
Extended Mode
Register (Ex)
Address Bus
9765438210
A10A12 A11BA0BA1
10111213
02
14
Posted CAS# Additive Latency (AL)
0
1
2
3
4
Reserved
Reserved
Reserved
E3
0
1
0
1
0
1
0
1
E4
0
0
1
1
0
0
1
1
E5
0
0
0
0
1
1
1
1
0
1
DLL Enable
Enable (Normal)
Disable (Test/Debug)
E0
15
0
1
RDQS Enable
No
Yes
E11
OCD Program
A13
ODS
RTT
DQS#
0
1
DQS# Enable
Enable
Disable
E10
RDQS
Rtt (nominal)
RTT disabled
75Ω
150Ω
50Ω
E2
0
1
0
1
E6
0
0
1
1
0
1
Outputs
Enabled
Disabled
E12
0
1
0
1
Mode Register Set
Mode register set (MRS)
Extended mode register (EMRS)
Extended mode register (EMRS2)
Extended mode register (EMRS3)
E15
0
0
1
1
E14
MRS
OCD Operation
OCD not supported1
Reserved
Reserved
Reserved
OCD default state1
E7
0
1
0
0
1
E8
0
0
1
0
1
E9
0
0
0
1
1
0
1
Output Drive Strength
E1
Full strength (18Ω target)
Reduced strength (40Ω target)
RTT
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 25 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Output Drive Strength
Output Drive Strength
The output drive strength is defined by bit E1, as shown in Figure 10 on page 24. The
normal drive strength for all outputs are specified to be SSTL_18. Programming bit E1 = 0
selects normal (full strength) drive strength for all outputs. Selecting a reduced drive
strength option (E1 = 1) will reduce all outputs to approximately 60 percent of the
SSTL_18 drive strength. This option is intended for the support of lighter load and/or
point-to-point environments.
DQS# Enable/Disable
The DQS# ball is enabled by bit E10. When E10 = 0, DQS# is the complement of the
differential data strobe pair DQS/DQS#. When disabled (E10 = 1), DQS is used in a
single-ended mode and the DQS# ball is disabled. When disabled, DQS# should be left
floating. This function is also used to enable/disable RDQS#. If RDQS is enabled (E11 =
1) and DQS# is enabled (E10 = 0), then both DQS# and RDQS# will be enabled.
RDQS Enable/Disable
The RDQS ball is enabled by bit E11, as shown in Figure 10 on page 24. This feature is
only applicable to the x8 configuration. When enabled (E11 = 1), RDQS is identical in
function and timing to data strobe DQS during a READ. During a WRITE operation,
RDQS is ignored by the DDR2 SDRAM.
Output Enable/Disable
The OUTPUT ENABLE function is defined by bit E12, as shown in Figure 10 on page 24.
When enabled (E12 = 0), all outputs (DQs, DQS, DQS#, RDQS, RDQS#) function
normally. When disabled (E12 = 1), all DDR2 SDRAM outputs (DQs, DQS, DQS#, RDQS,
RDQS#) are disabled, thus removing output buffer current. The output disable feature is
intended to be used during IDD characterization of read current.
On-Die Termination (ODT)
ODT effective resistance, RTT (EFF), is defined by bits E2 and E6 of the EMR, as shown in
Figure 10 on page 24. The ODT feature is designed to improve signal integrity of the
memory channel by allowing the DDR2 SDRAM controller to independently turn on/off
ODT for any or all devices. RTT effective resistance values of 50Ω, 75Ω, and 150Ω are
selectable and apply to each DQ, DQS/DQS#, RDQS/RDQS#, UDQS/UDQS#, LDQS/
LDQS#, DM, and UDM/LDM signals. Bits (E6, E2) determine what ODT resistance is
enabled by turning on/off “sw1,” “sw2,” or “sw3.” The ODT effective resistance value is
selected by enabling switch “sw1,” which enables all R1 values that are 150Ω each,
enabling an effective resistance of 75Ω (RTT2 (EFF) = R2/2). Similarly, if “sw2” is enabled,
all R2 values that are 300Ω each, enable an effective ODT resistance of 150Ω (RTT2 (EFF)
= R2/2). Switch “sw3” enables R1 values of 100Ω, enabling effective resistance of 50Ω.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
The ODT control ball is used to determine when RTT (EFF) is turned on and off,
assuming ODT has been enabled via bits E2 and E6 of the EMR. The ODT feature and
ODT input ball are only used during active, active power-down (both fast-exit and slow-
exit modes), and precharge power-down modes of operation. ODT must be turned off
prior to entering self refresh. During power-up and initialization of the DDR2 SDRAM,
ODT should be disabled until issuing the EMR command to enable the ODT feature, at
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 26 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Off-Chip Driver (OCD) Impedance Calibration
which point the ODT ball will determine the RTT (EFF) value. Any time the EMR enables
the ODT function, ODT may not be driven HIGH until eight clocks after the EMR has
been enabled. See “ODT Timing” on page 74 for ODT timing diagrams.
Off-Chip Driver (OCD) Impedance Calibration
The OFF-CHIP DRIVER function is no longer supported and must be set to the default
state. See “Initialization” on page 16 for proper setting of OCD defaults.
Posted CAS Additive Latency (AL)
Posted CAS additive latency (AL) is supported to make the command and data bus effi-
cient for sustainable bandwidths in DDR2 SDRAM. Bits E3–E5 define the value of AL, as
shown in Figure 10 on page 24. Bits E3–E5 allow the user to program the DDR2 SDRAM
with an inverse AL of 0, 1, 2, 3, or 4 clocks. Reserved states should not be used as
unknown operation or incompatibility with future versions may result.
In this operation, the DDR2 SDRAM allows a READ or WRITE command to be issued
prior to tRCD (MIN) with the requirement that AL ≤ tRCD (MIN). A typical application
using this feature would set AL = tRCD (MIN) - 1 x tCK. The READ or WRITE command is
held for the time of the AL before it is issued internally to the DDR2 SDRAM device. RL is
controlled by the sum of AL and CL; RL = AL + CL. Write latency (WL) is equal to RL
minus one clock; WL = AL + CL - 1 x tCK. An example of RL is shown in Figure 11. An
example of a WL is shown in Figure 12 on page 27.
Figure 11: READ Latency
Notes: 1. BL = 4.
2. Shown with nominal tAC, tDQSCK, and tDQSQ.
3. CL = 3.
4. AL = 2.
5. RL = AL +CL = 5.
DOUT
n + 3
DOUT
n + 2
DOUT
n + 1
CK
CK#
COMMAND
DQ
DQS, DQS#
AL = 2
ACTIVE n
T0 T1 T2
DON’T CARETRANSITIONING DATA
READ nNOP NOP
DOUT
n
T3 T4 T5
NOP
T6
NOP
T7 T8
NOP NOP
CL = 3
RL = 5
tRCD (MIN)
NOP
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 27 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Extended Mode Register 2
Figure 12: WRITE Latency
Notes: 1. BL = 4.
2. CL = 3.
3. AL = 2.
4. WL = AL + CL - 1 = 4.
Extended Mode Register 2
The extended mode register 2 (EMR2) controls functions beyond those controlled by the
mode register. Currently all bits in EMR2 are reserved, except for E7, which is for
commercial or high-temperature operations, as shown in Figure 13. The EMR2 is
programmed via the LM command and will retain the stored information until it is
programmed again or the device loses power. Reprogramming the EMR will not alter the
contents of the memory array, provided it is performed correctly.
Bit E7 (A7) must be programmed as “1” to provide a faster refresh rate on IT devices if the
TCASE exceeds 85°C.
EMR2 must be loaded when all banks are idle and no bursts are in progress, and the
controller must wait the specified time tMRD before initiating any subsequent opera-
tion. Violating either of these requirements could result in unspecified operation.
Figure 13: Extended Mode Register 2 (EMR2) Definition
Notes: 1. E13 (A13)–E8 (A8) and E6 (A6)–E0 (A0) are reserved for future use and must all be pro-
grammed to “0.” A13 is not used in x16 configuration.
CK
CK#
COMMAND
DQ
DQS, DQS#
ACTIVE n
T0 T1 T2
DON’T CARETRANSITIONING DATA
NOP NOP
T3 T4 T5
NOPWRITE n
T6
NOP
D
IN
n + 3
D
IN
n + 2
D
IN
n + 1
WL = AL + CL - 1 = 4
T7
NOP
D
IN
n
t
RCD (MIN)
NOP
AL = 2 CL - 1 = 2
A9 A7 A6A5 A4 A3A8 A2 A1 A0
Extended Mode
Register (Ex)
Address Bus
9765438210
A10A12 A11BA0BA1
10111213
01
1415
A13
0
1
0
1
Mode Register Definition
Mode register (MR)
Extended mode register (EMR)
Extended mode register (EMR2)
Extended mode register (EMR3)
M15
0
0
1
1
M14
EMR2 01010101010101010101010101
High Temperature Self Refresh rate enable
Commercial temperature default
Industrial temperature option;
use if TC exceeds 85°C
E7
0
1
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 28 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Extended Mode Register 3
Extended Mode Register 3
The extended mode register 3 (EMR3) controls functions beyond those controlled by the
mode register. Currently all bits in EMR3 are reserved, as shown in Figure 14 on page 28.
The EMR3 is programmed via the LM command and will retain the stored information
until it is programmed again or the device loses power. Reprogramming the EMR will not
alter the contents of the memory array, provided it is performed correctly.
EMR3 must be loaded when all banks are idle and no bursts are in progress, and the
controller must wait the specified time tMRD before initiating any subsequent opera-
tion. Violating either of these requirements could result in unspecified operation.
Figure 14: Extended Mode Register 3 (EMR3) Definition
Notes: 1. E13 (A13)–E0 (A0) are reserved for future use and must all be programmed to “0.” A13 is
not used in x16 configuration.
A9 A7 A6A5 A4 A3A8 A2 A1 A0
Extended Mode
Register (Ex)
Address Bus
9765438210
A10A12 A11BA0BA1
101112131415
A13
0
1
0
1
Mode Register Definition
Mode register (MR)
Extended mode register (EMR)
Extended mode register (EMR2)
Extended mode register (EMR3)
M15
0
0
1
1
M14
EMR3 01010101010101010101010101
01
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 29 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Command Truth Tables
Command Truth Tables
The following tables provide a quick reference of DDR2 SDRAM available commands,
including CKE power-down modes, and bank-to-bank commands.
Notes: 1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the
rising edge of the clock.
2. Bank addresses (BA) BA0–BA1 determine which bank is to be operated upon. BA during a
LM command selects which mode register is programmed.
3. Burst reads or writes at BL = 4 cannot be terminated or interrupted. See Figure 21 on
page 40 and Figure 35 on page 53 for other restrictions and details.
4. The power-down mode does not perform any REFRESH operations. The duration of power-
down is limited by the refresh requirements outlined in the AC parametric section.
5. The state of ODT does not affect the states described in this table. The ODT function is not
available during self refresh. See “ODT Timing” on page 74 for details.
6. “X” means “H or L” (but a defined logic level).
7. SELF REFRESH exit is asynchronous.
Table 5: Truth Table – DDR2 Commands
Notes: 1, 5, and 6 apply to all
Function
CKE
CS# RAS# CAS# WE# BA1
BA0
A13,
A12,
A11
A10 A9–A0 Notes
Previous
Cycle
Current
Cycle
LOAD MODE H H L L L L BA OP Code 2
REFRESH HHLLLHXXXX
SELF REFRESH entry HLLLLHXXXX
SELF REFRESH exit LH
HXXX XXXX 7
LHHH
Single bank
PRECHARGEHHLLHLBAXLX2
All banks
PRECHARGEHHLLHLXXHX
Bank activate H H L L H H BA Row Address
WRITE HHLHLLBA
Column
Address LColumn
Address 2, 3
WRITE with auto
precharge HHLHLLBA
Column
Address HColumn
Address 2, 3
READ HHLHLHBA
Column
Address LColumn
Address 2, 3
READ with auto
precharge HHLHLHBA
Column
Address HColumn
Address 2, 3
NO OPERATION HXLHHHXXXX
Device DESELECT HXHXXXXXXX
Power-down entry HL
HXXX XXXX 4
LHHH
Power-down exit LH
HXXX XXXX 4
LHHH
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 30 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Command Truth Tables
Notes: 1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH and after tXSNR has been met
(if the previous state was self refresh).
2. This table is bank-specific, except where noted (the current state is for a specific bank and
the commands shown are those allowed to be issued to that bank when in that state).
Exceptions are covered in the notes below.
3. Current state definitions:
4. The following states must not be interrupted by a command issued to the same bank. Issue
DESELECT or NOP commands, or allowable commands to the other bank, on any clock edge
occurring during these states. Allowable commands to the other bank are determined by its
current state and this table, and according to Table 7 on page 32.
Table 6: Truth Table – Current State Bank n - Command to Bank n
Notes: 1–6; notes appear below and on next page
Current
State CS# RAS# CAS# WE# Command/Action Notes
Any HXXX
DESELECT (NOP/continue previous operation)
LHHH
NO OPERATION (NOP/continue previous
operation)
Idle LLHH
ACTIVE (select and activate row)
LLLH
REFRESH 7
LLLL
LOAD MODE 7
Row active LHLH
READ (select column and start READ burst) 9
LHLL
WRITE (select column and start WRITE burst) 9
LLHL
PRECHARGE (deactivate row in bank or banks) 8
Read (auto-
precharge
Disabled
LHLH
READ (select column and start new READ burst) 9
LHLL
WRITE (select column and start WRITE burst) 9, 10
LLHL
PRECHARGE (start PRECHARGE) 8
Write (auto-
precharge
disabled)
LHLH
READ (select column and start READ burst) 9
LHLL
WRITE (select column and start new WRITE burst) 9
LLHL
PRECHARGE (start PRECHARGE) 8
Idle: The bank has been precharged, tRP has been met, and any READ burst is
complete.
Row active: A row in the bank has been activated, and tRCD has been met. No data bursts/
accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not
yet terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not
yet terminated.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP
is met. Once tRP is met, the bank will be in the idle state.
Read with auto
precharge enabled:
Starts with registration of a READ command with auto precharge
enabled and ends when tRP has been met. Once tRP is met, the bank
will be in the idle state.
Row activating: Starts with registration of an ACTIVE command and ends when tRCD is
met. Once tRCD is met, the bank will be in the “row active” state.
Write with auto
precharge enabled:
Starts with registration of a WRITE command with auto precharge
enabled and ends when tRP has been met. Once tRP is met, the bank
will be in the idle state.
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 31 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Command Truth Tables
5. The following states must not be interrupted by any executable command (DESELECT or
NOP commands must be applied on each positive clock edge during these states):
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle and bursts are not in progress.
8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a
valid state for precharging.
9. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto
precharge enabled and READs or WRITEs with auto precharge disabled.
10. A WRITE command may be applied after the completion of the READ burst.
Refreshing: Starts with registration of a REFRESH command and ends when tRFC is
met. Once tRFC is met, the DDR2 SDRAM will be in the all banks idle state.
Accessing mode
register:
Starts with registration of the LM command and ends when tMRD has
been met. Once tMRD is met, the DDR2 SDRAM will be in the all banks idle
state.
Precharging all: Starts with registration of a PRECHARGE ALL command and ends when
tRP is met. Once tRP is met, all banks will be in the idle state.
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 32 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Command Truth Tables
Notes: 1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH and after tXSNR has been met
(if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted (i.e., the current state is
for bank n and the commands shown are those allowed to be issued to bank m, assuming
that bank m is in such a state that the given command is allowable). Exceptions are covered
in the notes below.
3. Current state definitions:
Table 7: Truth Table – Current State Bank n - Command to Bank m
Notes: 1–6; notes appear below and on next page
Current State CS# RAS# CAS# WE# Command/Action Notes
Any HXXX
DESELECT (NOP/continue previous operation)
LHHH
NO OPERATION (NOP/continue previous operation)
Idle XXXX
Any command otherwise allowed to bank m
Row Activating,
Active, or
Precharging
LLHH
ACTIVE (select and activate row)
LHLH
READ (select column and start READ burst) 7
LHLL
WRITE (select column and start WRITE burst) 7
LLHL
PRECHARGE
Read (auto
precharge
disabled
LLHH
ACTIVE (select and activate row)
LHLH
READ (select column and start new READ burst) 7
LHLL
WRITE (select column and start WRITE burst) 7, 9
LLHL
PRECHARGE
Write (auto
precharge
disabled.)
LLHH
ACTIVE (select and activate row)
LHLH
READ (select column and start READ burst) 7, 8
LHLL
WRITE (select column and start new WRITE burst) 7
LLHL
PRECHARGE
Read (with auto-
precharge)
LLHH
ACTIVE (select and activate row)
LHLH
READ (select column and start new READ burst) 7, 3
LHLL
WRITE (select column and start WRITE burst) 7, 9, 3
LLHL
PRECHARGE
Write (with auto-
precharge)
LLHH
ACTIVE (select and activate row)
LHLH
READ (select column and start READ burst) 7, 3
LHLL
WRITE (select column and start new WRITE burst) 7, 3
LLHL
PRECHARGE
Idle: The bank has been precharged, tRP has been met, and any READ burst is
complete.
Row active: A row in the bank has been activated and tRCD has been met. No data bursts/
accesses and no register accesses are in progress.
Read: A READ burst has been initiated with auto precharge disabled, and has not
yet terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not
yet terminated.
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 33 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Command Truth Tables
The minimum delay from a READ or WRITE command with auto precharge
enabled to a command to a different bank is summarized in Table 8:
4. REFRESH and LM commands may only be issued when all banks are idle.
5. Not used.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto
precharge enabled and READs or WRITEs with auto precharge disabled.
8. Requires appropriate DM.
9. A WRITE command may be applied after the completion of the READ burst.
10. The number of clock cycles required to meet tWTR is either 2 or tWTR/tCK, whichever is
greater.
READ with
auto
precharge
enabled/
WRITE with
auto
precharge
enabled:
The READ with auto precharge enabled or WRITE with auto precharge
enabled states can each be broken into two parts: the access period and the
precharge period. For READ with auto precharge, the precharge period is
defined as if the same burst was executed with auto precharge disabled and
then followed with the earliest possible PRECHARGE command that still
accesses all of the data in the burst. For WRITE with auto precharge, the
precharge period begins when tWR ends, with tWR measured as if auto
precharge was disabled. The access period starts with registration of the
command and ends where the precharge period (or tRP) begins. This device
supports concurrent auto precharge such that when a READ with auto
precharge is enabled or a WRITE with auto precharge is enabled, any
command to other banks is allowed, as long as that command does not
interrupt the read or write data transfer already in process. In either case, all
other related limitations apply (contention between read data and write data
must be avoided).
Table 8: Minimum Delay with Auto Precharge Enabled
From Command
(Bank n)To Command (Bank m)Minimum Delay (With
Concurrent Auto Precharge) Units
WRITE with auto
precharge
READ or READ with auto
precharge
(CL - 1) + (BL / 2) + tWTR tCK
WRITE or WRITE with auto
precharge
(BL / 2) tCK
PRECHARGE or ACTIVE 1 tCK
READ with auto
precharge
READ or READ with auto
precharge
(BL / 2) tCK
WRITE or WRITE with auto
precharge
(BL / 2) + 2 tCK
PRECHARGE or ACTIVE 1 tCK
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 34 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
DESELECT, NOP, and LM Commands
DESELECT, NOP, and LM Commands
DESELECT
The DESELECT function (CS# HIGH) prevents new commands from being executed by
the DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Operations already in
progress are not affected. DESELECT is also referred to as COMMAND INHIBIT.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to instruct the selected DDR2 SDRAM to
perform a NOP (CS# is LOW; RAS#, CAS#, and WE are HIGH). This prevents unwanted
commands from being registered during idle or wait states. Operations already in
progress are not affected.
LOAD MODE (LM)
The mode registers are loaded via inputs BA1–BA0 and A13–A0 for x4 and x8, and A12–A0
for x16 configurations. BA1–BA0 determine which mode register will be programmed.
See “Mode Register (MR)” on page 19. The LM command can only be issued when all
banks are idle, and a subsequent executable command cannot be issued until tMRD is
met.
Bank/Row Activation
ACTIVE Command
The ACTIVE command is used to open (or activate) a row in a particular bank for a
subsequent access. The value on the BA1–BA0 inputs selects the bank, and the address
provided on inputs (A13–A0 for x4 and x8, and A12–A0 for x16) selects the row. This row
remains active (or open) for accesses until a PRECHARGE command is issued to that
bank. A PRECHARGE command must be issued before opening a different row in the
same bank.
ACTIVE Operation
Before any READ or WRITE commands can be issued to a bank within the DDR2
SDRAM, a row in that bank must be opened (activated), even when additive latency is
used. This is accomplished via the ACTIVE command, which selects both the bank and
the row to be activated, as shown in Figure 15 on page 35.
After a row is opened with an ACTIVE command, a READ or WRITE command may be
issued to that row subject to the tRCD specification. tRCD (MIN) should be divided by
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. The same procedure is used to convert other specification limits from time
units to clock cycles. For example, a tRCD (MIN) specification of 20ns with a 266 MHz
clock (tCK = 3.75ns) results in 5.3 clocks, rounded up to 6. This is reflected in Figure 17 on
page 37, which covers any case where 5 < tRCD (MIN) / tCK ≤ 6. Figure 17 also shows the
case for tRRD where 2 < tRRD (MIN) / tCK ≤ 3.
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been closed (precharged). The minimum time interval
between successive ACTIVE commands to the same bank is defined by tRC.
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 35 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Bank/Row Activation
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to different banks is defined by
tRRD.
Figure 15: ACTIVE Command
DDR2 SDRAM also supports the AL feature, which allows a READ or WRITE command to
be issued prior to tRCD (MIN) by delaying the actual registration of the READ/WRITE
command to the internal device by AL clock cycles.
DON’T CARE
CK
CK#
CS#
RAS#
CAS#
WE#
CKE
Row
Bank
ADDRESS
BANK ADDRESS
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 36 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
READs
READs
READ Command
The READ command is used to initiate a burst read access to an active row. The value on
the BA1–BA0 inputs selects the bank, and the address provided on inputs A0–i (where i =
A9 for x16, A9 for x8, or A9, A11 for x4) selects the starting column location. The value on
input A10 determines whether or not auto precharge is used. If auto precharge is
selected, the row being accessed will be precharged at the end of the READ burst; if auto
precharge is not selected, the row will remain open for subsequent accesses.
READ Operation
READ bursts are initiated with a READ command, as shown in Figure 16 on page 37. The
starting column and bank addresses are provided with the READ command and auto
precharge is either enabled or disabled for that burst access. If auto precharge is
enabled, the row being accessed is automatically precharged at the completion of the
burst. If auto precharge is disabled, the row will be left open after the completion of the
burst.
During READ bursts, the valid data-out element from the starting column address will
be available READ latency (RL) clocks later. RL is defined as the sum of AL and CL;
RL = AL + CL. The value for AL and CL are programmable via the MR and EMR
commands, respectively. Each subsequent data-out element will be valid nominally at
the next positive or negative clock edge (i.e., at the next crossing of CK and CK#).
Figure 18 on page 38 shows examples of RL based on different AL and CL settings.
DQS/DQS# is driven by the DDR2 SDRAM along with output data. The initial LOW state
on DQS and HIGH state on DQS# is known as the read preamble (tRPRE). The LOW state
on DQS and HIGH state on DQS# coincident with the last data-out element is known as
the read postamble (tRPST).
Upon completion of a burst, assuming no other commands have been initiated, the DQ
will go High-Z. A detailed explanation of tDQSQ (valid data-out skew), tQH (data-out
window hold), and the valid data window are depicted in Figure 27 on page 46 and
Figure 28 on page 47. A detailed explanation of tDQSCK (DQS transition skew to CK) and
tAC (data-out transition skew to CK) is shown in Figure 29 on page 48.
Data from any READ burst may be concatenated with data from a subsequent READ
command to provide a continuous flow of data. The first data element from the new
burst follows the last element of a completed burst. The new READ command should be
issued x cycles after the first READ command, where x equals BL / 2 cycles. This is shown
in Figure 19 on page 39.
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 37 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
READs
Figure 16: READ Command
Figure 17: Example: Meeting tRRD (MIN) and tRCD (MIN)
DON’T CARE
CK
CK#
CS#
RAS#
CAS#
WE#
CKE
Col
Bank
ADDRESS
BANK ADDRESS
AUTO PRECHARGE
ENABLE
DISABLE
A10
M
AND
DON’T CARE
T1T0 T2 T3 T4 T5 T6T7
tRRD
Row Row Col
Bank xBank yBank y
NOPACT NOP NOPACT NOP NOP RD/WR
tRCD
0
, BA1
CK#
D
RESS
CK
T8 T9
NOP NOP
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 38 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
READs
Figure 18: READ Latency
Notes: 1. DO n = data-out from column n.
2. BL = 4.
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Shown with nominal tAC, tDQSCK, and tDQSQ.
READ NOP NOP NOP NOP NOP
Bank a,
Col n
CK
CK#
COMMAND
ADDRESS
DQ
DQS, DQS#
DO
n
DO
n
T0 T1 T2 T3 T4n T5nT4 T5
CK
CK#
COMMAND
READ NOP NOP NOP NOP NOP
ADDRESS
Bank a,
Col n
RL = 3 (AL = 0, CL = 3)
DQ
DQS, DQS#
DO
n
T0 T1 T2 T3 T3n T4nT4 T5
CK
CK#
COMMAND
READ NOP NOP NOP NOP NOP
ADDRESS
Bank a,
Col n
RL = 4 (AL = 0, CL = 4)
DQ
DQS, DQS#
T0 T1 T2 T3 T3n T4nT4 T5
AL = 1 CL = 3
RL = 4 (AL = 1 + CL = 3)
DON’T CARE TRANSITIONING DATA
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 39 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
READs
Figure 19: Consecutive READ Bursts
Notes: 1. DO n (or b) = data-out from column n (or column b).
2. BL = 4.
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Three subsequent elements of data-out appear in the programmed order following DO b.
5. Shown with nominal tAC, tDQSCK, and tDQSQ.
6. Example applies only when READ commands are issued to same device.
Nonconsecutive read data is illustrated in Figure 20 on page 40. Full-speed random read
accesses within a page (or pages) can be performed. DDR2 SDRAM supports the use of
concurrent auto precharge timing, shown in Table 9 on page 41.
DDR2 SDRAM does not allow interrupting or truncating of any READ burst using BL = 4
operations. Once the BL = 4 READ command is registered, it must be allowed to
complete the entire READ burst. However, a READ (with auto precharge disabled) using
BL = 8 operation may be interrupted and truncated only by another READ burst as long
as the interruption occurs on a 4-bit boundary due to the 4n prefetch architecture of
DDR2 SDRAM. READ burst BL = 8 operations may not be interrupted or truncated with
any command except another READ command, as shown in Figure 21 on page 40.
CK
CK#
COMMAND
READ NOP READ NOP NOP NOP NOP
ADDRESS
Bank,
Col nBank,
Col b
COMMAND
READ NOP READ NOP NOP NOP
ADDRESS
Bank,
Col nBank,
Col b
RL = 3
CK
CK#
COMMAND
ADDRESS
DQ
DQS, DQS#
RL = 4
DQ
DQS, DQS#
DO
n
DO
b
DO
nDO
b
T0 T1 T2 T3 T3n T4nT4 T5 T6
T5n T6n
T0 T1 T2 T3T2n
NOP
T3n T4nT4 T5 T6
T5n T6n
DON’T CARE TRANSITIONING DATA
tCCD
tCCD
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 40 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
READs
Figure 20: Nonconsecutive READ Bursts
Notes: 1. DO n (or b) = data-out from column n (or column b).
2. BL = 4.
3. Three subsequent elements of data-out appear in the programmed order following DO n.
4. Three subsequent elements of data-out appear in the programmed order following DO b.
5. Shown with nominal tAC, tDQSCK, and tDQSQ.
6. Example applies when READ commands are issued to different devices or nonconsecutive
READs.
Figure 21: READ Interrupted by READ
Notes: 1. BL = 8 required; auto precharge must be disabled (A10 = LOW).
2. READ command can be issued to any valid bank and row address (READ command at T0 and
T2 can be either same bank or different bank).
3. Interrupting READ command must be issued exactly 2 x tCK from previous READ.
4. Auto precharge can be either enabled (A10 = HIGH) or disabled (A10 = LOW) by the inter-
rupting READ command.
5. NOP or COMMAND INHIBIT commands are valid. PRECHARGE command cannot be issued to
banks used for READs at T0 and T2.
6. Example shown uses AL = 0; CL = 3, BL = 8, shown with nominal tAC, tDQSCK, and tDQSQ.
CK
CK#
COMMAND READ NOP NOP NOP NOP NOP NOP NOP
ADDRESS Bank,
Col n
READ
Bank,
Col b
COMMAND
ADDRESS
CL = 3
CK
CK#
COMMAND
ADDRESS
DQ
DQS, DQS#
CL = 4
DQ
DQS, DQS#
DO
n
T0 T1 T2 T3 T3n T4 T5 T7 T8T6T4n T6n T7n
NOP NOP NOP NOP
T5 T7 T8T5n T6T4n T7n
READ NOP NOP NOP
Bank,
Col n
READ
Bank,
Col b
T0 T1 T2 T3 T4
DO
b
DO
nDO
b
DON’T CARE TRANSITIONING DATA
CK
CK#
COMMAND
DQ
DQS, DQS#
CL = 3 (AL = 0)
READ
1
T0 T1 T2
DON’T CARETRANSITIONING DATA
NOP
5
NOP
5
D
OUT
T3 T4 T5
VALID VALID
T6
VALID
READ
3
VALID VALID VALID
T7 T8 T9
CL = 3 (AL = 0)
tCCD
ADDRESS
A10 VALID
4
VALID
2
VALID
2
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
D
OUT
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 41 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
READs
Data from any READ burst must be completed before a subsequent WRITE burst is
allowed. An example of a READ burst followed by a WRITE burst is shown in Figure 24 on
page 43. The tDQSS (MIN) case is shown; the tDQSS (MAX) case has a longer bus idle
time. (tDQSS [MIN] and tDQSS [MAX] are defined in Figure 31 on page 51.)
A READ burst may be followed by a PRECHARGE command to the same bank, provided
that auto precharge was not activated. The minimum READ-to-PRECHARGE command
spacing to the same bank is AL + BL/2 clocks and must also satisfy a minimum analog
time from the rising clock edge that initiates the last 4-bit prefetch of a READ-to-
PRECHARGE command. This READ-to-PRECHARGE time is called tRTP. For BL = 4 this
is the time from the actual READ (AL after the READ command) to PRECHARGE
command. For BL = 8 this is the time from AL + 2CK after the READ-to-PRECHARGE
command. Following the PRECHARGE command, a subsequent command to the same
bank cannot be issued until tRP is met.
Note: Part of the row precharge time is hidden during the access of the last data elements.
Examples of READ-to-PRECHARGE are shown in Figure 22 on page 42 for BL = 4 and
Figure 23 on page 42 for BL = 8. The delay from READ-to-PRECHARGE command to the
same bank is AL + BL/2 + MAX (tRTP/tCK or 2CK) - 2CK.
If A10 is HIGH when a READ command is issued, the READ with auto precharge function
is engaged. The DDR2 SDRAM starts an auto precharge operation on the rising edge,
which is AL + (BL/2) cycles later than the READ with auto precharge command if tRAS
(MIN) and tRTP are satisfied. If tRAS (MIN) is not satisfied at the edge, the start point of
auto precharge operation will be delayed until tRAS (MIN) is satisfied. If tRTP (MIN) is
not satisfied at the edge, the start point of the auto precharge operation will be delayed
until tRTP (MIN) is satisfied. In case the internal precharge is pushed out by tRTP, tRP
starts at the point where the internal precharge happens (not at the next rising clock
edge after this event). For BL = 4, the minimum time from READ with auto precharge to
the next ACTIVATE command becomes AL + (tRTP + tRP)*, shown in Figure 22 on
page 42; for BL = 8, the time from READ with auto precharge to the next ACTIVATE
command is AL + 2 clocks + (tRTP + tRP)*, shown in Figure 23 on page 42. The * indicates
each parameter term is divided by tCK and rounded up to the next integer. In any event,
internal precharge does not start earlier than two clocks after the last 4-bit prefetch.
Table 9: READ Using Concurrent Auto Precharge
From
Command
(Bank n)
To Command
(Bank m)
Minimum Delay (with
Concurrent Auto Precharge) Units
READ with
auto
precharge
READ or READ with auto precharge BL/2 tCK
WRITE or WRITE with auto precharge (BL/2) + 2 tCK
PRECHARGE or ACTIVE 1 tCK
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 42 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
READs
Figure 22: READ-to-PRECHARGE – BL = 4
Notes: 1. RL = 4 (AL = 1, CL = 3); BL = 4.
2. tRTP ≥ 2 clocks.
3. Shown with nominal tAC, tDQSCK, and tDQSQ.
Figure 23: READ-to-PRECHARGE – BL = 8
Notes: 1. RL = 4 (AL = 1, CL = 3); BL = 8.
2. tRTP ≥ 2 clocks.
3. Shown with nominal tAC, tDQSCK, and tDQSQ.
CK
CK#
COMMAND
DQ
DQS, DQS#
CL = 3
READ
T0 T1 T2
DON’T CARETRANSITIONING DATA
NOP
PRECHG
D
OUT
T3 T4 T5 T6
ACTIVE
T7
ADDRESS
A10
AL = 1
NOP
Bank a
≥tRTP (MIN)
Bank a
≥tRAS (MIN)
Bank a
≥tRP (MIN)
NOP NOP
AL + BL/2 + MAX(tRTP/tCK or 2CK) - 2CK
NOP
≥tRC (MIN)
4-bit
prefetch
Valid Valid
D
OUT
D
OUT
D
OUT
CK
CK#
COMMAND
DQ
DQS, DQS#
CL = 3
READ
T0 T1 T2
DON’T CARETRANSITIONING DATA
NOP
DOUT
T3 T4 T5 T6 T7 T8
ADDRESS
A10
AL = 1
NOP
Bank a
≥tRC (MIN)
≥tRTP (MIN)
NOP
NOP
first 4-bit
prefetch
second 4-bit
prefetch
≥tRP (MIN)
PRECHG
Bank aBank a
NOP
NOP ACTIVE
≥tRAS (MIN)
Valid Valid
AL + BL/2 + MAX(tRTP/tCK or 2CK) -2CK
DOUT DOUT DOUT DOUT DOUT DOUT DOUT
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 43 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
READs
Figure 24: READ-to-WRITE
Notes: 1. BL = 4; CL = 3; AL = 2.
2. Shown with nominal tAC, tDQSCK, and tDQSQ.
CK
CK#
COMMAND
DQ
DQS, DQS#
AL = 2
ACTIVE n
T0 T1 T2
DON’T CARETRANSITIONING DATA
NOP NOP
D
OUT
n
T3 T4 T5
NOP WRITE n
T6
NOP
WL = RL - 1 = 4
T7 T8
NOP NOP NOP
T9 T10 T11
NOP NOP
CL = 3
RL = 5
tRCD = 3
READ n
D
OUT
n + 1 D
OUT
n + 2 D
OUT
n + 3
DIN
nDIN
n + 1 DIN
n + 2 DIN
n + 3
NOP NOP NOP
WRITE
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 44 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
READs
Figure 25: Bank Read – Without Auto Precharge
Notes: 1. DO n = data-out from column n; subsequent elements are applied in the programmed
order.
2. BL = 4 and AL = 0 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T5.
5. PRE = PRECHARGE, ACT = ACTIVE, RA = row address, BA = bank address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
7. The PRECHARGE command can only be applied at T6 if tRAS (MIN) is met.
8. READ-to-PRECHARGE = AL + BL/2 + (tRTP - 2 clocks).
9. I/0 balls, when entering or exiting HIGH-Z are not referenced to a specific voltage level, but
to when the device begins to drive or no longer drives, respectively.
CK
CK#
CKE
A10
BA0, BA1
tCK tCH tCL
RA
tRCD
tRAS7
tRC
tRP
CL = 3
DM
T0 T1 T2 T3 T4 T5 T7n T8nT6T7 T8
DQ1
DQS, DQS#
Case 1: tAC (MIN)
and tDQSCK (MIN)
Case 2: tAC (MAX)
and tDQSCK (MAX)
DQ1
DQS, DQS#
t
RPRE
tRPRE
tRPST
tRPST
t
DQSCK (MIN)
t
DQSCK (MAX)
t
LZ (MIN)
t
LZ (MAX)
t
AC (MIN)
t
LZ (MIN)
DO
n
t
HZ (MAX)
t
AC (MAX)
t
LZ (MIN)
DO
n
NOP6
NOP6
COMMAND5ACT
RA Col n
PRE
7
Bank x
RA
RA
Bank xBank x4
9
9
99
ACT
Bank x
NOP6NOP6NOP6NOP6
t
HZ (MIN)
ONE BANK
ALL BANKS
DON’T CARE TRANSITIONING DATA
READ2
ADDRESS
3
tRTP
8
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 45 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
READs
Figure 26: Bank Read – With Auto Precharge
Notes: 1. DO n = data-out from column n; subsequent elements are applied in the programmed
order.
2. BL = 4, RL = 4 (AL = 1, CL = 3) in the case shown.
3. Enable auto precharge.
4. ACT = ACTIVE, RA = row address, BA = bank address.
5. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
6. The DDR2 SDRAM internally delays auto precharge until both tRAS (MIN) and tRTP (MIN)
have been satisfied.
7. I/0 balls, when entering or exiting HIGH-Z are not referenced to a specific voltage level, but
to when the device begins to drive or no longer drives, respectively.
4-bit
prefetch
CK
CK#
CKE
A10
BA0, BA1
tCK tCH tCL
RA
tRCD
tRAS
tRC
tRP
CL = 3
DM
T0 T1 T2 T3 T4 T5 T7n T8nT6 T7 T8
DQ1
DQS, DQS#
Case 1: tAC (MIN)
and tDQSCK (MIN)
Case 2: tAC (MAX)
and tDQSCK (MAX)
DQ1
DQS, DQS#
t
RPRE
tRPRE
tRPST
tRPST
t
DQSCK (MIN)
t
DQSCK (MAX)
t
LZ (MIN)
t
LZ (MAX)
t
AC (MIN)
t
LZ (MIN)
DO
n
t
HZ (MAX)
t
AC (MAX)
t
LZ (MAX)
DO
n
NOP5
NOP5
COMMAND5ACT
RA Col n
Bank x
RA
RA
Bank x
ACT
Bank x
NOP5NOP5NOP5NOP5NOP5
t
HZ (MIN)
DON’T CARE TRANSITIONING DATA
READ2,6
ADDRESS
AL = 1
tRTP
Internal
precharge
3
7
7
77
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 46 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
READs
Figure 27: x4, x8 Data Output Timing – tDQSQ, tQH, and Data Valid Window
Notes: 1. DQ transitioning after DQS transition define tDQSQ window. DQS transitions at T2 and at
T2n are “early DQS,” at T3 are “nominal DQS,” and at T3n are “late DQS.”
2. DQ0, DQ1, DQ2, DQ3 for x4 or DQ0–DQ7 for x8.
3. tDQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS
transitions, and ends with the last valid transition of DQ.
4. tQH is derived from tHP: tQH = tHP - tQHS.
5. tHP is the lesser of tCL or tCH clock transitions collectively when a bank is active.
6. The data valid window is derived for each DQS transition and is defined as tQH - tDQSQ.
DQ (Last data valid)
DQ2
DQ2
DQ2
DQ2
DQ2
DQ2
DQS#
DQS1
DQ (Last data valid)
DQ (First data no longer valid)
DQ (First data no longer valid)
All DQs and DQS, collectively6
Earliest signal transition
Latest signal transition
T2
T2
T2
T2n
T2n
T2n
T3
T3
T3
T3n
T3n
T3n
CK
CK#
T1 T2 T3 T4T2n T3n
tQH
4
tHP
5
tHP
5
tHP
5
tQH
4
tQH
4
tHP
5
tHP
5
tHP
5
tQH
4
tDQSQ
3
tDQSQ
3
tDQSQ
3
tDQSQ
3
Data
Valid
Window
Data
Valid
Window
Data
Valid
Window
Data
Valid
Window
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 47 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
READs
Figure 28: x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window
Notes: 1. DQ transitioning after DQS transitions define the tDQSQ window. LDQS defines the lower
byte, and UDQS defines the upper byte.
2. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
3. tDQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS
transitions, and ends with the last valid transition of DQ.
4. tQH is derived from tHP: tQH = tHP - tQHS.
5. tHP is the lesser of tCL or tCH clock transitions collectively when a bank is active.
6. The data valid window is derived for each DQS transition and is tQH - tDQSQ.
7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.
DQ (Last data valid)2
DQ2
DQ2
DQ2
DQ2
DQ2
DQ2
LDSQ#
LDQS1
DQ (Last data valid)2
DQ (First data no longer valid)2
DQ (First data no longer valid)2
DQ0–DQ7 and LDQS, collectively6
T2
T2
T2
T2n
T2n
T2n
T3
T3
T3
T3n
T3n
T3n
CK
CK#
T1 T2 T3 T4T2n T3n
tQH
4
tQH
4
tDQSQ
3
tDQSQ
3
tDQSQ
3
tDQSQ
3
Data Valid
Window
Data Valid
Window
DQ (Last data valid)7
DQ7
DQ7
DQ7
DQ7
DQ7
DQ7
UDQS#
UDQS1
DQ (Last data valid)7
DQ (First data no longer valid)7
DQ (First data no longer valid)7
DQ8–DQ15 and UDQS, collectively6
T2
T2
T2
T2n
T2n
T2n
T3
T3
T3
T3n
T3n
T3n
tQH
4
tQH
4
tQH
4
tQH
4
tDQSQ
3
tDQSQ
3
tDQSQ
3
tDQSQ
3
tHP
5
tHP
5
tHP
5
tHP
5
tHP
5
tHP
5
tQH
4
tQH
4
Data Valid
Window
Data Valid
Window
Data Valid
Window
Data Valid
Window
Data Valid
Window
Upper Byte
Lower Byte
Data Valid
Window
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 48 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
READs
Figure 29: Data Output Timing – tAC and tDQSCK
Notes: 1. tDQSCK is the DQS output window relative to CK and is the “long-term” component of DQS
skew.
2. DQ transitioning after DQS transitions define tDQSQ window.
3. All DQ must transition by tDQSQ after DQS transitions, regardless of tAC.
4. tAC is the DQ output window relative to CK and is the “long term” component of DQ skew.
5. tLZ (MIN) and tAC (MIN) are the first valid signal transitions.
6. tHZ (MAX) and tAC (MAX) are the latest valid signal transitions.
7. READ command with CL = 3, AL = 0 issued at T0.
8. I/O balls, when entering or exiting HIGH-Z, are not referenced to a specific voltage level,
but to when the device begins to drive or no longer drives, respectively.
CK
CK#
DQS#/DQS, or
LDQS#/LDQS / UDQ#/UDQS2
T07T1 T2 T3 T3n T4 T4n T5 T5n T6 T6n T7
tRPST
tLZ (MIN) tDQSCK1 (MIN)
tDQSCK1 (MAX)
tHZ (MAX)
tRPRE
DQ (Last data valid)
DQ (First data valid)
All DQs collectively3
tAC4 (MIN) tAC4 (MAX)
tLZ (MIN) tHZ (MAX)
T3
T3
T3n T4n T5n T6n
T3n
T3n
T4n
T4n
T5n
T5n
T6n
T6n
T4
T5
T5
T6
T6
T3 T4 T5 T6
T4
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 49 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
WRITEs
WRITEs
WRITE Command
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA1–BA0 inputs selects the bank, and the address provided on inputs A0–i (where
i = A9 for x8 and x16; or A9, A11 for x4) selects the starting column location. The value on
input A10 determines whether or not auto precharge is used. If auto precharge is
selected, the row being accessed will be precharged at the end of the WRITE burst; if
auto precharge is not selected, the row will remain open for subsequent accesses.
Figure 30: WRITE Command
Note: CA = column address; BA = bank address; EN AP = enable auto precharge; and DIS AP = dis-
able auto precharge.
Input data appearing on the DQ is written to the memory array subject to the DM input
logic level appearing coincident with the data. If a given DM signal is registered LOW, the
corresponding data will be written to memory; if the DM signal is registered HIGH, the
corresponding data inputs will be ignored, and a WRITE will not be executed to that
byte/column location (Figure 40 on page 58).
WRITE Operation
WRITE bursts are initiated with a WRITE command, as shown in Figure 30. DDR2
SDRAM uses WL equal to RL minus one clock cycle [WL = RL - 1CK = AL + (CL - 1CK)].
The starting column and bank addresses are provided with the WRITE command, and
auto precharge is either enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst. For the generic
WRITE commands used in the following illustrations, auto precharge is disabled.
CS#
WE#
CAS#
RAS#
CKE
CA
A10
BANK ADDRESS
HIGH
EN AP
DIS AP
BA
CK
CK#
DON’T CARE
ADDRESS
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 50 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
WRITEs
During WRITE bursts, the first valid data-in element will be registered on the first rising
edge of DQS following the WRITE command, and subsequent data elements will be
registered on successive edges of DQS. The LOW state on DQS between the WRITE
command and the first rising edge is known as the write preamble; the LOW state on
DQS following the last data-in element is known as the write postamble.
The time between the WRITE command and the first rising DQS edge is WL ±tDQSS.
Subsequent DQS positive rising edges are timed, relative to the associated clock edge, as
±tDQSS. tDQSS is specified with a relatively wide range (25 percent of one clock cycle).
All of the WRITE diagrams show the nominal case, and where the two extreme cases
(tDQSS [MIN] and tDQSS [MAX]) might not be intuitive, they have also been included.
Figure 31 on page 51 shows the nominal case and the extremes of tDQSS for BL = 4. Upon
completion of a burst, assuming no other commands have been initiated, the DQ will
remain High-Z and any additional input data will be ignored.
Data for any WRITE burst may be concatenated with a subsequent WRITE command to
provide continuous flow of input data. The first data element from the new burst is
applied after the last element of a completed burst. The new WRITE command should
be issued x cycles after the first WRITE command, where x equals BL/2.
Figure 32 on page 52 shows concatenated bursts of BL = 4. An example of nonconsecu-
tive WRITEs is shown in Figure 33 on page 52. Full-speed random write accesses within a
page or pages can be performed as shown in Figure 34 on page 53. DDR2 SDRAM
supports concurrent auto precharge options, as shown in Table 10.
DDR2 SDRAM does not allow interrupting or truncating any WRITE burst using BL = 4
operation. Once the BL = 4 WRITE command is registered, it must be allowed to
complete the entire WRITE burst cycle. However, a WRITE BL = 8 operation (with auto
precharge disabled) might be interrupted and truncated ONLY by another WRITE burst
as long as the interruption occurs on a 4-bit boundary, due to the 4n prefetch architec-
ture of DDR2 SDRAM. WRITE burst BL = 8 operations may not be interrupted or trun-
cated with any command except another WRITE command, as shown in Figure 35 on
page 53.
Data for any WRITE burst may be followed by a subsequent READ command. To follow a
WRITE, tWTR should be met, as shown in Figure 36 on page 54. The number of clock
cycles required to meet tWTR is either 2 or tWTR/tCK, whichever is greater. Data for any
WRITE burst may be followed by a subsequent PRECHARGE command. tWR must be
met, as shown in Figure 37 on page 55. tWR starts at the end of the data burst, regardless
of the data mask condition.
Table 10: WRITE Using Concurrent Auto Precharge
From Command
(Bank n)
To Command
(Bank m)
Minimum Delay (with
Concurrent Auto Precharge) Units
WRITE with auto
precharge
READ or READ with auto
precharge
(CL - 1) + (BL/2) + tWTR tCK
WRITE or WRITE with
auto precharge
(BL/2) tCK
PRECHARGE or ACTIVE 1 tCK
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 51 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
WRITEs
Figure 31: WRITE Burst
Notes: 1. DI b = data-in for column b.
2. Three subsequent elements of data-in are applied in the programmed order following
DI b.
3. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.
4. A10 is LOW with the WRITE command (auto precharge is disabled).
5. Subsequent rising DQS signals must align to the clock within tDQSS.
DQS, DQS#
tDQSS (MAX)
tDQSS (NOM)
tDQSS (MIN)
WL ± tDQSS
DM
DQ
CK
CK#
COMMAND
WRITE NOP NOP
ADDRESS
Bank a,
Col b
NOP NOP
T0 T1 T2 T3T2n T4T3n
DQS, DQS#
WL + tDQSS
5
5
5
DM
DQ
DQS, DQS#
WL - tDQSS
DM
DQ
DI
b
DI
b
DI
b
DON’T CARE TRANSITIONING DATA
tDQSS
tDQSS
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 52 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
WRITEs
Figure 32: Consecutive WRITE-to-WRITE
Notes: 1. DI b, etc. = data-in for column b, etc.
2. Three subsequent elements of data-in are applied in the programmed order following
DI b.
3. Three subsequent elements of data-in are applied in the programmed order following
DI n.
4. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.
5. Each WRITE command may be to any bank.
6. Subsequent rising DQS signals must align to the clock within tDQSS.
Figure 33: Nonconsecutive WRITE-to-WRITE
Notes: 1. DI b, etc. = data-in for column b, etc.
2. Three subsequent elements of data-in are applied in the programmed order following
DI b.
3. Three subsequent elements of data-in are applied in the programmed order following
DI n.
4. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.
5. Each WRITE command may be to any bank.
6. Subsequent rising DQS signals must align to the clock within tDQSS.
CK
CK#
COMMAND WRITE NOP WRITE NOP NOP NOP
ADDRESS Bank,
Col b
NOP
Bank,
Col n
T0 T1 T2 T3T2n T4 T5T4n T6T5nT3nT1n
DQ
DQS, DQS#
DM
DI
n
DI
b
DON’T CARE TRANSITIONING DATA
WL ± tDQSS
t
DQSS (NOM)
WL = 2
tCCD
WL = 2
66
6
CK
CK#
COMMAND WRITE NOP NOP NOP NOP NOP
ADDRESS Bank,
Col b
WRITE
Bank,
Col n
T0 T1 T2 T3T2n T4 T5T4nT3n T5n T6 T6n
DQ
DQS, DQS#
DM
DI
n
DI
b
tDQSS (NOM) WL ± tDQSS
DON’T CARE TRANSITIONING DATA
WL = 2 WL = 2
666
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 53 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
WRITEs
Figure 34: Random WRITE Cycles
Notes: 1. DI b, etc. = data-in for column b, etc.
2. Three subsequent elements of data-in are applied in the programmed order following
DI b.
3. Three subsequent elements of data-in are applied in the programmed order following
DI n.
4. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.
5. Each WRITE command may be to any bank.
6. Subsequent rising DQS signals must align to the clock within tDQSS.
Figure 35: WRITE Interrupted by WRITE
Notes: 1. BL = 8 required and auto precharge must be disabled (A10 = LOW).
2. WRITE command can be issued to any valid bank and row address (WRITE command at T0
and T2 can be either same bank or different bank).
3. Interrupting WRITE command must be issued exactly 2 x tCK from previous WRITE.
4. Auto precharge can be either enabled (A10 = HIGH) or disabled (A10 = LOW) by the inter-
rupting WRITE command.
5. NOP or COMMAND INHIBIT commands are valid. PRECHARGE command cannot be issued to
banks used for WRITEs at T0 and T2.
6. Earliest WRITE-to-PRECHARGE timing for WRITE at T0 is WL + BL/2 + tWR where tWR starts
with T7 and not T5 (since BL = 8 from MR and not the truncated length).
7. Example shown uses AL = 0; CL = 4, BL = 8.
8. Subsequent rising DQS signals must align to the clock within tDQSS.
CK
CK#
COMMAND WRITE NOP WRITE NOP NOP NOP
ADDRESS Bank,
Col b
NOP
Bank,
Col n
T0 T1 T2 T3T2n T4 T5T4n T6T5nT3nT1n
DQ
DQS, DQS#
DM
DI
n
DI
b
DON’T CARE TRANSITIONING DATA
WL ± tDQSS
t
DQSS (NOM)
WL = 2
tCCD
WL = 2
66
6
CK
CK#
COMMAND
DQ
DQS, DQS#
WL = 3
WRITE1
a
T0 T1 T2
DON’T CARETRANSITIONING DATA
DIN
a
T3 T4 T5 T6
WRITE3
b
DIN
b
T7 T8 T9
WL = 32 clock requirement
ADDRESS
A10 VALID
4
VALID
2
VALID
2
VALID
6
VALID
6
VALID
6
NOP
5
NOP
5
NOP
5
NOP
5
NOP
5
8 8888
DIN
a + 1 DIN
a + 3
DIN
a + 2 DIN
b + 1 DIN
b + 2 DIN
b + 3 DIN
b + 4 DIN
b + 5 DIN
b + 6 DIN
b + 7
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 54 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
WRITEs
Figure 36: WRITE-to-READ
Notes: 1. DI b = data-in for column b; DOUT n = data-out from column n.
2. BL = 4, AL = 0, CL = 3; thus, WL = 2.
3. One subsequent element of data-in is applied in the programmed order following DI b.
4. tWTR is referenced from the first positive CK edge after the last data-in pair.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
6. The number of clock cycles required to meet tWTR is either 2 or tWTR/tCK, whichever is
greater.
7. tWTR is required for any READ following a WRITE to the same device, but it is not required
between module ranks.
8. Subsequent rising DQS signals must align to the clock within tDQSS.
tDQSS (NOM)
CK
CK#
COMMAND WRITE NOP NOP NOP NOP NOP NOP NOP
ADDRESS Bank a,
Col bBank a,
Col n
READ
T0 T1 T2 T3T2n T4 T5 T9nT3n T6 T7 T8 T9
tWTR7
CL = 3
CL = 3
CL = 3
DQ
DQS, DQS#
DM
DI
b
tDQSS (MIN)
DQ
DQS, DQS#
DM
DI
b
tDQSS (MAX)
DQ
DQS, DQS#
DM
DI
bDout
Dout
DON’T CARE TRANSITIONING DATA
WL ± tDQSS
WL - tDQSS
WL + tDQSS
NOP
Dout
8
8
8
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 55 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
WRITEs
Figure 37: WRITE-to-PRECHARGE
Notes: 1. DI b = data-in for column b.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. BL = 4, CL = 3, AL = 0; thus, WL = 2.
4. tWR is referenced from the first positive CK edge after the last data-in pair.
5. The PRECHARGE and WRITE commands are to the same bank. However, the PRECHARGE
and WRITE commands may be to different banks, in which case tWR is not required and the
PRECHARGE command could be applied earlier.
6. A10 is LOW with the WRITE command (auto precharge is disabled).
7. PRE = PRECHARGE command.
8. Subsequent rising DQS signals must align to the clock within tDQSS.
tDQSS (NOM)
CK
CK#
COMMAND WRITE NOP NOP NOP NOPNOP
ADDRESS Bank a,
Col bBank,
(a or all)
NOP
T0 T1 T2 T3T2n T4 T5T3n T6 T7
tWR tRP
DQ
DQS#
DQS
DM
DI
b
tDQSS (MIN)
DQ
DQS#
DQS
DM
DI
b
tDQSS (MAX)
DQ
DQS#
DQS
DM
DI
b
DON’T CARE TRANSITIONING DATA
WL + tDQSS
WL - tDQSS
WL + tDQSS
PRE7
8
8
8
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 56 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
WRITEs
Figure 38: Bank Write – without Auto Precharge
Notes: 1. DI n = data-in from column n; subsequent elements are applied in the programmed order.
2. BL = 4, AL = 0, and WL = 2 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T9.
5. PRE = PRECHARGE, ACT = ACTIVE, RA = row address, BA = bank address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
7. tDSH is applicable during tDQSS (MIN) and is referenced from CK T5 or T6.
8. tDSS is applicable during tDQSS (MAX) and is referenced from CK T6 or T7.
9. Subsequent rising DQS signals must align to the clock within tDQSS.
CK
CK#
CKE
A10
BA0, BA1
tCK tCH tCL
RA
tRCD
tRAS tRP
tWR
T0 T1 T2 T3 T5 T6 T6n T7 T8 T9T5n
NOP6
NOP6
COMMAND5
3
9
ACT
RA Col n
WRITE2NOP6
ONE BANK
ALL BANKS
Bank x
PRE
Bank x
NOP6NOP6NOP6
tDQSL tDQSH tWPST
Bank x4
DQ1
DM
DI
n
DON’T CARE TRANSITIONING DATA
WL ± tDQSS (NOM)
tWPRE
DQS, DQS#
ADDRESS
NOP6
WL = 2
T4
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 57 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
WRITEs
Figure 39: Bank Write – with Auto Precharge
Notes: 1. DI n = data-in from column n; subsequent elements are applied in the programmed order.
2. BL = 4, AL = 0, and WL = 2 in the case shown.
3. Enable auto precharge.
4. ACT = ACTIVE, RA = row address, BA = bank address.
5. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
6. tDSH is applicable during tDQSS (MIN) and is referenced from CK T5 or T6.
7. tDSS is applicable during tDQSS (MAX) and is referenced from CK T6 or T7.
8. WR is programmed via MR[11, 10, 9] and is calculated by dividing tWR (in nanoseconds) by
tCK and rounding up to the next integer value.
9. Subsequent rising DQS signals must align to the clock within tDQSS.
CK
CK#
CKE
A10
BA0, BA1
tCK tCH t
CL
RA
tRCD
tRAS tRP
WR
8
T0 T1 T2 T3 T4 T5 T5n T6 T7 T8T6n
NOP
5
NOP
5
COMMAND
4
3
ACT
RA Col n
WRITE
2
NOP
5
Bank x
NOP
5
Bank x
NOP
5
NOP
5
NOP
5
tDQSL tDQSH tWPST
DQ
1
DM
WL ± tDQSS (NOM)
DON’T CARE
TRANSITIONING DATA
tWPRE
DQS,DQS#
ADDRESS
T9
NOP
5
WL = 2
DI
n
9
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 58 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
WRITEs
Figure 40: WRITE – DM Operation
Notes: 1. DI n = data-in from column n; subsequent elements are applied in the programmed order.
2. Burst length = 4, AL = 1, and WL = 2 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T11.
5. PRE = PRECHARGE, ACT = ACTIVE, RA = row address, BA = bank address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
7. tDSH is applicable during tDQSS (MIN) and is referenced from CK T6 or T7.
8. tDSS is applicable during tDQSS (MAX) and is referenced from CK T7 or T8.
9. tWR starts at the end of the data burst regardless of the data mask condition.
10. Subsequent rising DQS signals must align to the clock within tDQSS.
CK
CK#
CKE
A10
BA0, BA1
t
CK
t
CH
t
CL
RA
t
RCD
t
RAS tRPA
tWR9
T0 T1 T2 T3 T4 T5 T7nT6 T7 T8T6n
NOP
6
NOP
6
COMMAND
5
3
ACT
RA Col n
WRITE
2
NOP
6
ONE BANK
ALL BANKS
Bank x
Bank x
NOP
6
NOP
6
NOP
6
NOP
6
NOP
6
NOP
6
tDQSL tDQSH
tWPST
Bank x4
DQ
1
DM
DON’T CARETRANSITIONING DATA
WL ±
t
DQSS (NOM)
tWPRE
PRE
DQS, DQS#
ADDRESS
T9 T10 T11
AL = 1 WL = 2
DI
n
10
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 59 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
WRITEs
Figure 41: Data Input Timing
Notes: 1. tDSH (MIN) generally occurs during tDQSS (MIN).
2. tDSS (MIN) generally occurs during tDQSS (MAX).
3. WRITE command issued at T0.
4. For x16, LDQS controls the lower byte and UDQS controls the upper byte.
5. WRITE command with WL = 2 (CL = 3, AL = 0) issued at T0.
6. Subsequent rising DQS signals must align to the clock within tDQSS.
DQS
DQS#
WL - tDQSS (NOM)
tDQSH tWPST
tDQSL
tDSS2tDSH1
tDSH1tDSS2
DM
DQ
CK
CK#
T1T0 T1n T2 T2n T3 T4T3n
DI
DON’T CARE
TRANSITIONING DATA
t
WPRE
6
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 60 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Precharge
Precharge
PRECHARGE Command
The PRECHARGE command, illustrated in Figure 42 on page 60, is used to deactivate the
open row in a particular bank or the open row in all banks. The bank(s) will be available
for a subsequent row activation a specified time (tRP) after the PRECHARGE command
is issued, except in the case of concurrent auto precharge, where a READ or WRITE
command to a different bank is allowed as long as it does not interrupt the data transfer
in the current bank and does not violate any other timing parameters. Once a bank has
been precharged, it is in the idle state and must be activated prior to any READ or WRITE
commands being issued to that bank. A PRECHARGE command is allowed if there is no
open row in that bank (idle state) or if the previously open row is already in the process
of precharging. However, the precharge period will be determined by the last
PRECHARGE command issued to the bank.
PRECHARGE Operation
Input A10 determines whether one or all banks are to be precharged, and in the case
where only one bank is to be precharged, inputs BA1–BA0 select the bank. Otherwise
BA1–BA0 are treated as “Don’t Care.”
When all banks are to be precharged, inputs BA1–BA0 are treated as “Don’t Care.” Once a
bank has been precharged, it is in the idle state and must be activated prior to any READ
or WRITE commands being issued to that bank. tRPA timing applies when the
PRECHARGE (ALL) command is issued, regardless of the number of banks already open
or closed. If a single-bank PRECHARGE command is issued, tRP timing applies.
Figure 42: PRECHARGE Command
Note: BA = bank address (if A10 is LOW; otherwise “Don’t Care”).
CS#
WE#
CAS#
RAS#
CKE
A10
BA0, BA1
HIGH
ALL BANKS
ONE BANK
BA
ADDRESS
CK
CK#
DON’T CARE
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 61 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Self Refresh
Self Refresh
SELF REFRESH Command
The SELF REFRESH command can be used to retain data in the DDR2 SDRAM, even if
the rest of the system is powered down. When in the self refresh mode, the DDR2
SDRAM retains data without external clocking. All power supply inputs (including VREF )
must be maintained at valid levels upon entry/exit and during SELF REFRESH opera-
tion.
The SELF REFRESH command is initiated like a REFRESH command except CKE is LOW.
The DLL is automatically disabled upon entering self refresh and is automatically
enabled upon exiting self refresh (200 clock cycles must then occur before a READ
command can be issued). The differential clock should remain stable and meet tCKE
specifications at least 1 x tCK after entering self refresh mode. All command and address
input signals except CKE are “Don’t Care” during self refresh.
The procedure for exiting self refresh requires a sequence of commands. First, the differ-
ential clock must be stable and meet tCK specifications at least 1 x tCK prior to CKE
going back HIGH. Once CKE is HIGH (tCKE [MIN] has been satisfied with four clock
registrations), the DDR2 SDRAM must have NOP or DESELECT commands issued for
tXSNR because time is required for the completion of any internal refresh in progress. A
simple algorithm for meeting both refresh and DLL requirements is to apply NOP or
DESELECT commands for 200 clock cycles before applying any other command.
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 62 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Self Refresh
Figure 43: Self Refresh
Notes: 1. Clock must be stable and meeting tCK specifications at least 1 x tCK after entering self
refresh mode and at least 1 x tCK prior to exiting self refresh mode.
2. Device must be in the all banks idle state prior to entering self refresh mode.
3. tXSNR is required before any non-READ command can be applied.
4. tXSRD (200 cycles of CK) is required before a READ command can be applied at state Td0.
5. REF = REFRESH command.
6. Self refresh exit is asynchronous; however, tXSNR and tXSRD timing starts at the first rising
clock edge where CKE HIGH satisfies tISXR.
7. NOP or DESELECT commands are required prior to exiting self refresh until state Tc0, which
allows any non-READ command.
8. ODT must be disabled and RTT off (tAOFD and tAOFPD have been satisfied) prior to entering
SELF REFRESH at state T1.
9. Once self refresh has been entered, tCKE (MIN) must be satisfied prior to exiting self refresh.
10. CKE must stay HIGH until tXSRD is met; however, if self refresh is being re-entered, CKE may
go back LOW after tXSNR is satisfied.
11. Once exiting SELF REFRESH, ODT must remain LOW until tXSRD is satisfied.
CK1
CK#
COMMAND5NOP REF
ADDRESS
CKE1
VALID
DQ
DM
DQS#,
DQS
NOP7
tRP
2
tCHtCLtCK
1
tCK
1
tXSNR
3, 6, 11
tISXR
6
Enter self refresh
mode (synchronous)
Exit self refresh
mode (asynchronous)
T0 T1 Ta2Ta1
DON’T CARE
Ta0 Tc0Tb0
tXSRD
4,6
VALID3
NOP7
tCKE (MIN)
9
T2
ODT8
tAOFD / tAOFPD
8
Td0
VALID4
VALID3
Indicates a break in
time scale
tIH
tIH
tCKE10
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 63 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
REFRESH
REFRESH
REFRESH Command
REFRESH is used during normal operation of the DDR2 SDRAM and is analogous to
CAS#-Before-RAS# (CBR) REFRESH. This command is nonpersistent, so it must be
issued each time a refresh is required. The addressing is generated by the internal refresh
controller. This makes the address bits a “Don’t Care” during an REFRESH command.
The 512Mb DDR2 SDRAM requires REFRESH cycles at an average interval of 7.8125µs
(MAX). To allow for improved efficiency in scheduling and switching between tasks,
some flexibility in the absolute refresh interval is provided. A maximum of eight
REFRESH commands can be posted (to defer issuing REFRESH commands) to any given
DDR2 SDRAM, meaning that the maximum absolute interval between any REFRESH
command and the next REFRESH command is 9 × 7.8125µs (70.3µs; 3.9µs for high-
temperature operation). The refresh period begins when the REFRESH command is
registered and ends tRFC (MIN) later.
Figure 44: Refresh Mode
Notes: 1. PRE = PRECHARGE, ACT = ACTIVE, AR = REFRESH, RA = row address, BA = bank address.
2. NOP commands are shown for ease of illustration; other valid commands may be possible at
these times. CKE must be active during clock positive transitions.
3. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active
(i.e., must precharge all active banks).
4. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.
5. The second REFRESH is not required and is only shown as an example of two back-to-back
REFRESH commands.
CK
CK#
COMMAND
1
NOP
2
NOP
2
NOP
2
PRE
CKE
RA
ADDRESS
A10
1
BANK
1
Bank(s)
3
BA
REF NOP
2
REF
5
NOP
2
ACT
NOP
2
ONE BANK
ALL BANKS
tCK tCH tCL
RA
DQ
4
DM
4
DQS, DQS#
4
tRFC
5
tRP tRFC(MIN)
T0 T1 T2 T3 T4 Ta0 Tb0
Ta1 Tb1 Tb2
DON’T CARE
Indicates a break in
time scale
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 64 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Power-Down Mode
Power-Down Mode
DDR2 SDRAMs support multiple power-down modes that allow significant power
savings over normal operating modes. CKE is used to enter and exit different power-
down modes. Power-down entry and exit timings are shown in Figure 45 on page 65.
Detailed power-down entry conditions are shown in Figures 46 through 53. The CKE
Truth Table, Table 11, is shown on page 66.
DDR2 SDRAMs require CKE to be registered HIGH (active) at all times that an access is
in progress—from the issuing of a READ or WRITE command until completion of the
burst. Thus, a clock suspend is not supported. For READs, a burst completion is defined
when the read postamble is satisfied; for WRITEs, a burst completion is defined when
the write postamble and tWR or tWTR are satisfied, as shown in Figures 48 and 49 on
page 68. The number of clock cycles required to meet tWTR is either two or tWTR/tCK,
whichever is greater.
Power-down mode (see Figure 45 on page 65) is entered when CKE is registered LOW
coincident with a NOP or DESELECT command. CKE is not allowed to go LOW during a
mode register or extended mode register command time, or while a READ or WRITE
operation is in progress. If power-down occurs when all banks are idle, this mode is
referred to as precharge power-down. If power-down occurs when there is a row active in
any bank, this mode is referred to as active power-down. Entering power-down deacti-
vates the input and output buffers, excluding CK, CK#, ODT, and CKE. For maximum
power savings, the DLL is frozen during precharge power-down. Exiting active power-
down requires the device to be at the same voltage and frequency as when it entered
power-down. Exiting precharge power-down requires the device to be at the same
voltage as when it entered power-down; however, the clock frequency is allowed to
change. See “Precharge Power-Down Clock Frequency Change” on page 71.
The maximum duration for either active or precharge power-down is limited by the
refresh requirements of the device tRFC (MAX). The minimum duration for power-down
entry and exit is limited by the tCKE (MIN) parameter. While in power-down mode, CKE
LOW, a stable clock signal, and stable power supply signals must be maintained at the
inputs of the DDR2 SDRAM, while all other input signals are “Don’t Care” except ODT.
Detailed ODT timing diagrams for different power-down modes are shown in Figures 56
through 63.
The power-down state is synchronously exited when CKE is registered HIGH (in
conjunction with an NOP or DESELECT command), as shown in Figure 45 on page 65.
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 65 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Power-Down Mode
Figure 45: Power-Down
Notes: 1. If this command is a PRECHARGE (or if the device is already in the idle state), then the
power-down mode shown is precharge power-down. If this command is an ACTIVE (or if at
least one row is already active), then the power-down mode shown is active power-down.
2. No column accesses are allowed to be in progress at the time power-down is entered. If the
DLL was not in a locked state when CKE went LOW, the DLL must be reset after exiting
power-down mode for proper READ operation.
3. tCKE (MIN) of three clocks means CKE must be registered on three consecutive positive clock
edges. CKE must remain at the valid input level the entire time it takes to achieve the three
clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid
level during the time period of tIS + 2 x tCK + tIH. CKE must not transition during its tIS and
tIH window.
4. tXP timing is used for exit precharge power-down and active power-down to any non-READ
command.
5. tXARD timing is used for exit active power-down to READ command if fast exit is selected
via MR (bit 12 = 0).
6. tXARDS timing is used for exit active power-down to READ command if slow exit is selected
via MR (bit 12 = 1).
CK
CK#
COMMAND NOP NOP NOP
ADDRESS
CKE
DQ
DM
DQS, DQS#
VALID
tCK tCH tCL
Enter
power-down
mode2
Exit
power-down
mode DON’T CARE
tCKE (MIN)3
tCKE (MIN)
3
VALIDVALID1
VALID
tXP
4
, tXARD
5
tXARDS
6
VALID VALID
tIS
tIH
tIH
T1 T2 T3 T4 T5 T6 T7 T8
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 66 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Power-Down Mode
Notes: 1. CKE (n) is the logic state of CKE at clock edge n; CKE (n-1) was the state of CKE at the previ-
ous clock edge.
2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge n.
3. Command (n) is the command registered at clock edge n, and action (n) is a result of com-
mand (n).
4. All states and sequences not shown are illegal or reserved unless explicitly described else-
where in this document.
5. On self refresh exit, DESELECT or NOP commands must be issued on every clock edge occur-
ring during the tXSNR period. READ commands may be issued only after tXSRD (200 clocks)
is satisfied.
6. Self refresh mode can only be entered from the all banks idle state.
7. Must be a legal command as defined in the Command Truth Table, Table 5 on page 29.
8. Valid commands for power-down entry and exit are NOP and DESELECT only.
9. Valid commands for self refresh exit are NOP and DESELECT only.
10. Power-down and self refresh can not be entered while READ or WRITE operations, LOAD
MODE operations, or PRECHARGE operations are in progress. See “Power-Down Mode” on
page 64 and See “Self Refresh” on page 61 for a list of detailed restrictions.
11. Minimum CKE HIGH time is tCKE = 3 x tCK. Minimum CKE LOW time is tCKE = 3 x tCK. This
requires a minimum of 3 clock cycles of registration.
12. The state of ODT does not affect the states described in this table. The ODT function is not
available during self refresh. See “ODT Timing” on page 74 for more details and specific
restrictions.
13. Power-down modes do not perform any REFRESH operations. The duration of power-down
mode is therefore limited by the refresh requirements.
14. “X” means “Don’t Care” (including floating around VREF) in self refresh and power-down.
However, ODT must be driven HIGH or LOW in power-down if the ODT function is enabled
via EMR(1).
Table 11: CKE Truth Table
Notes 1–3, 12
Current
State
CKE
Command (n)
CS#, RAS#,
CAS#, WE# Action (n)Notes
Previous
Cycle
(n-1)
Current
Cycle (n)
Power-down L L X Maintain power-down 13, 14
L H DESELECT or NOP Power-down exit 4, 8
Self refresh L L X Maintain self refresh 14
L H DESELECT or NOP Self refresh exit 4, 5, 9
Bank(s) active H L DESELECT or NOP Active power-down
entry
4, 8, 10, 11
All banks idle H L DESELECT or NOP Precharge power-down
entry
4, 8, 10
H L REFRESH Self refresh entry 6, 9, 11
H H Shown in Table 5 on page 29 7
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 67 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Power-Down Mode
Figure 46: READ to Power-Down or Self Refresh Entry
Notes: 1. Power-down or self refresh entry may occur after the READ burst completes.
2. In the example shown, READ burst completes at T5; earliest power-down or self refresh
entry is at T6.
Figure 47: READ with Auto Precharge to Power-Down or Self Refresh Entry
Notes: 1. Power-down or self refresh entry may occur after the READ burst completes.
2. In the example shown, READ burst completes at T5; earliest power-down or self refresh
entry is at T6.
DOUT
CK
CK#
COMMAND
DQ
DQS, DQS#
RL = 3
T0 T1 T2
DON’T CARE
TRANSITIONING DATA
NOP NOP
T3 T4 T5
VALID
T6 T7
tCKE (MIN)
ADDRESS
A10
NOP
CKE
READ
VALID
Power-down
1
or self refresh
entry
NOP2
VALID
DOUTDOUT DOUT
CK
CK#
COMMAND
DQ
DQS, DQS#
RL = 3
T0 T1 T2
DON’T CARE
TRANSITIONING DATA
NOP NOP
T3 T4 T5
VALID VALID
T6 T7
tCKE (MIN)
ADDRESS
A10
NOP
CKE
READ
VALID
Power-down
or self refresh
1
entry
NOP2
DOUT DOUTDOUT DOUT
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 68 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Power-Down Mode
Figure 48: WRITE to Power-Down or Self-Refresh Entry
Notes: 1. Power-down or self refresh entry may occur after the WRITE burst completes.
Figure 49: WRITE with Auto Precharge to Power-Down or Self Refresh Entry
Notes: 1. WR is programmed through MR[9, 10, 11] and represents (tWR [MIN] ns / tCK) rounded up
to next integer tCK.
2. Internal PRECHARGE occurs at Ta0 when WR has completed; power-down entry may occur
1 x tCK later at Ta1, prior to tRP being satisfied.
CK
CK#
COMMAND
DQ
DQS, DQS#
WL = 3
T0 T1 T2
DON’T CARETRANSITIONING DATA
NOP NOP
DOUT
T3 T4 T5
VALID VALID
T6
VALID
T7 T8
tCKE (MIN)
ADDRESS
A10
NOP
CKE
WRITE
VALID
Power-down
or self refresh
entry1
tWTR
NOP
1
DOUT DOUT DOUT
CK
CK#
COMMAND
DQ
DQS, DQS#
WL = 3
T0 T1 T2
DON’T CARE
TRANSITIONING DATA
NOP NOP
D
OUT
T3 T4 T5
VALID VALID
Ta0
VALID
2
NOP
Ta1 Ta2
tCKE (MIN)
ADDRESS
A10
NOP
CKE
WRITE
VALID
Power-down
or self refresh
entry
WR1
Indicates a break in
time scale
D
OUT
D
OUT
D
OUT
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 69 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Power-Down Mode
Figure 50: REFRESH Command to Power-Down Entry
Notes: 1. The earliest precharge power-down entry may occur is at T2 which is 1 x tCK after the
REFRESH command. Precharge power down entry occurs prior to tRFC (MIN) being satisfied.
Figure 51: ACTIVE Command to Power-Down Entry
Notes: 1. The earliest active power-down entry may occur is at T2, which is 1 x tCK after the ACTIVE
command. Active power-down entry occurs prior to tRCD (MIN) being satisfied.
CK
CK#
COMMAND
DON’T CARE
T0 T1
VALID
REFRESH
T2 T3
t
CKE (MIN)
CKE
Power-down
1
entry
1 x
t
CK
NOP
CK
CK#
COMMAND
DON’T CARE
T0 T1
VALID ACTIVE
T2
NOP
T3
tCKE (MIN)
CKE
Power-down
1
entry
1 tCK
ADDRESS
VALID
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 70 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Power-Down Mode
Figure 52: PRECHARGE Command to Power-Down Entry
Notes: 1. The earliest precharge power-down entry may occur is at T2, which is 1 x tCK after the PRE-
CHARGE command. Precharge power-down entry occurs prior to tRP (MIN) being satisfied.
Figure 53: LOAD MODE Command to Power-Down Entry
Notes: 1. The earliest precharge power-down entry is at T3, which is after tMRD is satisfied.
2. All banks must be in the precharged state and tRP met prior to issuing LM command.
3. Valid address for LM command includes MR, EMR, EMR(2), and EMR(3) registers.
CK
CK#
COMMAND
DON’T CARE
T0 T1
VALID
PRECHARGE
T2
NOP
T3
tCKE (MIN)
CKE
Power-down
1
entry
1 x tCK
ADDRESS
A10
VALID
ALL BANKS
vs
SINGLE BANK
CK
CK#
COMMAND
DON’T CARE
T0 T1
VALID LM
T2
NOP
T3 T4
tCKE (MIN)
CKE
Power-down
1
entry
tMRD
ADDRESS VALID3
tRP
2
NOP
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 71 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Precharge Power-Down Clock Frequency Change
Precharge Power-Down Clock Frequency Change
When the DDR2 SDRAM is in precharge power-down mode, ODT must be turned off
and CKE must be at a logic LOW level. A minimum of two differential clock cycles must
pass after CKE goes LOW before clock frequency may change. The device input clock
frequency is allowed to change only within minimum and maximum operating frequen-
cies specified for the particular speed grade. During input clock frequency change, ODT
and CKE must be held at stable LOW levels. Once the input clock frequency is changed,
new stable clocks must be provided to the device before precharge power-down may be
exited, and DLL must be reset via EMR after precharge power-down exit. Depending on
the new clock frequency, an additional LM command might be required to appropriately
set the WR MR[11, 10, 9]. During the DLL relock period of 200 cycles, ODT must remain
off. After the DLL lock time, the DRAM is ready to operate with a new clock frequency.
Figure 54: Input Clock Frequency Change During Precharge Power-Down Mode
Notes: 1. If this command is a PRECHARGE (or if the device is already in the idle state), then the
power-down mode shown is precharge power-down, which is required prior to the clock
frequency change.
2. A minimum of 2 x tCK is required after entering precharge power-down prior to changing
clock frequencies.
3. Once the new clock frequency has changed and is stable, a minimum of 1 x tCK is required
prior to exiting precharge power-down.
4. Minimum CKE HIGH time is tCKE = 3 x tCK. Minimum CKE LOW time is tCKE = 3 x tCK. This
requires a minimum of three clock cycles of registration.
CK
CK#
COMMAND VALID1NOP
ADDR
CKE
DQ
DM
DQS, DQS#
NOP
tCK
Enter precharge
power-down mode Exit precharge
power-down mode
T0 T1 T3 Ta0T2
DON’T CARE
VALID
tCKE (MIN)
4
tCKE (MIN)
4
tXP
LM
DLL RESET
VALID
VALID
NOP
tCH tCL
Ta1 Ta2 Tb0Ta3
2 x tCK (MIN)
2
1 x tCK (MIN)
3
tCH tCL
tCK
ODT
200 x tCK
NOP
Ta4
PREVIOUS CLOCK FREQUENCY NEW CLOCK FREQUENCY
Frequency
change
High-Z
High-Z
Indicates a break in
time scale
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 72 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
RESET Function
RESET Function
(CKE LOW Anytime)
DDR2 SDRAM applications may go into a reset state anytime during normal operation.
If an application enters a reset condition, CKE is used to ensure the DDR2 SDRAM
device resumes normal operation after re-initializing. All data will be lost during a reset
condition; however, the DDR2 SDRAM device will continue to operate properly if the
following conditions outlined in this section are satisfied.
The reset condition defined here assumes all supply voltages (VDD, VDDQ, VDDL, and
VREF ) are stable and meet all DC specifications prior to, during, and after the RESET
operation. All other input pins of the DDR2 SDRAM device are a “Don’t Care” during
RESET with the exception of CKE.
If CKE asynchronously drops LOW during any valid operation (including a READ or
WRITE burst), the memory controller must satisfy the timing parameter tDELAY before
turning off the clocks. Stable clocks must exist at the CK, CK# inputs of the DRAM before
CKE is raised HIGH, at which time the normal initialization sequence must occur. See
“Initialization” on page 16. The DDR2 SDRAM device is now ready for normal operation
after the initialization sequence. Figure 55 on page 73 shows the proper sequence for a
RESET operation.
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 73 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
RESET Function
Figure 55: RESET Function
Notes: 1. Either NOP or DESELECT command may be applied.
2. PRE = PRECHARGE command.
3. DM represents DM for x4/x8 configuration and UDM, LDM for x16 configuration. DQS rep-
resents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, RDQS# for the appropriate configu-
ration (x4, x8, x16).
4. Initialization timing is shown in Figure 7 on page 16.
5. In certain cases where a READ cycle is interrupted, CKE going HIGH may result in the com-
pletion of the burst.
6. VDD, VDDL, VDDQ, VTT, and VREF must be valid at all times.
CKE
R
TT
BA0, BA1
High-Z
DM
3
DQS
3
High-Z
ADDRESS
A10
CK
CK#
tCL
COMMAND2NOP1PRE
ALL BANKS
Ta0
DON’T CARE TRANSITIONING DATA
tRPA
tCL
tCK
ODT
DQ
3
High-Z
T = 400ns (MIN)
Tb0
READ NOP1
T0 T1 T2
Col n
Bank a
tDELAY
6
D
OUT
D
OUT
READ NOP1
Col n
Bank b
D
OUT
High-Z
High-Z
Unknown RTT ON
System
RESET
T3 T4 T5
Start of normal
4
initialization
sequence
NOP1
Indicates a break in
time scale
5
tCKE (MIN)
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 74 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
ODT Timing
ODT Timing
Once a 12ns delay (tMOD) has been satisfied, and after the ODT function has been
enabled via the EMR LOAD MODE command, ODT can be accessed under two timing
categories. ODT will operate in either synchronous mode or asynchronous mode,
depending on the state of CKE. ODT can switch anytime except during self refresh mode
and a few clocks after being enabled via EMR, as shown in Figure 56 on page 75.
There are two timing categories for ODT—turn-on and turn-off. During active mode
(CKE HIGH) and fast-exit power-down mode (any row of any bank open, CKE LOW,
MR[12 = 0]), tAOND, tAON, tAOFD, and tAOF timing parameters are applied, as shown in
Figure 58 on page 76 and Table 12 on page 76.
During slow-exit power-down mode (any row of any bank open, CKE LOW, MR[12] = 1)
and precharge power-down mode (all banks/rows precharged and idle, CKE LOW),
tAONPD and tAOFPD timing parameters are applied, as shown in Figure 59 on page 77
and Table 13 on page 77.
ODT turn-off timing, prior to entering any power-down mode, is determined by the
parameter tANPD (MIN), as shown in Figure 60 on page 78. At state T2, the ODT HIGH
signal satisfies tANPD (MIN) prior to entering power-down mode at T5. When tANPD
(MIN) is satisfied, tAOFD and tAOF timing parameters apply. Figure 60 on page 78 also
shows the example where tANPD (MIN) is not satisfied since ODT HIGH does not occur
until state T3. When tANPD (MIN) is not satisfied, tAOFPD timing parameters apply.
ODT turn-on timing prior to entering any power-down mode is determined by the
parameter tANPD, as shown in Figure 61 on page 79. At state T2, the ODT HIGH signal
satisfies tANPD (MIN) prior to entering power-down mode at T5. When tANPD (MIN) is
satisfied, tAOND and tAON timing parameters apply. Figure 61 also shows the example
where tANPD (MIN) is not satisfied since ODT HIGH does not occur until state T3. When
tANPD (MIN) is not satisfied, tAONPD timing parameters apply.
ODT turn-off timing after exiting any power-down mode is determined by the parameter
tAXPD (MIN), as shown in Figure 62 on page 80. At state Ta1, the ODT LOW signal satis-
fies tAXPD (MIN) after exiting power-down mode at state T1. When tAXPD (MIN) is satis-
fied, tAOFD and tAOF timing parameters apply. Figure 62 also shows the example where
tAXPD (MIN) is not satisfied since ODT LOW occurs at state Ta0. When tAXPD (MIN) is
not satisfied, tAOFPD timing parameters apply.
ODT turn-on timing after exiting either slow-exit power-down mode or precharge
power-down mode is determined by the parameter tAXPD (MIN), as shown in Figure 63
on page 81. At state Ta1, the ODT HIGH signal satisfies tAXPD (MIN) after exiting power-
down mode at state T1. When tAXPD (MIN) is satisfied, tAOND and tAON timing param-
eters apply. Figure 63 also shows the example where tAXPD (MIN) is not satisfied since
ODT HIGH occurs at state Ta0. When tAXPD (MIN) is not satisfied, tAONPD timing
parameters apply.
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 75 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
ODT Timing
Figure 56: ODT Timing for Entering and Exiting Power-Down Mode
MRS Command to ODT Update Delay
During normal operation, the value of the effective termination resistance can be
changed with an EMRS set command. tMOD (MAX) updates the RTT setting.
Figure 57: Timing for MRS Command to ODT Update Delay
Notes: 1. LM command directed to mode register, which updates the information in EMR(1)[A6, A2],
i.e., RTT (nominal).
2. To prevent any impedance glitch on the channel, the following conditions must be met:
tAOFD must be met before issuing the LM command; ODT must remain LOW for the entire
duration of the tMOD window, until tMOD is met.
tANPD (3 tCKs)
1st CKE latched LOW
tAXPD (8 tCKs)
1st CKE latched HIGH
Synchronous
Applicable modes
Applicable timing parameters
SynchronousSynchronous or
Asynchronous
Any mode except
self refresh mode
Any mode except
self refresh mode
Active power-down fast (synchronous)
Active power-down slow (asynchronous)
Precharge power-down (asynchronous)
tAOND/tAOFD (synchronous)
tAONPD/tAOFPD (asynchronous)
tAOND/tAOFD tAOND/tAOFD
CKE
CK#
CK
ODT2
Internal
RTT Setting
EMRS1NOP NOPNOP NOP NOP
CMD
tAOFD tMOD
Old SettingUndefinedNew Setting
0ns
2
tIS
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 76 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
ODT Timing
Figure 58: ODT Timing for Active or Fast-Exit Power-Down Mode
Note: The half-clock of tAOFD’s 2.5 tCK assumes a 50/50 clock duty cycle. This half-clock value
must be derated by the amount of half-clock duty cycle error. For example, if the clock
duty cycle was 47/53, tAOFD would actually be 2.5 - 0.03, or 2.47, for tAOF (MIN) and 2.5 +
0.03, or 2.53, for tAOF (MAX).
Table 12: DDR2-400/533 ODT Timing for Active and Fast-Exit Power-Down Modes
Parameter Symbol Min Max Units
ODT turn-on delay tAOND 2 2 tCK
ODT turn-on tAON tAC (MIN) tAC (MAX) + 1,000 ps
ODT turn-off delay tAOFD 2.5 2.5 tCK
ODT turn-off tAOF tAC (MIN) tAC (MAX) + 600 ps
T1T0 T2 T3 T4 T5 T6
VALIDVALID VALID VALIDVALID VALID VALID
CK#
CK
CKE
tAOF (MAX)
ODT
R
TT
tAON (MIN)
tAON (MAX)
tAOND
ADDR
tAOFD
tAOF (MIN)
VALIDVALID VALID VALIDVALID VALID VALID
CMD
t
CH
t
CL
t
CK
DON’T CARE
R
TT
Unknown R
TT
On
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 77 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
ODT Timing
Figure 59: ODT Timing for Slow-Exit or Precharge Power-Down Modes
Table 13: DDR2-400/533 ODT Timing for Slow-Exit and Precharge Power-Down Modes
Parameter Symbol Min Max Units
ODT turn-on
(power-down mode)
tAONPD tAC (MIN) + 2,000 2 x tCK +tAC (MAX) +
1,000
ps
ODT turn-off
(power-down mode)
tAOFPD tAC (MIN) + 2,000 2.5 x tCK + tAC (MAX) +
1,000
ps
DON’T CARE
T1T0 T2 T3 T4 T5 T6
VALIDVALID VALID VALIDVALID VALID VALID
CK#
CK
CKE
ODT
R
TT
ADDR
VALIDVALID VALID VALIDVALID VALID VALID
CMD
tCHtCL
tCK
tAONPD (MIN)
tAONPD (MAX)
tAOFPD (MIN)
tAOFPD (MAX)
Transitioning R
TT
T7
VALID
VALID
R
TT
Unknown R
TT
On
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 78 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
ODT Timing
Figure 60: ODT Turn-off Timings when Entering Power-Down Mode
Note: The half-clock of tAOFD’s 2.5 tCK assumes a 50/50 clock duty cycle. This half-clock value
must be derated by the amount of half-clock duty cycle error. For example, if the clock
duty cycle was 47/53, tAOFD would actually be 2.5 - 0.03, or 2.47, for tAOF (MIN) and 2.5 +
0.03, or 2.53, for tAOF (MAX).
Table 14: DDR2-400/533 ODT Turn-off Timings when Entering Power-Down Mode
Parameter Symbol Min Max Units
ODT turn-off delay tAOFD 2.5 2.5 tCK
ODT turn-off tAOF tAC (MIN) tAC (MAX) + 600 ps
ODT turn-off
(power-down mode)
tAOFPD tAC (MIN) +
2,000
2.5 x tCK + tAC
(MAX) + 1,000
ps
ODT to power-down entry latency tANPD 3 tCK
T1T0 T2 T3 T4 T5 T6
NOPNOP NOP NOPNOP NOP NOP
CK#
CK
CKE
tANPD (MIN)
ODT
RTT
tAOF (MIN)
tAOF (MAX)
tAOFD
ODT
RTT
tAOFPD (MIN)
tAOFPD (MAX)
DON’T CARE
Transitioning RTT RTT Unknown RTT On
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 79 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
ODT Timing
Figure 61: ODT Turn-On Timing when Entering Power-Down Mode
Table 15: DDR2-400/533 ODT Turn-on Timing when Entering Power-Down Mode
Parameter Symbol Min Max Units
ODT turn-on delay tAOND 2 2 tCK
ODT turn-on tAON tAC (MIN) tAC (MAX) + 1,000 ps
ODT turn-on
(power-down mode)
tAONPD tAC (MIN) +
2,000
2 x tCK + tAC
(MAX) + 1,000
ps
ODT to power-down entry latency tANPD 3 tCK
T1T0 T2 T3 T4 T5 T6
NOPNOP NOP NOPNOP NOP NOP
CK#
CK
CKE
tANPD (MIN)
ODT
RTT
tAON (MIN)
tAON (MAX)
tAOND
ODT
RTT
tAONPD (MIN)
tAONPD (MAX)
DON’T CARE
Transitioning RTT RTT Unknown RTT On
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 80 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
ODT Timing
Figure 62: ODT Turn-Off Timing when Exiting Power-Down Mode
Note: The half-clock of tAOFD’s 2.5 tCK assumes a 50/50 clock duty cycle. This half-clock value
must be derated by the amount of half-clock duty cycle error. For example, if the clock
duty cycle was 47/53, tAOFD would actually be 2.5 - 0.03, or 2.47, for tAOF (MIN) and 2.5 +
0.03, or 2.53, fortAOF (MAX).
Table 16: DDR2-400/533 ODT Turn-off Timing when Exiting Power-Down Mode
Parameter Symbol Min Max Units
ODT turn-off delay tAOFD 2.5 2.5 tCK
ODT turn-off tAOF tAC (MIN) tAC (MAX) + 600 ps
ODT turn-off
(power-down mode)
tAOFPD tAC (MIN) +
2,000
2.5 x tCK + tAC
(MAX) + 1,000
ps
ODT to power-down exit latency tAXPD 8 tCK
T1T0 T2 T3 T4 Ta0 Ta1
NOPNOP NOP NOPNOP NOP NOP
CK#
CK
CKE
tAXPD (MIN)
ODT
RTT
tAOF (MAX)
ODT
RTT
tAOFPD (MIN)
tAOFPD (MAX)
COMMAND
tCKE (MIN)
Ta2 Ta3 Ta4 Ta5
NOPNOP NOP NOP
DON’T CARE
Transitioning RTT RTT Unknown RTT On
tAOF (MIN)
tAOFD
Indicates a break in
time scale
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 81 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
ODT Timing
Figure 63: ODT Turn-on Timing when Exiting Power-Down Mode
Table 17: DDR2-400/533 ODT Turn-On Timing when Exiting Power-Down Mode
Parameter Symbol Min Max Units
ODT turn-on delay tAOND 2 2 tCK
ODT turn-on tAON tAC (MIN) tAC (MAX) + 1,000 ps
ODT turn-on
(power-down mode)
tAONPD tAC (MIN) +
2,000
2 x tCK + tAC
(MAX) + 1,000
ps
ODT to power-down exit latency tAXPD 8 tCK
T1T0 T2 T3 T4 Ta0 Ta1
NOPNOP NOP NOPNOP NOP NOP
CK#
CK
CKE
tAXPD (MIN)
COMMAND
Ta2 Ta3 Ta4 Ta5
NOPNOP NOP NOP
ODT
RTT
tAON (MIN)
tAON (MAX)
tAOND
ODT
RTT
tAONPD (MIN)
tAONPD (MAX)
DON’T CARE
Transitioning RTT RTT Unknown RTT On Indicates a break in
time scale
tCKE (MIN)
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 82 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Absolute Maximum Ratings
Absolute Maximum Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
Notes: 1. VDD, VDDQ, and VDDL must be within 300mV of each other at all times.
2. VREF ≤ 0.6 x VDDQ; however, VREF may be ≥ VDDQ provided that VREF ≤ 300mV.
3. Voltage on any I/O may not exceed voltage on VDDQ.
Temperature and Thermal Impedance
It is imperative that the DDR2 SDRAM device’s temperature specifications, shown in
Table 18 on page 83, be maintained in order to ensure the junction temperature is in the
proper operating range to meet data sheet specifications. An important step in main-
taining the proper junction temperature is using the device’s thermal impedances
correctly. The thermal impedances are listed in Table 19 on page 83 for the applicable
and available die revision and packages.
Incorrectly using thermal impedances can produce significant errors. Read Micron
Technical Note TN-00-08, “Thermal Applications,” prior to using the thermal imped-
ances listed below. For designs that are expected to last several years and require the
flexibility to use several designs, consider using final target theta values, rather than
existing values, to account for larger thermal impedances.
The DDR2 SDRAM device’s safe junction temperature range can be maintained when
the TC specification is not exceeded. In applications where the device’s ambient temper-
ature is too high, use of forced air and/or heat sinks may be required in order to satisfy
the case temperature specifications.
Table 17: Absolute Maximum DC Ratings
Parameter Symbol Min Max Units Notes
VDD supply voltage relative to VSS VDD –1.0 2.3 V 1
VDDQ supply voltage relative to VSSQVDDQ –0.5 2.3 V 1, 2
VDDL supply voltage relative to VSSLVDDL–0.5 2.3 V 1
Voltage on any ball relative to VSS VIN, VOUT –0.5 2.3 V 3
Input leakage current; any input 0V ≤ VIN ≤ VDD; all other balls
not under test = 0V)
II–5 5 µA
Output leakage current; 0V
≤
V
OUT
≤
V
DD
Q; DQ and ODT disabled
IOZ –5 5 µA
VREF leakage current; VREF = Valid VREF level IVREF –2 2 µA
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 83 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Temperature and Thermal Impedance
Notes: 1. MAX storage case temperature; TSTG is measured in the center of the package, as shown in
Figure 64. This case temperature limit is allowed to be exceeded briefly during package
reflow, as noted in Micron technical note, TN-00-15, “Recommended Soldering Parame-
ters.”
2. MAX operating case temperature; TC is measured in the center of the package, as shown in
Figure 64.
3. Device functionality is not guaranteed if the device exceeds maximum TC during operation.
4. Both temperature specifications must be satisfied.
5. Operating ambient temperature surrounding the package.
Notes: 1. Thermal resistance data is based on a number of samples from multiple lots and should be
viewed as a typical number.
2. This is an estimate; simulated number and actual results could vary.
Figure 64: Example Temperature Test Point Location
Table 18: Temperature Limits
Parameter Symbol Min Max Units Notes
Storage temperature TSTG–55 100 °C 1
Operating temperature – commercial TC085°C2, 3
Operating temperature – industrial TC–40 95 °C 2, 3, 4
TAMB –40 85 °C 4, 5
Table 19: Thermal Impedance
Die Rev Package Substrate
θ JA (°C/W)
Airflow =
0m/s
θ JA (°C/W)
Airflow =
1m/s
θ JA (°C/W)
Airflow =
2m/s θ JB (°C/W) θ JC (°C/W)
B160-ball 2-layer 53.2 40.0 37.2 27.5 2.9
4-layer 37.4 30.9 27.7 24.2
84-ball 2-layer 50.2 36.8 32.1 24.5 3.1
4-layer 34.9 28.0 25.5 21.3
C160-ball 2-layer 56.9 43.6 38.5 30.6 3.8
4-layer 40.6 34.1 31.3 27.0
84-ball 2-layer 56.8 42.8 37.7 24.8 3.9
4-layer 40.3 33.2 30.4 23.5
Last shrink
target260-ball 2-layer 60.0 48.0 45.0 32.0 5.0
4-layer 42.0 36.0 34.0 29.0
84-ball 2-layer 59.0 45.0 40.0 27.0 5.2
4-layer 44.0 35.0 34.0 26.0
12.00
6.00
12.50
6.75
12mm x 12.5 mm “CC” FBGA
Test Point
10.00
5.00
12.50
6.75
10mm x 12.5 mm “BN” FBGA
Test Point
12.00
6.00
10.00
5.00
12mm x 10 mm “CB” FBGA
Test Point
10.00
5.00
10.00
5.00
10mm x 10mm “B6” FBGA
Test Point
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 84 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
AC and DC Operating Conditions
AC and DC Operating Conditions
Notes: 1. VDD and VDDQ must track each other. VDDQ must be ≤ VDD.
2. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the
DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed ±1
percent of the DC value. Peak-to-peak AC noise on VREF may not exceed ±2 percent of
VREF(DC). This measurement is to be taken at the nearest VREF bypass capacitor.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resis-
tors, is expected to be set equal to VREF, and must track variations in the DC level of VREF.
4. VDDQ tracks with VDD; VDDL tracks with VDD.
5. VSSQ = VSSL = VSS.
Notes: 1. RTT1(EFF) and RTT2(EFF) are determined by separately applying VIH(AC) and VIL(AC) to the ball
being tested, and then measuring current, I(VIH(AC)), and I(VIL(AC)), respectively.
2. Measure voltage (VM) at tested ball with no load.
3. IT device minimum values are derated by six percent when device operates between –40°C
and 0°C (TC).
Table 20: Recommended DC Operating Conditions (SSTL_18)
All voltages referenced to VSS
Parameter Symbol Min Nom Max Units Notes
Supply voltage VDD 1.7 1.8 1.9 V 1, 5
VDDL supply voltage VDDL 1.7 1.8 1.9 V 4, 5
I/O supply voltage VDDQ 1.7 1.8 1.9 V 4, 5
I/O reference voltage VREF(DC) 0.49 x VDDQ 0.50 x VDDQ0.51 X VDDQV 2
I/O termination voltage (system) VTT VREF(DC) - 40 VREF(DC)VREF(DC) + 40 mV 3
Table 21: ODT DC Electrical Characteristics
All voltages referenced to VSS
Parameter Symbol Min Nom Max Units Notes
RTT effective impedance value for 75Ω setting
EMR (A6, A2) = 0, 1
RTT1(EFF)60 75 90 Ω1, 3
RTT effective impedance value for 150Ω setting
EMR (A6, A2) = 1, 0
RTT2(EFF) 120 150 180 Ω1, 3
RTT effective impedance value for 50Ω setting
EMR (A6, A2) = 1, 1
RTT3(EFF)40 50 60 Ω1, 3
Deviation of VM with respect to VDDQ/2 ΔVM –6 6 % 2
RTT EFF() VIH AC()VIL AC()–
IV
IH AC()()IVIL AC()()–
-------------------------------------------------------------
=
ΔVM 2VM×
VDDQ
------------------1–
⎝⎠
⎛⎞
100×=
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 85 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Input Electrical Characteristics and Operating Conditions
Input Electrical Characteristics and Operating Conditions
Figure 65: Single-Ended Input Signal Levels
Note: Numbers in diagram reflect nominal values.
Table 22: Input DC Logic Levels
All voltages referenced to VSS
Parameter Symbol Min Max Units
Input HIGH (logic 1) voltage VIH(DC)VREF(DC) + 125 VDDQ + 300 mV
Input LOW (logic 0) voltage VIL(DC) –300 VREF(DC) - 125 mV
Table 23: Input AC Logic Levels
All voltages referenced to VSS
Parameter Symbol Min Max Units
Input HIGH (logic 1) voltage (-5E/-37E) VIH(AC)VREF(DC) + 250 – mV
Input HIGH (logic 1) voltage (-3/-3E/-25/-25E) VIH(AC)VREF(DC) + 200 – mV
Input LOW (logic 0) voltage (-5E/-37E) VIL(AC)–VREF(DC) - 250 mV
Input LOW (logic 0) voltage (-3/-3E/-25/-25E) VIL(AC)–VREF(DC) - 200 mV
650mV
775mV
864mV
882mV
900mV
918mV
936mV
1,025mV
1,150mV
VIL(AC)
VIL(DC)
VREF - AC Noise
VREF - DC Error
VREF + DC Error
VREF + AC Noise
VIH(DC)
VIH(AC)
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 86 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Input Electrical Characteristics and Operating Conditions
Notes: 1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK,
CK#, DQS, DQS#, LDQS, LDQS#, UDQS, UDQS#, and RDQS, RDQS#.
2. VID(DC) specifies the input differential voltage | VTR - VCP | required for switching, where VTR
is the true input (such as CK, DQS, LDQS, UDQS) level and VCP is the complementary input
(such as CK#, DQS#, LDQS#, UDQS#). The minimum value is equal to VIH(DC) - VIL(DC). Differ-
ential input signal levels are shown in Figure 66.
3. VID(AC) specifies the input differential voltage | VTR - VCP | required for switching, where VTR
is the true input (such as CK, DQS, LDQS, UDQS, RDQS) level and VCP is the complementary
input (such as CK#, DQS#, LDQS#, UDQS#, RDQS#). The minimum value is equal to VIH(AC) -
VIL(AC), as shown in Table 23 on page 85.
4. The typical value of VIX(AC) is expected to be about 0.5 x VDDQ of the transmitting device
and VIX(AC) is expected to track variations in VDDQ. VIX(AC) indicates the voltage at which
differential input signals must cross, as shown in Figure 66.
5. VMP(DC) specifies the input differential common mode voltage (VTR + VCP)/2 where VTR is
the true input (CK, DQS) level and VCP is the complementary input (CK#, DQS#). VMP(DC) is
expected to be approximately 0.5 x VDDQ.
Figure 66: Differential Input Signal Levels
Notes: 1. This provides a minimum of 850mV to a maximum of 950mV and is expected to be VDDQ/2.
2. TR and CP must cross in this region.
3. TR and CP must meet at least VID(DC) MIN when static and is centered around VMP(DC).
4. TR and CP must have a minimum 500mV peak-to-peak swing.
5. TR and CP may not be more positive than VDDQ + 0.3V or more negative than VSS - 0.3V.
6. For AC operation, all DC clock requirements must also be satisfied.
7. Numbers in diagram reflect nominal values (VDDQ = 1.8V).
8. TR represents the CK, DQS, RDQS, LDQS, and UDQS signals; CP represents CK#, DQS#,
RDQS#, LDQS#, and UDQS# signals.
Table 24: Differential Input Logic Levels
All voltages referenced to VSS
Parameter Symbol Min Max Units Notes
DC input signal voltage VIN(DC)–300 VDDQ + 300 mV 1
DC differential input voltage VID(DC) 250 VDDQ + 600 mV 2
AC differential input voltage VID(AC) 500 VDDQ + 600 mV 3
AC differential cross-point voltage VIX(AC) 0.50 x VDDQ - 175 0.50 x VDDQ + 175 mV 4
Input midpoint voltage VMP(DC) 850 950 mV 5
TR8
CP8
2.1V
@ VDDQ = 1.8V
2
3
VIN(DC) MAX5
VIN(DC) MIN5
4
- 0.30V
0.9V
1.075V
0.725 V
VID(AC)
VID(DC)
X
VMP(DC)1
VIX(AC)
X
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 87 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Input Electrical Characteristics and Operating Conditions
Notes: 1. All voltages referenced to VSS.
2. Input waveform setup timing (tISb) is referenced from the input signal crossing at the
VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under
test, as shown in Figure 75 on page 102.
3. Input waveform hold (tIHb) timing is referenced from the input signal crossing at the VIL(DC)
level for a rising signal and VIH(DC) for a falling signal applied to the device under test, as
shown in Figure 75 on page 102.
4. Input waveform setup timing (tDS) and hold timing (tDH) for single-ended data strobe is
referenced from the crossing of DQS, UDQS, or LDQS through the VREF level applied to the
device under test, as shown in Figure 77 on page 103.
5. Input waveform setup timing (tDS) and hold timing (tDH) when differential data strobe is
enabled is referenced from the cross-point of DQS/DQS#, UDQS/UDQS#, or LDQS/LDQS#, as
shown in Figure 76 on page 102.
6. Input waveform timing is referenced to the crossing point level (VIX) of two input signals
(VTR and VCP) applied to the device under test, where VTR is the “true” input signal and VCP
is the complementary input signal, as shown in Figure 78 on page 103.
7. See “Input Slew Rate Derating” on page 88.
8. The slew rate for single-ended inputs is measured from DC-level to AC-level, (VIL(DC) to
VIH(AC) on the rising edge and VIL(AC) to VIH(DC) on the falling edge. For signals referenced
to VREF, the valid intersection is where the “tangent” line intersects VREF, as shown in
Figures 68, 70, 72, and 74.
9. The slew rate for differentially ended inputs is measured from twice the DC-level to twice
the AC-level: 2 x VIL(DC) to 2 x VIH(AC) on the rising edge and 2 x VIL(AC) to 2 x VIH(DC) on the
falling edge). For example, the CK/CK# would be –250mV to +500mV for CK rising edge and
would be +250mV to –500mV for CK falling edge.
Table 25: AC Input Test Conditions
Parameter Symbol Min Max Units Notes
Input setup timing measurement reference level
BA1–BA0, A0–A12 A0–A13 (A12 x16), CS#, RAS#, CAS#,
WE#, ODT, DM, UDM, LDM, and CKE
VRS See Note 2 1, 2, 7,
8
Input hold timing measurement reference level
BA1–BA0, A0–A13 (A12 x16), CS#, RAS#, CAS#, WE#, ODT,
DM, UDM, LDM, and CKE
VRH See Note 3 1, 3, 7,
8
Input timing measurement reference level (single-ended)
DQS for x4, x8; UDQS, LDQS for x16
VREF(DC)VDDQ x 0.49 VDDQ x 0.51 V 1, 4, 7,
8
Input timing measurement reference level (differential)
CK, CK# for x4, x8, x16
DQS, DQS# for x4, x8; RDQS, RDQS# for x8
UDQS, UDQS#, LDQS, LDQS# for x16
VRD VIX(AC) V 1, 5, 6,
7, 9
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 88 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Input Slew Rate Derating
For all input signals, the total tIS (setup time) and tIH (hold time) required is calculated
by adding the data sheet tIS (base) and tIH (base) value to the ΔtIS and ΔtIH derating
value, respectively. Example: tIS (total setup time) = tIS (base) + ΔtIS.
tIS, the nominal slew rate for a rising signal, is defined as the slew rate between the last
crossing of VREF(DC) and the first crossing of VIH(AC) MIN. Setup nominal slew rate (tIS)
for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and
the first crossing of VIL(AC) MAX.
If the actual signal is always earlier than the nominal slew rate line between shaded
“VREF(DC) to AC region,” use nominal slew rate for derating value (Figure 67 on page 90).
If the actual signal is later than the nominal slew rate line anywhere between shaded
“VREF(DC) to AC region,” the slew rate of a tangent line to the actual signal from the AC
level to DC level is used for derating value (see Figure 68 on page 91).
tIH, the nominal slew rate for a rising signal, is defined as the slew rate between the last
crossing of VIL(DC) MAX and the first crossing of VREF(DC). tIH, nominal slew rate for a
falling signal, is defined as the slew rate between the last crossing of VIH(DC) MIN and
the first crossing of VREF(DC).
If the actual signal is always later than the nominal slew rate line between shaded “DC to
VREF(DC) region,” use nominal slew rate for derating value (Figure 69 on page 92).
If the actual signal is earlier than the nominal slew rate line anywhere between shaded
“DC to VREF(DC)) region,” the slew rate of a tangent line to the actual signal from the DC
level to VREF(DC) level is used for the derating value (Figure 70 on page 93).
Although the total setup time might be negative for slow slew rates (a valid input signal
will not have reached VIH(AC)/VIL(AC) at the time of the rising clock transition), a valid
input signal is still required to complete the transition and reach VIH(AC)/VIL(AC).
For slew rates in between the values listed in Tables 26 and 27, the derating values may
obtained by linear interpolation.
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 89 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Table 26: DDR2-400/533 Setup and Hold Time Derating Values (tIS and tIH)
Command/
Address Slew
Rate (V/ns)
CK, CK# Differential Slew Rate
Units
2.0 V/ns 1.5 V/ns 1.0 V/ns
ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH
4.0 +187 +94 +217 +124 +247 +154 ps
3.5 +179 +89 +209 +119 +239 +149 ps
3.0 +167 +83 +197 +113 +227 +143 ps
2.5 +150 +75 +180 +105 +210 +135 ps
2.0 +125 +45 +155 +75 +185 +105 ps
1.5 +83 +21 +113 +51 +143 +81 ps
1.0 0 0 +30 +30 +60 +60 ps
0.9 –11 –14 +19 +16 +49 +46 ps
0.8 –25 –31 +5 –1 +35 +29 ps
0.7 –43 –54 –13 –24 +17 +6 ps
0.6 –67 –83 –37 –53 –7 –23 ps
0.5 –110 –125 –80 –95 –50 –65 ps
0.4 –175 –188 –145 –158 –115 –128 ps
0.3 –285 –292 –255 –262 –225 –232 ps
0.25 –350 –375 –320 –345 –290 –315 ps
0.2 –525 –500 –495 –470 –465 –440 ps
0.15 –800 –708 –770 –678 –740 –648 ps
0.1 –1450 –1125 –1420 –1095 –1390 –1065 ps
Table 27: DDR2-667 Setup and Hold Time Derating Values (tIS and tIH)
Command/
Address Slew
Rate (V/ns)
CK, CK# Differential Slew Rate
Units
2.0 V/ns 1.5 V/ns 1.0 V/ns
ΔtIS ΔtIH ΔtIS ΔtIH ΔtIS ΔtIH
4.0 +150 +94 +180 +124 +210 +154 ps
3.5 +143 +89 +173 +119 +203 +149 ps
3.0 +133 +83 +163 +113 +193 +143 ps
2.5 +120 +75 +150 +105 +180 +135 ps
2.0 +100 +45 +160 +75 +160 +105 ps
1.5 +67 +21 +97 +51 +127 +81 ps
1.0 0 0 +30 +30 +60 +60 ps
0.9 –5 –14 +25 +16 +55 +46 ps
0.8 –13 –31 +17 –1 +47 +29 ps
0.7 –22 –54 +8 –24 +38 +6 ps
0.6 –34 –83 –4 –53 +36 –23 ps
0.5 –60 –125 –30 –95 0 –65 ps
0.4 –100 –188 –70 –158 –40 –128 ps
0.3 –168 –292 –138 –262 –108 –232 ps
0.25 –200 –375 –170 –345 –140 –315 ps
0.2 –325 –500 –295 –470 –265 –440 ps
0.15 –517 –708 –487 –678 –457 –648 ps
0.1 –1,000 –1,125 –970 –1,095 –940 –1,065 ps
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 90 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Figure 67: Nominal Slew Rate for tIS
VSS
CK#
CK
tIH
tIStIH
Setup slew rate
rising signal
Setup slew rate
falling signal
ΔTF ΔTR
Δ
TF
=
V
IH
(
AC
) MIN -
V
REF
(DC)
Δ
TR
=
VDDQ
tIS
Nominal
slew rate
V
REF
to AC
region
VREF to AC
region
V
REF
(DC)
- V
IL
(
AC
) MAX
VIH(DC) MIN
VREF(DC)
VIL(AC) MAX
VIL(DC) MAX
VIH(AC) MIN
Nominal
slew rate
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 91 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Figure 68: Tangent Line for tIS
Setup slew rate
rising signal
ΔTF ΔTR
tangent line [V
IH
(
AC
) MIN - V
REF
(
DC
)]
ΔTR
=
Tangent
line
Tangent
line
V
REF
to AC
region
Nominal
line
Nominal
line
tIH
tIStIH tIS
VSS
CK#
CK
VDDQ
VIH(AC) MIN
VIH(DC) MIN
VREF(DC)
VIL(DC) MAX
VIL(AC) MAX
V
REF
to AC
region
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 92 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Figure 69: Nominal Slew Rate for tIH
ΔTR ΔTF
Nominal
slew rate
DC to V
REF
region
tIH
tIStIS
VSS
CK#
CK
VDDQ
VIH(DC) MIN
VREF(DC)
VIL(AC) MAX
VIL(DC) MAX
VIH(AC) MIN
DC to V
REF
region
Nominal
slew rate
tIH
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 93 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Figure 70: Tangent Line for tIH
Tangent
line
DC to V
REF
region
tIH
tIStIS
VSS
VDDQ
VIH(DC) MIN
VREF(DC)
VIL(AC) MAX
VIL(DC) MAX
VIH(AC) MIN
DC to V
REF
region
Tangent
line
tIH
CK
CK#
Hold slew rate
falling signal
ΔTF
ΔTR
tangent line [VIH(DC) MIN - VREF(DC)]
ΔTF
=
Nominal line
Hold slew rate
rising signal
tangent line [VREF(DC) - VIL(DC) MAX]
ΔTR
=
Nominal
line
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 94 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Notes: 1. For all input signals, the total tDS and tDH required is calculated by adding the data sheet
value to the derating value listed in Table 28.
2. tDS nominal slew rate for a rising signal is defined as the slew rate between the last crossing
of VREF(DC) and the first crossing of VIH(AC) MIN. tDS nominal slew rate for a falling signal is
defined as the slew rate between the last crossing of VREF(DC) and the first crossing of
VIL(AC) MAX. If the actual signal is always earlier than the nominal slew rate line between
shaded “VREF(DC) to AC region,” use nominal slew rate for derating value (see Figure 71). If
the actual signal is later than the nominal slew rate line anywhere between shaded
“VREF(DC) to AC region,” the slew rate of a tangent line to the actual signal from the AC
level to DC level is used for derating value (see Figure 72).
3. tDH nominal slew rate for a rising signal is defined as the slew rate between the last cross-
ing of VIL(DC) MAX and the first crossing of VREF(DC). tDH nominal slew rate for a falling sig-
nal is defined as the slew rate between the last crossing of VIH(DC) MIN and the first crossing
of VREF (DC). If the actual signal is always later than the nominal slew rate line between
shaded “DC level to VREF(DC) region,” use nominal slew rate for derating value (see
Figure 73). If the actual signal is earlier than the nominal slew rate line anywhere between
shaded “DC to VREF(DC) region,” the slew rate of a tangent line to the actual signal from the
DC level to VREF(DC) level is used for derating value (see Figure 74).
4. Although the total setup time might be negative for slow slew rates (a valid input signal
will not have reached VIH(AC)/VIL(AC) at the time of the rising clock transition), a valid input
signal is still required to complete the transition and reach VIH(AC)/VIL(AC).
5. For slew rates between the values listed in this table, the derating values may be obtained
by linear interpolation.
6. These values are typically not subject to production test. They are verified by design and
characterization.
7. Single-ended DQS requires special derating. The values in Table 30 are the DQS single-
ended slew rate derating with DQS referenced at VREF and DQ referenced at the logic levels
tDSb and tDHb. Table 31 provides the VREF-based fully derated values for the DQ (tDSa and
tDHa) for DDR2-667. Table 32 provides the VREF-based fully derated values for the DQ (tDSa
and tDHa) for DDR2-533. Table 33 provides the VREF-based fully derated values for the DQ
(tDSa and tDHa) for DDR2-400.
Table 28: DDR2-400/533 tDS, tDH Derating Values with Differential Strobe
Notes: 1–7; all units in ps
DQ
Slew
Rate
(V/ns)
DQS, DQS# Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns
ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH
2.0125451254512545––––––––––––
1.5 8321832183219533 – – – – – – – – – –
1.0 00000012122424––––––––
0.9 – – –11 –14 –11 –14 1 –2 13 10 25 22 – – – – – –
0.8 – – – – –25 –31 –13 –19 –1 –7 11 5 23 17 – – – –
0.7 –––––––31–42–19–30–7–185–6176––
0.6 – – – – – – – – –43 –59 –31 –47 –19 –35 –7 –23 5 –11
0.5 – – – – – – – – – – –74 –89 –62 –77 –50 –65 –38 –53
0.4 – – – – – – – – – – – – –127 –140 –115 –128 –103 –116
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 95 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Notes: 1. For all input signals the total tDS and tDH required is calculated by adding the data sheet
value to the derating value listed in Table 29.
2. tDS nominal slew rate for a rising signal is defined as the slew rate between the last crossing
of VREF(DC) and the first crossing of VIH(AC) MIN. tDS nominal slew rate for a falling signal is
defined as the slew rate between the last crossing of VREF(DC) and the first crossing of
VIL(AC) MAX. If the actual signal is always earlier than the nominal slew rate line between
shaded “VREF(DC) to AC region,” use nominal slew rate for derating value (see Figure 71). If
the actual signal is later than the nominal slew rate line anywhere between shaded
“VREF(DC) to AC region,” the slew rate of a tangent line to the actual signal from the AC
level to DC level is used for derating value (see Figure 72).
3. tDH nominal slew rate for a rising signal is defined as the slew rate between the last
crossing of VIL(DC) MAX and the first crossing of VREF(DC). tDH nominal slew rate for a falling
signal is defined as the slew rate between the last crossing of VIH(DC) MIN and the first
crossing of VREF (DC). If the actual signal is always later than the nominal slew rate line
between shaded “DC level to VREF(DC) region,” use nominal slew rate for derating value
(see Figure 73). If the actual signal is earlier than the nominal slew rate line anywhere
between shaded “DC to VREF(DC) region,” the slew rate of a tangent line to the actual signal
from the DC level to VREF(DC) level is used for derating value (see Figure 74).
4. Although the total setup time might be negative for slow slew rates (a valid input signal
will not have reached VIH(AC)/VIL(AC) at the time of the rising clock transition), a valid input
signal is still required to complete the transition and reach VIH(AC)/VIL(AC).
5. For slew rates between the values listed in this table, the derating values may be obtained
by linear interpolation.
6. These values are typically not subject to production test. They are verified by design and
characterization.
7. Single-ended DQS requires special derating. The values in Table 30 are the DQS single-
ended slew rate derating with DQS referenced at VREF and DQ referenced at the logic levels
tDSb and tDHb. Table 31 provides the VREF-based fully derated values for the DQ (tDSa and
tDHa) for DDR2-667. Table 32 provides the VREF-based fully derated values for the DQ (tDSa
and tDHa) for DDR2-533. Table 33 provides the VREF-based fully derated values for the DQ
(tDSa and tDHa) for DDR2-400.
Table 29: DDR2-667 tDS, tDH Derating Values with Differential Strobe
Notes: 1–7; all units in ps
DQ
Slew
Rate
(V/ns)
DQS, DQS# Differential Slew Rate
2.8 V/ns 2.4 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns
ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH
2.0 100 63 100 63 100 63 112 75 124 87 136 99 148 111 160 123 172 135
1.5 67 42 67 42 67 42 79 54 91 66 103 78 115 90 127 102 139 114
1.0 0 0 0 0 0 0 121224243636484860607272
0.9 –5–14–5–14–5–147 –219103122433455466758
0.8 –13 –31 –13 –31 –13 –31 –1 –19 11 –7 23 5 35 17 47 29 59 41
0.7 –22 –54 –22 –54 –22 –54 –10 –42 2 –30 14 –18 26 –6 38 6 50 18
0.6 –34 –83 –34 –83 –34 –83 –22 –71 –10 –59 2 –47 14 –35 26 –23 38 –11
0.5 –60 –125 –60 –125 –60 –125 –48 –113 –36 –101 –24 –89 –12 –77 0 –65 12 –53
0.4 –100 –188 –100 –188 –100 –188 –88 –176 –76 –164 –64 –152 –52 –140 –40 –128 –28 –116
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 96 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Notes: 1. Derating values, to be used with base tDSb- and tDHb-specified values.
Table 30: Single-Ended DQS Slew Rate Derating Values Using tDSb and tDHb
Reference points indicated in bold
DQ
(V/ns)
DQS Single-Ended Slew Rate Derated (at VREF)
2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns 0.6 V/ns 0.4V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
2 130 53 130 53 130 53 130 53 130 53 145 48 155 45 165 41 175 38
1.59732973297329732973211227122241322014217
1 30–1030–1030–1030–1030–1045 –15 55 –18 65 –22 75 –25
0.9 25 –24 25 –24 25 –24 25 –24 25 –24 40 –29 50 –32 60 –36 70 –39
0.8 17 –41 17 –41 17 –41 17 –41 17 –41 32 –46 42 –49 52 –53 61 –56
0.7 5 –64 5 –64 5 –64 5 –64 5 –64 20 –69 30 –72 40 –75 50 –79
0.6 –7 –93 –7 –93 –7 –93 –7 –93 –7 –93 8 –98 18 –102 28 –105 38 –108
0.5 –28 –135 –28 –135 –28 –135 –28 –135 –28 –135 –13 –140 –3 –143 7 –147 17 –150
0.4 –78 –198 –78 –198 –78 –198 –78 –198 –78 –198 –63 –203 –53 –206 –43 –210 –33 –213
Table 31: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-667
Reference points indicated in bold
DQ
(V/ns)
DQS Single-Ended Slew Rate Derated (at VREF)
2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns 0.6 V/ns 0.4V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
2 330 291 330 291 330 291 330 291 330 291 345 286 355 282 365 29 375 276
1.5 330 290 330 290 330 290 330 290 330 290 345 285 355 282 365 279 375 275
1 330 290 330 290 330 290 330 290 330 290 345 285 355 282 365 278 375 275
0.9 347 290 347 290 347 290 347 290 347 290 362 285 372 282 382 278 392 275
0.8 367 290 367 290 367 290 367 290 367 290 382 285 392 282 402 278 412 275
0.7 391 290 391 290 391 290 391 290 391 290 406 285 416 281 426 278 436 275
0.6 426 290 426 290 426 290 426 290 426 290 441 285 451 282 461 278 471 275
0.5 472 290 472 290 472 290 472 290 472 290 487 285 497 282 507 278 517 275
0.4 522 289 522 289 522 289 522 289 522 289 537 284 547 281 557 278 567 274
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 97 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Table 32: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-533
Reference points indicated in bold
DQ
(V/ns)
DQS Single-Ended Slew Rate Derated (at VREF)
2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns 0.6 V/ns 0.4V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
2 355 341 355 341 355 341 355 341 355 341 370 336 380 332 390 329 400 326
1.5 364 340 364 340 364 340 364 340 364 340 379 335 389 332 399 329 409 325
1 380 340 380 340 380 340 380 340 380 340 395 335 405 332 415 328 425 325
0.9 402 340 402 340 402 340 402 340 402 340 417 335 427 332 437 328 447 325
0.8 429 340 429 340 429 340 429 340 429 340 444 335 454 332 464 328 474 325
0.7 463 340 463 340 463 340 463 340 463 340 478 335 488 331 498 328 508 325
0.6 510 340 510 340 510 340 510 340 510 340 525 335 535 332 545 328 555 325
0.5 572 340 572 340 572 340 572 340 572 340 587 335 597 332 607 328 617 325
0.4 647 339 647 339 647 339 647 339 647 339 662 334 672 331 682 328 692 324
Table 33: Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-400
Reference points indicated in bold
DQ
(V/ns)
DQS Single-Ended Slew Rate Derated (at VREF)
2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns 0.6 V/ns 0.4V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
2 405 391 405 391 405 391 405 391 405 391 420 386 430 382 440 379 450 376
1.5 414 390 414 390 414 390 414 390 414 390 429 385 439 382 449 379 459 375
1 430 390 430 390 430 390 430 390 430 390 445 385 455 382 465 378 475 375
0.9 452 390 452 390 452 390 452 390 452 390 467 385 477 382 487 378 497 375
0.8 479 390 479 390 479 390 479 390 479 390 494 385 504 382 514 378 524 375
0.7 513 390 513 390 513 390 513 390 513 390 528 385 538 381 548 378 558 375
0.6 560 390 560 390 560 390 560 390 560 390 575 385 585 382 595 378 605 375
0.5 622 390 622 390 622 390 622 390 622 390 637 385 647 382 657 378 667 375
0.4 697 389 697 389 697 389 697 389 697 389 712 384 722 381 732 378 742 374
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 98 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Figure 71: Nominal Slew Rate for tDS
Notes: 1. DQS, DQS# signals must be monotonic between VIL(DC) MAX and VIH(DC) MIN.
V
REF
to AC
region
V
REF
to AC
region
Setup slew rate
rising signal
Setup slew rate
falling signal
Δ
TF
Δ
TR
VREF(DC)
- V
IL
(
AC
) MAX
ΔTF
=
V
IH
(
AC
) MIN -
VREF(DC)
ΔTR
=
Nominal
slew rate
VSS
DQS#
1
DQS
1
VDDQ
VIH(DC) MIN
VREF(DC)
VIL(AC) MAX
VIL(DC) MAX
VIH(AC) MIN
tDH
tDS
Nominal
slew rate
tDH
tDS
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 99 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Figure 72: Tangent Line for tDS
Notes: 1. DQS, DQS# signals must be monotonic between VIL(DC) MAX and VIH(DC) MIN.
Δ
TF
Δ
TR
Setup Slew Rate
Rising Signal
Setup Slew Rate
Falling Signal
tangent line [V
REF
(
DC
) - V
IL
(
AC
) MAX]
ΔTF
=tangent line [V
IH
(
AC
) MIN - V
REF
(
DC
)]
ΔTR
=
tDH
tDS
tDH
tDS
VSS
DQS#
1
DQS
1
VDDQ
VIH(DC) MIN
VREF(DC)
VIL(AC) MAX
VIL(DC) MAX
VIH(AC) MIN
Nominal line
Tangent line
Nominal
line
Tangent line
V
REF
to AC
region
V
REF
to AC
region
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 100 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Figure 73: Nominal Slew Rate for tDH
Notes: 1. DQS, DQS# signals must be monotonic between VIL(DC) MAX and VIH(DC) MIN.
Hold slew rate
falling signal
Hold slew rate
rising signal
VREF(DC) -
V
IL
(
DC
) MAX
ΔTR
=
V
IH
(
DC
) MIN -
VREF(DC)
ΔTF
=
ΔTR ΔTF
Nominal
slew rate
DC to V
REF
region
tIH
tIStIS
VSS
DQS#
1
DQS
1
VDDQ
VIH(DC) MIN
VREF(DC)
VIL(AC) MAX
VIL(DC) MAX
VIH(AC) MIN
DC to V
REF
region
Nominal
slew rate
tIH
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 101 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Figure 74: Tangent Line for tDH
Notes: 1. DQS, DQS# signals must be monotonic between VIL(DC) MAX and VIH(DC) MIN.
Tangent
line
DC to V
REF
region
tIH
tIStIS
VSS
VDDQ
VIH(DC) MIN
VREF(DC)
VIL(AC) MAX
VIL(DC) MAX
VIH(AC) MIN
DC to V
REF
region
Tangent
line
tIH
DQS
1
DQS#
1
Hold Slew Rate
Falling Signal
ΔTF
ΔTR
tangent line [VIH(DC) MIN - VREF(DC)]
ΔTF
=
Nominal line
Hold Slew Rate
Rising Signal
tangent line [VREF(DC) - VIL(DC) MAX]
ΔTR
=
Nominal
line
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 102 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Figure 75: AC Input Test Signal Waveform Command/Address Balls
Figure 76: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential)
VREF(DC)
VIL(DC) MAX
VIL(AC) MAX
VSSQ
VIH(DC) MIN
VIH(AC) MIN
VDDQ
VSWING (MAX)
tIS
a
Logic Levels
VREF Levels
tIH
a
tIS
a
tIH
a
tIS
b
tIH
b
tIS
b
tIH
b
CK#
CK
VSWING (MAX)
DQS#
DQS
tDSatDHatDSatDHa
tDSbtDHbtDSbtDHb
Logic Levels
VREF Levels
VREF(DC)
VIL(DC) MAX
VIL(AC) MAX
VSSQ
VIH(DC) MIN
VIH(AC) MIN
VDDQ
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 103 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Figure 77: AC Input Test Signal Waveform for Data with DQS (single-ended)
Figure 78: AC Input Test Signal Waveform (differential)
VSWING (MAX)
DQS
VREF
VREF(DC)
VIL(DC) MAX
VIL(AC) MAX
VSSQ
VIH(DC) MIN
VIH(AC) MIN
VDDQ
Logic Levels
VREF LevelsVREF Levels
tDSatDHatDSatDHa
tDSbtDHbtDSbtDHb
VTR
VSWING
VCP
VDDQ
VSSQ
VIX
Crossing Point
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 104 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Power and Ground Clamp Characteristics
Power and Ground Clamp Characteristics
Power and ground clamps are provided on the following input-only balls: BA1–BA0, A0–
A13 (A12 x16), CS#, RAS#, CAS#, WE#, ODT, and CKE.
Figure 79: Input Clamp Characteristics
Table 34: Input Clamp Characteristics
Voltage Across Clamp
(V)
Minimum Power Clamp
Current (mA)
Minimum Ground Clamp
Current (mA)
0.0 0.0 0.0
0.1 0.0 0.0
0.2 0.0 0.0
0.3 0.0 0.0
0.4 0.0 0.0
0.5 0.0 0.0
0.6 0.0 0.0
0.7 0.0 0.0
0.8 0.1 0.1
0.9 1.0 1.0
1.0 2.5 2.5
1.1 4.7 4.7
1.2 6.8 6.8
1.3 9.1 9.1
1.4 11.0 11.0
1.5 13.5 13.5
1.6 16.0 16.0
1.7 18.2 18.2
1.8 21.0 21.0
Voltage Across Clamp (V)
Minimum Clamp Current (mA)
25.0
20.0
15.0
10.0
5.0
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 105 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
AC Overshoot/Undershoot Specification
AC Overshoot/Undershoot Specification
Some revisions will support the 0.9V maximum average amplitude instead of the 0.5V
maximum average amplitude that is shown in Table 35 and Table 36.
Figure 80: Overshoot
Figure 81: Undershoot
Table 35: Address and Control Balls
Applies to BA1–BA0, A0–A13 (A12 x16), CS#, RAS#, CAS#, WE#, CKE, ODT
Parameter
Specification
-5E -37E -3/-3E -25/-25E
Maximum peak amplitude allowed for overshoot area (see Figure 80) 0.50V 0.50V 0.50V 0.50V
Maximum peak amplitude allowed for undershoot area (see Figure 81) 0.50V 0.50V 0.50V 0.50V
Maximum overshoot area above VDD (see Figure 80) 1.33 Vns 1.00 Vns 0.80 Vns 0.66 Vns
Maximum undershoot area below VSS (see Figure 81) 1.33 Vns 1.00 Vns 0.80 Vns 0.66 Vns
Table 36: Clock, Data, Strobe, and Mask Balls
Applies to DQ, DQS, DQS#, RDQS, RDQS#, UDQS, UDQS#, LDQS, LDQS#, DM, UDM, LDM
Parameter
Specification
-5E -37E -3/-3E -25/-25E
Maximum peak amplitude allowed for overshoot area (see Figure 80) 0.50V 0.50V 0.50V 0.50V
Maximum peak amplitude allowed for undershoot area (see Figure 81) 0.50V 0.50V 0.50V 0.50V
Maximum overshoot area above VDDQ (see Figure 80) 0.38 Vns 0.28 Vns 0.23 Vns 0.19 Vns
Maximum undershoot area below VSSQ (see Figure 81) 0.38 Vns 0.28 Vns 0.23 Vns 0.19 Vns
Overshoot Area
Maximum Amplitude
VSS/VSSQ
Volts (V
)
Time (ns)
VDD/VDDQ
Undershoot Area
Maximum Amplitude
VSS/VSSQ
Volts (V)
Time (ns)
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 106 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Output Electrical Characteristics and Operating Conditions
Output Electrical Characteristics and Operating Conditions
Notes: 1. The typical value of VOX(AC) is expected to be about 0.5 x VDDQ of the transmitting device
and VOX(AC) is expected to track variations in VDDQ. VOX(AC) indicates the voltage at which
differential output signals must cross.
Figure 82: Differential Output Signal Levels
Table 37: Differential AC Output Parameters
Parameter Symbol Min Max Units Notes
AC Differential Cross-Point Voltage VOX(AC) 0.50 x VDDQ - 125 0.50 x VDDQ + 125 mV 1
AC Differential Voltage Swing VSWING1.0 mV
VTR
VSWING
VCP
VDDQ
VSSQ
VOX
Crossing Point
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 107 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Output Electrical Characteristics and Operating Conditions
Notes: 1. For IOH(DC); VDDQ = 1.7V, VOUT = 1,420mV. (VOUT - VDDQ)/IOH must be less than 21Ω for val-
ues of VOUT between VDDQ and VDDQ - 280mV.
2. For IOL(DC); VDDQ = 1.7V, VOUT = 280mV. VOUT/IOL must be less than 21Ω for values of VOUT
between 0V and 280mV.
3. The DC value of VREF applied to the receiving device is set to VTT.
4. The values of IOH(DC) and IOL(DC) are based on the conditions given in Notes 1 and 2. They
are used to test device drive current capability to ensure VIH (MIN) plus a noise margin and
VIL (MAX) minus a noise margin are delivered to an SSTL_18 receiver. The actual current val-
ues are derived by shifting the desired driver operating point (see output IV curves) along a
21Ω load line to define a convenient driver current for measurement.
Notes: 1. Absolute specifications: 0°C ≤ TC ≤ +85°C; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V.
2. Impedance measurement conditions for output source DC current: VDDQ = 1.7V; VOUT =
1,420mV; (VOUT - VDDQ)/IOH must be less than 23.4Ω for values of VOUT between VDDQ and
VDDQ - 280mV. Impedance measurement condition for output sink DC current: VDDQ = 1.7V;
VOUT = 280mV; VOUT/IOL must be less than 23.4Ω for values of VOUT between 0V and 280mV.
3. Mismatch is absolute value between pull-up and pull-down; both are measured at same
temperature and voltage.
4. Output slew rate for falling and rising edges is measured between VTT - 250mV and VTT +
250mV for single-ended signals. For differential signals (DQS - DQS#), output slew rate is
measured between DQS - DQS# = –500mV and DQS# - DQS = +500mV. Output slew rate is
guaranteed by design, but is not necessarily tested on each device.
5. The absolute value of the slew rate as measured from VIL(DC) MAX to VIH(DC) MIN is equal to
or greater than the slew rate as measured from VIL(AC) MAX to VIH(AC) MIN. This is guaran-
teed by design and characterization.
6. IT devices require an additional 0.4 V/ns in the MAX limit when TC is between –40°C and
0°C.
Figure 83: Output Slew Rate Load
Table 38: Output DC Current Drive
Parameter Symbol Value Units Notes
Output minimum source DC current IOH –13.4 mA 1, 2, 4
Output minimum sink DC current IOL 13.4 mA 2, 3, 4
Table 39: Output Characteristics
Parameter Min Nom Max Units Notes
Output impedance See “Full Strength Pull-Down Driver
Characteristics” on page 108
Ω1, 2
Pull-up and Pull-down mismatch 04
Ω1, 2, 3
Output slew rate 1.5 5 V/ns 1, 4, 5, 6
Output
(VOUT)
Reference
Point
25Ω
VTT = VDDQ/2
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 108 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Full Strength Pull-Down Driver Characteristics
Full Strength Pull-Down Driver Characteristics
Figure 84: Full Strength Pull-Down Characteristics
Table 40: Full Strength Pull-Down Current (mA)
Voltage (V) Minimum Nominal Maximum
0.0 0.00 0.00 0.00
0.1 4.3 5.63 7.95
0.2 8.6 11.3 15.90
0.3 12.9 16.52 23.85
0.4 16.9 22.19 31.80
0.5 20.4 27.59 39.75
0.6 23.28 32.39 47.70
0.7 25.44 36.45 55.55
0.8 26.79 40.38 62.95
0.9 27.67 44.01 69.55
1.0 28.38 47.01 75.35
1.1 28.96 49.63 80.35
1.2 29.46 51.71 84.55
1.3 29.90 53.32 87.95
1.4 30.29 54.9 90.70
1.5 30.65 56.03 93.00
1.6 30.98 57.07 95.05
1.7 31.31 58.16 97.05
1.8 31.64 59.27 99.05
1.9 31.96 60.35 101.05
Pull-down Characteristics
0.00
20.00
40.00
60.00
80.00
100.00
120.00
0.0 0.5 1.0 1.5
VOUT(V)
IOUT (mA)
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 109 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Full Strength Pull-Up Driver Characteristics
Full Strength Pull-Up Driver Characteristics
Figure 85: Full Strength Pull-up Characteristics
Table 41: Full Strength Pull-Up Current (mA)
Voltage (V) Minimum Nominal Maximum
0.0 0.00 0.00 0.00
0.1 –4.3 –5.63 –7.95
0.2 –8.6 –11.3 –15.90
0.3 –12.9 –16.52 –23.85
0.4 –16.9 –22.19 –31.80
0.5 –20.4 –27.59 –39.75
0.6 –23.28 –32.39 –47.70
0.7 –25.44 –36.45 –55.55
0.8 –26.79 –40.38 –62.95
0.9 –27.67 –44.01 –69.55
1.0 –28.38 –47.01 –75.35
1.1 –28.96 –49.63 –80.35
1.2 –29.46 –51.71 –84.55
1.3 –29.90 –53.32 –87.95
1.4 –30.29 –54.90 –90.70
1.5 –30.65 –56.03 –93.00
1.6 –30.98 –57.07 –95.05
1.7 –31.31 –58.16 –97.05
1.8 –31.64 –59.27 –99.05
1.9 –31.96 –60.35 –101.05
Pull-up Characteristics
-120.0
-100.0
-80.0
-60.0
-40.0
-20.0
0.0
0.0 0.5 1.0 1.5
VDDQ - VOUT (V)
IOUT (mA)
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 110 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Reduced Strength Pull-Down Driver Characteristics
Reduced Strength Pull-Down Driver Characteristics
Figure 86: Reduced Strength Pull-Down Characteristics
Table 42: Reduced Strength Pull-Down Current (mA)
Voltage (V) Minimum Nominal Maximum
0.0 0.000.000.00
0.1 1.722.984.77
0.2 3.445.999.54
0.3 5.16 8.75 14.31
0.4 6.76 11.76 19.08
0.5 8.16 14.62 23.85
0.6 9.31 17.17 28.62
0.7 10.18 19.32 33.33
0.8 10.72 21.40 37.77
0.9 11.07 23.32 41.73
1.0 11.35 24.92 45.21
1.1 11.58 26.30 48.21
1.2 11.78 27.41 50.73
1.3 11.96 28.26 52.77
1.4 12.12 29.10 54.42
1.5 12.26 29.70 55.80
1.6 12.39 30.25 57.03
1.7 12.52 30.82 58.23
1.8 12.66 31.41 59.43
1.9 12.78 31.98 60.63
Pull-down Characteristics
0.00
10.00
20.00
30.00
40.00
50.00
60.00
70.00
0.0 0.5 1.0 1.5
VOUT (V)
IOUT (mA)
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 111 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Reduced Strength Pull-Up Driver Characteristics
Reduced Strength Pull-Up Driver Characteristics
Figure 87: Reduced Strength Pull-up Characteristics
Table 43: Reduced Strength Pull-Up Current (mA)
Voltage (V) Minimum Nominal Maximum
0.0 0.00 0.00 0.00
0.1 –1.72 –2.98 –4.77
0.2 –3.44 –5.99 –9.54
0.3 –5.16 –8.75 –14.31
0.4 –6.76 –11.76 –19.08
0.5 –8.16 –14.62 –23.85
0.6 –9.31 –17.17 –28.62
0.7 –10.18 –19.32 –33.33
0.8 –10.72 –21.40 –37.77
0.9 –11.07 –23.32 –41.73
1.0 –11.35 –24.92 –45.21
1.1 –11.58 –26.30 –48.21
1.2 –11.78 –27.41 –50.73
1.3 –11.96 –28.26 –52.77
1.4 –12.12 –29.10 –54.42
1.5 –12.26 –29.69 –55.8
1.6 –12.39 –30.25 –57.03
1.7 –12.52 –30.82 –58.23
1.8 –12.66 –31.42 –59.43
1.9 –12.78 –31.98 –60.63
Pull-up Characteristics
-70.0
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
0.0 0.5 1.0 1.5
VDDQ - VOUT (V)
IOUT
(mA)
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 112 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
FBGA Package Capacitance
FBGA Package Capacitance
Notes: 1. This parameter is sampled. VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V, VREF = VSS, f = 100 MHz,
TC = 25°C, VOUT(DC) = VDDQ/2, VOUT (peak-to-peak) = 0.1V. DM input is grouped with I/O
balls, reflecting the fact that they are matched in loading.
2. The input capacitance per ball group will not differ by more than this maximum amount for
any given device.
3. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum
amount for any given device.
4. Reduce MAX limit by 0.5pF for -3/-3E/-25/-25E speed devices.
5. Reduce MAX limit by 0.25pF for -3/-3E/-25/-25E speed devices.
Table 44: Input Capacitance
Parameter Symbol Min Max Units Notes
Input capacitance: CK, CK# CCK 1.0 2.0 pF 1
Delta input capacitance: CK, CK# CDCK – 0.25 pF 2
Input capacitance: BA1–BA0, A0–A13 (A12 x16), CS#,
RAS#, CAS#, WE#, CKE, ODT
CI 1.0 2.0 pF 1
Delta input capacitance: BA1–BA0, A0–A13 (A12
x16), CS#, RAS#, CAS#, WE#, CKE, ODT
CDI – 0.25 pF 2
Input/Output capacitance: DQs, DQS, DM, NF CIO 2.5 4.0 pF 1, 4
Delta input/output capacitance: DQs, DQS, DM, NF CDIO – 0.5 pF 3
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 113 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
I
DD
Specifications and Conditions
IDD Specifications and Conditions
Table 45: DDR2 IDD Specifications and Conditions
Notes: 1–7; notes appear on page 114
Parameter/Condition Sym Config -25E -25 -3E -3 -37E -5E Units
Operating one bank active-precharge current:
tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are
switching
IDD0
x4, x8 100 100 90 90 80 80
mA
x16 135 135 120 120 110 110
Operating one bank active-read-precharge
current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK
= tCK (IDD), tRC = tRC (Idd), tRAS = tRAS MIN (IDD),
tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between
valid commands; Address bus inputs are switching;
Data pattern is same as IDD4W
IDD1
x4, x8 115 115 105 105 95 90
mA
x16 165 165 150 150 135 130
Precharge power-down current: All banks idle;
tCK = tCK (IDD); CKE is LOW; Other control and
address bus inputs are stable; Data bus inputs are
floating
IDD2P x4, x8, x16 7 7 7 7 7 7 mA
Precharge quiet standby current: All banks idle;
tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other
control and address bus inputs are stable; Data bus
inputs are floating
IDD2Q x4, x8 50 50 45 45 40 35
mA
x16 656555554540
Precharge standby current: All banks idle; tCK =
tCK (IDD); CKE is HIGH, CS# is HIGH; Other control and
address bus inputs are switching; Data bus inputs are
switching
IDD2N x4, x8 55 55 50 50 45 40
mA
x16 707060605045
Active power-down current: All banks open; tCK =
tCK (IDD); CKE is LOW; Other control and address bus
inputs are stable; Data bus inputs are floating IDD3P
Fast PDN exit
MR[12] = 0 40 40 35 35 30 25
mA
Slow PDN exit
MR[12] = 1 12 12 12 12 12 12
Active standby current: All banks open; tCK = tCK
(IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is
HIGH, CS# is HIGH between valid commands; Other
control and address bus inputs are switching; Data
bus inputs are switching
IDD3N
x4, x8 70 70 65 65 55 45
mA
x16 757570706050
Operating burst write current: All banks open,
continuous burst writes; BL = 4, CL = CL (IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are
switching
I
DD
4W
x4, x8 195 195 170 170 140 115
mA
x16 295 295 250 250 205 160
Operating burst read current: All banks open,
continuous burst reads, IOUT = 0mA; BL = 4, CL = CL
(IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),
tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between
valid commands; Address bus inputs are switching;
Data bus inputs are switching
IDD4R
x4, x8 205 205 180 180 145 115
mA
x16 275 275 235 235 195 155
Burst refresh current: tCK = tCK (IDD); refresh
command at every tRFC (IDD) interval; CKE is HIGH,
CS# is HIGH between valid commands; Other control
and address bus inputs are switching; Data bus inputs
are switching
IDD5
x4, x8 230 230 180 180 170 165
mA
x16 230 230 185 185 175 170
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 114 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
I
DD
Specifications and Conditions
Notes: 1. IDD specifications are tested after the device is properly initialized. 0°C ≤ TC ≤ +85°C.
VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V, VDDL = +1.8V ±0.1V, VREF = VDDQ/2.
–37V VDDQ = +1.9V ±0.1V, VDDL = +1.9V ±0.1.
2. Input slew rate is specified by AC parametric test conditions (Table 46 on page 115).
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and UDQS#.
IDD values must be met with all combinations of EMR bits 10 and 11.
5. Definitions for IDD conditions:
6. IDD1, IDD4R, and IDD7 require A12 in EMR1 to be enabled during testing.
7. The following IDDs must be derated (IDD limits increase) on IT-option devices when operated
outside of the range 0°C ≤ TC ≤ 85°C:
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V;
Other control and address bus inputs are floating;
Data bus inputs are floating
IDD6
x4, x8, x16
777777
mA
IDD6L 333333
Operating bank interleave read current: All bank
interleaving reads, IOUT = 0mA; BL = 4, CL = CL (IDD),
AL = tRCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC =
tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is
HIGH, CS# is HIGH between valid commands; Address
bus inputs are stable during deselects; Data bus
inputs are switching (see Table 47 on page 115 for
details)
IDD7
x4, x8 300 300 240 240 225 220
mA
x16 370 370 350 340 340 340
LOW VIN ≤ VIL(AC) MAX
HIGH VIN ≥ VIH(AC) MIN
Stable Inputs stable at a HIGH or LOW level
Floating Inputs at VREF = VDDQ/2
Switching Inputs changing between HIGH and LOW every other clock cycle (once per two
clocks) for address and control signals
Switching Inputs changing between HIGH and LOW every other data transfer (once per
clock) for DQ signals, not including masks or strobes
When
TC ≤ 0°C
IDD2P and IDD3P (slow) must be derated by 4 percent; IDD4R and IDD5W must be
derated by 2 percent; and IDD6 and IDD7 must be derated by 7 percent
When
TC ≥ 85°C
IDD0, IDD1, IDD2N, IDD2Q, IDD3N, IDD3P (fast), IDD4R, IDD4W, and IDD5W must be
derated by 2 percent; IDD2P must be derated by 20 percent; IDD3Pslow must be
derated by 30 percent; and IDD6 must be derated by 80 percent (IDD6 will
increase by this amount if TC < 85°C and the 2x refresh option is still enabled)
Table 45: DDR2 IDD Specifications and Conditions (continued)
Notes: 1–7; notes appear on page 114
Parameter/Condition Sym Config -25E -25 -3E -3 -37E -5E Units
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 115 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
I
DD
7 Conditions
IDD7 Conditions
The detailed timings are shown below for IDD7. Changes will be required if timing
parameter changes are made to the specification. Where general IDD parameters in
Table 46 on page 115 conflict with pattern requirements of Table 47, then Table 47
requirements take precedence.
Notes: 1. A = active; RA = read auto precharge; D = deselect.
2. All banks are being interleaved at minimum tRC (IDD) without violating tRRD (IDD) using a
BL = 4.
3. Control and address bus inputs are STABLE during DESELECTs.
4. IOUT = 0mA.
Table 46: General IDD Parameters
IDD Parameter -25E -25 -3E -3 -37E -5E Units
CL (IDD)564543
tCK
tRCD (IDD)12.51512151515ns
tRC (IDD)57.56057606055ns
tRRD (IDD) - x4/x8 (1KB) 7.57.57.57.57.57.5ns
tRRD (IDD) - x16 (2KB) 10 10 10 10 10 10 ns
tCK (IDD)2.5 2.5 3 3 3.75 5 ns
tRAS MIN (IDD)45 45 45 45 45 40 ns
tRAS MAX (IDD)70,000 70,000 70,000 70,000 70,000 70,000 ns
tRP (IDD)12.51512151515ns
tRFC (IDD)105 105 105 105 105 105 ns
tFAW (1KB) (IDD)35 35 37.5 37.5 37.5 37.5 ns
tFAW (2KB) (IDD)45 45 50 50 50 50 ns
Table 47: IDD7 Timing Patterns (4-bank)
All bank interleave READ operation
Speed Grade IDD7 Timing Patterns for x4/x8/x16
-5E A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D
-37E A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
-3 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D
-3E A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D
-25 A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D D
-25E A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 116 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
AC Operating Specifications
AC Operating Specifications
Table 48: AC Operating Conditions for -3E, -3, -37E, and -5E Speeds (Sheet 1 of 6)
Notes: 1–5; notes appear on page 126; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics -3E -3 -37E -5E Units Notes
Parameter Symbol Min Max Min Max Min Max Min Max
Clock
Clock cycle
time
CL = 5
t
CK
AVG
(5)
3,0008,0003,0008,000––––ps16, 22,
36, 38
CL = 4
t
CK
AVG
(4)
3,000 8,000 3,750 8,000 3,750 8,000 5,000 8,000 ps
CL = 3
t
CK
AVG
(3)
– – 5,000 8,000 5,000 8,000 5,000 8,000 ps
CK high-level width tCHAVG0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 tCK 45
CK low-level width tCLAVG0.48 0.52 0.48 0.52 0.48 0.52 0.48 0.52 tCK
Half clock period tHP MIN
(
t
CH,
t
CL)
MIN
(
t
CH,
t
CL)
MIN
(tCH,
tCL)
MIN
(tCH,
tCL)
ps 46
Clock (absolute)
Absolute tCK tCKabs tCKAVG
(MIN) +
tJITPER
(MIN)
tCKAVG
(MAX) +
tJITPER
(MAX)
tCKAVG
MIN) +
tJITPER
(MIN)
tCKAVG
(MAX) +
tJITPER
(MAX)
tCKAVG(
MIN) +
tJITPER
(MIN)
tCKAVG(
MAX) +
tJITPER
(MAX)
tCKAVG(
MIN) +
tJITPER
(MIN)
tCKAVG
(MAX) +
tJITPER
(MAX)
ps
Absolute CK high-
level width
tCHabs tCKAVG
(MIN) *
tCHAVG
(MIN) +
tJITDTY
(MIN)
tCKAVG
(MAX) *
tCHAVG
(MAX) +
tJITDTY
(MAX)
tCKAVG
(MIN)*
tCHAVG
(MIN)+
tJITDTY
(MIN)
tCKAVG
(MAX) *
tCHAVG
(MAX) +
tJITDTY
(MAX)
tCKAVG
(MIN) *
tCHAVG
(MIN) +
tJITDTY
(MIN)
tCKAVG
(MAX) *
tCHAVG
(MAX) +
tJITDTY
(MAX)
tCKAVG
(MIN)*
tCHAVG
(MIN)+
tJITDTY
(MIN)
tCKAVG
(MAX) *
tCHAVG
(MAX) +
tJITDTY
(MAX)
ps
Absolute CK low-
level width
tCLabs tCKAVG
(MIN) *
tCLAVG
(MIN) +
tJITDTY
(MIN)
tCKAVG
(MAX) *
tCLAVG
(MAX) +
tJITDTY
(MAX)
tCKAVG
(MIN) *
tCLAVG
(MIN) +
tJITDTY
(MIN)
tCKAVG
(MAX) *
tCLAVG
(MAX) +
tJITDTY
(MAX)
tCKAVG
(MIN) *
tCLAVG
(MIN) +
tJITDTY
(MIN)
tCKAVG
(MAX) *
tCLAVG
(MAX) +
tJITDTY
(MAX)
tCKAVG
(MIN) *
tCLAVG
(MIN) +
tJITDTY
(MIN)
tCKAVG
(MAX) *
tCLAVG
(MAX) +
tJITDTY
(MAX)
ps
Clock Jitter
Clock jitter – period tJITPER –125 125 –125 125 –125 125 –125 125 ps 39
Clock jitter – half
period
tJITDUTY –125 125 –125 125 –125 125 –150 150 ps 40
Clock jitter – cycle to
cycle
tJITCC 250 250 250 250 ps 41
Cumulative jitter
error, 2 cycles
tERR2per –175 175 –175 175 –175 175 –175 175 ps 42
Cumulative jitter
error, 3 cycles
tERR3per –225 225 –225 225 –225 225 –225 225 ps 42
Cumulative jitter
error, 4 cycles
tERR4per –250 250 –250 250 –250 250 –250 250 ps 42
Cumulative jitter
error, 5 cycles
tERR5per –250 250 –250 250 –250 250 –250 250 ps 42, 48
Cumulative jitter
error, 6–10 cycles
tERR6-
10per
–350 350 –350 350 –350 350 –350 350 ps 42, 48
Cumulative jitter
error, 11–50 cycles
tERR11-
50per
–450 450 –450 450 –450 450 –450 450 ps 42
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 117 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
AC Operating Specifications
Data
DQ hold skew factor tQHS – 340 – 340 – 400 – 450 ps 47
DQ output access
time from CK/CK#
tAC -450 +450 -450 +450 -500 +500 -600 +600 ps 34, 43
Data-out High-Z
window from CK/
CK#
tHZ
tAC
(MAX)
tAC
(MAX)
tAC
(MAX)
tAC
(MAX) ps 8, 9,
43
DQS Low-Z window
from CK/CK#
tLZ1
tAC
(MIN)
tAC
(MAX)
tAC
(MIN)
tAC
(MAX)
tAC
(MIN)
tAC
(MAX)
tAC
(MIN)
tAC
(MAX) ps 8, 10,
43
DQ Low-Z window
from CK/CK#
tLZ2
2 * tAC
(MIN)
tAC
(MAX)
2 * tAC
(MIN)
tAC
(MAX)
2 * tAC
(MIN)
tAC
(MAX)
2 * tAC
(MIN)
tAC
(MAX) ps 8, 10,
43
DQ and DM input
setup time relative to
DQS
tDSa300 300 350 400 ps 7, 15,
19
DQ and DM input
hold time relative to
DQS
tDHa300 300 350 400 ps 7, 15,
19
DQ and DM input
setup time relative to
DQS
tDSb100 100 100 150 ps 7, 15,
19
DQ and DM input
hold time relative to
DQS
tDHb175 175 225 275 ps 7, 15,
19
DQ and DM input
pulse width (for each
input)
tDIPW 0.35 0.35 0.35 0.35 tCK 37
Data hold skew
factor
tQHS 340 340 400 450 ps 47
DQ–DQS hold, DQS
to first DQ to go
nonvalid, per access
tQH
tHP -
tQHS
tHP -
tQHS
tHP -
tQHS
tHP -
tQHS ps 15,
17, 47
Data valid output
window (DVW)
tDVW
tQH -
tDQSQ
tQH -
tDQSQ
tQH -
tDQSQ
tQH -
tDQSQ ns 15, 17
Table 48: AC Operating Conditions for -3E, -3, -37E, and -5E Speeds (Sheet 2 of 6)
Notes: 1–5; notes appear on page 126; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics -3E -3 -37E -5E Units Notes
Parameter Symbol Min Max Min Max Min Max Min Max
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 118 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
AC Operating Specifications
Data Strobe
DQS input-high pulse
width
tDQSH 0.35 0.35 0.35 0.35 tCK 37
DQS input-low pulse
width
tDQSL 0.35 0.35 0.35 0.35 tCK 37
DQS output access
time from CK/CK#
tDQSCK –400 +400 –400 +400 –450 +450 –500 +500 ps 34, 43
DQS falling edge to
CK rising – setup
time
tDSS 0.2 0.2 0.2 0.2 tCK 37
DQS falling edge
from CK rising – hold
time
tDSH 0.2 0.2 0.2 0.2 tCK 37
DQS–DQ skew, DQS
to last DQ valid, per
group, per access
tDQSQ 240 240 300 350 ps 15, 17
DQS read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK 33, 34,
37, 43
DQS read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 33, 34,
37, 43
Write preamble
setup time
tWPRES 0 0 0 0 ps 12, 13
DQS write preamble tWPRE 0.35 0.35 0.25 0.25 tCK 37
DQS write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK 11, 37
Positive DQS latching
edge to associated
clock edge
tDQSS –0.25 0.25 –0.25 0.25 –0.25 0.25 –0.25 0.25 tCK 37
WRITE command to
first DQS latching
transition
WL -
tDQSS
WL +
tDQSS
WL -
tDQSS
WL +
tDQSS
WL -
tDQSS
WL +
tDQSS
WL -
tDQSS
WL +
tDQSS
tCK
Table 48: AC Operating Conditions for -3E, -3, -37E, and -5E Speeds (Sheet 3 of 6)
Notes: 1–5; notes appear on page 126; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics -3E -3 -37E -5E Units Notes
Parameter Symbol Min Max Min Max Min Max Min Max
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 119 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
AC Operating Specifications
Command and Address
Address and control
input pulse width for
each input
tIPW 0.6 0.6 0.6 0.6 tCK 37
Address and control
input setup time
tISa400 400 500 600 ps 6, 19
Address and control
input hold time
tIHa400 400 500 600 ps 6, 19
Address and control
input setup time
tISb200 200 250 350 ps 6, 19
Address and control
input hold time
tIHb275 275 375 475 ps 6, 19
CAS# to CAS#
command delay
tCCD 2 2 2 2 tCK 37
ACTIVE-to-ACTIVE
(same bank)
command
tRC 54 55 55 55 ns 31, 37
ACTIVE bank a to
ACTIVE bank b
command
tRRD
(x4, x8) 7.5 7.5 7.5 7.5 ns 25, 37
tRRD
(x16) 10 10 10 10 ns 25, 37
ACTIVE-to-READ or
WRITE delay
tRCD12151515ns37
4-Bank activate
period
tFAW
(x4, x8) 37.5 37.5 37.5 37.5 ns 28, 37
4-Bank activate
period
tFAW
(x16) 50 50 50 50 ns 28, 37
ACTIVE-to-
PRECHARGE
command
tRAS 40 70,000 40 70,000 40 70,000 40 70,000 ns 18, 31,
37
Internal READ-to-
PRECHARGE
command delay
tRTP 7.5 7.5 7.5 7.5 ns 21, 25,
37
Write recovery time tWR 15 15 15 15 ns 25, 37
Auto precharge
write recovery +
precharge time
tDAL
tWR +
tRP
tWR +
tRP
tWR +
tRP
tWR +
tRP ns 20
Internal WRITE-to-
READ command
delay
tWTR 7.5 7.5 7.5 10 ns 25, 37
PRECHARGE
command period
tRP 12 15 15 15 ns 29, 37
PRECHARGE ALL
command period
tRPA
tRP +
tCK
tRP +
tCK
tRP +
tCK
tRP +
tCK ns 29
LOAD MODE
command cycle time
tMRD 2 2 2 2 tCK 37
Table 48: AC Operating Conditions for -3E, -3, -37E, and -5E Speeds (Sheet 4 of 6)
Notes: 1–5; notes appear on page 126; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics -3E -3 -37E -5E Units Notes
Parameter Symbol Min Max Min Max Min Max Min Max
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 120 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
AC Operating Specifications
Refresh
CKE LOW to CK, CK#
uncertainty
tDELAY tIS + tCK +tIH tIS + tCK +tIH tIS + tCK +tIH tIS + tCK +tIH ns 26
REFRESH-to-ACTIVE
or REFRESH-to-
REFRESH command
interval
tRFC 105 70,000 105 70,000 105 70,000 105 70,000 ns 14, 37
Average periodic
refresh interval
(commercial)
tREFI 7.8 7.8 7.8 7.8 µs 14, 37
Average periodic
refresh interval
(industrial)
tREFIIT 3.9 3.9 3.9 3.9 µs 14, 37
Self Refresh
Exit SELF REFRESH to
non-READ command tXSNR
tRFC
(MIN) +
10
tRFC
(MIN) +
10
tRFC
(MIN) +
10
tRFC
(MIN) +
10
ns
Exit SELF REFRESH to
READ command
tXSRD 200 200 200 200 tCK 37
Exit SELF REFRESH
timing reference
tISXR tIS tIS tIS tIS ps 6, 27
ODT
ODT turn-on delay tAOND22222222
tCK 37
ODT turn-on tAON
tAC
(MIN)
tAC
(MAX) +
700
tAC
(MIN)
tAC
(MAX) +
700
tAC
(MIN)
tAC
(MAX) +
1,000
tAC
(MIN)
tAC
(MAX) +
1000
ps 23, 43
ODT turn-off delay tAOFD 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 tCK 35, 37
ODT turn-off tAOF
tAC
(MIN)
tAC
(MAX) +
600
tAC
(MIN)
tAC
(MAX) +
600
tAC
(MIN)
tAC
(MAX) +
600
tAC
(MIN)
tAC
(MAX) +
600
ps 24, 44
ODT turn-on (power-
down mode) tAONPD
tAC
(MIN) +
2,000
2 x tCK
+ tAC
(MAX) +
1,000
tAC
(MIN) +
2,000
2 x tCK
+ tAC
(MAX) +
1,000
tAC
(MIN) +
2000
2 x tCK +
tAC
(MAX) +
1,000
tAC
(MIN) +
2,000
2 x tCK
+ tAC
(MAX) +
1000
ps
ODT turn-off (power-
down mode) tAOFPD
tAC
(MIN) +
2,000
2.5 x
tCK +
tAC
(MAX) +
1,000
tAC
(MIN) +
2,000
2.5 x
tCK +
tAC
(MAX) +
1,000
tAC
(MIN) +
2,000
2.5 x
tCK +
tAC
(MAX) +
1,000
tAC
(MIN) +
2,000
2.5 x
tCK +
tAC
(MAX) +
1,000
ps
ODT to power-down
entry latency
tANPD 3 3 3 3 tCK 37
ODT power-down
exit latency
tAXPD8888
tCK 37
ODT enable from
MRS command
tMOD12121212ns37, 49
Table 48: AC Operating Conditions for -3E, -3, -37E, and -5E Speeds (Sheet 5 of 6)
Notes: 1–5; notes appear on page 126; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics -3E -3 -37E -5E Units Notes
Parameter Symbol Min Max Min Max Min Max Min Max
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 121 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
AC Operating Specifications
Power-Down
Exit active power-
down to READ
command,
MR[12] = 0
tXARD2222
tCK 37
Exit active power-
down to READ
command,
MR[12] = 1
tXARDS 7 - AL 7 - AL 6 - AL 6 - AL tCK 37
Exit precharge
power-down to any
non-READ command
tXP2222
tCK 37
CKE MIN HIGH/LOW
time
tCKE 3 3 3 3 tCK 32, 37
Table 48: AC Operating Conditions for -3E, -3, -37E, and -5E Speeds (Sheet 6 of 6)
Notes: 1–5; notes appear on page 126; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics -3E -3 -37E -5E Units Notes
Parameter Symbol Min Max Min Max Min Max Min Max
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 122 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
AC Operating Specifications
Table 49: AC Operating Conditions for -25E and -25 Speeds (Sheet 1 of 4)
Notes: 1–5; notes appear on page 126; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics -25E -25 Units Notes
Parameter Symbol Min Max Min Max
Clock
Clock cycle time CL = 6
t
CK
AVG
(6)
N/A N/A 2,500 8,000 ps 16, 22,
36, 38
CL = 5
t
CK
AVG
(5)
2,500 8,000 3,000 8,000 ps
CL = 4
t
CK
AVG
(4)
3,750 8,000 — — ps
CK high-level width tCHAVG0.48 0.52 0.48 0.52 tCK 45
CK low-level width tCLAVG0.48 0.52 0.48 0.52 tCK 45
Half-clock period tHP MIN
(
t
CH,
t
CL)
MIN
(
t
CH,
t
CL)
ps 46
Absolute tCK tCKabs
t
CK
AVG(MIN)
+
t
JIT
PER(MIN)
t
CK
AVG(MAX)
+
t
JIT
PER(MAX)
t
CK
AVG(MIN)
+
t
JIT
PER(MIN)
t
CK
AVG(MAX)
+
t
JIT
PER(MAX)
ps
Absolute CK high-level width tCHABS
t
CK
AVG(MIN)
*
t
CH
AVG(MIN)
+
t
JIT
DTY(MIN)
t
CK
AVG(MAX)
*
t
CH
AVG(MAX)
+
t
JIT
DTY(MAX)
t
CK
AVG(MIN)
*
t
CH
AVG(MIN)
+
t
JIT
DTY(MIN)
t
CK
AVG(MAX)
*
t
CH
AVG(MAX)
+
t
JIT
DTY(MAX)
ps
Absolute CK low-level width tCLABS
t
CK
AVG(MIN)
*
t
CL
AVG(MIN)
+
t
JIT
DTY(MIN)
t
CK
AVG(MAX)
*
t
CL
AVG(MAX)
+
t
JIT
DTY(MAX)
t
CK
AVG(MIN)
*
t
CL
AVG(MIN)
+
t
JIT
DTY(MIN)
t
CK
AVG(MAX)
*
t
CL
AVG(MAX)
+
t
JIT
DTY(MAX)
ps
Clock Jitter
Clock jitter – period tJITPER –100 100 –100 100 ps 39
Clock jitter – half period tJITDUTY –100 100 –100 100 ps 40
Clock jitter – cycle to cycle tJITCC 200 200 ps 41
Cumulative jitter error, 2 cycles tERR2per –150 150 –150 150 ps 42
Cumulative jitter error, 3 cycles tERR3per –175 175 –175 175 ps 42
Cumulative jitter error, 4 cycles tERR4per –200 200 –200 200 ps 42
Cumulative jitter error, 5 cycles tERR5per –200 200 –200 200 ps 42, 48
Cumulative jitter error, 6–10 cycles
t
ERR
6-
10per
–300 300 –300 300 ps 42, 48
Cumulative jitter error, 11–50 cycles
t
ERR
11-50per
–450 450 –450 450 ps 42
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 123 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
AC Operating Specifications
Data
DQ output access time from CK/CK# tAC –400 +400 –400 +400 ps 34, 43
Data-out High-Z window from CK/CK# tHZ tAC (MAX) tAC (MAX) ps 8, 9, 43
DQS Low-Z window from CK/CK# tLZ1tAC (MIN) tAC (MAX) tAC (MIN) tAC (MAX) ps 8, 10,
43
DQ Low-Z window from CK/CK# tLZ2
2 * tAC
(MIN)
tAC (MAX) 2 * tAC
(MIN)
tAC (MAX) ps 8, 10,
43
DQ and DM input setup time relative to
DQS
tDSa250 250 ps 15, 19
DQ and DM input hold time relative to
DQS
tDHa250 250 ps 15, 19
DQ and DM input setup time relative to
DQS
tDSb50 50 ps 15, 19
DQ and DM input hold time relative to
DQS
tDHb125 125 ps 15, 19
DQ and DM input pulse width
(for each input)
tDIPW 0.35 0.35 tCK 37
Data hold skew factor tQHS 300 300 ps 47
DQ–DQS hold from DQS tQH tHP -tQHS tHP -tQHS ps 15, 17,
47
Data valid output window (DVW) tDVW
tQH -
tDQSQ
tQH -
tDQSQ ns 15, 17
Data Strobe
DQS input-high pulse width tDQSH 0.35 0.35 tCK 37
DQS input-low pulse width tDQSL 0.35 0.35 tCK 37
DQS output access time from CK/CK# tDQSCK –350 +350 –350 +350 ps 34, 43
DQS falling edge to CK rising – setup time tDSS 0.2 0.2 tCK 37
DQS falling edge from CK rising – hold
time
tDSH 0.2 0.2 tCK 37
DQS–DQ skew, DQS to last DQ valid, per
group, per access
tDQSQ 200 200 ps 15, 17
DQS read preamble tRPRE0.91.10.91.1
tCK 33, 34,
37, 43
DQS read postamble tRPST0.40.60.40.6
tCK 33, 34,
37, 43
Write preamble setup time tWPRES 0 0 ps 12, 13
DQS write preamble tWPRE 0.35 0.35 tCK 37
DQS write postamble tWPST 0.4 0.6 0.4 0.6 tCK 11, 37
Positive DQS latching edge to associated
clock edge
tDQSS –0.25 +0.25 –0.25 +0.25 tCK 37
WRITE command to first DQS latching
transition WL - tDQSS WL + tDQSS WL - tDQSS WL + tDQSS tCK
Table 49: AC Operating Conditions for -25E and -25 Speeds (Sheet 2 of 4)
Notes: 1–5; notes appear on page 126; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics -25E -25 Units Notes
Parameter Symbol Min Max Min Max
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 124 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
AC Operating Specifications
Command and Address
Address and control input pulse width for
each input
tIPW 0.6 0.6 tCK 37
Address and control input setup time tISa375 375 ps 19
Address and control input hold time tIHa375 375 ps 19
Address and control input setup time tISb175 175 ps 19
Address and control input hold time tIHb250 250 ps 19
CAS# to CAS# command delay tCCD 2 2 tCK 37
ACTIVE-to-ACTIVE (same bank) command tRC 55 55 ns 31, 37
ACTIVE bank a to ACTIVE bank b
command
tRRD
(x4, x8) 7.5 7.5 ns 25, 37
tRRD
(x16) 10 10 ns 25, 37
ACTIVE-to-READ or WRITE delay tRCD 12.5 15 ns 37
4-bank activate period tFAW
(1K page)
37.5 37.5 ns 28, 37
4-bank activate period tFAW
(2K page)
50 50 ns 28, 37
ACTIVE-to-PRECHARGE command tRAS 45 70,000 45 70,000 ns 18, 31,
37
Internal READ-to-PRECHARGE command
delay
tRTP 7.5 7.5 ns 21, 25,
37
Write recovery time tWR 15 15 ns 25, 37
Auto precharge write recovery +
precharge time
tDAL tWR + tRP tWR + tRP ns 20
Internal WRITE-to-READ command delay tWTR 7.5 10 ns 25, 37
PRECHARGE command period tRP 12.5 15 ns 29, 37
PRECHARGE ALL command period tRPA tRP + tCK tRP + tCK ns 29
LOAD MODE command cycle time tMRD 2 2 tCK 37
Refresh
CKE low to CK, CK# uncertainty tDELAY tIS + tCK +tIH tIS + tCK +tIH ns 26
REFRESH-to-ACTIVE or REFRESH-to-
REFRESH command interval
tRFC 105 70,000 105 70,000 ns 14, 37
Average periodic refresh interval tREFI 7.8 7.8 µs 14, 37
Average periodic refresh interval
(industrial)
tREFIIT 3.9 3.9 µs 14, 37
Self Refresh
Exit self refresh to non-READ command tXSNR
tRFC
(MIN) + 10
tRFC
(MIN) + 10 ns
Exit self refresh to READ command tXSRD 200 200 tCK 37
Exit self refresh timing reference tISXR tIS tIS ps 6, 27
Table 49: AC Operating Conditions for -25E and -25 Speeds (Sheet 3 of 4)
Notes: 1–5; notes appear on page 126; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics -25E -25 Units Notes
Parameter Symbol Min Max Min Max
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 125 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
AC Operating Specifications
ODT
ODT turn-on delay tAOND2222
tCK 37
ODT turn-on tAON tAC (MIN)
tAC (MAX)
+ 700
tAC (MIN)
tAC (MAX)
+ 700 ps 23, 43
ODT turn-off delay tAOFD2.52.52.52.5
tCK 35, 37
ODT turn-off tAOF tAC (MIN)
tAC (MAX)
+ 600
tAC (MIN)
tAC (MAX)
+ 600 ps 24, 44
ODT turn-on (power-down mode) tAONPD
tAC
(MIN) +
2,000
2 x tCK +
tAC
(MAX) +
1,000
tAC
(MIN) +
2,000
2 x tCK +
tAC
(MAX) +
1,000
ps
ODT turn-off (power-down mode) tAOFPD
tAC (MIN) +
2,000
2.5 x tCK +
tAC
(MAX) +
1,000
tAC (MIN) +
2,000
2.5 x tCK +
tAC
(MAX) +
1,000
ps
ODT to power-down entry latency tANPD 3 3 tCK 37
ODT power-down exit latency tAXPD 10 10 tCK 37
ODT enable from MRS command tMOD 12 12 ns 37, 49
Power-Down
Exit active power-down to READ
command, MR[12] = 0
tXARD 2 2 tCK 37
Exit active power-down to READ
command, MR[12] = 1
tXARDS 8 - AL 8 - AL tCK 37
Exit precharge power-down to any non-
READ command
tXP 2 2 tCK 37
CKE minimum high/low time tCKE 3 3 tCK 32, 37
Table 49: AC Operating Conditions for -25E and -25 Speeds (Sheet 4 of 4)
Notes: 1–5; notes appear on page 126; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics -25E -25 Units Notes
Parameter Symbol Min Max Min Max
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 126 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Notes
Notes
1. All voltages are referenced to VSS.
2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted
at nominal reference/supply voltage levels, but the related specifications and device
operation are guaranteed for the full voltage range specified. ODT is disabled for all
measurements that are not ODT-specific.
3. Outputs measured with equivalent load:
4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.0V in the test environ-
ment and parameter specifications are guaranteed for the specified AC input levels
under normal use conditions. The slew rate for the input signals used to test the
device is 1.0 V/ns for signals in the range between VIL(AC) and VIH(AC). Slew rates
other than 1.0 V/ns may require the timing parameters to be derated as specified.
5. The AC and DC input level specifications are as defined in the SSTL_18 standard (i.e.,
the receiver will effectively switch as a result of the signal crossing the AC input level
and will remain in that state as long as the signal does not ring back above [below] the
DC input LOW [HIGH] level).
6. There are two sets of values listed for Command/Address: tISa, tIHa and tISb, tIHb. The
tISa, tIHa values (for reference only) are equivalent to the baseline values of tISb, tIHb
at VREF when the slew rate is 1 V/ns. The baseline values, tISb, tIHb, are the JEDEC-
defined values, referenced from the logic trip points. tISb is referenced from VIH(AC)
for a rising signal and VIL(AC) for a falling signal, while tIHb is referenced from VIL(DC)
for a rising signal and VIH(DC) for a falling signal. If the Command/Address slew rate is
not equal to 1 V/ns, then the baseline values must be derated by adding the values
from Tables 26 and 27 on page 89.
7. The values listed are for the differential DQS strobe (DQS and DQS#) with a differen-
tial slew rate of 2 V/ns (1 V/ns for each signal). There are two sets of values listed: tDSa,
tDHa and tDSb, tDHb. The tDSa, tDHa values (for reference only) are equivalent to the
baseline values of tDSb, tDHb at VREF when the slew rate is 2 V/ns, differentially. The
baseline values, tDSb, tDHb, are the JEDEC-defined values, referenced from the logic
trip points. tDSb is referenced from VIH(AC) for a rising signal and VIL(AC) for a falling
signal, while tDHb is referenced from VIL(DC) for a rising signal and VIH(DC) for a fall-
ing signal. If the differential DQS slew rate is not equal to 2 V/ns, then the baseline val-
ues must be derated by adding the values from Tables 28 and 29 on pages 94–95. If the
DQS differential strobe feature is not enabled, then the DQS strobe is single-ended,
the baseline values not applicable, and timing is not referenced to the logic trip
points. Single-ended DQS data timing is referenced to DQS crossing VREF. The correct
timing values for a single-ended DQS strobe are listed in Tables 30–33 on pages 96–97;
listed values are already derated for slew rate variations and can be used directly from
the table.
8. tHZ and tLZ transitions occur in the same access time windows as valid data transi-
tions. These parameters are not referenced to a specific voltage level, but specify
when the device output is no longer driving (tHZ) or begins driving (tLZ).
9. This maximum value is derived from the referenced test load. tHZ (MAX) will prevail
over tDQSCK (MAX) + tRPST (MAX) condition.
10. tLZ (MIN) will prevail over a tDQSCK (MIN) + tRPRE (MAX) condition.
Output
(VOUT)
Reference
Point
25Ω
VTT = VDDQ/2
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 127 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Notes
11. The intent of the “Don’t Care” state after completion of the postamble is that the DQS-
driven signal should either be HIGH, LOW, or High-Z, and that any signal transition
within the input switching region must follow valid input requirements. That is, if
DQS transitions HIGH (above VIH[DC] MIN), then it must not transition LOW (below
VIH[DC]) prior to tDQSH (MIN).
12. This is not a device limit. The device will operate with a negative value, but system
performance could be degraded due to bus turnaround.
13. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE com-
mand. The case shown (DQS going from High-Z to logic LOW) applies when no
WRITEs were previously in progress on the bus. If a previous WRITE was in progress,
DQS could be HIGH during this time, depending on tDQSS.
14. The refresh period is 64ms (commercial) or 32ms (industrial). This equates to an aver-
age refresh rate of 7.8125µs (commercial) or 3.9607µs (industrial). However, a
REFRESH command must be asserted at least once every 70.3µs or tRFC (MAX). To
ensure all rows of all banks are properly refreshed, 8,192 REFRESH commands must
be issued every 64ms (commercial) or 32ms (industrial).
15. Referenced to each output group: x4 = DQS with DQ0–DQ3; x8 = DQS with DQ0–DQ7;
x16 = LDQS with DQ0–DQ7; and UDQS with DQ8–DQ15.
16. CK and CK# input slew rate is referenced at 1 V/ns (2 V/ns if measured differentially).
17. The data valid window is derived by achieving other specifications: tHP (tCK/2),
tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates in direct propor-
tion to the clock duty cycle and a practical data valid window can be derived.
18. READs and WRITEs with auto precharge are allowed to be issued before tRAS (MIN) is
satisfied since tRAS lockout feature is supported in DDR2 SDRAM.
19. VIL/VIH DDR2 overshoot/undershoot. See “AC Overshoot/Undershoot Specification”
on page 105.
20. tDAL = (nWR) + (tRP/tCK). Each of these terms, if not already an integer, should be
rounded up to the next integer. tCK refers to the application clock period; nWR refers
to the tWR parameter stored in the MR[11, 10, 9]. For example, -37E at tCK = 3.75ns
with tWR programmed to four clocks would have tDAL = 4 + (15ns/3.75ns) clocks = 4 +
(4) clocks = 8 clocks.
21. The minimum internal READ to PRECHARGE time. This is the time from the last 4-bit
prefetch begins to when the PRECHARGE command can be issued. A 4-bit prefetch is
when the READ command internally latches the READ so that data will output CL
later. This parameter is only applicable when tRTP / (2 x tCK) > 1, such as frequencies
faster than 533 MHz when tRTP = 7.5ns. If tRTP / (2 x tCK) ≤ 1, then equation AL + BL/
2 applies. tRAS (MIN) also has to be satisfied as well. The DDR2 SDRAM will automat-
ically delay the internal PRECHARGE command until tRAS (MIN) has been satisfied.
22. Operating frequency is only allowed to change during self refresh mode (see Figure 54
on page 71), precharge power-down mode, or system reset condition (See “Reset
Function” on page 72). SSC allows for small deviations in operating frequency, pro-
vided the SSC guidelines are satisfied.
23. ODT turn-on time tAON (MIN) is when the device leaves High-Z and ODT resistance
begins to turn on. ODT turn-on time tAON (MAX) is when the ODT resistance is fully
on. Both are measured from tAOND.
24. ODT turn-off time tAOF (MIN) is when the device starts to turn off ODT resistance.
ODT turn off time tAOF (MAX) is when the bus is in High-Z. Both are measured from
tAOFD.
25. This parameter has a two clock minimum requirement at any tCK.
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 128 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Notes
26. tDELAY is calculated from tIS + tCK + tIH so that CKE registration LOW is guaranteed
prior to CK, CK# being removed in a system RESET condition. See “Reset Function” on
page 72.
27. tISXR is equal to tIS and is used for CKE setup time during self refresh exit, as shown in
Figure 43 on page 62.
28. No more than four bank-ACTIVE commands may be issued in a given tFAW (MIN)
period. tRRD (MIN) restriction still applies. The tFAW (MIN) parameter applies to all
8-bank DDR2 devices, regardless of the number of banks already open or closed.
29. tRPA timing applies when the PRECHARGE (ALL) command is issued, regardless of
the number of banks already open or closed. If a single-bank PRECHARGE command
is issued, tRP timing applies. tRPA (MIN) applies to all 8-bank DDR2 devices.
30. N/A.
31. This is applicable to READ cycles only. WRITE cycles generally require additional time
due to tWR during auto precharge.
32. tCKE (MIN) of three clocks means CKE must be registered on three consecutive posi-
tive clock edges. CKE must remain at the valid input level the entire time it takes to
achieve the three clocks of registration. Thus, after any CKE transition, CKE may not
transition from its valid level during the time period of tIS + 2 x tCK + tIH.
33. This parameter is not referenced to a specific voltage level, but specified when the
device output is no longer driving (tRPST) or beginning to drive (tRPRE).
34. When DQS is used single-ended, the minimum limit is reduced by 100ps.
35. The half-clock of tAOFD’s 2.5 tCK assumes a 50/50 clock duty cycle. This half-clock
value must be derated by the amount of half-clock duty cycle error. For example, if the
clock duty cycle was 47/53, tAOFD would actually be 2.5 - 0.03, or 2.47, for tAOF (MIN)
and 2.5 + 0.03, or 2.53, for tAOF (MAX).
36. The clock’s tCKAVG is the average clock over any 200 consecutive clocks and tCKAVG
(MIN) is the smallest clock rate allowed, except a deviation due to allowed clock jitter.
Input clock jitter is allowed provided it does not exceed values specified. Also, the jit-
ter must be of a random Gaussian distribution in nature.
37. The inputs to the DRAM must be aligned to the associated clock; that is, the actual
clock that latches it in. However, the input timing (in ns) references to the tCKAVG
when determining the required number of clocks. The following input parameters are
determined by taking the specified percentage times the tCKAVG rather than tCK: tIPW,
tDIPW, tDQSS, tDQSH, tDQSL, tDSS, tDSH, tWPST, and tWPRE.
38. Spread spectrum is not included in the jitter specification values. However, the input
clock can accommodate spread spectrum at a sweep rate in the range 20–60 KHz with
additional one percent of tCKAVG as a long-term jitter component; however, the
spread spectrum may not use a clock rate below tCKAVG(MIN) or above tCKAVG(MAX).
39. The period jitter (tJITPER) is the maximum deviation in the clock period from the aver-
age or nominal clock allowed in either the positive or negative direction. JEDEC spec-
ifies tighter jitter numbers during DLL locking time. During DLL lock time, the jitter
values should be 20 percent less than noted in the table (DLL locked).
40. The half-period jitter (tJITDTY) applies to either the high pulse of clock or the low pulse
of clock; however, the two cumulatively can not exceed tJITPER.
41. The cycle-to-cycle jitter (tJITCC) is the amount the clock period can deviate from one
cycle to the following cycle. JEDEC specifies tighter jitter numbers during DLL locking
time. During DLL lock time, the jitter values should be 20 percent less than noted in
the table (DLL locked).
42. The cumulative jitter error (tERRnPER), where n is 2, 3, 4, 5, 6–10, or 11–50, is the
amount of clock time allowed to consecutively accumulate away from the average
clock over any number of clock cycles.
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 129 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Notes
43. The DRAM output timing is aligned to the nominal or average clock. Most output
parameters must be derated by the actual jitter error when input clock jitter is
present; this will result in each parameter becoming larger. The following parameters
are required to be derated by subtracting tERR5PER (MAX): tAC (MIN), tDQSCK (MIN),
tLZDQS (MIN), tLZDQ (MIN), tAON (MIN); while these following parameters are
required to be derated by subtracting tERR5PER (MIN): tAC (MAX), tDQSCK (MAX), tHZ
(MAX), tLZDQS (MAX), tLZDQ (MAX), tAON (MAX). The parameter tRPRE (MIN) is der-
ated by subtracting tJITPER (MAX), while tRPRE (MAX), is derated by subtracting tJITPER
(MIN). The parameter tRPST (MIN) is derated by subtracting tJITDTY (MAX), while
tRPST (MAX), is derated by subtracting tJITDTY (MIN).
44. Half-clock output parameters must be derated by the actual tERR5PER and tJITDTY
when input clock jitter is present; this will result in each parameter becoming larger.
The parameter tAOF (MIN) is required to be derated by subtracting both tERR5PER
(MAX) and tJITDTY (MAX). The parameter tAOF (MAX) is required to be derated by
subtracting both tERR5PER (MIN) and tJITDTY (MIN).
45. MIN(tCL, tCH) refers to the smaller of the actual clock LOW time and the actual clock
HIGH time driven to the device. The clock’s half period must also be of a Gaussian dis-
tribution; tCHAVG and tCLAVG must be met with or without clock jitter and with or
without duty cycle jitter. tCHAVG and tCLAVG are the average of any 200 consecutive CK
falling edges.
46. tHP (MIN) is the lesser of tCL and tCH actually applied to the device CK and CK#
inputs; thus, tHP (MIN) ≥ the lesser of tCLABS (MIN) and tCHABS (MIN).
47. tQH = tHP - tQHS; the worst case tQH would be the smaller of tCLABS (MAX) or tCHABS
(MAX) times tCKABS (MIN) - tQHS. Minimizing the amount of tCHAVG offset and value
of tJITDTY will provide a larger tQH, which in turn will provide a larger valid data out
window.
48. JEDEC specifies using tERR6–10PER when derating clock-related output timing (notes
43–44). Micron requires less derating by allowing tERR5PER to be used.
49. Requires 8 tCK for backwards compatibility.
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 130 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Package Dimensions
Package Dimensions
Figure 88: 84-Ball FBGA Package – 12mm x 12.5mm (x16)
Note: All dimensions are in millimeters.
0.80 ±0.05
0.10 CC
MOLD COMPOUND: EPOXY NOVALAC
SOLDER BALL MATERIAL:
96.5% Sn, 3% Ag, 0.5% Cu
SOLDER BALL PAD:
Ø0.33 NON SOLDER MASK DEFINED
SUBSTRATE MATERIAL: PLASTIC LAMINATE
5.60
11.20
BALL A1 ID
BALL A1
BALL A1 ID
0.80
TYP
6.00 ±0.053.20
12.00 ±0.10
6.40
BALL A9
SEATING
PLANE
12.50 ±0.10
6.25 ±0.05
0.80 TYP
84X Ø0.45
C
L
C
L
SOLDER BALL
DIAMETER REFERS
TO POST-REFLOW
CONDITION.
1.20 MAX
0.155 ±0.013
1.80 ±0.05
CTR
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 131 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Package Dimensions
Figure 89: 84-Ball FBGA Package – 10mm x 12.5mm (x16)
Note: All dimensions are in millimeters.
BALL A1 ID
1.20 MAX
BALL A9
BALL A1 ID
0.80
TYP
0.80 TYP
3.20
6.40
BALL A1
10.00 ±0.10
5.00 ±0.05
SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE PRE-
REFLOW DIAMETER IS 0.42
84X ∅0.45
SOLDER BALL MATERIAL:
62% Sn, 36% Pb, 2% Ag OR
96.5% Sn, 3% Ag, 0.5%Cu
NON SOLDER MASK DEFINED BALL PAD: Ø 0.33
MOLD COMPOUND: EPOXY NOVOLAC
SUBSTRATE MATERIAL: PLASTIC LAMINATE
11.20
5.60
6.25 ±0.05
12.50 ±0.10
C
L
C
L
0.80 ±0.05
0.155 ±0.013
SEATING PLANE
C1.80 ±0.05
CTR
0.10 C
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 132 ©2004 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 DDR2 SDRAM
Package Dimensions
Figure 90: 60-Ball FBGA Package – 12mm x 10mm (x4, x8)
Note: All dimensions are in millimeters.
0.80 ±0.05
0.10 CC
0.155 ±0.013
MOLD COMPOUND: EPOXY NOVALAC
SOLDER BALL MATERIAL:
96.5% Sn, 3% Ag, 0.5% Cu
SOLDER BALL PAD:
Ø0.33 NON SOLDER MASK DEFINED
SUBSTRATE MATERIAL: PLASTIC LAMINATE
4.00
8.00
BALL A1 ID
BALL A1
BALL A1 ID
0.80
TYP
6.00 ±0.053.20
12.00 ±0.10
6.40
BALL A9
SEATING
PLANE
10.00 ±0.10
5.00 ±0.05
0.80 TYP
60X Ø0.45
C
L
C
L
1.20 MAX
1.80 ±0.05
CTR
SOLDER BALL
DIAMETER REFERS
TO POST-REFLOW
CONDITION.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
512Mb: x4, x8, x16 DDR2 SDRAM
Package Dimensions
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
512MbDDR2_2.fm - Rev. K 3/06 EN 133 ©2004 Micron Technology, Inc. All rights reserved.
Figure 91: 60-Ball FBGA Package – 10mm x 10mm (x4, x8)
Note: All dimensions are in millimeters.
BALL A1 ID
1.20 MAX
MOLD COMPOUND: EPOXY NOVOLAC
SUBSTRATE MATERIAL: PLASTIC LAMINATE
SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2%Ag OR
96.5% Sn, 3%Ag, 0.5%Cu
NON SOLDER MASK DEFINED BALL PAD: Ø0.33
BALL A9
0.80 TYP
10.00 ±0.10
5.00 ±0.053.20
4.00
0.80 ±0.05
0.155 ±0.013
SEATING PLANE
C
8.00
6.40
1.80 ±0.05
CTR
0.10 C
60X Ø0.45
SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE PRE-
REFLOW DIAMETER IS 0.42
C
L
10.00 ±0.10
BALL A1
BALL A1 ID
0.80 TYP
5.00 ±0.05
C
L
