DS119 (v1.2) October 18, 2004 www.xilinx.com 1
Advance Product Specification 1-800-255-7778
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Features
• Guaranteed to meet full electrical specifications over TA
= –40°C to +125°C
• Technology: 0.35 µm EEPROM process
• Full Boundary Scan Test (IEEE 1149.1) for flexible
in-system device and system testing
• Fast programming times in production saves time and
money
- Increases system reliability through reduced device
handling
• High-speed pin-to-pin delays of 10 ns (100 MHz)
• Slew rate control per output to reduce EMI
• 100% routable which enables all device resources to
be utilized
• Refer to XPLA3 Family data sheet (DS012) for
architecture description
• Refer to XCR3032XL data sheet (DS023) for pin
descriptions
Description
The CoolRunner™ XCR3032XL-Q CPLD Automotive IQ
product is targeted for low power systems that include por-
table, handheld, automotive, and power sensitive applica-
tions. This device includes Fast Zero Power™ (FZP) design
technology that combines low power and high speed. With
this design technique, the XCR3032XL-Q delivers low
standby current without the need for "turbo bits" or other
power down schemes. By replacing conventional sense
amplifier methods for implementing product terms (a tech-
nique that has been used in PLDs since the bipolar era) with
a cascaded chain of pure CMOS gates, the dynamic power
is also substantially lower than any other CPLD. CoolRun-
ner devices are the only TotalCMOS PLDs, as they use both
a CMOS process technology and the patented full CMOS
FZP design technique.
The CoolRunner XCR3032XL-Q employs a full PLA struc-
ture for logic allocation within a functon block. The PLA pro-
vides maximum flexibility and logic density, with superior pin
locking capability, while maintaining deterministic timing.
The CoolRunner XCR3032XL-Q is supported by Web-
PACK™ and WebFITTER™ from Xilinx and industry stan-
dard CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor,
Synopsys, ViewLogic, and Synplicity), using text (ABEL,
VHDL, Verilog) and schematic capture design entry. Design
verification uses industry standard simulators for functional
and timing simulation. Development is supported on per-
sonal computer, Sparc, and HP platforms.
The XCR3032XL-Q features also include industry-stan-
dard, IEEE 1149.1, JTAG interface through which bound-
ary-scan testing and In-System Programming (ISP) and
reprogramming of the device can occur. This device is elec-
trically reprogrammable using industry standard device
programmers.
0
XCR3032XL 32 Macrocell
Automotive IQ CPLD
DS119 (v1.2) October 18, 2004 014
Advance Product Specification
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Table 1:
CoolRunner XCR3032XL-Q
XCR3032XL-Q
Macrocells 32
Usable Gates 750
Registers 32
FSYSTEM (MHz) 95
User I/O (44-pin VQFP) 36
Figure 1:
ICC vs. Frequency at VCC = 3.3V, 25°C
5
0
1
0
1
5
2
0
0
2
0
4
0
60
80
1
00
12
0
14
0
1
60
1
80
2
00
Frequenc
y
(MHz
)
DS023
_
01
_
08010
1
Ty
pical I
CC
(
mA
)
Table 2:
ICC vs. Frequency (VCC = 3.3V, 25°C)
Frequency (MHz) 0 1 5 10 20 50 100 200
Typ ic al I CC (mA) 0.02 0.13 0.54 1.06 2.09 5.2 10.26 20.3
XCR3032XL 32 Macrocell Automotive IQ CPLD
2www.xilinx.com DS119 (v1.2) October 18, 2004
1-800-255-7778 Advance Product Specification
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Absolute Maximum Ratings(1)
Recommended Operating Conditions
Quality and Reliability Characteristics
Symbol Parameter Min. Max. Unit
VCC Supply voltage(2) relative to GND –0.5 4.0 V
VIInput voltage(3) relative to GND –0.5 5.5(4) V
IOUT Output current, per pin –100 100 mA
TJMaximum junction temperature –40 150 °C
TSTR Storage temperature –65 150 °C
Notes:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional
operation at these or any other condition above those indicated in the operational and programming specification is not implied.
2. The chip supply voltage must rise monotonically.
3. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins may undershoot to –2.0V or overshoot to 7.0V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.
4. External I/O voltage may not exceed VCC by 4.0V.
Symbol Parameter Min. Max. Unit
TAAmbient temperature –40 +125 °C
VCC Supply voltage 3.0 3.6 V
VIL Low-level input voltage 0 0.8 V
VIH High-level input voltage 2.0 5.5 V
VOOutput voltage 0 VCC V
TRInput rise time - 20 ns
TFInput fall time - 20 ns
Symbol Parameter Min Max Units
TDR Data retention 20 - Years
NPE Program/erase cycles (Endurance) @ TA = 70°C 10,000 - Cycles
XCR3032XL 32 Macrocell Automotive IQ CPLD
DS119 (v1.2) October 18, 2004 www.xilinx.com 3
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DC Electrical Characteristics Over Recommended Operating Conditions
Symbol Parameter Test Conditions Min. Max. Unit
VOH(1)Output High voltage IOH = –500 µA 90%VCC(2)-V
VCC = 3.0V, IOH = –8 mA 2.4 - V
VOL Output Low voltage IOL = 8 mA - 0.4 V
IIL(3)Input leakage current VIN = GND or VCC –10 10 µA
IIH(3)I/O High-Z leakage current VIN = GND or VCC –10 10 µA
ICCSB Standby current VCC = 3.6V - 1.0 mA
ICC Dynamic current(4)f = 1 MHz - 2.0 mA
f = 50 MHz - 10 mA
CIN Input pin capacitance(5)f = 1 MHz - 8 pF
CCLK Clock input capacitance(5)f = 1 MHz - 12 pF
CI/O I/O pin capacitance(5)f = 1 MHz - 10 pF
Notes:
1. See Figure 2 for output drive characteristics of the XPLA3 family.
2. This parameter guaranteed by design and characterization, not by testing.
3. Typical leakage current is less than 1 µA.
4. This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and
unloaded. Inputs are tied to VCC or ground. This parameter guaranteed by design and characterization, not testing.
5. Typical values, not tested.
Figure 2:
Typical I/V Curve for the XPLA3 Family, 3.3V, 25°C
0
0
1
0
2
0
30
4
0
50
60
7
0
80
90
1
00
0
.
5
1
1.
5
2
2.
5
3
3
.
5
4
4.
5
5
Volt
s
I
O
L
(
3.3V
)
I
O
H
(
3.3V
)
I
O
H
(
2.7V
)
mA
DS012
_
10
_
04040
2
XCR3032XL 32 Macrocell Automotive IQ CPLD
4www.xilinx.com DS119 (v1.2) October 18, 2004
1-800-255-7778 Advance Product Specification
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AC Electrical Characteristics Over Recommended Operating Conditions(1)
Symbol Parameter
-10
Unit Min. Max.
TPD1 Propagation delay time (single p-term) - 9.1 ns
TPD2 Propagation delay time (OR array) - 10.0 ns
TCO Clock to output (global synchronous pin clock) - 6.5 ns
TSUF Setup time (fast input register) 3.0 - ns
TSU1(2) Setup time (single p-term) 5.4 - ns
TSU2 Setup time (OR array) 6.3 - ns
TH(2) Hold time 0 - ns
TWLH(2) Global Clock pulse width (High or Low) 4.0 - ns
TPLH(2) P-term clock pulse width 6.0 - ns
TR(2) Input rise time - 20 ns
TL(2) Input fall time - 20 ns
fSYSTEM(2) Maximum system frequency - 95 MHz
TCONFIG(2) Configuration time(3) -60µs
TINIT ISP initialization time - 60 µs
TPOE(2) P-term OE to output enabled - 11.2 ns
TPOD(2) P-term OE to output disabled(4) -11.2ns
TPCO(2) P-term clock to output - 10.7 ns
TPAO (2) P-term set/reset to output valid - 11.2 ns
Notes:
1. Specifications measured with one output switching.
2. These parameters guaranteed by design and/or characterization, not testing.
3. Typical current draw during configuration is 3 mA at 3.6V.
4. Output CL = 5 pF.
XCR3032XL 32 Macrocell Automotive IQ CPLD
DS119 (v1.2) October 18, 2004 www.xilinx.com 5
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Internal Timing Parameters(1)
Symbol Parameter
-10
UnitMin. Max.
Buffer Delays
TIN Input buffer delay - 2.2 ns
TFIN Fast Input buffer delay - 3.1 ns
TGCK Global Clock buffer delay - 1.3 ns
TOUT Output buffer delay - 3.6 ns
TEN Output buffer enable/disable delay - 5.7 ns
Internal Register, Product Term, and Combinatorial Delays
TLDI Latch transparent delay - 2.0 ns
TSUI Register setup time 1.2 - ns
THI Register hold time 0.7 - ns
TECSU Register clock enable setup time 3.0 - ns
TECHO Register clock enable hold time 5.5 - ns
TCOI Register clock to output delay - 1.6 ns
TAOI Register async. S/R to output delay - 2.1 ns
TRAI Register async. recovery - 6.0 ns
TPTCK Product term clock delay - 3.3 ns
TLOGI1 Internal logic delay (single p-term) - 3.3 ns
TLOGI2 Internal logic delay (PLA OR term) - 4.2 ns
Feedback Delays
TFZIA delay - 2.9 ns
Time Adders
TLOGI3 Fold-back NAND delay - 3.0 ns
TUDA Universal delay - 2.5 ns
TSLEW Slew rate limited delay - 6.0 ns
Notes:
1. These parameters guaranteed by design and characterization, not testing.
XCR3032XL 32 Macrocell Automotive IQ CPLD
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Switching Characteristics
Figure 3:
Typical AC Load Circuit
DS023_03_102401
Component Values
R1 390Ω
R2 390Ω
C1 35 pF
Measurement S1 S2
TPOE (High)
TPOE (Low)
TP
Open Closed
Closed Open
Closed Closed
VCC
VOUT
VIN
C1
R1
R2
S1
S2
Note: For TPOD, C1 = 5 pF. Delay measured at
output level of VOL + 300 mV, VOH – 300 mV.
Figure 4:
Typical Voltage Waveform
90%
10%
1.5 ns 1.5 ns
DS023_06_042800
+3.0V
0V
Measurements:
All circuit delays are measured at the +1.5V level of
inputs and outputs, unless otherwise specified.
T
R
T
L
XCR3032XL 32 Macrocell Automotive IQ CPLD
DS119 (v1.2) October 18, 2004 www.xilinx.com 7
Advance Product Specification 1-800-255-7778
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Device Part Marking
Revision History
The following table shows the revision history for this document.
Ordering Combination Information
Device Ordering and Part
Marking Number
Speed
(pin-to-pin
delay)
Pkg.
Symbol
No. of
Pins Package Type
Operating
Range(1)
XCR3032XL-10VQ44Q 10 ns VQ44 44 Very Thin Quad Flat Pack (VQFP) Q
Notes:
1. Q = Automotive: TA = –40° to +125°C
Date Version Revision
10/28/02 1.0 Initial Xilinx release.
02/14/03 1.1 Deleted architecture and pinout sections.
10/18/04 1.2 Added "Not to be used in new designs" watermark; moved to "Mature Products"
XCRxxxxXL
VQ44
10Q
De vice Type
Package
Speed
Operating Range
This line not
related to device
part number
Sample package with part marking.
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