Lead (Pb) Free Product - RoHS Compliant
Red PDSP2110
Yellow PDSP2111
Super-red PDSP2112
Green PDSP2113
High Efficiency Green PDSP2114
5.10 mm (0.200") 8-Ch aracter 5x7 Dot Matr ix Parallel Input
Alphanumeric Intelligent Display® Devices
2006-01-23 1
DESCRIPTION
The PDSP2110 (Red), PDSP2111 (Yellow), PDSP2112
(Super-red), PDSP2113 (Green), and PDSP2114 (High
Efficiency Green) are eight digit, 5 x 7 dot matrix, parallel
input, alphanumeric Intelligent Display devices. The
5.10 mm (0.200’’) high digits are packaged in a rugged,
high quality, optically transparent, 15.24 mm (0.6’’) lead
spacing, 28 pin plastic DIP.
The on-board CMOS has a built-in 256 character ROM.
Both pages are mask programmable for 256 custom
characters.The first page of ROM of a standard product
contains 128 characters including ASCII, selected Euro-
pean and Scientific symbols. The second page contains
Katakana Japanese characters, more European charac-
ters, Avionics, and other graphic symbols .
The PDSP211X is design ed f or standard micro processor
interf ace techniques, and is fully TTL compatible. The
Clock I/O and Clock Select pins allow the user to cas-
cade multiple display modules.
FEATURES
• Eight 5.10 mm (0.200’’) Dot Matrix Characters in Red,
Yellow, Super-red, Green, High
Efficiency Green
• Built-in 2 Page, 256 Character ROM,
Both pages are Mask Programmable for
Custom Fonts
• Readable from 2.5 meters (8 feet)
• Built-in Decoders, Multiplexers and Drivers
• Wide Viewing Angle, X Axis ± 55°, Y Axis ± 65°
• Programmable Features:
– Individual Flashing Character
– Full Display Blinking
– Multi-Level Dimmi ng and Blanking
– Clear Function
– Lamp Test
• Internal or External Clock
• End Stackable Dual-In-Line Pla sti c Package
2006-01-23 2
PDSP2110, PDSP2111, PDSP2112, PDSP2113, PDSP2114
Package Outlines Dimensions in mm (inch)
Ordering Information
Type Color of Emission Character Height
mm (inch) Ordering Code
PDSP2110 red
5.10 (0.200)
Q68000A8474
PDSP2111 yellow Q68000A8503
PDSP2112 super-red Q68000A8504
PDSP2113 green Q68000A8505
PDSP2114 high efficiency green Q68000A8533
IDOD5020
19.58 (0.771)
5.34 (0.210)
42.67 (1.680) max. 2.67 (0.105)
4.81 (0.189)
9.8 (0.386)
Pin 1
Indicator
5.31 (0.209)
15.24 (0.600)
0.3 (0.012) typ.
2.19 (0.086)
4.79 (0.189) 2.54 (0.100) typ. 0.46 (0.018) typ.
4.06 (0.160)
±0.5 (0.020)
PDSP211X Z
OSRAM YYWW V Y
Part Number Code
EIA Date Intensity
Code Color Bin
PDSP2110, PDSP2111, PDSP2112, PDSP2113, PDSP2114
2006-01-23 3
Maximum Ratings (TA=25°C)
Parameter Symbol Value Unit
Operating temperatur e range Top – 40 … + 85 °C
Storage temperature range Tstg – 40 … + 100 °C
DC Supply Voltage, VCC to GND
(max. voltage with no LEDs on) VCC -0.5 to + 7.0 V
Input Voltage Levels Relative to GND -0.5 to VCC + 0.5 V
Solder Temperature
1.59 mm (0.063“) below seating plane, t < 5.0 s TS260 °C
Relative Humidity (non-condensing) 85 %
Optical Characteristics at 25°C
(VCC=5.0 V at 100% brightness level)
Description Symbol Values Unit
Red
PDSP2110
Yellow
PDSP2111
Super-red
PDSP2112
Green
PDSP2113
High Efficiency Green
PDSP2114
Peak Luminous Intensity1) (min.)
(typ.) IVpeak 70
90 130
210 150
330 150
260 200
510 µcd/dot
µcd/dot
Peak Wavelength (typ.) λpeak 660 583 630 565 568 nm
Dominant Wavelength (typ.) λdom 639 585 626 570 574 nm
Note:
1) Peak luminous intensity is measured at TA=TJ=25°C. No time is allowed for the device to warm up prior to measurement.
PDSP2110, PDSP2111, PDSP2112, PDSP2113, PDSP2114
2006-01-23 4
Enlarged Character Font Dimensions in inch (mm)
Write Cycle Timing Diagram
Notes:
1. All input voltages are VIL=0.8 V, VIH=2.0 V.
2. These wave forms are not edge triggered.
3. Tbw=Tas+Tah
IDOD5202
C1 C2 C3 C4 C5 R1
R2
R3
R4
R5
R6
R7
2.85 (0.112)
0.76 (0.030) typ.
0.65 (0.026) typ.
4.81 (0.189)
0.254 (0.010)
IDTC5054
Data Wait Data
Write control word -
clear bit enabled Wait 130 ns clear bit enabled
Write control word -
Switching Specifications
(over operating temperature range and VCC=4.5 V)
Symbol Description Min. Units
Tbw Time Between Writes 30 ns
Tacc (2) Display Access Time 130 ns
Tas Address Setup Time 10 ns
Tces Chip Enable Setup Time 0ns
Tah Address Hold Time 20 ns
Tceh Chip Enable Hold Time 0ns
TwWrite Active Time 100 ns
Tds Data Valid Prior to Rising Edge
of Write 50 ns
Tdh Data Hold Time 20 ns
Trc (1) Reset Active Time 300 ns
Tclr (3 ) Clear Cycle Time 3.0 µs
Notes:
1) Wait 300 ns min. after the reset function is turned off.
2) Tacc=Tas+Tw+Tah
3) The Clear Cycle Time may be shorten ed by writing a se cond
Control Word w ith t he Clea r Bit di sabl ed, 16 0 ns afte r the f irst
control word that enabled the Clear Bit.
The Flash RAM and Character RAM may not be accessed
until the Clear Cycle is complete.
Tas Tah
Tceh
Tces
Tw
Tdh
Tds
Tbw
CE
D7-D0
WR
FL, A3-A0 see Notes
Tacc
see Notes
see Notes
see Notes
PDSP2110, PDSP2111, PDSP2112, PDSP2113, PDSP2114
2006-01-23 5
Electrical Characteristics at 25°C
Parameters Limits Conditions
Min. Typ. Max. Units
VCC 4.5 5.0 5.5 V —
ICC Blank —0.5 1.0 mA VCC=5.0 V, VIN=5.0 V
ICC 8 digits1)
12 dots/character —200 255 mA VCC=5.0 V, “V” di spl a yed i n
all eight digits
ICC 8 digits1)
20 dots/character —300 370 mA VCC=5.0 V, “#” displayed in
all eight digits
IIP Curre nt
(with pull-up) —11 18 µAVCC=5.0 V, VIN=0 V to VCC
(WR, CE, FL, RST, CLKSEL)
I, Input Leakage Current
(no pull-up) ——±1.0 µAVCC=5.0 V,VIN=0 V to VCC
(Clk I/O, A0–A3, D0–D7)
VIH Input Voltage High 2.0 —VCC
+0.3 VVCC=4.5 V to 5.5 V
VIL Input Voltage Low GND
–0.3 —0.8 VVCC=4.5 V to 5.5 V
VOL Output Vo ltage Low
(Clock Pin) ——0.4 VVCC=4.5 V to 5.5 V
IOL=1.6 mA
VOH Output Voltage High
(Clock Pin) 2.4 — — V VCC=4.5 V to 5.5 V
IOH=40 mA
IOH Output Current High
(Clock I/O) –0.9 — — mA VCC=4.5 V, VOH=–2.4 V
IOL Output Current Low
(Clock I/O) 1.6 2.0 —mA VCC=4.5 V, VOL=–0.4 V
θJC Thermal Resistance
Junction to Case —25 —°C/W —
FEXT External Clock
Input Frequency2) 28 —81.14 kHz VCC=5.0 V, CLKSEL=0
FOSC Internal Clock
Output Frequency2) 28 —81.14 kHz VCC=5.0 V, CLKSEL=1
Clock I/ O Buss Loading ——240 pF —
Clock Out Rise Time ——500 ns VCC=4.5 V, VOH=2 .4 V
Clock Out Fall Time ——500 ns VCC=4.5 V, VOL=0.4 V
FM, Digit Multiplex Frequency 125 256 362.5 Hz —
Blinking Rate 0.98 2.0 2.83 Hz —
Notes:
1) Average ICC measured at full brightness. Peak ICC=2 x IAVG ICC (# displayed).
2) Internal/exter na l fr equ en cy duty facto r is 50% .
PDSP2110, PDSP2111, PDSP2112, PDSP2113, PDSP2114
2006-01-23 6
Top View
Pin Assignments
Pin Function Pin Function
1RST 28 D7
2FL 27 D6
3A0 26 D5
4A1 25 D4
5A2 24 D3
6A3 23 D2
7Substr. bias 22 No Pin
821
920 D1
10 No Connect 19 D0
11 CLKSEL 18 No Connect
12 CLK I/O 17 CE
13 WR 16 GND (logic)
14 VCC 15 GND (supply)
IDPA5116
01234567
Digit
Pins1
28 Pins 15
14
Pin Definitions
Pin Function Definition
1RST Used for initialization of a display and
sychronization of blinking for multiple displays
2FL Low input accesses the Flash RAM
3A0 Address input LSB
4A1 Address input
5A2 Address input MSB
6A3 Mode selector
7-9 Substr. bias Used to bias IC substrate, must be connected
to VCC. Can't be used to supply power to
display.
10 No connect —
11 CLKSEL Selects internal/external clock source
12 CLK I/O Outputs master clock or inputs external clock
13 WR A low will write data into the di splay if CE is
low
14 VCC Positive power supply input
15 GND Analog Ground for LED drivers
16 GND Digital Ground for internal logic
17 CE Enables access to the display
18 No Connect —
19 D0 Data input LSB
20 D1 Data input
21 No pin —
22
23 D2 Data input
24 D3
25 D4
26 D5
27 D6
28 D7 Data input MSB, selects ROM, page 1 or 2
PDSP2110, PDSP2111, PDSP2112, PDSP2113, PDSP2114
2006-01-23 7
Cascading the PDSP211X Di spla ys
IDCD5031
RD WR FL CLK CLK
Display
CC
V
D0-D7 A0-A4 CE
Up to 14 more
displays in between
I/O SEL
CE
Display
D0-D7 A0-A4
Data I/O
Address
Decoder
Address Address Decode Chip 1 to 14
A6
A7
A9
WR
FL
RST
RST
0
15
RD
RSTRD WR FL CLK
SEL
CLK
I/O
A8
2006-01-23 8
PDSP2110, PDSP2111, PDSP2112, PDSP2113, PDSP2114
Character Set
ROM Page 1 (D7= 0)
ROM Page 2 (D7=1)
IDCS5093
ASCII
CODE
D0
D1
D2
D3
HEX
D4D5D6
0000
1
100
2
010
3
011
4
100
5
101
6
110
7
111
0
0
0
0
01
0
0
1
0
2
0
0
0
1
3
0
0
1
1
4
0
1
0
0
5
0
1
1
0
6
0
1
0
1
7
0
1
1
1
8
1
0
0
0
9
1
0
1
0
A
1
0
0
1
B
1
0
1
1
C
1
1
0
0
D
1
1
1
0
E
1
1
0
1
F
1
1
1
1
IDCS5094
ASC||
CODE
D0
D1
D2
D3
HEX
D4D5D6
0000
1
100
2
010
3
011
4
100
5
101
6
110
7
111
0
0
0
0
01
0
0
1
0
2
0
0
0
1
3
0
0
1
1
4
0
1
0
0
5
0
1
1
0
6
0
1
0
1
7
0
1
1
1
8
1
0
0
0
9
1
0
1
0
A
1
0
0
1
B
1
0
1
1
C
1
1
0
0
D
1
1
1
0
E
1
1
0
1
F
1
1
1
1
PDSP2110, PDSP2111, PDSP2112, PDSP2113, PDSP2114
2006-01-23 9
Block Diagram
Functional Description
The PDSP211X block d ia g ram is comprised of the following maj or
blocks and registers.
Display Memory consists of a 8 x 8 bit RAM block. Each of the
eight 8-bit words holds the 7-bit ASCII data (bit D0-D6). The 8th
bit, D7 selects 1 of the 2 pages of character ROM. D7=0 selects
Page 1 of the ROM and D7=1 selects Page 2 of the ROM. A3=1.
RST can be used to initialize display operation upon power up or
during normal operation. Whe n acti vated, RST will clear the Flash
RAM and Control Word Register (00H) and reset the internal
counter. All eight display memory locations will be set to 20H to
show blanks in all digits.
FL pin enab les a ccess to t he Flash RAM. The Flash RAM will set
(D0=0) or reset (D0=0) flashing of the character addressed by
A0-A2.
The 1 x 8 bit Control Word RAM is loaded with attribute data
if A3=0.
The Control Word Logic decodes attribute data for prop er imple-
mentation.
Character ROM is designed f or two pa ges of 128 chara cters each.
Both pages of the R OM are Mask P rog ram mable f or cust om fonts .
On the standard product page one contains standard ASCII,
selected European characters and some scientific symbols. Page
two contains Kat akana char acters , more Eur opean char acters , a vi-
onics, and other graphic symbols.
The Clock Source could either be the internal oscillator
(CLKSEL=1) of the device or an external clock (CLKSEL=0) could
be an input from another PDSP 21 1X displ ay for the synchroniza-
tion of blinking for multiple displays.
The Displa y Multiplex er controls the Row Drivers so no additional
logic is required for a display system.
The Display has eight digits. Each digit has 35 LEDs clustered
into a 5 x 7 dot matrix.
Theory of O p er ation
The PDSP211X Progr ammab le displa y is d esigned to w ork with all
major microprocessors. Data entry is via an eight bit parallel bus.
Three bits of address route the data to the proper digit location in
the RAM. Standard control signals like WR and CE allow the data
to be written into the display.
D0- D7 data bits are used for both ASCII and control word data
input. A3 acts as the mode selector. If A3=0, D0-D7 load the RAM
with control word data. If A3=1, D0-D7 will load the RAM with
ASCII and page select d at a. I n t he late r mode, D7=0 selects Page
1 of Character ROM and D7=1 selects Page 2 of Character ROM.
For normal op eration FL pin should be held high. When FL is held
low, Flash RAM is access ed to set char acter blinking.
The seven bit ASCII code is decoded by the Character ROM to
generate Column data. Twenty columns worth of data is sent out
each displa y cycle and it takes fourteen display cycles to write into
eight digits.
The rows are being multiplexed in two sets of seven rows each.
The internal timing and control logi c synchroniz es the turning on of
rows and presentation of column data to assure proper display
operation.
IDBD5068
Display
Memory
8 x 8 bits
D0
D4
D2
D1
D3
D6
D5
D7
Control Word
Decode
Logic
Latches
7-bit
Code
Flash RAM
8 x 1 bit
Address
Address Decoder
A0 A1 A2 A3 WR CE FL
Column Decoder
Character
Decode
(4.48 kbits)
ROM 1
ASCII
128 x 7 bit ASCII
Character
(4.48 kbits)
Decode
128 x 7 bit
ROM 2
Row Decoder
Data
Master
Slave
Latches
Digit
0 to 8
Column
Drivers
0 to 8
for Digit
Column
Lines
Control
Word
ASCII
OSC Counter
32
Counter 7Counter
128
CLK I/O
CLKSEL
RST
MUX Rate
Rate
Blink
Row Control Logic
& Row Drivers
Control
Timing &
Logic
Rows
0
Display
312
0 to 13
654 7
Columns 0 to 19
PDSP2110, PDSP2111, PDSP2112, PDSP2113, PDSP2114
2006-01-23 10
Power up Sequence
Upon power up display will come on at random. Thus the display
should be reset on power-up. The reset will clear the Flash RAM,
Control Word Register and reset the internal counter. All the dig-
its will show blanks and display brightness level will be 100%.
Microprocessor Interface
The interface to a microprocessor is through the 8-bit data bus
(D0-D7), the 4-bit address bus (A0-A3) and control lines FL , CE
and WR.
To write data (ASCII/ Control Word) into the display CE should be
held low, address and data signals stable and WR should be
brought low.
The Control Word is decoded by the Control Word Decode Logic.
Each code has a d iff erent functi on. The code f or displa y brightness
changes the duty cycle for the column drivers. The peak LED cur-
rent stays the same but the average LED current diminishes
depending on the intensity level.
The chara cter Fl ash En able causes 2.0 Hz coming o ut o f th e
counter to be A N DE D wit h co l um n d riv e signal and makes t he col -
umn driver to cycle a t 2. 0 Hz. Thus the character flashes at 2.0 Hz.
The display Blink works the same way as the Flash Enable but
causes all twenty column drivers to cycle a t 2.0 Hz thereb y ma king
all eight digits to blink at 2.0 Hz.
The Lamp Test causes the column drivers to run at 1/2 duty cycle
thus all the LEDs in all eight d igits turn on at 50% intensity.
Clear bit clears the character RAM and writes a blank into the dis-
play memory. It however does not clear the control word.
ASCII Data or Control Word Data can be written into the display at
this point. For multiple displa y operation, CLK I/O must be properly
selected. CLK I/O will output the internal clock if CLKSEL=1, or will
allow input from an external clock if CLKSEL=0.
Data Input Commands
Signals
CE WR FL A3 A2 A1 A0 Operation
1 XXXXXX
X 1XXXXX No operation
No operation
0 010000 Write Co nt r o l Register
0 011000
0 011001
0 011010
0 011011
0 011100
0 011101
0 111100
0 011111
Digit 0 (left)
Digit 1
Digit 2
Digit 3
Digit 4
Digit 5
Digit 6
Digit 7 (right)
Write display data to
user RAM and Page
Select Register
D0–D6=ASCII Data
D7=0 Select ROM 1
D7=1 Select ROM 2
0 00X000
0 00X001
0 00X010
0 00X111
0 00X100
0 00X101
0 00X110
0 00X111
Digit 0 (left)
Digit 1
Digit 2
Digit 3
Digit 4
Digit 5
Digit 6
Digit 7 (right)
Write Flash RAM Register
D0=0 Flashing Charac. off
D0=1 Flashing Charac. on
D1–D7=X
X=Don’t care
PDSP2110, PDSP2111, PDSP2112, PDSP2113, PDSP2114
2006-01-23 11
Control Word Format
Flash RAM Function
Character Flash is controlled by FL pin, bit D0 and control word bit D3. Combination of FL being low, proper digit address and D0 being
high will write a flash bit into the Flash RAM Register. In the control word mode when D3 is brought high, the above mentioned character
will flash.
Display Brightness
The display can be programmed to vary between blank, 13%, 20%, 27%, 40%, 53%, 80% and full brightness.
Bits D0, D1 and D2 control the display brightness.
CE WR FL A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Display Brightness
001
001
001
001
001
001
001
001
0X X X
0X X X
0X X X
0X X X
0X X X
0X X X
0X X X
0X X X
0 0XXX000
0 0XXX001
0 0XXX010
0 0XXX011
0 0XXX100
0 0XXX101
0 0XXX110
0 0XXX111
100% Brightness
80% Brightness
53% Brightness
40% Brightness
27% Brightness
20% Brightness
13% Brightness
Blank Display
X=Don’t Care
Setting the Flas h B it
CE WR FL A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation
000
000
XA A A
XA A A
X XXXXXX0
X XXXXXX1
Flash RAM Disabled
Flash RAM Enabled
X=Don’t Care A=Select ed Add re ss
Character Flash Control Word
CE WR FL A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation
001
0010X X X
0X X X
0 0X00BBB
0 0X01BBB
Disable Flashing Character
Enable Flashing Character
X=Don’t Care B=Sel ect ed Br ig ht ness
Display Blinking
Blinking Function is independent of Flash function. When D4 is held high, entire display blinks at 2.0 Hz.
CE WR FL A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation
001
0010X X X
0X X X
0 0X00BBB
0 0X10BBB
Display Blinking Disabled
Display Blinking Enabled
X=Don’t Care B=Sel ect ed Br ig ht ness
Lamp Test
Bit D6 when brought high wi ll cause all the LEDs in all eight digits to light up at 53% brightness.
Selecting or de-selecting Lamp Test bit has no effect on the display memory.
CE WR FL A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation
001
001
0X X X
0X X X
0 0X0XXXX
0 1X00XXX
Lamp Test Disabled
Lamp Test Enabled
X=Don’t Care
2006-01-23 12
PDSP2110, PDSP2111, PDSP2112, PDSP2113, PDSP2114
Control Word Format
Clear Function
Clear function will clear the display. The Flash RAM will be set to all zeros. An ASCII blank code (20H) will be written into the display
memory. The user must wait 3.0 ms or wr ite a new control word to the display with con trol word bit D7 = 0 to disable clear before writing
any data to the display memory, otherwise a ll new data to the display memory will rema in cleared. See Switching Specifications for clear
function timing.
CE WR FL A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation
001
001
0X X X
0X X X
0 XXXXXXX
1 XXXXXXX
Clear Disabled
Clear User RAM,
Page RAM, Flash
RAM and Display
X=Don’t Care
IDCW5164
Enable
BlinkLamp
Enable Brightness Control
D7 D6 D5 D4 D3 D2 D1 D0
D1 D0 Brightness
100% 0080%01
1 53%0
1 40%1
Disable Flashing Character
Flash EnableD3
0Enable Flashing Character1
Enable Blinking Display
Disable Blinking Display
Blinking Display
D4
1
0
Disable Lamp Test
Enable Lamp Test (all dots on at 53% brightness)
Lamp Test
Enable Clear (clear Data RAM, Page RAM, Flash RAM)
Disable Clear0
1
Clear EnableD7
Clear Flash
Enable
D2
0
0
0
0
27%
0% Blank11
1
11
0
10
1
0
1 20%
13%
0
0
1
D6
Test Not Used
PDSP2110, PDSP2111, PDSP2112, PDSP2113, PDSP2114
2006-01-23 13
Electrical and Mechanical Considerations
Voltage Transient Suppression
For best results power the display and the components that inter-
face with the display to avoid logic inputs higher than VCC. Addi-
tionally, the LEDs may cause transients in the power supply line
while they change display states. The common practice is to place
a parallel combin ation of a 0.01 µF an d a 22 µF capacitor between
VCC and GND for all display packa ge s.
ESD Protection
The input protection structure of the PDSP2110/1/2/3/4 provides
significant protection against ESD damage. It is capable of with-
standing discharges greater than 2.0 kV. Take all the standard pre-
cautions, normal for CMOS components. These include properly
grounding personnel, tools, tables, and transport carriers that come
in contact with unshielded parts. If these conditions are not, or can-
not be met, keep the leads of the device shorted together or the
parts in anti-static packaging.
Soldering Considerations
The PDSP2110/1/2/3/4 can be hand soldered with SN63 solder
using a grounded iron set to 260°C.
Wave soldering is also possible following these conditions: Pre-
heat that does n ot e xceed 93°C on t he solder side of t he PC boar d
or a package surface temperature of 85°C. Water soluble organic
acid flux (except carboxylic acid) or rosin-based RMA flux without
alcohol can be used.
Wave temper at ure o f 2 45°C ± 5°C with a dwell betw ee n 1.5 sec. to
3.0 sec. Exposu re to the wave should no t exceed temperat ur es
above 260°C for five seconds at 1.59 mm (0.063") belo w the seating
plane. The p ackages should not be immer se d in the wave.
Po st Solder Cl eaning Procedures
The least offensive cleaning solution is hot D.I. water (60 °C) for
less than 15 minutes. Addition of mild saponifiers is acceptable.
Do not use commercial dishwa sher detergents.
For faster cleaning, solvents may be used. Exercise care in choos-
ing solvents as some may chemically attack the nylon package.
Maximum exposure should not exceed two minutes at elevated
temperatur es. Acceptable solv e nt s are TF (t richoro t rifluorethane),
TA, 111 Trichloroethane, and unheated acetone.(1)
Note:
1) Acceptable commercial solvents are: Basic TF, Arklone, P.
Genesolv, D. Genesolv DA, Blaco-Tron TF and Blaco-Tron TA.
Unacceptable solvents contai n alcohol, methanol, methylene
chloride, ethanol, TP35, TCM, TMC, TMS+, TE, or TES. Since
many commercial mixtures exist, contact a solvent vendor for
chemical co mpos itio n infor ma tio n. So me maj or so lvent manufac-
turers are: Allied Chemical Co rporation, Speci alty Chemi cal Divi-
sion, Morristown, NJ; Bar on-Blakeslee, Chicago, IL; Dow
Chemical, Midland, MI; E.I. DuPont de Nemours & Co., Wilming-
ton, DE.
For further information refer to Appnote s 18 and 19 at
www.osram-os.com
An alternative to sold ering and cleaning the display modules is to
use sock ets. Naturally, 28 pin DIP sockets 1 5 .2 4 m m (0.600") wide
with 2.54 mm (0.100") centers work well for single displays.
Multiple display assemblies are best handled by longer SIP sock-
ets or DIP sockets when available for uniform package alignment.
Socket manufacturers are Aries Electronics, Inc., Frenchtown, NJ;
Garry Manufa ctu ring, N ew Brunswic k, N J; R o binso n- N ug ent , N ew
Albany, IN; and Samtec Electronic Hardward, New Albany, IN.
For further information refer to Appnote 22 at www.osram-os.com
Optical Considerations
The 5.10 mm ( 0.200" ) high chara cter of th e PDSP211X gi v es read -
ability up to eight feet. Proper filter selection enh anc es readability
over this distance.
Using filters emphasizes the contrast ratio between a lit LED and
the character background. This will increase the discrimination of
different characters. The only limitation is cost. Take into consider-
ation the ambient lighting environment for the best cost/benefit
ratio for filters.
Incandescent (wit h almost no g reen) or fluorescent (w ith almost no
red) lights do not have the flat spectral response of sunlight. Plas-
tic band-pass filter s are an in expensive an d effective w ay to
strengthen contr ast ratios . The PDSP 2110/2112 ar e red/super -red
displays and should be matched with long wavelength pass filter in
the 570 nm to 590 nm range. The PDSP2111/2113/2114 should
be matched with a yellow-green band-pass filter that peaks at
565 nm. For displays of multiple colors, neutral density grey filters
offer the best compromise.
Additional contrast enhancement is gained by shading the dis-
plays. Plastic band-pass filters with built-in louvers offe r the next
step up in contrast improvement. Plastic filters can be improved
further with anti-refle ctive coatings to re duce glare . The trad e-off is
fuzzy characters. Mounting the filters close to the display reduces
this effect. Tak e care not to overhe at the plastic filter by allowing f or
proper air flow.
Optimal filter enhancements are gained by using circular polar-
ized, anti-ref lective, band-pass filters. The circular polarizing fur-
ther enhances contrast by reducing the light that travels through
the filter and reflects back off the display to less than 1%.
Several filter manufacturers supply quality filter materials. Some of
them are: Panelgraphic Corporation, W. Caldwell, NJ; SGL Homa-
lite, Wilmington, DE; 3M Company, Visual Products Division, St.
Paul, MN; Polaroid Corporation, Polarizer Division, Cambridge,
MA; Marks Polarized Corporation, Deer Park, NY, Hoya Optics,
Inc., Fremont, CA.
One last note on mounting filters: recessing displays and bezel
assemblies is an inexpensive way to provide a shading effect in
overhead lighting situations. Several bezel manufacturers are:
R.M.F. Products, Batavia, IL; Nobex Components, Griffith Plastic
Corp., Burlingame, CA; Photo Chemical Prod ucts of Califor nia,
Santa Monica, CA; I.E.E.–Atlas, Van Nuys, CA.
2006-01-23 14
PDSP2110, PDSP2111, PDSP2112, PDSP2113, PDSP2114
Published by
OSRAM Opto Semiconductors GmbH
Wernerwerkstrasse 2, D-93049 Regensburg
www.osram-os.com
© All Rights Reserved.
Attention please!
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved. Due to technical requirements components may contain
dangerous substances. For information on the types in question please contact our Sales Organization.
If printed or downloaded, please find the late st version in the Internet.
Packing
Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office.
By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing
material that is retu rned to us unsorted or which we are not obliged to a ccept, we shall have t o invoice you for any costs
incurred.
Components used in life-support devices or systems must be expressly authorized for such purpose! Critical
components1) may only be used in life-support devices or systems2) with the express written approval of OSRAM OS.
1) A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the
failure of that life-support device or system, or to affect its safety or the effectiveness of that device or system.
2) Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain
human life. If they fail, it is reasonable to assume that the health and the life of the user may be endangered.
Revision History: 2006-01-23
Previous Version: 2005-01-10
Page Subjects (major changes since last revision) Date of change
all Lead free device 2006-01-23
