CYRF69313
Programmable Radio-on-Chip LPstar
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 001-66503 Rev. *B Revised February 28, 20 12
Features
■Radio System-on-Chip, with built-in 8-bit MCU in a single
device.
■Operates in the unlicensed worldwide Industrial, Scientific, and
Medical (ISM) band (2.400 GHz to 2.483 GHz).
■On Air compatible with second generation radio
WirelessUSB™ LP and PRoC LP.
■Pin-to-pin compatible with PRoC LP except the Pin31 and
Pin37.
Intelligent
■M8C based 8-bit CPU, optimized for human interface devices
(HID) applications
■256 bytes of SRAM
■8 Kbytes of flash memory with EEPROM emulation
■In-System reprogrammable through D+/D– pins
■CPU speed up to 12 MHz
■16-bit free running timer
■Low power wakeup timer
■12-bit programmable interval timer with interrupts
■Watchdog timer
Low Power
■21 mA operating current (Transmit at –5 dBm)
■Sleep current less than 1 µA
■Operating voltage from 4.0 V to 5.25 V DC
■Fast startup and fast channel changes
■Supports coin-cell operated applications
Reliable and Robust
■Receive sensitivity typical –90 dBm
■ AutoRate™ – dynamic data rate reception
❐Enables data reception for any of the supported bit rates
automatically.
❐DSSS (250 Kbps), GFSK (1 Mbps)
■ Operating temperature from 0 °C to 70 °C
■ Closed-loop frequency synthesis for minimal frequency drift
Simple Development
■Auto transaction sequencer (ATS): MCU can stay sleeping
longer to save power
■Framing, length, CRC16, and Auto ACK
■Separate 16 byte transmit and receive FIFOs
■Receive signal strength indication (RSSI)
■Built-in serial peripheral interface (SPI) control while in sleep
mode
■Advanced development tools based on Cypress’s PSoC® T ools
■Flexible I/O
■2 mA source current on all GPIO pins. Configurab le 8 mA or
50 mA/pin current sink on designated pins
■Each GPIO pin supports high impedance inputs, configurable
pull-up, open-drain output, CMOS/TTL inputs, and CMOS
output
■Maskable in terrupts on all I/O pin s
BOM Savings
■Low external component count
■Small footprint 40-pin QFN (6 mm × 6 mm)
■GPIOs that require no external components
■Operates off a single crystal
■Integrated 3.3 V regulator
■Integrated pull-up on D-
USB Specific ation Compliance
■Conforms to USB specification version 2.0
■Conforms to USB HID specification version 1.1
■Supports one low speed USB device address
■Supports one control endpoint and two data end points
■Integrated USB transceiver
Applications
■Wireless keyboards and mice
■Presentation tools
■Wireless gamepads
■Remote controls
■Toys
■Fitness
CYRF69313
Document #: 001-66503 Rev. *B Page 2 of 78
Microcontroller
Function Radio
Function
RFn
RFp
RFbias
Xtal
12MHz
VBat0
RESV
VSS
P0_1,3,4,7
P1_6:7
P2_0:1
GND
. . . . . . .
IRQ/GPIO
MISO/GPIO
XOUT/GPIO
GND
Vbus
VDD_MICRO
D+/D-
P1.2 / VReg
P1.5/MOSI
P1.4/SCK
P1.3/nSS
RST
MOSI
SCK
nSS
VBat1
VBat2
VCC1
VCC2
VCC3
VIO
GND
. . . . .
2
2
2
4
1ohm
VCC4
Logic Block Diagram
CYRF69313
Document #: 001-66503 Rev. *B Page 3 of 78
Contents
Functional Description ................... ... .............. ... .. ............4
Functional Overview .............. .............. .. ... .......................4
2.4 GHz Radio Function ............ ............................ ... ...4
USB Microcontroller Function ......................................4
Backward Compatibility ...............................................4
Pinouts ..............................................................................5
Pin Configuration .............................................................5
PRoC LPstar Functional Ov erv i ew .................................6
Functional Block Overview ....................... ... ... .................7
2.4 GHz Radio ............. .............. ... ............................ ...7
Frequency Synthesizer ................................................7
Baseband and Framer ....................... ..........................7
Packet Buffers .............................................................8
Auto Transaction Sequencer (ATS) ............................8
Interrupts .....................................................................8
Clocks ..........................................................................8
GPIO Interface ............................................................8
Power-on Reset ...........................................................9
Power Management ............... .....................................9
Timers .........................................................................9
USB Interface ..............................................................9
Low Noise Amplifier (LNA) and Received
Signal Strength Indication (RSSI) .......................................9
SPI Interface ............. ............... .. ............................ ............9
3-Wire SPI Interface ....................................................9
Four-Wire SPI Interface .............................................10
SPI Communication and Transactions ......................10
SPI I/O Voltage References .............. ... ... ... ...............10
SPI Connects to External Devices ............................10
CPU Architecture ................. ... .. ......................................11
CPU Registers ......................... ............................ ............12
Flags Register ............. ............................ ... ... ............12
Accumulator Register ................................................12
Index Register ............. ............................ ... ... ............12
Stack Pointer Register ...............................................13
CPU Program Counter High Register .......................13
CPU Program Counter Low Register ........................13
Addressing Modes .........................................................14
Source Immediate .......... ............................ ... .. ..........14
Source Direct ............ ... .............. ... .............. ... .. ..........14
Source Indexed .............. ... ........................................14
Destination Direct ......................... ... .............. .. ... .......14
Destination Indexed ...................................................15
Destination Direct Source Immediate ........................15
Destination Indexed Source Immediate ....................15
Destination Direct Source Direct ...............................15
Source Indirect Pos t Incr ement ................................. 16
Destination Indirect Post Increment ................... ... ....16
Instruction Set Summary ...............................................17
Memory Organization ...................................... ... ............18
Flash Program Memory Organization .......................18
Data Memory Organization .......................................19
Flash ..........................................................................19
SROM ........................................................................19
SROM Function Descriptions ....................................20
SROM Table Read Description ............ .. ... .............. ... ... .23
Clocking ..........................................................................24
Clock Architecture Description ..................................25
CPU Clock During Sleep Mode ......................... ... .....31
Reset ................................................................................31
Power-on Reset ..............................................................33
Watchdog Timer Reset ..............................................33
Sleep Mode ......................................................................33
Sleep Sequence ........................................................33
Wakeup Sequence ....................................................34
Low Power in Sleep Mode .........................................34
Power-on Reset Control ................................................36
POR Compare State .................................................36
ECO Trim Register ....................................................36
General-Purpose I/O Ports .............................................37
Port Data Registers ...................................................37
GPIO Port Configuration ...........................................38
GPIO Configurations for Low Power Mode: ..............42
Serial Peripheral Interface (SPI) ....................................43
SPI Data Register ......................................................44
SPI Configure Register .............................................44
Timer Registers ..............................................................46
Registers ...................................................................46
Interrupt Controller .........................................................49
Architectural Description ...........................................49
Interrupt Processing ..................................................50
Interrupt Latency .......................................................50
Interrupt Registers .....................................................50
USB Transceiver ..... ... .....................................................54
USB Transceiver Configuration .................................54
USB Serial Interface Engine (SIE) .................................54
USB Device ....... ... ... ............................ ... ... ......................55
Endpoint 0 Mode ........................... ... ... ......................56
Endpoint Data Buffers ......................... ......................58
USB Mode Tables ....................... .. ... ............................ ...59
Mode Column ............................................................59
Encoding Column ......................................................59
SETUP, IN, and OUT Columns ................... ... ... ... .....59
Details of Mode for Differing Traffic Conditions ..........60
Register Summary ..... ... ..................................................62
Radio Function Register Descripti on s .................... .. ...64
Absolute Maximum Ratings ..........................................65
DC Characteristics (T = 25 °C) ......................... ... ... ........65
RF Characteristics ..........................................................67
AC Test Loads and Waveforms for Digital Pins ..........68
Ordering Information ......................................................74
Ordering Code Definitions .........................................74
Package Handling ...........................................................75
Package Diagram ............................................................75
Acronyms ........................................................................77
Document Conventions .................. ... ............................77
Document History Page ........................ ... .............. ... .. ...78
Sales, Solutions, and Legal Information ......................78
Worldwide Sales and Design Support .......................78
Products .................................................................... 78
PSoC Solutions ............ .............................................78
CYRF69313
Document #: 001-66503 Rev. *B Page 4 of 78
Functional Description
PRoC LPstar devices are integrated radio and microcontroller
functions in the same package to provide a dual role single-chip
solution.
Communication between the microcontroller and the radio is via
the SPI interfac e be tw een both funct i on s.
Functional Overview
The CYRF69313 is a complete Radio System-on-Chip device,
providing a complete RF system solution with a single device and
a few discrete components. The CYRF69313 is designed to
implement low cost wireless systems operating in the worldwide
2.4 GHz Industrial, Scientific, and Medical (ISM) frequency band
(2.400 GHz–2.4835 GHz).
2.4 GHz Radi o Fun c tio n
The SoC contains a 2.4 GHz, 1 Mbps GFSK radio transceiver,
packet data buffering, packet framer , DSSS baseband controller,
Received Signal St rength Indication (RSSI), and SPI interface
for data transfer and device configuration.
The radio supports 98 discrete 1 MHz channels (regulations may
limit the use of some of these channels in certain jurisdictions).
The baseband performs DSSS spreading/despreading, Start of
Packet (SOP), End of Packet (EOP) detection, and CRC16
generation and checking. The baseband may also be configured
to automatically transmit Acknowledge (ACK) handshake
packets whenever a valid packet is received.
When in receive mode, with packet framing enabled, the device
is always ready to receive data transmitted at any of th e
supported bit rates. This enables the implementation of
mixed-rate systems in which different devices use dif ferent data
rates. This also enables the implementation of dynamic data rate
systems that use high data rates at shorter distances or in a
low-moderate interference environment or both. It changes to
lower data rates at longer distances or in high interference
environments or both.
USB Microcontroller Func tion
The microcontroller function is based on the powerful
CYRF69313 microcontroller. It is an 8-bit Flash programmable
microcontroller with integrated low speed USB interface.
The microcontroller has up to 14 GPIO pins to support USB,
PS/2 and other applications. Each GPIO port supports high
impedance inputs, configurable pull-up, open drain output,
CMOS/TTL inputs and CMOS output. Up to two pins support
programmable drive strength of up to 50 mA. Additionally each
I/O pin can be used to generate a GPIO interrupt to the micro-
controller. Each GPIO port has its own GPIO interrupt vector with
the exception of GPIO Port 0.
The microcontroller features an internal oscillator. With the
presence of USB traffic, the internal oscillator can be set to
precisely tune to USB timing require ments (24 MHz ± 1.5%).
The PRoC LPstar has up to 8 Kbytes of Flash for user’s firmware
code and up to 256 bytes of RAM for stack space and user
variables.
Backward Compatibility
The CYRF69313 IC is fully interoperable with the main modes
of the second generation Cypress radio SoC namely the
CYRF6936, CYRF69103 and CYRF69213.
CYRF69313 IC device may transmit data to or receive data
from a second generation device, or both.
CYRF69313
Document #: 001-66503 Rev. *B Page 5 of 78
Pinouts
Figure 1. 40-Pin QFN
RFBIAS
VBAT2
XTAL
P2.1
VCC
VBAT1
P0.4
VCC
P0.1
P0.3
P0.7
P1.6
VBAT0
P1.7
VIO
VDD_1.8
RST
RFN
NC
P2.0
VCC
NC
NC
RESV
NC
GND
RFP
VDD_Micro
P1.3 / SS
P1.4 / SCK
IRQ / GPIO
P1.5 / MOSI
MISO / GPIO
XOUT / GPIO
P1.2
P1.1/D-
P1.0/D+
* E- PAD Bottom Side
21
22
23
24
25
26
27
28
29
30
11
12
13
14
15
16
17
18
19
20
10
9
8
7
6
5
4
3
2
40
39
38
37
36
35
34
33
32
31
1
CYRF69313
PRoC LPstar
Corner
tabs
NC
GND
VCC
Pin Configuration
Pin Name Function
1 P0.4 Individually configured GPIO
2 Xtal_in 12 MHz Crystal. External clock in
3, 7, 16, 40 VCC Connected to pin 24 via 0.047 F capacitor
4 P0.3 Individually configured GPIO
5 P0.1 Individually configured GPIO
6, 9, 39 Vbat Connected to pin 24 via 0.047 Fshunt capacitor
8 P2.1 GPIO. Port 2 Bit 1
10 RF Bias RF pin voltage reference
11 RFpDifferential RF input to/from antenna
12 GND Ground
13 RFnDifferential RF to/from antenna
14, 17, 18, 20, 36 NC
15 P2.0 GPIO. Port 2 Bit 0
19 RESV Reserved. Must connect to GND
21 P1.0 / D+ GPIO 1.0 / Low speed USB I/O
22 P1.1 / D– GPIO 1.1 / Low speed USB I/O
23 VDD_micro 4.0–5.5 for 12 MHz CPU/4.75–5.5 for 24 MHz CPU
24 P1.2 Must be configured as 3.3 V output. It must have a 1–2 F output capacitor
25 P1.3 / nSS Slave select SPI Pin
26 P1.4 / SCK Serial Clock Pin from MCU function to radio function
27 IRQ Interrupt ou tp ut , con fi gure high/ l ow or GPI O
28 P1.5 / MOSI Master Out Slave In
29 MISO Master In Slave Out, from radio function. Can be configured as GPIO
CYRF69313
Document #: 001-66503 Rev. *B Page 6 of 78
PRoC LPstar Functional Overview
The SoC contains a 2.4 GHz 1 Mbps GFSK radio transceiver,
packet data buffering, packet framer , DSSS baseband controller,
Received Signal St rength Indication (RSSI), and SPI interface
for data transfer and device configuration.
The radio supports 98 discrete 1 MHz channels (regulations may
limit the use of some of these channels in certain jurisdictions).
In DSSS modes the baseband performs DSSS
spreading/despreading, while in GFSK Mode (1 Mb/s - GFSK)
the baseband performs Start of Frame (SOF), End of Frame
(EOF) detection and CRC16 generati on and checking. The
baseband may also be configured to automatically transmit
Acknowledge (ACK) handshake packets whenever a valid
packet is received.
When in receive mode, with packet framing enabled, the device
is always ready to receive data transmitted at any of th e
supported bit rates. This enables the implementation of
mixed-rate systems in which different devices use dif ferent data
rates. This also enables the implementation of dynamic data rate
systems that use high data rates at shorter distances or in a
low-moderate interference environment or both. It changes to
lower data rates at longer distances or in high interference
environments or both.
The MCU function is an 8-bit Flash programmable microcon-
troller with integrated low speed U SB interface. The instruction
set has been optimized specifically for USB operations, although
it can be used for a variety of other embedded applications.
The MCU function has up to eight Kbytes of Flash for user’s code
and up to 256 bytes of RAM for stack space and user variables.
In addition, the MCU function includes a Watchdog timer, a
vectored interrupt controller, a 16-bit Free-Running Timer, and
12-bit Programmable Interrupt Timer.
The MCU function supports in-system programming by using the
D+ and D– pins as the serial programming mode interface. The
programming protocol is not USB.
30 XOUT Bufferd CLK or GPIO
31 NC Must be floating
32 P1.6 GPIO. Port 1 Bit 6
33 VIO I/O interface voltage. Connected to pin 24 via 0.047 F
34 Reset Radio Reset. Connected to VDD via 0.47 F capacitor or to microcontroller GPIO pin. Must have
a RESET = HIGH event the very first time power is applied to the radio otherwise the state of
the radio function control registers is unknown
35 P1.7 GPIO. Port 1 Bit 7
36 VDD_1.8 Regulated logic bypass. Connected via 0.47 F to GND
37 GND Must be connected to ground
38 P0.7 GPIO. Port 0 Bit 7
41 E-pad Must be connected to GND
42 Corner Tabs Do not connect corner tabs
Pin Configuration (continued)
Pin Name Function
CYRF69313
Document #: 001-66503 Rev. *B Page 7 of 78
Functional Block Overview
All the blocks that make up the PRoC LPstar are presented here.
2.4 GHz Radio
The radio transceiver is a dual conversion low IF architecture
optimized for power and range/robustness. The radio employs
channel matched filters to achieve high performance in the
presence of interference. An integrated Power Amplifier (PA)
provides up to 0 dBm transmit power, with an output power
control range of 30 dB in six steps. The supply current of the
device is reduced as the RF output power is reduced.
Frequency Synthesizer
Before transmission or reception may commence, it is necessary
for the frequency synthesizer to settle. The settling time varies
depending on channel; 25 fa st channels are provided with a
maximum settling time of 100 s.
The ‘fast channels’ (<100 s settling time) are every th i rd
frequency, starting at 2400 MHz up to and including 2472 MHz
(for example, 0,3,6,9…….69 and 72).
Baseband and Framer
The baseband and framer blocks provide the DSSS encoding
and decoding, SOP generation and reception and CRC16 gener-
ation and checking, and EOP detection and le ngth field.
Data Rates and Data Transmission Modes
The SoC supports two different data transmission modes:
■In GFSK mode, data is transmitted at 1 Mbps, without any
DSSS.
■In DSSS mode eight bits (8DR, 32 chip) are encoded in each
derived code symbol transmitted, resulting in effective
250 Kbps data rate.
32 chip Pseudo Noise (PN) codes are supported. The two data
transmission modes apply to the data after the SOP. In particular
the length, data, and CRC16 are all sent in the same mode. In
general, DSSS reduce packet error rate in any environment.
Link Layer Modes
The CYRF69313 IC device supports the following data packet
framing features:
SOP
Packets begin with a two-symbol SoP marker. If framing is
disabled then an SOP event is inferred whenever two successive
correlations are detected. The SOP_CODE_ADR code used for
the SOP is different from that used for the “body” of the packet,
and if desired may be a different length. SOP must be configured
to be the same length on both sides of the link.
Length
Length field is the first eight bits after the SOP symbol, and is
transmitted at the payload data rate. An EoP condition is inferred
after reception of the number of bytes defined in the length field,
plus two bytes for the CRC16.
CRC16
The device may be configured to append a 16-bit CRC16 to each
packet. The CRC16 uses the USB CRC polynomial with the
added programmability of the seed. If enabled, the receiver
verifies the calculated CRC16 for the payload data against the
received value in the CRC16 field. The starting value for the
CRC16 calculation is configurable, and the CRC16 transmitted
may be calculated using either the loaded seed value or a zero
seed; the received data CRC16 is checked against both the
configured and zero CRC16 seeds.
CRC16 detects the following errors:
■ Any one bit in error
■ Any two bits in error (irrespective of how far apart, which
column, and so on)
■ Any odd number of bits in error (irrespective of the location)
■ An error burst as wide as the checksum itself
Figure 2 shows an example packet with SOP, CRC16 and lengths fields enabled.
Figure 2. Example Default Packet Format
Table 1. Internal PA Output Power Step Table
PA Setting T ypical Output Power (dBm)
60
5–5
4 –10
3 –15
2 –20
1 –25
0 –30
Preamble SOP1 SOP2 <== P a y l o a d ==> CRC 16Length
Preamble N*16us
1st Framing Symbol*
2nd Framing Symbol*
Packet length 1 Byte Period *Note: 32 us
CYRF69313
Document #: 001-66503 Rev. *B Page 8 of 78
Packet Buffers
Packet data and configuration registers are accessed through
the SPI interfac e. All conf i gu ra ti o n re gi ste r s are directly
addressed through the address field in the SPI packet. Configu-
ration registers are provided to allow configuration of DSSS PN
codes, data rate, operating mode, interrupt masks, interrupt
status, and others.
Packet Buffers
All data transmission and reception uses the 16-byte packet
buffers—one for transmission and one for reception.
The transmit buffer allows a complete packet of up to 16 bytes of
payload data to be loaded in one burst SPI transaction,.This is
then transmitted with no further MCU intervention. Similarly, the
receive buffer allows an entire packet of payload data up to 16
bytes to be received with no firmware intervention required until
packet reception is complete.
The CYRF69313 IC supports packet length of up to 40 bytes;
interrupts are provided to allow an MCU to use the transmit and
receive buffers as FIFOs. When transmitting a packet longer
than 16 bytes, the MCU can load 16 bytes initially, and add
further bytes to the transmit buffer as transmission of data
creates space in the buffer. Similarly, when receiving packets
longer than 16 bytes, the MCU function must fetch received data
from the FIFO periodically during packet reception to prevent it
from overflowing.
Auto Transaction Sequencer (ATS)
The CYRF69313 IC prov ides automated support for trans-
mission and reception of acknowledged data packets.
When transmitting a data packet, the device automatically st arts
the crystal and synthesizer, enters transmit mode, transmits the
packet in the transmit buffer, and then automatically switches to
receive mode and waits for a handshake packet—and then
automatically reverts to sleep mode or idle mode when either an
ACK packet is received, or a timeout period expires.
Similarly, when receiving in transaction mode, the device waits
in receive mode for a valid packet to be received, then automat-
ically transitions to transmit mode, transmits an ACK packet, and
then switches back to receive mode to await the next packet. The
contents of the packet buffers are not affected by the trans-
mission or reception of ACK packets.
In each case, the entire packet transaction takes place without
any need for MCU firmware action; to transmit data the MCU
simply needs to load the data packet to be transmitted, set the
length, and set the TX GO bit. Similarly , when receiving packets
in transaction mode, firmware simply needs to retrieve the fu lly
received packet in response to an interrupt request indicating
reception of a packet.
Interrupts
The radio function provi des an interrupt (IRQ) output, which is
configurable to indicate the occurrence of various different
events. The IRQ pin may be programmed to be either active high
or active low, and be either a CMOS or open drain output. The
IRQ pin can be multiplexed on the SPI if routed to an external pin.
The radio function features three sets of interrupts: transmit,
receive, and system interrupts. Thes e interrupts all share a
single pin (IRQ), but can be independently enabled/disabled. In
transmit mode, all receive interrupts are automatically disabled,
and in receive mode all transmit interrupts are automatically
disabled. However, th e contents of the enable registers are
preserved when switching between transmit and receive modes.
If more than one radio interrupt is enabled at any time, it is
necessary to read the relevant status register to determine which
event caused the IRQ pin to assert. Even when an interrupt
source is disabled, the status of the condition that would
otherwise cause an interrupt can be determined by reading the
appropriate status register. It is therefore possible to use the
devices without making use of the IRQ pin by polling the status
register(s) to wait for an event, rather than using th e IRQ pin.
The microcontroller function supports 23 maskable interrupts in
the vectored interrupt controller . Interrupt sources include a USB
bus reset, POR, a programmable interval timer, a 1.024-ms
output from the Free Running Timer, three USB endpoints, two
capture timers, five GPIO Ports, three GPIO pins, two SPI, a
16-bit free running time r wrap, an internal wakeup timer, and a
bus active interrupt. The wakeup timer causes periodic interrupts
when enabled. The USB endpoints interrupt after a USB trans-
action complete is on the bus. The capture timers interrupt
whenever a new timer value is saved due to a selected GPIO
edge event. A total of eight GPIO interrupts support both TTL or
CMOS thresholds. For additional flexibility , on the edge sensitive
GPIO pins, the interrupt polarity is programmable to be either
rising or falling.
Clocks
The radio function has a 12 MHz crystal (30-ppm or better)
directly connected between XT AL and GND without the need for
external capacitors. A digital clock out function is provided, with
selectable output frequencies of 0.75, 1.5, 3, 6, or 12 MHz. This
output may be used to clock an external microcontroller (MCU)
or ASIC. This output is enabled by default, but may be disabled.
Following are the requirements for the crystal to be directly
connected to XTAL pin and GND:
■Nominal Frequency: 12 MHz
■Operating Mode: Fundamental Mode
■Resonance Mode: Parallel Resonant
■Frequency Stability: ±30 pp m
■Series Resistance: <60 ohms
■Load Capacitance: 10 pF
■Drive Level:100 W
The MCU function features an internal oscillator. With the
presence of USB traffic, the internal oscillator can be set to
precisely tune to USB timing requirements (24 MHz ±1.5%). The
clock generator provides the 12 MHz and 24 MHz clocks that
remain internal to the microcontroller.
GPIO Interface
The MCU function features up to 20 general purpose I/O (GPIO)
pins to support USB, PS/2, and other applications. The I/O pins
are grouped into five ports (Port 0 to 4). The pins on Port 0 and
Port 1 may each be configured individually while the pins on
Ports 2, 3, and 4 may only be configured as a group. Each GPIO
port supports high impedance inputs, configurable pull-up, open
CYRF69313
Document #: 001-66503 Rev. *B Page 9 of 78
drain output, CMOS/TTL inputs, and CMOS output with up to five
pins that support programmable drive strength of up to 50 mA
sink current. GPIO Port 1 features four pins that interface at a
voltage level of 3.3 volts. Additionally, each I/O pin can be used
to generate a GPIO interrupt to the microcontroller. Each GPIO
port has its own GPIO interrupt vector with the exception of GPIO
Port 0. GPIO Port 0 has three dedicated pins that have
independent interrupt vectors (P0.3–P0.4).
Power-on Reset
The power-on reset (POR) circuit detects logic when power is
applied to the device, resets the logic to a known state, and
begins executing instructions at Flash address 0x0000. When
power falls below a programmable trip voltage, it generates reset
or may be configured to generate interrupt. The W atchdog timer
can be used to ensure the firmware never gets stalled in an
infinite loop.
Power Management
The device draws its power supply from the USB Vbus line. The
Vbus supplies power to the MCU function, which has an internal
3.3 V regulator. This 3.3 V is supplied to the radio function via
P1.2 after proper filtering as shown in Figure 3
Figure 3. Power Management From Internal Regulat or
Timers
The free-running 16-bit timer provides two interrupt sources: the
programmable interval timer with 1 s resolution and the
1.024 ms outputs. The timer can be used to measure the
duration of an event under firmware control by reading the timer
at the start and at the end of an event, then calculating the
difference between the two values.
USB Interface
The MCU function includes an integrated USB serial interface
engine (SIE) that allows the chip to easily interface to a USB
host. The hardware supports one USB device address with three
endpoints.
Low Noise Amplifier (LNA) and Received
Signal Strength Indication (RSSI)
The gain of the receiver may be controlled directly by clearin g
the AGC EN bit and writing to the low noise amplifier (LNA) bit of
the RX_CFG_ A D R register. When the LNA bi t is cleared, the
receiver gain is reduced by approximately 20 dB, allowing
accurate reception of very strong received signals (for example
when operating a receiver very close to the transmitter). An
additional 20 dB of receiver attenuation can be added by setting
the Attenuation (A TT) bit; this allows data reception to be limited
to devices at very short ranges. Disabling AGC and enabling
LNA is recommended unless receiving fro m a de vice using
external PA.
The RSSI register returns the relative signal strength of the
on-channel signal power.
When receiving, the device may be configured to automatically
measure and store the relative strength of th e signal being
received as a 5-bit value. When enabled, an RSSI read ing is
taken and may be read through the SPI interface. An RSSI
reading is taken automatically when the start of a packet is
detected. In addition, a new RSSI reading is taken every time the
previous reading is read from the RSSI regi ster, allowing the
background RF energy level on any channel to be easily
measured when RSSI is read when no signal is being received.
A new reading can occur as fast as once every 12 s.
SPI Interface
The SPI interface between the MCU function and the radio
function is a 3-wire SPI Interface. The three pins are MOSI
(Master Out Slave In), SCK (Serial Clock), SS (Slave Select).
There is an alternate 4-wire MISO Interface that requires the
connection of two external pins. The SPI interface is control led
by configuring the SPI Configure Regi ster (SICR Address:
0x3D).
3-Wire SPI Interface
The radio function receives a clock from the MCU function on the
SCK pin. The MOSI pin is multiplexed with the MISO pin.
Bidirectional data transfer takes place between the MCU function
and the radio function through this multiplexed MOSI pin. When
using this mode the user firmware should ensure that the MOSI
pin on the MCU function is in a high impedance state, except
when the MCU is actively transmitting data. Firmware must also
control the direction of data flow and switch directions between
MCU function and radio function by setting the SWAP bit [Bit 7]
of the SPI Configure Register. The SS pin is asserted prior to
initiating a data transfer between the MCU function and the radio
function. The IRQ function may be optionally multiplexed with the
MOSI pin; when this option is enabled the IRQ function is not
available while the SS pin is low. When using this configuration,
user firmware should ensure that the MOSI function on MCU
function is in a high impedance state whenever SS is high.
CYRF69313
VBat0
VBat1
VBat2
VCC1
VCC2
VCC3
GND VIO
0.047µF
0.047µF
0.047µF
0.047µF
0.047µF
0.047µF
0.047µF
0.047µF
VDD_MICRO
Vbus
0.1µF
P1.2
1 ohm
VCC4
CYRF69313
Document #: 001-66503 Rev. *B Page 10 of 78
Figure 4. 3-Wi re SPI Mode
Four-Wire SPI Interface
The 4-wire SPI communication s interface consists of MOSI,
MISO, SCK, and SS.
The device receives SCK from the MCU function on the SCK pin.
Data from the MCU function is shifted in on the MOSI pin. Data
to the MCU function is shifted out on the MISO pin. The active
low SS pin must be asserted for the two functions to commu-
nicate. The IRQ function may be optionally multiplexed with the
MOSI pin; when this option is enabled the IRQ function is not
available while the SS pin is low . When using this configuration,
user firmware should ensure that the MOSI function on MCU
function is in a high impedance state whenever SS is high.
Figure 5. 4-WIRE SPI Mode
SPI Communication and Transactions
The SPI transactions can be single byte or multi-byte. The MCU
function initiates a data transfer through a Command/Address
byte. The following bytes are data bytes. The SPI transaction
format is shown in Figure 2.
The DIR bit specifies the direction of data transfer. 0 = Master
reads from slave. 1 = Master writes to slave.
The INC bit helps to read or write consecutive bytes from
contiguous memory lo cations in a single burst mode operation.
If Slave Select is asserted and INC = 1, then the master MCU
function reads a byte from the radio, the address is incremented
by a byte location, and then the byte at that location is read, and
so on. If Slave Select is asserted and INC = 0, then the MCU
function reads/writes the bytes in the same register in burst
mode, but if it is a register file then it reads/writes the bytes in
that register file.
The SPI interface between the radio function and the MCU is not
dependent on the internal 12 MHz oscillator of the radio.
Therefore, radio function registers can be read from or written
into while the radio is in sleep mode.
SPI I/O Voltage References
The SPI interfaces between MCU function and the radio and the
IRQ and RST have a separate voltage reference VIO, enabling
the radio function to directly interface with the MCU function,
which operates at higher supply voltage. The internal SPIO pins
between the MCU function and radio function should be
connected with a regulated voltage of 3.3 V (by setting [bit4] of
Registers P13CR, P14CR, P15CR, and P16CR of the MCU
function) and the internal 3.3 V regulator of the MCU function
should be turned on.
SPI Connects to External Devices
The three SPI wires, MOSI, SCK, and SS are also drawn out of
the package as external pins to allow the user to interface their
own external devices (such as optical sensors and others)
through SPI. The radio function also has its own SPI wires MISO
and IRQ, which can be used to send data back to the MCU
function or send an interrupt request to the MCU function. They
can also be configured as GPIO pins.
MCU F u nc ti on
P1.5/MOSI
P1.4/SCK
P1.3/nSS
MOSI
SCK
nSS
Radio Function
MOSI
SCK
nSS
MOSI/MISO multiplexed
on one MOSI pin
MCU Function
P1.5/MOSI
P1.4/SCK
P1.3/nSS
P1.6/MISO
MOSI
SCK
nSS
Radio Function
MISO
MOSI
SCK
nSS
This connection is ex ternal to the P RoC LPstar C h ip
CYRF69313
Document #: 001-66503 Rev. *B Page 11 of 78
CPU Architecture
This family of microcontrollers is based on a high performance,
8-bit, Harvard-architecture microprocessor. Five registers
control the pr ima ry op e r a ti o n of the CPU core . Th e se registers
are af f ected by various instructions, but are not directly ac ces-
sible through the register space by the user.
The 16-bit Program Counter Register (CPU_PC) allows for direct
addressing of the full eight Kbytes of program memory space.
The Accumulator Register (CPU_A) is the general purpose
register that holds the results of instructions that specify any of
the source addressing modes.
The Index Register (CPU_X) holds an offset value that is used
in the indexed addre ssing modes. Typically, this is used to
address a block of data within the data memory space.
The Stack Pointer Register (CPU_SP) holds the address of the
current top-of-stack in the data memory space. It is affe cted by
the PUSH, POP, LCALL, CALL, RETI, and RET instructions,
which manage the software stack. It can also be af fected by the
SWAP and ADD instructions.
The Flag Register (CPU_F) has three status bits: Zero Flag bit
[1]; Carry Flag bit [2]; Supervisory State bit [3]. The Global
Interrupt Enable bit [0] is used to globally enable or disable inter-
rupts. The user cannot manipulate the Supervisory State status
bit [3]. The flags are affected by arithmetic, logic, and shift opera-
tions. The manner in which each flag is changed is dependent
upon the instructi o n be i n g executed (for example, AND, OR,
XOR). See Table 20 on page 17.
Table 2. SPI Transaction Format
Byte 1 Byte 1+N
Bit# 7 6 [5:0] [7:0]
Bit Name DIR INC Address Data
Table 3. CPU Registers and Register Names
Register Register Name
Flags CPU_F
Program Counter CPU_PC
Accumulator CPU_A
Stack Pointer CPU_SP
Index CPU_X
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CPU Registers
Flags Regi st er
The Flags Register can only be set or reset with logical instruction.
Accumul at o r Re gi st er
Index Regi st er
Table 4. CPU Flags Re gister (CPU_F) [R/W]
Bit # 7 6 5 4 3 2 1 0
Field Reserved XIO Super Carry Zero Global IE
Read/Write – – – R/W R RW RW RW
Default 00000010
Bits 7:5 Reserved
Bit 4 XIO
Set by the user to select between the register banks
0 = Bank 0
1 = Bank 1
Bit 3 Super
Indicates whether the CPU is executing user code or Supervisor Code. (This code cannot be accessed directly by the user.)
0 = User Code
1 = Supervisor Code
Bit 2 Carry
Set by CPU to indicate whether there has been a carry in the previous logical/arithmetic operation
0 = No Carry
1 = Carry
Bit 1 Zero
Set by CPU to indicate whether there has bee n a zero result in the previous logical/arithmetic operation
0 = Not Equal to Zero
1 = Equal to Zero
Bit 0 Global IE
Determines whether all interrupts are enabled or disabled
0 = Disabled
1 = Enabled
Note CPU_F register is only readable with explicit register address 0xF7. The OR F, expr and AND F, expr instructions must be used
to set and clear the CPU_F bits
Table 5. CPU Accumulator Register (CPU_A)
Bit # 7 6 5 4 3 2 1 0
Field CPU Accumulator [7:0]
Read/Write ––––––––
Default 00000000
Bits 7:0 CPU Accumulator [7:0]
8-bit data value holds the result of any logical/arithmetic instruction that uses a source addressing mode
Table 6. CPU X Register (CPU_X)
Bit # 7 6 5 4 3 2 1 0
Field X [7:0]
Read/Write ––––––––
Default 00000000
Bits 7:0X [7:0]
8-bit data value holds an index for any instructi on that uses an indexed addressing mode
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Stac k Poi n te r Re gi st er
CPU Program Counter Low Register
Table 7. CPU Stack Pointer Register (CPU_SP)
Bit # 76543210
Field Stack Pointer [7:0]
Read/Write ––––––––
Default 00000000
Bits 7:0 Stack Pointer [7:0]
8-bit data value holds a pointer to the current top-of-sta ck
CPU Program Counter High Register
Table 8. CPU Program Counte r Hig h Re gister (CPU_PCH)
Bit # 7 6 5 4 3 2 1 0
Field Program Counter [15:8]
Read/Write ––––––––
Default 00000000
Bits 7:0Program Counter [15:8]
8-bit data value holds the higher byte of the program counter
Table 9. CPU Program Counter Low Register (CPU_PCL)
Bit # 7 6 5 4 3 2 1 0
Field Program Counter [7:0]
Read/Write ––––––––
Default 00000000
Bits 7:0 Program Counter [7:0]
8-bit data value holds the lower byte of the program counter
CYRF69313
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Addressing Modes
Examples of the different addressing modes are discussed in
this section and example code is given.
Source Immediate
The result of an instruction using this addressing mode is placed
in the A register , the F register , the SP register , or the X register ,
which is specified as part of the instruction opcode. Operand 1
is an immediate value that serves as a source for the instruction.
Arithmetic instructions require two sources. Instructions using
this addressing mode are two bytes in length.
Examples
Source Direct
The result of an instruction using this addressing mode is placed
in either the A register or the X register, which is specified as part
of the ins truction opcode. Operand 1 is an address that points to
a location in either the RAM memory space or the register space
that is the source for the instruction. Arithmetic instructions
require two sources; the second source is the A register or X
register specified in the opcode. Instructions using this
addressing mode are two bytes in length.
Examples
Source Indexe d
The result of an instruction using this addressing mode is placed
in either the A register or the X register, which is specified as part
of the instruction opcode. Operand 1 is added to the X reg ister
forming an address that points to a location in either the RAM
memory space or the register space that is the source for the
instruction. Arithmetic instructions require two sources; the
second source is the A register or X register specified in the
opcode. Instructions using this addressing mode are two bytes
in length.
Examples
Destination Direct
The result of an instruction using this addressing mode is placed
within either the RAM me mory space or the register space.
Operand 1 is an address that points to the location of the result.
The source for the instruction is either the A register or the X
register, which is specified as part of the instruction opcode.
Arithmetic instructions require two sources; the second source is
the location specified by Operand 1. Instructions using this
addressing mode are two bytes in length.
Examples
Table 10. Source Immediate
Opcode Operand 1
Instruction Immediate Value
ADD A, 7 ;In this case, the immediate value
;of 7 is added with the Accumulator,
;and the result is placed in the
;Accumulator.
MOV X, 8 ;In this case, the immediate value
;of 8 is moved to the X register.
AND F, 9 ;In this case, the immediate value
;of 9 is logically ANDed with the F
;register and the result is placed
;in the F register.
Table 11. Source Direct
Opcode Operand 1
Instruction Source Address
ADD A, [7] ;In this case, the value in
;the RAM memory location at
;address 7 is added with the
;Accumulator, and the result
;is placed in the Accumulator.
MOV X, REG[8] ;In this case, the value in
;the register space at address
;8 is moved to the X register.
Table 12. Source Indexed
Opcode Operand 1
Instruction Source Index
ADD A, [X+7] ;In this case, the value in
;the memory location at
;address X + 7 is added with
;the Accumulator, and the
;result is placed in the
;Accumulator.
MOV X, REG[X+8] ;In this case, the value in
;the register space at
;address X + 8 is moved to
;the X register.
Table 13. Destinati on Direct
Opcode Operand 1
Instruction Destination Address
ADD [7], A ;In this case, the value in
;the memory location at
;address 7 is added with the
;Accumulator, and the result
;is placed in the memory
;location at address 7. The
;Accumulator is unchanged.
MOV REG[8], A ;In this case, the Accumula-
;tor is moved to the regis-
;ter space location at
;address 8. The Accumulator
;is unchanged.
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Destination Indexed
The result of an instruction using this addressing mode is placed
within either the RAM memory space or the register space.
Operand 1 is added to the X register fo rming the address that
points to the lo cation of th e result. The source for the instruction
is the A register. Arithmetic instructions require two sources; the
second source is the location specified by Operand 1 added with
the X register. Instructions using this addressing mode are two
bytes in length.
Example
Destination Direct Source Immediate
The result of an instruction using this addressing mode is placed
within either the RAM memory space or the register space.
Operand 1 is the address of the result. The source for the
instruction is Operand 2, which is an immediate value. Arithmetic
instructions require two sources; the second source is the
location specified by Operand 1. Instructions using this
addressing mode are three bytes in length.
Examples
Destination Indexed Source Immediate
The result of an instruction using this addressing mode is placed
within either the RAM me mory space or the register space.
Operand 1 is added to the X register to form the address of the
result. The source for the instruction is Operand 2, which is an
immediate value. Arithmetic instructions require two sources; the
second source is the location specified by Operand 1 added with
the X register . Instructions using this addressing mode are three
bytes in length.
Examples
Destination Direct Source Direct
The result of an instruction using this addressing mode is placed
within the RAM memory. Operand 1 is the address of the result.
Operand 2 is an address that points to a location in the RAM
memory that is the source for the instruction. This addressing
mode is only valid on the MOV instruction. The instruction using
this addressing mode is three bytes in length.
Example
Tab le 14. Destination Indexed
Opcode Operand 1
Instruction Destination Index
ADD [X+7], A ;In this case, the value in the
;memory location at address X+7
;is added with the Accumulator,
;and the result is placed in
;the memory location at address
;x+7. The Accumulator is
;unchanged.
Table 15. Destination Direct Immediate
Opcode Operand 1 Operand 2
Instruction Destination Address Immediate Value
ADD [7], 5 ;In this case, value in the
;memory location at address 7 is
;added to the immediate value of
;5, and the result is placed in
;the memory location at address 7.
MOV REG[8], 6 ;In this case, the immediate
;value of 6 is moved into the
;register space location at
;address 8.
Table 16. Destination Indexed Immediate
Opcode Operand 1 Operand 2
Instruction Destination Index Immediate Value
ADD [X+7], 5 ;In this case, the value in
;the memory location at
;address X+7 is added with
;the immediate value of 5,
;and the result is placed
;in the memory location at
;address X+7.
MOV REG[X+8], 6 ;In this case, the immedi-
;ate value of 6 is moved
;into the location in the
;register space at
;address X+8.
Table 17. Destinati on Dir e ct Source Direct
Opcode Operand 1 Operand 2
Instruction Destination Address Source Address
MOV [7], [8] ;In this case, the value in the
;memory location at address 8 is
;moved to the memory location at
;address 7.
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Source Indirect Post Increment
The result of an instruction using this addressing mode is placed
in the Accumulator. Operand 1 is an address pointing to a
location within the me mory space, which contains an address
(the indirect address) for the source of the instruction. The
indirect address is increme nted as part of the instruction
execution. This addressing mode is only valid on the MVI
instruction. The instruction using this addressing mode is two
bytes in length. Refer to the PSoC Designer: Assembly
Language User Guide for further details on MVI instruction.
Example
Destination Indirect Post Incre m ent
The result of an instruction using this addressing mode is placed
within the memory space. Operand 1 is an address pointing to a
location within the me mory space, which contains an address
(the indirect address) for the destination of the instruction. The
indirect address is incremented as part of the instruction
execution. The source for the instruction is the Accumulator. This
addressing mode is only valid on the MVI instruction. The
instruction using this addressing mode is two bytes in length.
Example
Table 18. Source Indirect Post Increment
Opcode Operand 1
Instruction Source Address Address
MVI A, [8] ;In this case, the value in the
;memory location at address 8 is
;an indirect address. The memory
;location pointed to by the indi-
;rect address is moved into the
;Accumulator. The indirect
;address is then incremented.
Table 19. Destination Indirect Post Increment
Opcode Operand 1
Instruction Destination Address Address
MVI [8], A ;In this case, the value in
;the memory location at
;address 8 is an indirect
;address. The Accumulator is
;moved into the memory loca-
;tion pointed to by the indi-
;rect address. The indirect
;address is then incremented.
CYRF69313
Document #: 001-66503 Rev. *B Page 17 of 78
Instruction Set Summary
The instruction set is summarized in Table 20 numerically and serves as a quick reference. If more information is needed, the
Instruction Set Summary tables are described in detail in the PSoC Designer Assembly Language User Guide (available on
www.cypress.com).
Table 20. Instruction Set Summary Sorted Numerically by Opcode Order[1, 2]
Opcode Hex
Cycles
Bytes
Instruction Format Flags
Opcode Hex
Cycles
Bytes
Instruction Format Flags
Opcode Hex
Cycles
Bytes
Instruction Format Flags
00 15 1SSC 2D 8 2 OR [X+expr], A Z5A 5 2MOV [expr ], X
01 4 2 ADD A, expr C, Z 2E 9 3 OR [expr], expr Z5B 4 1MOV A, X Z
02 6 2 ADD A, [expr] C, Z 2F 10 3OR [X+expr], expr Z5C 4 1MO V X, A
03 7 2 ADD A, [X+expr] C, Z 30 9 1HALT 5D 6 2MOV A, reg[expr] Z
04 7 2 ADD [expr], A C, Z 31 4 2XOR A, expr Z5E 7 2M OV A, reg[X + expr] Z
05 8 2 ADD [X+expr], A C, Z 32 6 2XOR A, [expr] Z5F 10 3MO V [e xp r], [e xp r ]
06 9 3 ADD [expr], expr C, Z 33 7 2XOR A, [X+expr] Z60 5 2MOV reg[expr], A
07 10 3ADD [X+expr], expr C, Z 34 7 2XOR [expr], A Z61 6 2MOV reg[X+expr], A
08 4 1PUSH A 35 8 2XOR [X+expr], A Z62 8 3MOV reg[expr], expr
09 4 2 ADC A, expr C, Z 36 9 3XOR [expr], exp r Z63 9 3MOV reg[X+expr], expr
0A 6 2 ADC A, [expr] C, Z 37 10 3XOR [X+expr], ex pr Z64 4 1ASL A C, Z
0B 7 2 ADC A, [X+expr] C, Z 38 5 2ADD SP, expr 65 7 2ASL [expr] C, Z
0C 7 2 ADC [expr], A C, Z 39 5 2CMP A, expr if (A=B)
Z=1
if (A<B)
C=1
66 8 2ASL [X+expr] C, Z
0D 8 2 ADC [X+expr], A C, Z 3A 7 2CMP A, [expr] 67 4 1ASR A C, Z
0E 9 3 ADC [expr], expr C, Z 3B 8 2CMP A, [X+expr] 68 7 2ASR [expr] C, Z
0F 10 3ADC [X+expr], expr C, Z 3C 8 3CMP [expr], expr 69 8 2ASR [X+expr] C, Z
10 4 1PUSH X 3D 9 3CMP [X+expr], expr 6A 4 1RLC A C, Z
11 4 2SUB A, expr C, Z 3E 10 2MVI A, [ [expr]++ ] Z6B 7 2RLC [expr] C, Z
12 6 2SUB A, [expr] C, Z 3F 10 2MVI [ [expr]++ ], A 6C 8 2RLC [X+expr] C, Z
13 7 2SUB A, [X+expr] C, Z 40 4 1 NOP 6D 4 1RRC A C, Z
14 7 2SUB [expr], A C, Z 41 9 3AND reg[expr], expr Z6E 7 2RRC [expr] C, Z
15 8 2SUB [X+expr], A C, Z 42 10 3AND reg[X+expr], expr Z6F 8 2RRC [X+expr] C, Z
16 9 3SUB [expr], expr C, Z 43 9 3 OR reg[expr], expr Z70 4 2AND F, expr C, Z
17 10 3SUB [X+expr], expr C, Z 44 10 3OR reg[X+expr], expr Z71 4 2 OR F, expr C, Z
18 5 1POP A Z45 9 3XOR reg[expr], expr Z72 4 2XOR F, expr C, Z
19 4 2SBB A, expr C, Z 46 10 3XOR reg[X+expr], expr Z73 4 1CPL A Z
1A 6 2SBB A, [expr] C, Z 47 8 3TST [expr], expr Z74 4 1INC A C, Z
1B 7 2SBB A, [X+expr] C, Z 48 9 3TST [X+expr], expr Z75 4 1INC X C, Z
1C 7 2SBB [expr], A C, Z 49 9 3TST reg[expr], expr Z76 7 2INC [expr] C, Z
1D 8 2SBB [X+expr], A C, Z 4A 10 3TST reg[X+expr], expr Z77 8 2INC [X+expr] C, Z
1E 9 3SBB [expr], expr C, Z 4B 5 1SWAP A, X Z78 4 1DEC A C, Z
1F 10 3SBB [X+expr], expr C, Z 4C 7 2SWAP A, [expr] Z79 4 1DEC X C, Z
20 5 1POP X 4D 7 2SWAP X, [expr] 7A 7 2DEC [expr] C, Z
21 4 2AND A, expr Z4E 5 1SWAP A, SP Z7B 8 2DEC [X+expr] C, Z
22 6 2AND A, [expr] Z4F 4 1 MOV X, SP 7C 13 3LCALL
23 7 2AND A, [X+expr] Z50 4 2 MOV A, expr Z7D 7 3 LJMP
24 7 2AND [expr], A Z51 5 2 MOV A, [ex pr ] Z7E 10 1RETI C, Z
25 8 2AND [X+expr], A Z52 6 2 MOV A, [X+expr] Z7F 8 1RET
26 9 3AND [expr], expr Z53 5 2 MOV [e xp r ], A 8x 5 2JMP
27 10 3AND [X+expr], expr Z54 6 2 MOV [X +e xpr], A 9x 11 2CALL
28 11 1ROMX Z55 8 3 MOV [expr], exp r Ax 5 2 JZ
29 4 2 OR A, expr Z56 9 3 MOV [X+expr] , exp r Bx 5 2 JNZ
2A 6 2 OR A, [expr] Z57 4 2 MOV X, ex p r Cx 5 2 JC
2B 7 2 OR A, [X+expr] Z58 6 2 MOV X, [expr ] Dx 5 2 JNC
2C 7 2 OR [expr], A Z59 7 2 MOV X, [X+exp r] Ex 7 2 JACC
Fx 13 2INDEX Z
Notes
1. Interrupt routines take 13 cycles before execution resumes at interrupt vector table.
2. The number of cycles required by an instruction is increased by one for inst ructions that span 256-byte boundaries in the Flash memory spa ce .
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Memory Organization
Flash Program Memory Organization
Table 21. Program Memory Space with Interrupt Vector T able
after reset Address
16-bit PC 0x0000 Program execution begins here after a reset
0x0004 POR
0x0008 INT0
0x000C SPI T ransm itter Empty
0x0010 SPI Receiver Full
0x0014 GPIO Port 0
0x0018 GPIO Port 1
0x001C INT1
0x0020 EP0
0x0024 EP1
0x0028 EP2
0x002C USB Reset
0x0030 USB Active
0x0034 1 ms Interval Timer
0x0038 Programmable Interval Timer
0x003C Reserved
0x0040 Reserved
0x0044 16-bit Free Running Timer W rap
0x0048 INT2
0x004C Reserved
0x0050 GPIO Port 2
0x0054 Reserved
0x0058 Reserved
0x005C Reserved
0x0060 Reserved
0x0064 Sleep Timer
0x0068 Program Memory begins here (if below interrupts not used,
program memory can start lower)
0x1FFF 8 KB ends here
CYRF69313
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Data Memory Organization
The MCU function has 256 byte s of data RAM
Figure 6. Data Memory Organization
Flash
This section describes the Flash block of the CYRF69313. Much
of the user-visible Flash functionality, including programming
and security, are implemented in the M8C Supervisory Read
Only Memory (SROM). CYRF69313 Flash has an endurance of
1000 cycles and 10 year data retention.
Flash Programming and Security
All Flash programming is performed by code in the SROM. The
registers that control the Flash programming are only visib le to
the M8C CPU when it is executing out of SROM. This makes it
impossible to read, write, or erase the Flash by bypassing the
security mechanisms implemented in the SROM.
Customer firmware can only program the Flash via SROM calls.
The data or code images can be sourced by way of any interface
with the appropriate support firmware. This type of programming
requires a ‘bootloader’—a piece of firmware resident on the
Flash. For safety reasons this bootloader should not be
overwritt e n du ri n g fi rmw a r e re w rites.
The Flash provides four auxiliary rows that are used to hold Flash
block protection flags, boot time calibration values, configuration
tables, and any device values. The routines for accessing these
auxiliary rows are documented in the SROM section. The
auxiliary rows are not affected by the device erase function.
In-System Programming
Most designs that include an CYRF69313 part have a USB
connector attached to the USB D+/D– pins on the device. These
designs require the ability to program or reprogram a part
through these two pins alone.
CYRF69313 device enables this type of in-system programming
by using the D+ and D– pins as the se rial programming mode
interface. This allows an exte rnal controller to cause the
CYRF69313 part to enter serial programming mode and then to
use the test queue to issue Flash access functions in the SROM.
The programming protocol is not USB.
SROM
The SROM holds code that is used to boot the part, calibrate
circuitry, and perform Flash operations. (Table 22 lists the SROM
functions.) The functions of the SROM may be accessed in
normal user code or operating from Flash. The SROM exists in
a separate memory space from user code. The SROM functions
are accessed by executing the Supervisory System Call
instruction (SSC), which has an opcode of 00h. Prior to
executing the SSC, the M8C’s accumulator needs to be loaded
with the desired SROM function code from Table 22. Undefined
functions causes a HALT if called from user code. The SROM
functions are executing code with calls; therefore, the functions
require stack space. With the exception of Reset, all of the
SROM function s have a p arameter block in SRAM that must be
configured before executing the SSC. Table 23 lists all possible
parameter block variables. The meaning of each parameter, with
regards to a specific SROM function, is described later in this
section.
T wo important variables that are used for all functions are KEY1
and KEY2. These variables are used to help discriminate
between valid SSCs and inadvertent SSCs. KEY1 must always
have a value of 3Ah, while KEY2 must have the same value as
the stack pointer when the SROM function begins execution.
This would be the S tack Pointer value when the SSC opcode is
executed, plus three. If either of the keys do not match the
expected values, the M8C halts (with the exception of the
SWBootReset function). The following code puts the correct
after reset Address
8-bit PSP 0x00 Stack b egin s here and grows upward.
Top of RAM Memory 0xFF
Table 22. SROM Function Codes
Function Code Function Name Stack Space
00h SWBootReset 0
01h ReadBlock 7
02h WriteBlock 10
03h EraseBlock 9
05h EraseAll 11
06h TableRead 3
07h CheckSum 3
CYRF69313
Document #: 001-66503 Rev. *B Page 20 of 78
value in KEY1 and KEY2. The code starts with a halt, to force the
program to jump directly into the setup code and not run into it.
halt
SSCOP: mov [KEY1], 3ah
mov X, SP
mov A, X
add A, 3
mov [KEY2], A
The SROM also features Return Codes and Lockouts.
Return Codes
Return codes aid in the determination of success or failure of a
particular function. The return code is stored in KEY1’s position
in the parameter block. The CheckSum and T ableRead functions
do not have return codes because KEY1’s position in the
parameter block is used to ret urn other data.
Read, write, and erase operations may fail if the target block is
read or write protected. Blo ck protection levels are set during
device programming.
The EraseAll function overwrites data in addition to leaving the
entire user Flash in the erase state. The EraseAll function loops
through the number of Flash macros in the product, executing
the following sequence: erase, bulk program all zero s, erase.
After all the user space in all the Flash macros are erased, a
second loop erases and then programs each protection block
with zeros.
SROM Function Descriptions
All SROM functions are described in the following sections.
SWBootReset Function
The SROM function, SWBootReset, is the function that is
responsible for transitioning the device from a reset state to
running user code. The SWBootReset function is executed
whenever the SROM is entered with an M8C accumulator value
of 00h; the SRAM parameter block is not used as an input to the
function. This happens, by design, after a hardware reset,
because the M8C's accumulator is reset to 00h or when user
code executes the SSC instruction with an accumulator value of
00h. The SWBootReset function does not execute when the
SSC instruction is executed with a bad key value and a nonzero
function code. A CYRF69313 device executes the HALT
instruction if a bad value is given for either KEY1 or KEY2.
The SWBootReset function verifies the integrity of the calibration
data by way of a 16-bit checksum, before releasing the M8C to
run user code.
ReadBlock Function
The ReadBlock function is used to read 64 contiguous bytes
from Flash—a block.
The first thing this function does is to check the protection bits
and determine if the desired BLOCKID is readable. If read
protection is turned on, the ReadBlock function exits, setting the
accumulator and KEY2 back to 00h. KEY1 has a value of 01h,
indicating a read failure. If read protection is not enabled, the
function reads 64 bytes from the Flash using a ROMX instruction
and store the results in SRAM using an MVI instruction. The first
of the 64 bytes is stored in SRAM at the address indicated by the
value of the POINTER parameter. When the ReadBlock
completes successfully, the accumulator, KEY1, and KEY2 all
have a value of 00h.
WriteBlock Function
The WriteBlock function is used to store data in the Flash. Data
is moved 64 bytes at a time from SRAM to Flash using this
function. The first thing the WriteBlock function does is to check
the protection bits and determine if the desired BLOC KID is
writable. If write protection is turned on, the WriteBlock function
exits, setting the accumulator and KEY2 back to 00h. KEY1 has
a value of 01h, indicating a write failure. The configuration of the
WriteBlock function is straightforward. The BLOCKID of the
Flash block, where the data is stored, must be determined and
stored at SRAM address F Ah.
The SRAM address of the first of the 64 bytes to be stored in
Flash must be indicated using the POINTER variable in the
parameter block (SRAM address FBh). Finally, the CLOCK and
DELAY values must be set correctly. The CLOCK value deter-
mines the length of the write pulse that is used to store the data
in the Flash. The CLOCK and DELAY values are dependent on
the CPU speed. Refer to ‘Clocking’ Section for addition al infor-
mation.
Table 23. SROM Function Parameters
Variable Name SRAM Address
Key1/Counter/Return Code 0,F8h
Key2/TMP 0,F9h
BlockID 0,FAh
Pointer 0,FBh
Clock 0,FCh
Mode 0,FDh
Delay 0,FEh
PCL 0,FFh
Table 24 . SROM Return Codes
Return Code Description
00h Success
01h Function not allowed due to level of protection
on block
02h Software reset without hardware reset
03h Fatal error, SROM halted
Table 25. ReadBlock Par a me te r s
Name Address Description
KEY1 0,F8h 3Ah
KEY2 0,F9h Stack Pointer value, when SSC is
executed
BLOCKID 0,FAh Flash block number
POINTER 0 ,FBh First of 64 addresses in SRAM
where returned data should be
stored
CYRF69313
Document #: 001-66503 Rev. *B Page 21 of 78
EraseBlock Function
The EraseBlock function is used to erase a block of 64
contiguous bytes in Flash. The first thing the EraseBlock function
does is to check the protection bits and determine if the desired
BLOCKID is writable. If write protection is turned on, the Era s e-
Block function exits, setting the accumulator and KEY2 back to
00h. KEY1 has a value of 01h, indicating a write failure. The
EraseBlock function is only useful as the first step in
programming. Erasing a block does not cause data in a block to
be one hundred percent unreadable. If the objective is to oblit-
erate data in a block, the best method is to pe r fo rm an E rase-
Block followed by a WriteBlock of all zeros.
T o setup the parameter block for the EraseBlock function, correct
key values must be stored in KEY1 and KEY2. The block number
to be erased must be stored in the BLOCKID variable and the
CLOCK and DELAY values must be set based on the current
CPU speed.
ProtectBlock Function
The CYRF69313 device offers Flash protection on a
block-by-block basis. Table 28 lists th e protection modes
available. In the table, ER and EW are used to indicate the ability
to perform external reads and writes. For internal writes, IW is
used. Internal reading is always permitted by way of the ROMX
instruction. The ability to read by way of the SROM ReadBlock
function is indicated by SR. The protection level is stored in two
bits accordi ng to Table 28. These bits are bit packed into the 64
bytes of the protection block. Therefore, each protection block
byte stores the protection level for four Flash blocks. The bits are
packed into a byte, with the lowest numbered block’s protection
level stored in the lowest numbered bits.
The first address of the protection block contains the protection
level for blocks 0 through 3; the second address is for blocks 4
through 7. The 64th byte stores the protection level for blocks
252 through 255.
The level of protection is only decre ased by an EraseAll, which
places zeros in all locations of the protection block. To set the
level of protection, the ProtectBlock function is used. This
function takes data from SRAM, starting at address 80h, and
ORs it with the current values in the protection block. The result
of the OR operation is then stored in the pr ot ection block. The
EraseBlock function does not cha nge the protection level for a
block. Because the SRAM location for the protection data is fixed
and there is only one protection block per Flash macro, the
ProtectBlock function expects very few variables in the
parameter block to be set prior to calling the function. The
parameter block values that must be set, besides the keys, are
the CLOCK and DELAY values.
EraseAll Functi on
The EraseAll function performs a series of steps that destroy the
user data in the Flash macros and resets the protection block in
each Flash macro to all zeros (the unprotected state). The
EraseAll function does not affect the three hidden blocks above
the protection block in each Flash macro. The first of these four
hidden blocks is used to store the protection table for its eight
Kbytes of user data.
The EraseAll function begins by erasing the user space of the
Flash macro with the highest address range. A bulk program of
all zeros is then performed on the same Flash macro, to destroy
all traces of the previous contents. The bulk program is followed
by a second erase that leaves the Flash macro in a state ready
for writing. The erase, program, erase sequence is then
performed on the next lowest Flash macro in the address space
if it exists. Following the erase of the user space, the protection
block for the Flash macro with the highest address range is
Tab le 26. WriteBlock Parameters
Name Address Description
KEY1 0,F8h 3Ah
KEY2 0,F9h Stack Pointer value, when SSC is
executed
BLOCKID 0,FAh 8 KB Flash block number (00h–7Fh)
4 KB Flash block number (00h–3Fh)
3 KB Flash block number (00h–2Fh)
POINTER 0,FBh First of 64 addresses in SRAM, where
the data to be stored in Flash is located
prior to calling WriteBlock
CLOCK 0,FCh Clock divider used to set the write
pulse width
DELA Y 0,FEh For a CPU speed of 12 MHz set to 56h
Table 27. EraseBlock Parameters
Name Address Description
KEY1 0,F8h 3Ah
KEY2 0,F9h Stack Pointer value when SSC is
executed
BLOCKID 0,FAh Flash block number (00h–7Fh)
CLOCK 0,FCh Clock divider used to set the erase
pulse width
DELA Y 0,FEh For a CPU speed of 12 MHz set to 56h
Table 28. Protection Mode s
Mode Settings Description Marketing
00b SR ER EW IW Unprotected Unprotected
01b SR ER EW IW Read protect Factory upgrade
10b SR ER EW IW Disable external
write Field upgrade
11b SR ER EW IW Disable internal
write Full protection
7 6 5 4 3 2 1 0
Block n+3 Block n+2 Block n+1 Block n
Table 29. ProtectBlock Par a m eters
Name Address Description
KEY1 0,F8h 3Ah
KEY2 0,F9h Stack Pointer value when SSC is
executed
CLOCK 0,FCh Clock divider used to set the write
pulse width
DELAY 0,FEh For a CPU speed of 12 MHz set to 56h
CYRF69313
Document #: 001-66503 Rev. *B Page 22 of 78
erased. Following the erase of the protection block, zeros are
written into every bit of the protection table. The next lowest
Flash macro in the address space then has its protection block
erased and filled with zeros.
The end result of the EraseAll function is that all user data in the
Flash is destroyed and the Flash is left in an unprogrammed
state, ready to accept one of the various write commands. The
protection bi ts for all user data are also rese t to the zero state.
The parameter block values that must be set, besides the keys,
are the CLOCK and DELAY values.
TableRead Function
The TableRea d function gives the user access to part specific
data stored in the Flash during manufacturing. It also returns a
Revision ID for the die (not to be confused with the Silicon ID).
The table space for the CYRF69313 is simply a 64-byte row
broken up into eight tables of eight bytes. The tables are
numbered zero through seven. All user and hidden blocks in the
CYRF69313 parts consist of 64 bytes.
An internal table holds the Silicon ID and returns the Revision ID.
The Silicon ID is returned in SRAM, while the Revision ID is
returned in the CPU_A and CPU_X registers. The Silicon ID is a
value placed in the table by programming the Flash and is
controlled by Cypress Semiconductor Product Engineering. The
Revision ID is hard coded into the SROM. The Revision ID is
discussed in more detail later in this section.
An internal table holds alternate trim values for the device and
returns a one-byte internal revision counter. The internal revision
counter starts out with a value of zero and is incremented each
time one of the other revision numbers is not incremen ted. It is
reset to zero each time one of the other revision numbers is
incremented. The internal revision count is returned in the
CPU_A register . The CPU_X register is always set to FFh when
trim values are read . Th e BLOCKID value, in the parameter
block, is used to indicate which table should be returned to the
user. Only the three least significant bits of the BLOCKID
parameter are used by the TableRead function fo r the
CYRF69313. The upper five bits are ignored. When the function
is called, it transfers bytes from the table to SRAM addresses
F8h–FFh.
The M8C’s A and X registers are used by the T ableRead function
to return the die’s Revision ID. The Revision ID is a 16-bit value
hard coded into the SROM that uniquely identifie s the die’s
design.
Checksum Function
The Checksum function calculates a 16-bit checksum over a
user specifiable number of blocks, within a single Flash macro
(Bank) starting from block zero. The BLOCKID parameter is
used to pass in the number of blocks to calc ulate the checksum
over. A BLOCKID value of 1 calculates the checksum of only
block 0, while a BLOCKID value of 0 calculates the checksum of
all 256 user blocks. The 16-bit checksum is returned in KEY1 and
KEY2. The parameter KEY1 holds the lower eight bits of the
checksum and the parameter KEY2 ho lds the upper eight bits of
the checksum.
The checksum algorithm executes the following sequence of
three instructions over the number of blocks times 64 to be
checksummed.
romx
add [KEY1], A
adc [KEY2], 0
Table 30. EraseAll Parameters
Name Address Description
KEY1 0,F8h 3Ah
KEY2 0,F9h Stack Pointer value when SSC is
executed
CLOCK 0,FCh Clock divider used to set the write pulse
width
DELAY 0,FEh For a CPU speed of 12 MHz set to 56h
Tab le 31. Tabl e Read Parameters
Name Address Description
KEY1 0,F8h 3Ah
KEY2 0,F9h Stack Pointer value when SSC is
executed
BLOCKID 0,FAh Table number to read Table 32. Checksum Param e te rs
Name Address Description
KEY1 0,F8h 3Ah
KEY2 0,F9h Stack Pointer value when SSC is
executed
BLOCKID 0,FAh Number of Flash bloc ks to calculate
checksum on
CYRF69313
Document #: 001-66503 Rev. *B Page 23 of 78
SROM Table Read Description
Figure 7. SROM Table
The Silicon IDs for enCoRe II devices are stored in SROM tables in the part, as shown in Figure 7 on page 23.
The Silicon ID can be read out from the part using SROM Table reads. This is demonstrated in the follo wing pseudo code. As
mentioned in the section SROM on page 19, the SROM variables occupy address F8h through FFh in the SRAM. Each of the variables
and their definition in gi ven in the section SROM on page 19.
AREA SSCParmBlkA(RAM,ABS)
org F8h // Variables are defined starting at address F8h
SSC_KEY1: ; F8h supervisory key
SSC_RETURNCODE: blk 1 ; F8h result code
SSC_KEY2 : blk 1 ;F9h supervisory stack ptr key
SSC_BLOCKID: blk 1 ; FAh block ID
SSC_POINTER: blk 1 ; FBh pointer to data buffer
SSC_CLOCK: blk 1 ; FCh Clock
SSC_MODE: blk 1 ; FDh ClockW ClockE multiplier
SSC_DELAY: blk 1 ; FEh flash macro sequence delay count
SSC_WRITE_ResultCode: blk 1 ; FFh temporary result code
_main:
mov A, 0
mov [SSC_BLOCKID], A // To read from Table 0 - Silicon ID is stored in Table 0
//Call SROM operation to read the SROM table
mov X, SP ; copy SP into X
mov A, X ; A temp stored in X
add A, 3 ; create 3 byte stack frame (2 + pushed A)
mov [SSC_KEY2], A ; save stack frame for supervisory code
; load the supervisory code for flash operations
mov [SSC_KEY1], 3Ah ;FLASH_OPER_KEY - 3Ah
mov A,6 ; load A with specific operation. 06h is the code for Table read Table 22
SSC ; SSC call the supervisory ROM
// At the end of the SSC command the silicon ID is stored in F8 (MSB) and F9(LSB) of the SRAM
.terminate:
jmp .terminate
F8h
Table 0
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
F9h F8h F8h F8h F8h F8h F8h
Silicon ID
[15-8] Silicon ID
[7-0]
CYRF69313
Document #: 001-66503 Rev. *B Page 24 of 78
Clocking
The CYRF69313 internal oscillator outputs two frequencies, the Internal 24 MHz Oscillator and the 32 kHz Low power Oscillator .
The Internal 24 MHz Oscillator is designed such that it may be trimmed to an output frequency of 24 MHz over temperature and
voltage variation. With the presence of USB traffic, the Internal 24 MHz Oscillator can be set to precisely tune to USB timing
requirements (24 MHz ± 1.5%). Without USB traffic, the Internal 24 MHz Oscillator accuracy is 24 MHz ± 5% (between 0 °C –
70 °C). No external components are required to achieve this level of accuracy.
The internal low speed oscillator of nominally 32 kHz provides a slow clock source for the CYRF69313 in suspend mode,
particularly to generate a periodic wakeup interrupt and also to provide a clock to sequential logic during power-up and
power-down events when the main clock is stopped. In addition, this oscillator can also be used as a clocking source for the
Interval Timer clock (ITMRCLK) and Capture Timer clock (TCAPCLK). The 32 kHz Low power Oscillator can operate in low power
mode or can provide a more accurate clock in normal mode. The Internal 32 kHz Low power Oscillator accuracy ranges (between
0 °C – 70° C) as follows:
5 V Normal mode: –8% to + 16%
5 V LPstar mode: +12% to + 48%
When using the 32 kHz oscillator the PITMRL/H should be read until two consecutive readings match before sending/receiving
data. The following firmware example assumes the developer is interested in the lower byte of the PIT.
Read_PIT_counter:
mov A, reg[PITMRL]
mov [57h], A
mov A, reg[PITMRL]
mov [58h], A
mov [59h], A
mov A, reg{PITMRL]
mov [60h], A
;;;Start comparison
mov A, [60h]
mov X, [59h]
sub A, [59h]
jz done
mov A, [59h]
mov X, [58h]
sub A, [58h]
jz done
mov X, [57h]
;;;correct data is in memory location 57h
done:
mov [57h], X
ret
CYRF69313
Document #: 001-66503 Rev. *B Page 25 of 78
Clock Architecture Description
The CYRF69313 clock selection circuitry allows the selection of
independent clocks for the CPU, USB, Interval Timers, and
Capture Timers.
The CPU clock, CPUCLK, can be sourced from the Internal 24
MHz Oscillator . This clock source can optionally be divided by 2n
where n is 0–5,7 (see Table 36).
USBCLK, which must be 12 MHz for the USB SIE to function
properly, can be sourced by the Internal 24 MHz Oscillator. An
optional divide-by-tw o allows the use of the 24 MHz source.
The Interval Timer clock (ITMRCLK), can be sourced from the
Internal 24 MHz Oscillator , the Internal 32 kHz Low power Oscil-
lator , except when in sleep mode, or from the timer capture clock
(TCAPCLK). A programmable prescaler of 1, 2, 3, 4 then divides
the selected source.
The Timer Capture clock (TCAPCLK) can be sourced from the
Internal 24 MHz Oscillator, or the Internal 32 kHz Low power
Oscillator except when in sleep mode.
The CLKOUT pin (P0.1) can be driven from one of many
sources. This is used for test and can also be used in some
applications.
The sources that can dri ve th e CLKOUT are:
■CLKIN after the optional EFTB filter
■Internal 24 MHz Oscillator
■Internal 32 kHz Low power Oscillator except when in sleep
mode
■CPUCLK after the programmable divider
Figure 8. Cloc k Block Diagram
CPU_CLK
24 MHz
MUX CLK_USB
SEL SCALE
CLK_24MHz
CPUCLK
SEL
MUX
SCALE (divide by 2n,
n = 0-5,7)
CLK_32
KHz
Low power
OSC 32
KHz
SEL SCALE OUT
0X
12 MHz
0X
12 MHz
11RESERVED
11
RESERVED
CYRF69313
Document #: 001-66503 Rev. *B Page 26 of 78
Table 33. IOSC Trim (IOSCTR) [0x34] [R/W]
Bit # 7 6 5 4 3 2 1 0
Field foffset[2:0] Gain[4:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 D D D D D
The I/OSC Calibrate register is used to calibrate the internal oscillator. The reset value is undefined, but during boot the SROM writes
a calibration value that is determined during manufacturing test. This value should not require change during normal use. This is the
meaning of ‘D’ in the Defaul t field
Bits 7:5 foffset [2:0]
This value is used to trim the frequency of the internal oscillator. These bits are not used in factory calibration and is zero. Setting
each of these bits causes the appropriate fine offse t in oscil lator frequency
foffset bit 0 = 7.5 KHz
foffset bit 1 = 15 KHz
foffset bit 2 = 30 KHz
Bits 4:0 Gain [4:0]
The effective frequency change of the offset input is controlled through the gain input. A lower value of the gain setting increases
the gain of the offset input. Th is val ue se ts th e size of ea ch offset ste p for the in tern al oscilla to r. Nominal ga in ch ang e (KH z/off-
setStep) at each bit, typical conditions (24 MHz operation):
Gain bit 0 = –1.5 KHz
Gain bit 1 = –3.0 KHz
Gain bit 2 = –6 KHz
Gain bit 3 = –12 KHz
Gain bit 4 = –24 KHz
Table 34. LPOSC Trim (LPOSCTR) [0x36] [R/W]
Bit # 7 6 5 4 3 2 1 0
Field 32 kHz Low
Power Reserved 32 kHz Bias Trim [1:0] 32 kHz Freq Trim [3:0]
Read/Write R/W – R/W R/W R/W R/W R/W R/W
Default 0 D D D DDD D
This register is used to calibrate the 32 kHz Low speed Oscillator . The reset value is undefined, but during boot the SROM writes a
calibration value that is determined during manufacturing test. This value should not require change during normal use. This is the
meaning of ‘D’ in the Default field. If the 32 kHz Low power bit needs to be written, care sho uld be taken not to disturb the 32 kHz
Bias Trim and the 32 kHz Freq Trim fields from their factory calibrated values
Bit 7 32 kHz Low Power
0 = The 32 kHz Low speed Oscillator operates in normal mode
1 = The 32 kHz Low speed Oscillator operates in a low power mode. The oscillator continues to function normally but with reduced
accuracy
Bit 6 Reserved
Bits 5:4 32 kHz Bias Trim [1:0]
These bits control the bias current of the low power oscillator.
0 0 = Mid bias
0 1 = High bias
1 0 = Reserved
1 1 = Reserved
Important Note Do not program the 32 kHz Bias Trim [1:0] field with the reserved 10b value, as the oscillator does not oscillate at
all corner conditions with this setting
Bits 3:0 32 kHz Freq Trim [3:0]
These bits are used to trim the frequency of the low power oscillator
CYRF69313
Document #: 001-66503 Rev. *B Page 27 of 78
Table 35 . CPU/USB Clock Config CPUCLKCR) [0x30] [R/W]
Bit # 7 6 5 4 3 2 1 0
Field Reserved
Read/Write – R/W R/W – – – – R/W
Default 0 0 0 0 0 0 0 0
Bit 7 Reserved
Bit 6 Reserved
Bit 5 Reserved
Bits 4:1 Reserved
Bit 0 Reserved
Note The CPU speed selection is configured using th e OSC_CR0 Register (Table 36)
Tab le 36. OSC Control 0 (OSC_CR0) [0x1E0] [R/W]
Bit # 7 6 5 4 3 2 1 0
Field Reserved No Buzz Sleep Timer [1:0] CPU Speed [2:0]
Read/Write – – R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
CYRF69313
Document #: 001-66503 Rev. *B Page 28 of 78
Bits 7:6 Reserved
Bit 5 No Buzz
During sleep (the Sleep bit is set in the CPU_SCR Register—Table 40), the POR detection circuit is turned on periodically to de-
tect any POR ev ents on th e VCC pin (the Sleep Duty Cycle bits in the ECO_TR are used to control the duty cycle—Table 44). To
facilitate the detection of POR events, the No Buzz bit is used to force the POR detection circuit to be continuously enabled during
sleep. This results in a faster response to a POR event during sleep at the expense of a slightly higher than average sleep current
0 = The POR detection circuit is turned on periodically as configured in the Sleep Duty Cycle
1 = The Sleep Duty Cycle value is overridden. The POR detection circuit is always enabled
Note The periodic Sleep Duty Cycle enabling is independent with the sleep interval shown in the Sleep [1:0] bits below
Bits 4:3 Sleep Timer [1:0]
Note Sleep intervals are approximate
Bits 2:0 CPU Speed [2:0]
The CYRF69313 may operate over a range of CPU clock speeds. The reset value for the CPU Speed bits is zero; therefore, the
default CPU speed is one-eighth of the internal 24 MHz, or 3 MHz
Regardless of the CPU Speed bit’s setting, if the actual CPU speed is greater than 12 MHz, the 24 MHz operating requirements
apply. The operating voltage requirements are not relaxed until the CPU speed is at 12 MHz or less
Important Note Correct USB operations require the CPU clock speed be at least 1.5 MHz or not less than USB clock/8. If the two
clocks have the same source then the CPU clock divider should not be set to divide by more than 8. If the two clocks have dif ferent
sources, care must be taken to ensure that the maximum ratio of USB Clock/CPU Clock can never exceed 8 across the full specifi-
cation range of both clock sources
Tab le 36. OSC Control 0 (OSC_CR0) [0x1E0] [R/W] (continued)
Sleep Timer
[1:0] Sleep Timer Clock
Frequenc y (Nominal) Sleep Period
(Nominal) Watchdog Period
(Nominal)
00 512 Hz 1.95 ms 6 ms
01 64 Hz 15.6 ms 47 ms
10 8 Hz 125 ms 375 ms
11 1 Hz 1 se c 3 sec
CPU Speed [2:0] CPU
000 3 MHz (Default)
001 6 MHz
010 12 MHz
011 24 MHz
100 1.5 MHz
101 750 kHz
110 187 kHz
111 Reserved
CYRF69313
Document #: 001-66503 Rev. *B Page 29 of 78
Tab le 37 . USB Osclock Clock Configuratio n (OSCLCKCR) [0x39] [R/W]
Bit # 76543210
Field Reserved Fine Tune
Only USB Osclock
Disable
Read/Write – – – – – – R/W R/W
Default 00000000
This register is used to trim the Internal 24 MHz Oscillator using received low speed USB packets as a timing reference. The
USB Osclock circuit is active when the Internal 24 MHz Oscillator provides the USB clock
Bits 7:2 Reserved
Bit 1 Fine Tune Only
0 = Enable
1 = Disable the oscillator lock from performing the course-tune portion of its retuning. The oscillator lock must be allowed to
perform a course tuning to tune the oscillator for correct USB SIE operation. After the oscillator is properly tuned this bit can
be set to reduce variance in the internal oscillator frequency that would be caused by course tuning
Bit 0 USB Osclock Disable
0 = Enable. With the presence of USB traffic, the Intern al 24 MHz Oscillator precisely tunes to 24 MHz ± 1.5%
1 = Disable. The Internal 24 MHz Oscillat or is not trimmed based on USB packets. This setting is useful when the internal
oscillator is not sourcing the USBSIE cl ock
Table 38 . Timer Clock Config (TMRCLKCR) [0x31] [R/W]
Bit # 76543210
Field TCAPCL Divider TCAPCLK Select ITMRCLK Divider ITMRCLK Select
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default - - - - 1 1 0 0
Bits 7:6 TCAPCLK Divider
TCAPCLK Divider controls the TCAPCLK divisor
00 = Divide by 2
01 = Divide by 4
10 = Divide by 6
11 = Divide by 8
Bits 5:4 TCAPCLK Select
The TCAPCLK Select field controls the source of the TCAPCLK
0 0 = Internal 24 MHz Oscillator
0 1 = Reserved)
1 0 = Internal 32 kHz Low power Oscillator. Howeve r this configuration is not used in sleep mode.
1 1 = TCAPCLK Disabled
Note The 1024-s interval ti mer is based on the assumption that TCAPCLK is runni ng at 4 MHz. Changes in TCAPCLK frequency causes
a corresponding change in the 1024 s interval timer frequency
Bits 3:2 ITMRCLK Divider
ITMRCLK Divider controls the ITMRCLK divisor.
0 0 = Divider value of 1
0 1 = Divider value of 2
1 0 = Divider value of 3
1 1 = Divider value of 4
Bits 1:0 ITMRCLK Select
0 0 = Internal 24 MHz Oscillator
0 1 = Reserved
1 0 = Internal 32 kHz Low power Oscillator. However this configuration is not used in sleep mode.
1 1 = TCAPCLK
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Interval Timer Clock (ITMRCLK)
The Interval Timer Clock (ITMRCLK) can be sourced from the
Internal 24 MHz oscillator, the inte rnal 32 kHz low power oscil-
lator except when in sleep mode, or the timer capture clock. A
programmable prescaler of 1, 2, 3, or 4 then divides the selected
source. The 12-bit Progra mmable Interval Timer is a simple
down counter with a programmable reload value. It provides a 1
s resolution by default. When th e down counter reaches zero,
the next clock is spent reloading. The reload value can be read
and written while the counter is running, but care should be taken
to ensure that the counter does not unintentionally reload while
the 12-bit reload value is only partially stored—for example,
between the two writes of the 12-bit value. The programmable
interval timer generates an interrupt to the CPU on each reload.
The parameters to be set appears on the device editor view of
PSoC Designer after you place the CYRF69313 Timer User
Module. The parameters are PITIMER_Source and
PITIMER_Divider. The PITIMER_Source is the clock to the timer
and the PITMER_Divider is the value the clock is divided by.
The interval register (PITMR) holds the value that is loaded into
the PIT counter on terminal count. The PIT counter is a down
counter.
The Programmable Interval Timer resolution is configurable. For
example:
TCAPCLK divide by x of CPU clock (for example TCAPCLK
divide by 2 of a 24 MHz CPU clock gives a frequency of 12 MHz)
ITMRCLK divide by x of TCAPCLK (for example, ITMRCLK
divide by 3 of TCAPCLK is 4 MHz so resolution is 0.25 s)
Timer Capture Clock (TCAPCLK)
The Timer Capture clock can be sourced from the internal 24
MHz oscillator or the Internal 332 kHz low power oscillator except
when in sleep mode. A programmable prescale r of 2, 4, 6, or 8
then divides the selected source.
Figure 9. Programmable Interval Timer Block Diagram
System
Clock
Clock
Timer
Configuration
Status and
Control
12-bit
re lo ad
value
12-bit dow n
counter
12-bit
re lo ad
counter
In te r ru p t
Controller
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Figure 10. Timer Capture Block Diagram
CPU Clock During Sleep Mode
When the CPU enters sleep mode the CPUCLK Select (Bit [0],
Table 35) is forced to the internal oscillator, and the oscillator is
stopped. When the CPU comes out of sleep mode it is running
on the internal oscillator. The internal oscillator recovery time is
three clock cycles of the Internal 32 kHz Low power Oscillator.
Reset
The microcontroller supports two types of resets: Power on
Reset (POR) and Watchdog Reset (WDR). When reset is
initiated, all registers are restored to their default states and all
interrupts are disabled.
The occurrence of a reset is recorded in the System S tatus and
Control Register (CPU_SCR). Bits within this register record the
occurrence of POR and WDR Reset respectively. The firmware
can interrogate these bits to determine the cause of a reset.
The microcontroller resumes execution from Flash address
0x0000 after a reset. The internal clocking mode is active after a
reset.
Note The CPU clock defaults to 3 MHz (Internal 24 MHz Oscil-
lator divide-by-8 mode) at POR to guarantee operation at the low
VCC that might be present during the supply ramp.
16-bit counter
Configuration Status
and Control
Prescale Mux
Capture Registers
Interrupt Controller
1ms
timer Overflow
Interrupt
Captimer Clock
System Clock
Capture0 Int Ca pture1 Int
Table 39. Clock I/O Config (CLKIOCR) [0x32] [R/W]
Bit # 7 6 5 4 3 2 1 0
Field Reserved CLKOUT Select
Read/Write –––---R/W R/W
Default 00000000
Bits 7:2 Reserved
Bits 1:0 CLKOUT Select
0 0 = Internal 24 MHz Oscillator
0 1 = Reserved
1 0 = Internal 32 kHz Low power Oscillator.H owever this configu r ation is not used in sleep mode.
1 1 = CPUCLK
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Table 40. System Status and Control Register (CPU_SCR) [0xFF ] [R/W]
Bit # 7 6 5 4 3 2 1 0
Field GIES Reserved WDRS PORS Sleep Reserved Stop
Read/Write R – R/C[3] R/C[3] R/W – – R/W
Default 0001000 0
The bits of the CPU_SCR register are used to convey status and control of events for various functions of an CYRF69313 device
Bit 7 GIES
The Global Interrupt Enable Status bit is a read only status bit and its use is discouraged. The GIES bit is a legacy bit, which was
used to provide the ability to read the GIE bit of the CPU_F regi ster. However, the CPU_F regi ster is now readable. Whe n this
bit is set, it indicates that the GIE bit in the CPU_F regi ster is also set which, in turn, indicates that the microprocessor services
interrupts
0 = Global interrupts disabled
1 = Global interrupt enabled
Bit 6 Reserved
Bit 5 WDRS
The WDRS bit is se t by the CPU to indicate that a WDR event has occurred. The user can read this bit to determine the type of
reset that has occurred. The user can clear but not set this bit
0 = No WDR
1 = A WDR event has occurred
Bit 4 PORS
The PORS bit is set by the CPU to indicate that a POR event has occurred. The user can read this bit to determine the type of
reset that has occurred. The user can clear but not set this bit
0 = No POR
1 = A POR event has occurred. (Note that WDR events does not occur until this bit is cleared)
Bit 3 SLEEP
Set by the user to enab le CPU sleep sta te. CPU remains in slee p mode until any in terrupt is pendin g. The Sleep bit is cove red
in more detail in the Sleep Mode section
0 = Normal operation
1 = Sleep
Bit 2:1 Reserved
Bit 0 STOP
This bit is set by the user to halt the CPU. The CPU remains halted until a reset (WDR, POR, or external reset) has taken place.
If an application wants to stop code execution until a reset, the preferred method would be to use the HALT instruction rather than
writing to this bit
0 = Normal CPU operation
1 = CPU is halted (not recommended)
Note
3. C = Clear. This bit can only be cleared by the user and cannot be set by firmware
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Power-on Reset
POR occurs every time the power to the device is switched on.
POR is released when the supply is typically 2.6 V for the upward
supply transition, with typically 50 mV of hysteresis during the
power on transient. Bit 4 of the System Status and Control
Register (CPU_SCR) is set to record this event (the register
contents are set to 00010000 by the POR). After a POR, the
microprocessor is held off for approximately 20 ms for the VCC
supply to stabilize before executing the first instruction at
address 0x00 in the Flash. If the VCC voltage drops below the
POR downward supply trip point, POR is reasserted. The VCC
supply needs to ramp linearly from 0 to 4 V in 0 to 200 ms.
Important The PORS status bit is set at POR and can only be
cleared by the user. It cannot be set by firmware.
Watchdog Timer Reset
The user has the option to enable the WDT . The WDT is enabled
by clearing the PORS bit. When the PORS bit is cleared, the
WDT cannot be disabled. The only exception to this is if a POR
event takes place, which disables the WDT.
The sleep timer is used to generate the sleep time period and the
W atchdog time period. The sleep timer is clocked by the Internal
32 kHz Low power Oscillator system clock. The user can
program the sleep time period using the Sleep Timer bits of the
OSC_CR0 Register (Table 36). When the sleep time elapses
(sleep timer overflows), an interrupt to the Sleep Timer Interrupt
Vector is generated.
The Wa tchdog Timer period is automatically set to be three
counts of the Sleep Timer over flows. This represents between
two and three sleep intervals dependi ng on the count in the
Sleep Timer at the previous WDT clear . When this timer reaches
three, a WDR is generated.
The user can either clear the WDT, or the WDT and the Sleep
Timer. Whenever the user writes to the Reset WDT Register
(RES_WDT), the WDT is cleared. If the data that is written is the
hex value 0x38, the Sleep Timer is also cleared at the same time.
Sleep Mode
The CPU can only be put to sleep by the firmware. This is accom-
plished by setting the Sleep bit in the System S tatus and Control
Register (CPU_SCR). This stops the CPU from executing
instructions, and th e CP U remains asleep until an interrupt
comes pending, or there is a reset event (either a Power on
Reset, or a Wa tchdog Timer Reset).
The internal 32 kHz low speed oscillator remains running. Prior
to entering suspend mode, firmware can optionally configure the
32 kHz Low speed Oscillator to operate in a low power mode to
help reduce the overall power consumption (using Bit 7,
Table 34). This helps save approximately 5 A; however, the
trade off is that the 32 kHz Low speed Oscillator is less accurate.
All interrupts remain active. Only the occurrence of an interrupt
wakes the part from sleep. The Stop bit in the System Status and
Control Register (CPU_SCR) must be cleared for a part to
resume out of sleep. The Global Interrupt Enable bit of the CPU
Flags Register (CPU_F) does not have any effect. Any
unmasked interrupt wakes the system up. As a result, any inter-
rupts not intended for waking must be disabled through the
Interrupt Mask Registers.
When the CPU exits sleep mode the CPUCLK Select (Bit 1,
Table 35) is forced to the Internal Oscilla tor. The internal oscil-
lator recovery time is three clock cycles of the Internal 32 kHz
Low power Oscillator. The Internal 24 MHz Oscillator restarts
immediately on exiting Sleep mode.
On exiting sleep mode, when the cl ock is stable and the delay
time has expired, the instruction immediately following the sleep
instruction is executed before the interrupt service routine (if
enabled).
The Sleep interrupt allows the microcontroller to wake up period-
ically and poll system components while maintaining very low
average power consumption. The Sleep interrupt may also be
used to provide periodic interrupts during non sleep modes.
Sleep Sequence
The SLEEP bit is an input into the sleep logic circuit. This circuit
is designed to sequence the device into and out of the hardware
sleep state. The hardware sequence to put the device to sleep
is shown in Figure 11 and is defined as follows.
1. Firmware sets the SLEEP bit in the CPU_SCR0 register . The
Bus Request (BRQ) signal to the CPU is immediately
asserted. This is a request by the system to halt CPU
operation at an instruction boundary . The CPU samples BRQ
on the positive edge of CPUCLK.
2. Due to the specific timing of the register write, the CPU issues
a Bus Request Acknowledge (BRA) on the following positive
edge of the CPU clock. The sleep logic waits for the following
negative edge of the CPU clock and then asserts a
system-wide Power-down (PD) signal. In Figure 11 the CPU
is halted and the system-wide power-down signal is asserted.
3. The system-wide PD (power-down) signal controls several
major circuit blocks: The Flash memory module, the internal
24 MHz oscillator, the EFTB filter and the bandgap voltage
Table 41 . Reset Watchd og Timer (RESWDT) [0xE3] [W]
Bit # 76543210
Field Reset Watchdog Timer [7:0]
Read/Write WWWWWWW W
Default 0000000 0
Any write to this register clears Watchdog Timer, a write of 0x38 also clears the Sleep Timer
Bits 7:0 Reset Watchdog Timer [7:0]
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reference. These circuits transition into a zero power state.
The only operational circuits on chip are the low power oscil-
lator, the band gap refresh circuit, and the supply voltage
monitor (POR) circuit.
Note To achieve the lowest possible power consumption during
suspend/sleep, the following conditions must be observed in
addition to cons iderations for the sleep ti mer.
■All GPIOs must be set to outputs and driven low
■The USB pins P1.0 and P1.1 should be configured as inputs
with their pull-ups enabled.
Figure 11. Sleep Timing
Wakeup Sequence
When asleep, the only event that can wake the system up is an
interrupt. The global in terrupt enable of the CPU flag register
does not need to be set. Any unmasked interrupt wakes the
system up. It is optional for the CPU to actually take the interrupt
after the wakeup sequence. The wakeup sequence is sync hro-
nized to the 32 kHz clock for purpose s of sequencing a startup
delay, to allow the Flash memory module enough time to
power-up before the CPU asserts the first read access. Another
reason for the delay is to allow the oscillator , Bandgap, and POR
circuits time to settle before actually being used in the system.
As shown in Figure 12, the wakeup sequence is as follows:
1. The wakeup interrupt occurs and is synchronized by the neg-
ative edge of the 32 kHz clock.
2. At the following positive edge of the 32 kHz clock, the
system-wide PD signal is negated. The Flash memory
module, internal oscillator , EFTB, and bandgap circuit are all
powered up to a normal operatin g state.
3. At the following positive edge of the 32 kHz clock, the current
values for the precision POR have settled and are sampled.
4. At the following negative edge of the 32 kHz clock (after about
15 µs nominal), the BRQ signal is negated by the sleep logic
circuit. On the following CPUCLK, BRA is negated by the CPU
and instruction execution resumes. Note that in Figure 12
fixed function blocks, such as Flash, internal oscillator , EFTB,
and bandgap, have about 15 µs start up. The wakeu p times
(interrupt to CPU operational) ranges from 75 µs to 105 µs.
Low Power in Sleep Mode
The following steps are mandatory before configuring the system
into suspend mode to meet the specifications:
1. Clear P11CR[0], P10CR[0] - during USB and Non-USB oper-
ations
2. Clear the USB Enable USBCR[7] - during USB mode opera-
tions
3. Set P10CR[1] - during non-USB mode op erations
4. To avoid current consumpt ion make sure ITMRCLK,
TCPCLK, and USBCLK are not sourced by either low power
32 kHz oscillator or 24 MHz cryst al-less oscillator.
All the other blocks go to the power-down mode automatically on
suspend.
Firmware write to SC R
SLEEP bit causes an
immediate BRQ
IOW
SLEEP
BRQ
PD
BRA
CPUCLK
CPU captures
BRQ on next
CPUCLK edge
CPU
responds
with a BRA
On the falling edge of
CPUCLK, PD is asserted.
The 24/48 MHz system clock
is halted; the Flash and
bandgap are powered down
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The following steps are user configurable and help in reducing the average suspend mode power consumption.
1. Configure the power supply monitor at a large regular intervals, control register bits are 1,EB[7:6] (Power system sleep duty cycle
PSSDC[1:0]).
2. Configure the low power oscillator into low power mode, control register bit is LOPSCTR[7].
Figure 12. Wakeup Timing
INT
SLEEP
PD
PPOR
BANDGAP
CLK32K
SAMPLE
SAMPLE
POR
CPUCLK/
24MHz
BRA
BRQ
ENABLE
CPU
(Not to Scale)
Sleep Timer or GPIO
interrupt occurs
Interrupt is double sampled
by 32K clock and PD is
negated to system
CPU is restarted
after 90 ms
(nominal)
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Power-on Reset Control
This register controls the configuration of the Power on Rese t block
Bits 7:6 Reserved
Bits 5:4 PORLEV[1:0]
This field controls the level below which the precision power-on-reset (PPOR) detector generates a reset
0 0 = 2.7 V Range (trip near 2.6 V)
0 1 = 3 V Range (trip near 2.9 V)
1 0 = 5 V Range, >4.75 V (trip near 4.65 V). This setting must be used when operating the CPU above 12 MH z.
1 1 = PPOR does not generate a reset, but values read from the Voltage Monitor Comparators Register (Table 43) give the internal
PPOR comparator state with trip point set to the 3 V range setting
Bits 3:0 Reserved
POR Compare State
ECO Trim Register
Table 42 . Power On Reset Control Register (POR CR) [0x1E3] [R/W]
Bit # 7 6 5 4 3 2 1 0
Field Reserved PORLEV[1:0] Reserved
Read/Write – – R/W R/W ––– –
Default 0 0 0 0 000 0
Table 43. Voltage Monitor Comparators Register (VLTCMP) [0x1E4] [R]
Bit # 76543210
Field Reserved PPOR
Read/Write ––––––– R
Default 0000000 0
This read-only register allows reading the current state of the Precision-Power-On-Reset comparators
Bits 7:1 Reserved
Bit 0 PPOR
This bit is set to indicate that the precision-power-on-reset comparator has tripped, indicating that the supply voltage is below
the trip point set by PORLEV[1:0]
0 = No precision-power-on-reset event
1 = A precision-po w e r-on -re se t eve nt has tripped
Table 44 . ECO (ECO_TR) [0x1EB] [R/W]
Bit # 76543210
Field Sleep Duty Cycle [1 :0] Reserved
Read/Write R/W R/W – – – – – –
Default 0000000 0
This register co ntrols the ratios (in numbers of 32 kHz clock periods) of ‘on’ time versus ‘off’ time for POR detection circuit
Bits 7:6 Sleep Duty Cycle [1:0]
0 0 = 1/128 periods of the Internal 32 kHz Low speed Oscillator
0 1 = 1/512 periods of the Internal 32 kHz Low speed Oscillator
1 0 = 1/32 periods of the Internal 32 kHz Low speed Oscillator
1 1 = 1/8 periods of the Internal 32 kHz Low speed Oscillator
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General-Purpose I/O Ports
The general purpose I/O ports are discussed in the following sections.
Port Data Registers
Table 45. P0 Data Register (P0DATA)[0x00] [R/W]
Bit # 7 6 5 4 3 2 1 0
Field P0.7 Reserved Reserved P0.4/INT2 P0.3/INT1 Reserved P0.1 Reserved
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 00000000
This register contains the data for Port 0. Writing to this register sets the bit values to be output on output enabled pins. Reading
from this register returns the current state of the Port 0 pins
Bit 7 P0.7 Data
Bits 6:5 Reserved
The use of the pins as the P0.6–P0.5 GPIOs and the alternative functions exist in the CYRF69313
Bits 4:3 P0.4–P0.3 Data/INT2 – INT1
In addition to their use a s the P0.4–P0.3 GPIOs, these pins can also be used for the alternative fun ctions as the Interrupt pins
(INT0–INT2). To configure the P0.4–P0.3 pins, refer to the P0 .3/INT1–P0.4/INT2 Configuration Regi ster (Table 49)
The use of the pins as the P0.4–P0.3 GPIOs and the alternative functions exist in the CYRF69313
Bit 2 Reserved
Bit 1 P0.1
Bit 0 Reserved
Table 46 . P1 Data Register (P1DATA) [0x01] [R/W]
Bit # 7 6 5 4 3 2 1 0
Field P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P1.3/SSEL P1.2 P1.1/D– P1.0/D+
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
This register contains the data for Port 1. Writing to this register sets the bit values to be output on output enabled pins. Reading
from this register returns the current state of the Port 1 pins
Bit 7 P1.7 Data
Bits 6:3 P1.6–P1.3 Data/SPI Pins (SMISO, SMOSI, SCLK, SSEL)
In addition to their use as the P1.6–P1.3 GPIOs, these pins can also be used for the alternative function as the SPI interface pins.
To configure the P1.6–P1.3 pins, refer to the P1.3–P1.6 Configuration Register (Table 54)
The use of the pins as the P1.6–P1.3 GPIOs and the alternative functions exist in all the CYRF69313 parts
Bit 2 P1.2
This pin is used as the regulator output.
Bits 1:0 P1.1–P1.0/D– and D+
When USB mode is disabled (Bit 7 in Table 78 is clear), the P1.1 and P1.0 bits are used to control the state of the P1.0 and P1.1
pins. When the USB mode is enabled, the P1.1 and P1.0 pins are used as the D– an d D+ pins, respectively. If the USB F orce
State bit (Bit 0 in Table 77) is set, the state of the D– and D+ pins can be controlled by writing to the D– and D+ bits
Table 47 . P2 Data Register (P2DATA) [0x02] [R/W]
Bit # 76543210
Field Reserved P2.1–P2.0
Read/Write ------R/W R/W
Default 00000000
This register contains the data for Port 2. Writing to this register sets the bit values to be output on output enabled pins. Reading
from this register returns the current state of the Port 2 pins
Bits 7:2 Reserved Data [7:2]
Bits 1:0 P2 Data [1:0]
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GPIO Port Configuration
All the GPIO configuration registers have common configuration
controls. The following are the bit definitions of the GPIO config-
uration registers.
Int Enable
When set, the Int Enable bit allows the GPIO to generate inter-
rupts. Interrupt generate can occur regardless of whether the pin
is configured for input or output. All interrupts are edge sensitive,
however for any interrupt that is shared by multiple sources (that
is, Ports 2, 3, and 4) all inputs must be deasserted before a new
interrupt can occur.
When clear, the corresponding interrupt is disabled on the pin.
It is possible to configure GPIOs as outputs, enable the interrupt
on the pin and then to generate the interrupt by driving the appro-
priate pin state. This is useful in test and may have value in appli-
cations as well.
Int Act Low
When set, the corresponding interrupt is active on the falling
edge.
When clear, the corresponding interrupt is active on the rising
edge.
TTL Thresh
When set, the input has TTL threshold. When clear, the input has
standard CMOS threshold.
High Sink
When set, the output can sink up to 50 mA.
When clear, the output can sink up to 8 mA.
On the CYRF69313, only the P1.7–P1.3 have 50 mA sink drive
capability. Other pins have 8 mA sink drive capability.
Open Drain
When set, the output on the pin is determined by the Port Data
Register . If the corresponding bit in the Port Data Register is set,
the pin is in high impedance state. If the corresponding bit in the
Port Data Register is clear, the pin is driven low.
When clear, the outpu t is driven LOW or HIGH.
Pull-up Enable
When set the pin has a 7 K pull-up to VCC.
When clear, the pull-up is disabled.
Output Enable
When set, the output driver of the pin is enabled.
When clear, the output driver of the pin is disabled.
For pins with shared functions there are some special cases.
SPI Use
The P1.3 (SSEL), P1.4 (SCLK), P1.5 (SMOSI) and P1.6
(SMISO) pins can be used for their dedicated functions or for
GPIO.
The SPI function controls the output enable for its dedicated
function pins when their GPIO enable bit is clear.
3.3 V Drive
The P1.3 (SSEL), P1.4 (SCLK), P1.5 (SMOSI) and P1.6
(SMISO) pins have an alternate voltage source from the voltage
regulator. If the 3.3 V Drive bit is set a high level is driven from
the voltage regulator instead of from VCC.
Table 48. P0.1 Configuration (P01CR ) [0x06] R/W]
Bit # 76543210
Field Reserved Int Enable Int Act Low TTL Thresh High Sink Open Drain Pull-up
Enable Output
Enable
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0000000 0
This register is used to configure P0.1 In the CYRF69313, only 8 mA sink drive capability is available on this pin regardless of
the setting of the High Sink bit
Bit 7: Reserved
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Table 49. P0.3/INT1–P0.4/INT2 Configurat ion (P03CR–P04CR) [0x08–0x09] [R/W]
Bit # 76543210
Field Reserved Int Act Low TTL Thresh Reserved Open Drain Pull-up En-
able Output En-
able
Read/Write – – R/W R/W –R/WR/W R/W
Default 0000000 0
These registers control the operation of pins P0.3–P0.4, respectively . These pins are shared between the P0.3–P0.4 GPIOs and
the INT0–INT2. These registers exist in all CYRF69313 parts. The INT0–INT2 interrupts are different than all the other GPIO
interrupts. These pins are connected directly to the interrupt controller to provide three edge-sensitive interrupts with independent
interrupt vectors. These interrupts occur on a rising edge when Int act Low is clear and on a falling edge when Int act Low is set.
These pins are enabled as interrupt sources in the interrupt controll er registers (Table 75 and Table 73)
To use these pins as interrupt inputs configure them as inputs by clearing the corresponding Output Enable. If the INT0–INT2
pins are configured as outputs with interrupts enabled, firmware can generate an interrupt by writing the appropriate value to the
P0.3 and P0.4 data bits in the P0 Data Register
Regardless of whether the pins are used as Interrupt or GPIO pins the Int Enable, Int act Low , TTL Threshold, Open Drain, and
Pull-up Enable bits control the behavior of the pin
The P0.3/INT1–P0.4/INT2 pins are individually configured with the P0 3CR (0x08), and P04CR (0x09), respectively.
Note Changing the state of the Int Act Low bit can cause an unintentional interrupt to be generated. When configuring these
interrupt sources, it is best to follow the following procedure:
1. Disable interrupt source
2. Configure interrupt source
3. Clear any pending interrupts from the source
4. Enable interrupt source
Table 50. P0.7 Configuration (P07CR) [0x0C] [R/W]
Bit # 76543210
Field Reserved Int Enable In t Act Low TTL Thresh Reserved Open Drain Pull-up En-
able Output En-
able
Read/Write –R/W R/W R/W –R/W R/W R/W
Default 00000000
This regist er co nt rol s th e op e r a ti o n of pin P0.7.
Table 51. P1.0/D+ Configuration (P10CR) [0x0D] [R/W]
Bit # 76543210
Field Reserved Int Enable Int Act Low Reserved 5 K pull-up
enable Output En-
able
Read/Write R/W R/W R/W ––––R/W
Default 0000000 0
This register controls the ope r a ti o n of the P1.0 (D+ ) pin when the USB interface is not enabled, allowing the pin to be used as
a GPIO pin which is pulled up. See Table 78 for information on enabling USB. When USB is enabled, none of the controls in this
register have any effect on the P1.0 pin
Note The P1.0 is an open drain only output. It can actively drive a signal low, but cannot actively drive a signal high
Bit 1 5 K Pull-up Enable
0 = Disable the 5 k pull-up resistors
1 = Enable 5 k pull-up resistors for b oth P1.0 an d P1.1. Enable th e use of the P1.0 (D+) and P1.1 (D–) pins a s pulled up
GPIOs
Bit 0This bit enables the output on P1.0/D+. This bit should be cleared in sleep mode.
CYRF69313
Document #: 001-66503 Rev. *B Page 40 of 78
Tab le 52 . P1.1/D– Configuration (P11CR) [0x0E] [R/W]
Bit # 76543210
Field Reserved Int Enable Int Act Low Reserved Open Drain Reserved Output En-
able
Read/Write –R/W R/W ––R/W–R/W
Default 0000000 0
This regist er co nt rol s th e op e r a ti o n of the P1.1 (D–) pin when the USB interface is not enabled, allowing the pin to be used as
a GPIO. See Table 78 for information on enabling USB. When USB is enabled, none of the controls in this register have any
effect on the P1.1 pin. When USB is disabled, the 5 k pull-up resistor on this pin can be enabled by the 5 K Pull-up Enable bit
of the P10CR Register (Table 51)
Bit 0This bit enables the output on P1.1/D-. This bit should be clea red in sleep mode.
Note There is no 2 mA sourcing capability on this pin. The pin can only sink 5 mA at VOL3
Tab le 53. P1.2 Configurat ion (P12CR) [0x0F] [R/W]
Bit # 76543210
Field CLK Output Int Enable Int Act Low TTL Thresh-
old Reserved Open Drain Pull-up En-
able Output En-
able
Read/Write R/W R/W R/W R/W –R/WR/W R/W
Default 0000000 0
This register controls the ope r a ti o n of the P1.2
Bit 7 CLK Output
0 = The internally selected clock is not sent out onto P1.2 pin
1 = When CLK Output is set, the internally selected clock is sent out onto P1.2 pin
Table 54. P1.3 Configuration (P13CR) [0x10] [R/W]
Bit # 76543210
Field Reserved Int Enable Int Act Low 3.3 V Drive High Sink Open Drain Pull-up En-
able Output En-
able
Read/Write –R/W R/W R/W R/W R/W R/W R/W
Default 0000000 0
This register controls the ope r a ti o n of the P1.3 pin. This register exists in all CYRF69313 parts
The P1.3 GPIO’s threshold is always set to TTL
When the SPI hardware is enabled, the output enable and output state of the pin is controlled by the SPI circuitry . When the SPI
hardware is disabled, the pin is controlled by the Output Enable bit and the correspo nding bit in the P1 data register
Regardless of whether the pin is used as an SPI or GPIO pin the Int Enable, Int act Low, 3.3 V Drive, High Sink, Open Drain,
and Pull-up Enable control the behavior of the pin
The 50 mA sink drive capability is only available in the CY7C638xx.
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Table 55 . P1.4–P1.6 Configuration (P14CR–P16CR) [0x11–0x13] [R/W]
Bit # 7 6 5 4 3 2 1 0
Field SPI Use I nt Enable Int Act Low 3.3 V Drive High Sink Open Drain Pull-up En-
able Output En-
able
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0000000 0
These registers control the operation of pins P1.4–P1.6, respectively
The P1.4–P1.6 GPIO’s threshold is always set to TTL
When the SPI hardware is enabled, pins that are configured as SPI Use have their output enable and output state controlled by the
SPI circuitry. When the SPI hardware is disabled or a pin has its SPI Use bit clear , the pin is controlled by the Output Enable bit and
the corresponding bit in the P1 data register
Regardless of whether any pin is used as an SPI or GPIO pin the Int Enable, Int act Low, 3.3 V Drive, High Sink, Open Drain, and
Pull-up Enable control the beha vior of the pin
Bit 7 SPI Use
0 = Disable the SPI alternate function. The pin is use d as a GPIO
1 = Enable the SPI function. The SPI circuitry controls the outpu t of the pin
Important Note for Comm Modes 01 or 10 (SPI Master or SPI Slave, see Table 59)
When configured for SPI (SPI Use = 1 and Comm Modes [1:0] = SPI Master or SPI Slave mode), the input/output direction of pins
P1.3, P1.5, and P1.6 is set automatically by the SPI logic. However, pin P1.4's input/output direction is NOT automatically set; it must
be explicitly set by firmware. For SPI Master mode, pin P1.4 must be configured as an output; for SPI Slave mode, pin P1.4 must
be configured as an input
Table 56 . P1.7 Configuration (P17CR) [0x14] [R/W]
Bit # 7 6 5 4 3 2 1 0
Field Reserved Int Enable Int Act Low TTL Thresh High Sink Open Drain Pull-up Enable Output Enable
Read/Write – R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
This register controls the operation of pin P1.7. This register only exists in CY7C638xx
The 50 mA sink drive capability is only available in the CY7C638xx. The P1.7 GPIO’s threshold is always set to TTL
Tab le 57 . P2 C on f iguration (P2CR) [0x15] [R/W]
Bit # 7 6 5 4 3 2 1 0
Field Reserved Int Enable Int Act Low TTL Thresh High Sink Open Drain Pull-up Enable Output Enable
Read/Write – R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
This register only exists in CY7C638xx. This register controls the operation of pins P2.0–P2.1. In the CY7C638xx, only 8 mA sink drive capability is
available on this pin regardless of the setting of the High Sink bit
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GPIO Configurations for Low Power Mode:
To ensure low power mode, unbonded GPIO pins in CYRF69313 must be placed in a non floating state. The following assembly code
snippet shows how this is achieved. This snippe t c an be added as a part of the initialization routine.
//Code Snippet for addressing unbonded GPIOs
mov A, 00h
mov reg[1Fh],A
mov A, 01h
mov reg[16h],A // Port3 Configuration register - Enable ouptut
mov A, 00h
mov reg[03h],A // Asserting P3.0 and P3.1 outputs to '0'
mov A, 01h
mov reg[05h],A // Port0.0 Configuration register - Enable output
mov reg[07h],A // Port0.2 Configuration register - Enable output
mov reg[0Ah],A // Port0.5 Configuration register - Enable output
mov reg[0Bh],A // Port0.6 Configuration register - Enable output
mov A,reg[00h]
mov A,00h
and A,9Ah
mov reg[00h], A // Asserting outputs '0' to pins in port 1
When writing to port 0 , to access GPIOs P0.1,3,4,7, mask bits 0,2,5,6. Failing to do so voids the low power
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Serial Peripheral Interface (SPI)
The SPI Master/Slave Interface core logic runs on the SPI clock domain, making its functionality independent of system clock speed.
SPI is a four pin serial interface comprised of a clock, an enable and two data pins.
Figure 13. SPI Block Diagram
SPI State M achine
SS_N
Data (8 bit)
Load
Empty
Data (8 bit)
Load
Full
Sclk Output Enable
Slave Select Output Enable
M aster IN, Slave Out OE
M aster Out, Slave In, OE
S h ift Bu ffe r
Input Shift Buffer
Output Shift Buffer
SCK C lock Generation
SCK Clock Select
SCK C lock Phase/Polarity
Select
Register Block
SCK Speed Sel
Mas te r/S la v e S e l
SCK Polarity
SCK Phase
Little Endian Sel
MISO/MOSI
Crossbar
GPIO Block
SS_N
LE_SEL
SCK
LE_SEL
SCK_OE
SS_N_OE
MISO_OE
MOSI_OE
SCK
SCK_OE
SS_N_OE
SCK
SS_N
Ma s ter/Slave Se t MISO
MOSI
MISO_OE
MOSI_OE
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SPI Data Register
When an interrupt occurs to indicate to firmware that a byte of receive data is available, or the transmitter holding register is empty,
firmware has 7 SPI clocks to manage the buffers—to empty the receiver buffer , or to refill the transmit holding register . Failure to meet
this timing requirement results in incorrect data transfer.
SPI Configure Register
Table 58. SPI Data Register (SPIDATA) [0x3C] [R/W]
Bit # 76543210
Field SPIData[7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0000000 0
When read, this register returns the contents of the receive buffer. When written, it loads the transmit holding register
Bits 7:0 SPI Data [7:0]
Table 59. SPI Configure Register (SPICR) [0x3D] [R/W]
Bit # 76543210
Field Swap LSB First Comm Mode CPOL CPHA SCLK Select
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0000000 0
Bit 7 Swap
0 = Swap function disabled
1 = The SPI block swaps its use of SMOSI and SMISO. Among other things, this can be useful in implementing single wire
SPI-like communications
Bit 6 LSB First
0 = The SPI transmits and receives the MSB (Most Signifi c ant Bit) first
1 = The SPI transmits and receives the LSB (Least Significant Bit) first.
Bits 5:4 Comm Mode [1:0]
0 0: All SPI communication disabled
0 1: SPI master mode
1 0: SPI slave mode
1 1: Reserved
Bit 3 CPOL
This bit controls the SPI clock (SCLK) idle polarity
0 = SCLK idles low
1 = SCLK idles high
Bit 2 CPHA
The Clock Phase bit co ntrols the p hase of the clock on whi ch data is sample d. Table 60 shows the ti ming for the various com-
binations of LSB First, CPOL, and CPHA
Bits 1:0 SCLK Select
This field selects the speed of the master SCLK. When in master mode, SCLK is generated by dividing the base CPUCLK
Important Note for Comm Modes 01b or 10b (SPI Master or SPI Slave):
When configured for SPI, (SPI Use = 1—Table 55), the input/output direction of pins P1.3, P1.5, and P1.6 is set automatically by
the SPI logic. However, pin P1.4's input/output direction is NOT automatically set; it must be explicitly set by firmware. For SPI
Master mode, pin P1.4 must be configured as an output; for SPI Slave mode, pin P1.4 must be configured as an input
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Table 60. SPI Mode Timing vs. LSB First, CPOL and CPHA
LSB First CPHA CPOL Diagram
000
001
010
011
100
101
110
111
SCLK
SSEL
DATA X XMSB Bit 2Bit 3Bi t 4Bit 5Bi t 6Bi t 7 LSB
SCLK
SSEL
X X
DATA MSB Bit 2Bi t 3Bi t 4Bi t 5Bit 6Bi t 7 LSB
SCLK
SSEL
X X
DATA MSB Bit 2Bi t 3Bit 4Bi t 5Bit 6Bit 7 LSB
SCLK
SSEL
DATA X XMSB Bit 2Bi t 3Bit 4Bi t 5Bit 6Bit 7 LSB
SCLK
SSEL
DATA X XMSBBit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7LSB
SCLK
SSEL
X X
DATA MSBBit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7LSB
SCLK
SSEL
X X
DATA MSBBit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7LSB
SCLK
SSEL
DATA XMSB XBit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7LSB
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Timer Registers
All timer functions of the CYRF69313 are provided by a single timer block. The timer block is asynchronous from the CPU clock.
Registers
Free-Running Counter
The 16-bit free-running counter is clocked by a 4/6 MHz source.
It can be read in software for use as a general purpose time base.
When the low order byte is read, the high order byte is registered.
Reading the high order byte reads this register allowing the CPU
to read the 16-bit value atomically (loads all bits at one time). The
free-running timer generates an interrupt at a 1024 s rate. It can
also generate an interrupt when the free-running counter
overflow occurs—every 16.384 ms. This allows extending the
length of the timer in software.
Figure 14. 16-Bit Free-Running Co unter Block Diagram
Table 61. SPI SCLK Frequency
SCLK
Select CPUCLK
Divisor SCLK Frequency when CPUCLK =
12 MHz 24 MHz
00 6 2 MHz 4 MHz
01 12 1 MHz 2 MHz
10 48 250 KHz 500 KHz
11 96 125 KHz 250 KHz
Tim er Capture
Clock 16-bit Free
Ru nning C ounter
Overflow
Interrupt
1024-µs
Timer
Interrupt
Table 62. Free-Running Timer Low Order Byte (FRTMRL) [0x20] [R/W]
Bit # 76543210
Field Free-running Timer [7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0000000 0
Bits 7:0 Free-running Timer [7:0]
This register holds the low order byte of the 16-bit free-running timer. Reading this re gi st er ca uses the high orde r byt e to be
moved into a holding register allowing an automatic read of all 16 bi ts simultaneously.
For reads, the actual read occurs in the cycle when the low order is read. For writes, the actual time the write occurs is the cycle
when the high order is written
When reading the free-running timer, the low order byte should be read first and the high order second. Wh en writing, the low
order byte should be written first then the high order byte
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Table 63. Free-Running Timer High Order Byte (FRTMRH) [0x21] [R/W]
Bit # 76543210
Field Free-running Timer [15:8]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0000000 0
Bits 7:0 Free-running Timer [15:8]
When reading the free-running timer, the low order byte should be read first and the high order second. Wh en writing, the low
order byte should be written first then the high order byte
Table 64 . Programmable Interval Timer Low (PITMRL) [0x26] [R]
Bit # 7 6 5 4 3 2 1 0
Field Prog Interval Tim er [7:0]
Read/Write R R R R RRR R
Default 0000000 0
Bits 7:0 ‘Prog Interval Timer [7:0]
This register holds the low order byte of the 12-bit programmable interval timer . Reading this register causes the high order byte to
be moved into a holding register allowing an automatic read of all 12 bits simultaneously
Table 65. Programmable Interval Timer High (PITMRH) [0x27] [R]
Bit # 76543210
Field Reserved Prog Interval Timer [11:8]
Read/Write ––––RRR R
Default 0000000 0
Bits 7:4 Reserved
Bits 3:0 Prog Internal Timer [11:8]
This register holds the high order nibble of th e 12-bit programmable interval timer. Reading this register returns the high order
nibble of the 12-bit timer at the instant that the low order byte wa s last read
Table 66. Programmable Interval Reload Low (PIRL) [0x28] [R/W]
Bit # 76543210
Field Prog Interval [7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0000000 0
Bits 7:0 Prog Interval [7:0]
This register holds the lower 8 bits of the timer. While writing into the 12-bit reload register, write lower byte first then the higher
nibble
Table 67 . Programmable Interval Reload High (PIRH) [0x29] [R/W]
Bit # 76543210
Field Reserved Prog Interval[11:8]
Read/Write ––––R/W R/W R/W R/W
Default 0000000 0
Bits 7:4 Reserved
Bits 3:0 Prog Interval [11:8]
This register holds the higher 4 bits of the timer . While writing into the 12-bit reload register , write lower byte first then the higher
nibble
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Figure 15. 16-Bit Fre e-Running Counter Loading Timing Diagram
Figure 16. Me mory Mapped Registers Read/Write Timing Diagram
clk_sys
write
valid
addr
write data
FRT reload
ready
Clk Timer
12b Prog Timer
12b reload
interrupt
Capture timer
clk
16b free running
counter load
16b free
running counter 00A0 00A1 00A2 00A3 00A4 00A5 00A6 00A7 00A8 00A9 00AB 00AC 00AD 00AE 00AF 00B0 00B1 00B2 ACBE ACBF ACC0
16-bit free running count er loading t iming
12-bit program mable timer load timing
Memory mapped registers Read/Write timing diagram
clk_sys
rd_wrn
Valid
Addr
rdata
wdata
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Interrupt Controller
The interrupt controller and its associated registers allow the
user’s code to respond to an interrupt from almost every
functional block in the CYRF69313 devices. The registers
associated with the interrupt controller allow interrupts to be
disabled either globally or individually . The registers also provide
a mechanism by which a user may clear all pending and posted
interrupts, or clear individual posted or pending interrupts.
The following table lists all interrupts and the priorities that are
available in the CYRF69313.
Architectural Description
An interrupt is posted when its interrupt conditions occur. Th is
results in the flip-flop in Figure 17 clocking in a ‘1’. The interrupt
remains posted until the interrupt is taken or until it is cleared by
writing to the appropriate INT_CLRx register.
A posted interrupt is not pending unless it is enab led by setting
its interrupt mask bit (in the appropriate INT_MSKx register). All
pending interru pts are processed by the Priority Encoder to
determine the highest priority interrupt which is taken by the M8C
if the Global Interrupt Enable bit is set in the CPU_F register.
Disabling an interrupt by clearing its interrupt mask bit (in the
INT_MSKx register) does not clear a posted interrupt, nor does
it prevent an interrupt from being posted. It simply prevents a
posted interrupt from becoming pending.
Nested interrupts can be accomplished by re-enabling interrupts
inside an interrupt service routine. To do this, set the IE bit in the
Flag Register.
A block diagram of the CYRF69313 Interrupt Controller is shown
in Figure 17.
Figure 17. Interrupt Controller Block Diagram
Table 68. Interrupt Numbers, Priorities, Vectors
Interrupt
Priority Interrupt
Address Name
0 0000h Reset
1 0004h POR
2 0008h INT0
3 000Ch SPI Transmitter Empty
4 0010h SPI Receiver Full
5 0014h GPIO Port 0
6 0018h GPIO Port 1
7001ChINT1
8 0020h EP0
9 0024h EP1
10 0028h EP2
11 002Ch USB Reset
12 0030h USB Active
13 0034h 1 ms Interval timer
14 0038h Programmable Interval T imer
15 003Ch Reserved
16 0040h Reserved
17 0044h 16-bit Free Running Timer Wrap
18 0048h INT2
19 004Ch Reserved
20 0050h GPIO Port 2
21 0054h Reserved
22 0058h Reserved
23 005Ch Reserved
24 0060h Reserved
25 0064h Sleep Timer
Table 68. Interrupt Numbers, Priorities, Vectors (continued)
Interrupt
Priority Interrupt
Address Name
Interrupt
Source
(Timer,
GPIO, etc.)
Interrupt Taken
or
Posted
Interrupt Pending
Interrupt
GIE
Interrupt Vector
Mask Bit Setting
DRQ1
Priority
Encoder
M8C Cor e
Interrupt
Request
...
INT_MSKx
INT_CLRx Write
CPU_F[0]
...
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Interrupt Processing
The sequence of events that occur during interrupt processing is
as follows:
1. An interrupt becomes active, either because:
a. The interrupt condition occurs (for example, a timer expires).
b. A previously posted interrupt is enabled through an update
of an interrupt mask register.
c. An interrupt is pending and GIE is set from 0 to 1 in the CPU
Flag register.
d. The GPIO interrupts are edge triggered.
1. The current executing instruction finishes.
2. The internal interrupt is dispatched, taking 13 cycles. During
this time, the following actions occur:
a. The MSB and LSB of Program Counter and Flag registers
(CPU_PC and CPU_F) are stored onto the program stack
by an automatic CALL instruction (13 cycles) generated
during the interrupt acknowledge process.
b. The PCH, PCL, and Flag register (CPU_F) are stored onto
the program st a ck (in that order) by an automatic CAL L
instruction (13 cycles) generated during the interrupt
acknowledge process.
c. The CPU_F register is then cleared. Because this clears the
GIE bit to 0, additional interrupts are temporarily disabled
d. The PCH (PC[15:8]) is cleared to zero.
e. The interrupt vector is read from the interrupt controller and
its value pl a c e d int o PC L (PC [7:0]). This sets the program
counter to point to the appropriate address in the interrupt
table (for example, 0004h for the POR interrupt).
1. Program execution vectors to the interrupt table. Typically, a
LJMP instruction in the interrupt table sends execution to the
user's Interr up t Service Routine (ISR) for this interrupt.
2. The ISR executes. Note that interrupts are disabled because
GIE = 0. In the ISR, interrupts can be re-enabled if desired by
setting GIE = 1 (care must be taken to avoid stack overflow).
3. The ISR ends with a RETI instruction which restore s the
Program Counter and Flag registers (CPU_PC and CPU_F).
The restored Flag register re-enables interrupts, because GIE
= 1 again.
4. Execution resumes at the next instruction, after the one that
occurred before the interrupt. However, if there are more
pending interrupts, the subsequent interrupts are processed
before the next normal program instruction.
Interrupt Latency
The time between the assertion of an enabled interrupt and the
start of its ISR can be calculated from the following equation.
Latency = Time for current instruction to finish + Time for internal
interrupt routine to execute + Time for LJMP instruction in
interrupt table to execute.
For example, if the 5 cycle JMP instruction is executing when an
interrupt becomes active, the total number of CPU clock cycles
before the ISR begins would be as follows:
(1 to 5 cycles for JMP to finish) + (13 cycles for interrupt routine)
+ (7 cycles for LJMP) = 21 to 25 cycles.
In the example above, at 24 MHz, 25 clock cycles take 1.042 s.
Interrupt Registers
The Interrupt Registers are discusse d it the following sections.
Interrupt Clear Register
The Interrupt Clear Registers (INT_CLRx) are used to enable the
individual interrupt sources’ ability to clear posted interrupts.
When an INT_CLRx register is read, any bits that are set
indicates an interrupt has been posted for that hardware
resource. Ther efore, reading these register s gi ve s the user the
ability to determine all posted interrupts.
Table 69 . Interru pt Clear 0 (INT_CLR0) [0xDA] [R/W]
Bit # 76543210
Field GPIO Port 1 Sleep Timer INT1 GPIO Port 0 SPI Receive SPI Transmit INT0 POR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0000000 0
When reading this register,
0 = There’s no posted interrupt for the corresponding hardware
1 = Posted interrupt for the corresponding hardware present
Writing a ‘0’ to the bits clears the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits and to the ENSWINT
(Bit 7 of the INT_MSK3 Register) posts the corresponding hardware interrupt
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Interrupt Mask Registers
The Interrupt Mask Registers (INT_MSKx) are used to enable
the individual interru pt sources’ ability to create pending inter-
rupts.
There are four Interrupt Mask Registers (INT_MSK0,
INT_MSK1, INT_MSK2, and INT_MSK3), which may be referred
to in general as INT_MSKx. If cleared, each bit in an INT_MSKx
register prevents a posted interrupt from becoming a pendin g
interrupt (input to the priority encoder). However, an interrupt can
still post even if its mask bit is zero. All INT_MSKx bits are
independent of all other INT_MSKx bits.
If an INT_MSKx bit is set, the interrupt source associated with
that mask bit may generate an interrupt that becomes a pending
interrupt.
The Enable Software Interrup t (ENSWI NT) bit in INT_MSK3[7]
determines the way an individual bit value written to an
INT_CLRx register is interpreted. When is cleared, writing 1's to
an INT_CLRx register has no effect. However, writing 0's to an
INT_CLRx register, when ENSWINT is cleared, causes the
corresponding interrupt to clear. If the ENSWINT bit is set, any
0’s written to the INT_CLRx registers are ignored. However , 1’ s
written to an INT_CLRx register, while ENSWINT is set, causes
an interrupt to post for the corresponding interrupt.
Software interrupts can aid in debugging interrupt service
routines by eliminating the need to create system level interac-
tions that are sometimes necessary to create a hardware-only
interrupt.
Table 70 . Interru pt Clear 1 (INT_CLR1) [0xDB] [R/W]
Bit # 7 6 5 4 3 2 1 0
Field Reserved Prog Interval
Timer 1 ms Timer USB Active USB Reset USB EP2 USB EP1 USB EP0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0000000 0
When reading this register,
0 = There’s no posted interrupt for the corresponding hardware
1 = Posted interrupt for the corresponding hardware present
Writing a ‘0’ to the bits clears the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits AND to the ENSWINT
(Bit 7 of the INT_MSK3 Register) posts the corresponding hardware interrupt
Bit 7 Reserved
Table 71. Interrupt Clear 2 (INT_CLR2) [0xDC] [R/W]
Bit # 76543210
Field Reserved Reserved Reserved GPIO Port 2 Reserved INT2 16-bit Coun-
ter Wrap Reserved
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0000000 0
When reading this register,
0 = There’s no posted interrupt for the corresponding hardware
1 = Posted interrupt for the corresponding hardware present
Writing a ‘0’ to the bits clears the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits AND to the ENSWINT (Bit
7 of the INT_MSK3 Register) posts the corresponding hardware interrupt
Bits 7,6,5,3,0Reserved
Table 72. Interrupt Mask 3 (INT_MSK3) [0xDE] [R/W ]
Bit # 76543210
Field ENSWINT Reserved
Read/Write R/W – – – – – – –
Default 0000000 0
Bit 7 Enable Sof tware Interrupt (ENSWINT)
0 = Disable. Writing 0’s to an INT_CLRx register, when ENSWINT is cleared, causes the corresponding interrupt to clear
1 = Enable. Writing 1’s to an INT_CLRx register, when ENSWINT is set, causes the correspo nding interrupt to post
Bits 6:0 Reserved
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Table 73. Interrupt Mask 2 (INT_MSK2) [0xDF] [R/W]
Bit # 76543210
Field
Reserved Reserved Reserved GPIO Port 2
Int Enable Reserved INT2
Int Enable 16-bit Coun-
ter Wrap Int
Enable
Reserved
Read/Write –R/W R/W R/W R/W R/W R/W R/W
Default 0000000 0
Bit 7 Reserved
Bit 6 Reserved
Bit 5 Reserved
Bit 4 GPIO Port 2 Interrupt Enable
0 = Mask GPIO Port 2 interrupt
1 = Unmask GPIO Port 2 interrupt
Bit 3 Reserved
Bit 2 INT2 Interrupt Enable
0 = Mask INT2 interrupt
1 = Unmask INT2 interrupt
Bit 1 16-bit Counter Wrap Interrupt Enable
0 = Mask 16-bit Counter Wrap interrupt
1 = Unmask 16-bit Counter Wrap interrupt
Bit 0 Reserved
Table 74. Interrupt Mask 1 (INT_MSK1) [0xE1] [R/W]
Bit # 76543210
Field
Reserved Prog Interval
Timer
Int Enable
1 ms T imer
Int Enable USB Active
Int Enable USB Reset
Int Enable USB EP2
Int Enable USB EP1
Int Enable USB EP0
Int Enable
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0000000 0
Bit 7 Reserved
Bit 6 Prog Interval Timer Interrupt Enable
0 = Mask Prog Interval Timer interrupt
1 = Unmask Prog Interval Timer interrupt
Bit 5 1 ms Ti mer Interrupt Enable
0 = Mask 1 ms interrupt
1 = Unmask 1 ms interrupt
Bit 4 USB Active Interrupt Enable
0 = Mask USB Active interrupt
1 = Unmask USB Active interrupt
Bit 3 USB Reset Interrupt Enable
0 = Mask USB Reset interrupt
1 = Unmask USB Reset interrupt
Bit 2 USB EP2 Interrupt Enable
0 = Mask EP2 interrupt
1 = Unmask EP2 interrupt
Bit 1 USB EP1 Interrupt Enable
0 = Mask EP1 interrupt
1 = Unmask EP1 interrupt
Bit 0 USB EP0 Interrupt Enable
0 = Mask EP0 interrupt
1 = Unmask EP0 interrupt
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Interrupt Vector Clear Register
Table 75 . Interrup t Mask 0 (INT_MSK0) [0xE0] [R/W]
Bit # 76543210
Field GPIO Port 1
Int Enable Sleep Timer
Int Enable INT1
Int Enable GPIO Port 0
Int Enable SPI Receive
Int Enable SPI Transmit
Int Enable INT0
Int Enable POR
Int Enable
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0000000 0
Bit 7 GPIO Port 1 Interrupt Enable
0 = Mask GPIO Port 1 interrupt
1 = Unmask GPIO Port 1 interrupt
Bit 6 Sleep Timer Interrupt Enable
0 = Mask Sleep Timer interrupt
1 = Unmask Sleep T i mer interrupt
Bit 5 INT1 Interrupt Enable
0 = Mask INT1 interrupt
1 = Unmask INT1 interrupt
Bit 4 GPIO Port 0 Interrupt Enable
0 = Mask GPIO Port 0 interrupt
1 = Unmask GPIO Port 0 interrupt
Bit 3 SPI Receive Interrupt Enable
0 = Mask SPI Receive interrupt
1 = Unmask SPI Receive interrupt
Bit 2 SPI Transmit Interrupt Enable
0 = Mask SPI Transmit interrupt
1 = Unmask SPI Transmit interrupt
Bit 1 INT0 Interrupt Enable
0 = Mask INT0 interrupt
1 = Unmask INT0 interrupt
Bit 0 POR Interrupt Enable
0 = Mask POR interrupt
1 = Unmask POR interrupt
Table 76. Interrupt Vector Clear Register (INT_VC) [0xE2] [R/W]
Bit # 76543210
Field Pending Interrupt [7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0000000 0
The Interrupt V ector Clear Register (INT_VC) holds the interrupt vector for the highest priority pending interrupt when read, and
when written clears all pending interrupts
Bits 7:0 Pending Interrupt [7:0]
8-bit data value holds the interrupt vector for the highest priority pending interrupt. Writin g to this register clears all pending
interrupts
CYRF69313
Document #: 001-66503 Rev. *B Page 54 of 78
USB Transceiver
USB Transceiver Configuration
USB Serial Interface Engine (SIE)
The SIE allows the microcontroller to communicate with the USB
host at low speed data rates (1.5 Mbps). The SIE simplifies the
interface between the microcontroller and USB by incorporating
hardware that handles the following USB bus activity indepen-
dently of the microcontroller:
■Translating the encoded received data and formatting the data
to be transmitted on the bus
■CRC checking and generation. Flagging the microcontroller if
errors exist during transmission
■Address checking. Ignoring the transactions not addressed to
the device
■Sending appropriate ACK/NAK/STALL handshake s
■Identifying token type (SETUP, IN, or OUT). Setting the appro-
priate token bit after a valid token is received
■Placing valid received data in the appropriate endpoint FIFOs
■Sending and updating the data toggle bit (Data1/0)
■Bit stuffing/unstuffing.
Firmware is required to handle the rest of the USB interface with
the following tasks:
■Coordinate enumeration by decoding USB device requests
■Fill and empty the FI FOs
■Suspend/Resume coordination
■Verify and select Data toggle values
Table 77 . USB Transceiver Configure Register (USBXCR) [0x74] [R/W]
Bit # 76543210
Field USB Pull-up
Enable Reserved USB Force
State
Read/Write R/W ––––––R/W
Default 0000000 0
Bit 7 USB Pull-up Enable
0 = Disable the pull-up resistor on D–
1 = Enable the pull-up resistor on D–. This pull-up is to VCC. This bit should be cleared in sleep mode.
Bits 6:1 Reserved
Bit 0 USB Force State
This bit allows the state of the USB I/O pins DP and D+ to be forced to a state while USB is enabled
0 = Disable USB Force State
1 = Enable USB Force St ate. Allows the D– and D+ pins to be controlled by P1.1 and P1.0 respectively when the
USBIO is in USB mode. Refer to Table 46 for more information
Note The USB transceiver has a dedicated 3.3 V regulator for USB signalling purposes and to provide for the 1.5 K D– pull-up.
Unlike the other 3.3 V regulator , this regulator cannot be controlled/accessed by firmware. When the device is suspended, this
regulator is disabled along with the bandgap (which provides the reference voltage to the regulator) and the D– line is pulled up
to 5 V through an alternate 6.5 K resistor . During wakeup following a suspend, the band gap and the regulator are switched on
in any order . Under an extremely rare case when the device wakes up following a bus reset condition and the voltage regulator
and the band gap turn on in that particular order, there is possibility of a glitch/low pulse occurring on the D– line. The host can
misinterpret this as a deattach condition. This condition, although rare, can be avoided by keeping the bandgap circuitry enabled
during sleep. This is achieved by setting the ‘No Buzz’ bit, bit[5] in the OSC_CR0 register. This is an issue only if the device is
put to sleep during a bus reset condition
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USB Device
Table 78 . USB Device Address (USBCR) [0x40] [R/W]
Bit # 7 6 5 4 3 2 1 0
Field USB Enable Device Address[6:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0000000 0
The content of this register is cleared when a USB Bus Reset condition occurs
Bit 7 USB Enable
This bit must be enabled by fi rmware before the serial interface engine (SIE) re sponds to USB traffic at the address
specified in Device Address [6:0 ]. When this bit is cleared, the USB transceiver enters power-down state. User’s firm-
ware should clear this bit prior to entering sleep mode to save power
0 = Disable USB device address and put the USB transceiver into power-down state
1 = Enable USB device address and put the USB transceiver into normal operating mode
Bits 6:0 Device Address [6:0]
These bits must be set by firmware during the USB enumeration process (for example, SetAddress) to the non-zero
address assigned by the USB host
Table 79 . Endpoint 0, 1, and 2 Count (EP0CNT–EP2CNT) [0x41, 0x43, 0x45] [R/W]
Bit # 7 6 5 4 3 2 1 0
Field Data Toggle Data Valid Reserved Byte Count[3:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0000000 0
Bit 7 Data Toggle
This bit selects the DATA packet's toggle state. For IN transactions, firmware must set this bit to the select the trans-
mitted Data Toggle. For OUT or SETUP transactions, the hardware sets this bit to the state of the received Data Tog-
gle bit.
0 = DATA0
1 = DATA1
Bit 6 Dat a Valid
This bit is used for OUT and SETUP tokens only. This bit is cleared to ‘0’ if CRC, bitstuf f, or PID errors have occurred.
This bit does not update for some endpoint mode settings
0 = Data is invalid. If enabled, the endpoint interrupt occurs even if invalid data is received
1 = Data is va lid
Bits 5:4 Reserved
Bits 3:0 Byte Count Bit [3:0]
Byte Count Bits indi cate th e number of data bytes in a transacti on: For IN transactions, firmware loads the count with the
number of bytes to be transmitted to the host from the end point FIFO. Valid values are 0 to 8 inclusive. For OUT or
SETUP transactions, the count is updated by hardwa re to th e number of dat a bytes received, plus 2 for the CRC byte s.
Valid values are 2–10 inclusive.
For Endpoint 0 Count Register , whenever the count updates from a SETUP or OUT transaction, the count register locks and cannot
be written by the CPU. Reading the register unlocks it. This prevents firmware from overwriting a status update on it
CYRF69313
Document #: 001-66503 Rev. *B Page 56 of 78
Endpoint 0 Mode
Because both firmware and the SIE are allowed to write to the Endpoint 0 Mode and Count Registers the SIE provides an interlocking
mechanism to prevent accidental overwriting of data.
When the SIE writes to these registers they are locked and the processor cannot write to them until after it has read them. Writing to
this register clears the upper four bits regardless of the value written.
Table 80. Endpoint 0 Mode (EP0MODE) [0x44] [R/W]
Bit # 76543210
Field Setup
Received IN Received OUT Re-
ceived ACK’d Trans Mode[3:0]
Read/Write R/C[3] R/C[3] R/C[3] R/C[3] R/W R/W R/W R/W
Default 0000000 0
Bit 7 SETUP Received
This bit is set by hardware when a va lid SETUP packet is received. It is forced HIGH from the start of the data
packet phase of the SETUP transactions until the end of the data phase of a control write transfer and cannot be
cleared during this interval. While this bit is set to ‘1’, the CPU cannot write to the EP0 FIFO. This prevents firm-
ware from overwriting an incoming SETUP transaction before firmware has a chance to read the SETUP data
This bit is cleared by any non-locked writes to the register
0 = No SETUP receive d
1 = SETUP received
Bit 6 IN Received
This bit, when set, indicates a valid IN packet has been received. This bit is updated to ‘1’ after the host acknowl-
edges an IN data packet.When clear, it indicates that either no IN has been receive d or that the host didn’t
acknowledge the IN data by sending an ACK handshake
This bit is cleared by any non-locked writes to the register.
0 = No IN received
1 = IN received
Bit 5 OUT Received
This bit, when set, indicates a valid OUT packet has been received and ACKed. This bit is updated to ‘1’ after the
last received packet in an OUT transaction. When clear, it indicates no OUT received
This bit is cleared by any non-locked writes to the register
0 = No OUT receiv e d
1 = OUT received
Bit 4 ACK’d Transaction
The ACK’d transaction bit is set whenever the SIE engages in a transaction to the register’s endpoint that com-
pletes with a ACK packet
This bit is cleared by any non-locked writes to the register
1 = The transaction completes with an ACK
0 = The transaction does not complete with an ACK
Bits 3:0 Mode [3:0]
The endpoint modes determine how the SIE responds to USB traffic that the host sends to the endpoint. The
mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a
result of host packets to the endpoint
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Table 81. Endpoint 1 and 2 Mode (EP1MODE – EP2MODE) [0x45, 0x 46] [R/W]
Bit # 76543210
Field Stall Reserved NAK Int
Enable ACK’d
Transaction Mode[3:0]
Read/Write R/W R/W R/W R/C (Note 3) R/W R/W R/W R/W
Default 0000000 0
Bit 7 Stall
When this bit is set the SIE stalls an OUT packet if the Mode Bits are set to ACK-OUT, and the SIE stalls an IN
packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes
Bit 6 Reserved
Bit 5 NAK Int Enable
This bit, when set, causes an endpoint interrupt to be generated even when a transfer completes with a NAK.
Unlike enCoRe, CYRF69313 family members do not generate an endpoint interrupt under these conditions unless
this bit is set
0 = Disable interrupt on NAK’d transactions
1 = Enable interrupt on NAK’d transaction
Bit 4 ACK’d Transaction
The ACK’d transaction bit is set whenever the SIE engages in a transaction to the register’s endpoint that com-
pletes with an ACK packet
This bit is cleared by any writes to the register
0 = The transaction does not complete with an ACK
1 = The transaction completes with an ACK
Bits 3:0 Mode [3:0]
The endpoint modes determine how the SIE responds to USB traffic that the host sends to the endpoint. The
mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a
result of host packets to the endp oin t.
Note: When the SIE writes to the EP1MODE or the EP2MODE register it blocks firmware writes to the EP2MODE or the
EP1MODE registers, respectively (if both writes occur in the same clock cycle). This is because the design employs only one
common ‘update’ signal for both EP1MODE and EP2MODE registers. Thus, when SIE writes to the EP1MODE register, the
update signal is set and this prevents firmware writes to EP2MODE register. SIE writes to the endpoint mode registers have
higher priority than firmware writes. This mode register write block situation can put the endpoints in incorrect modes. Firmware
must read the EP1/2MODE registers immediately following a firmware write and rewrite if the value read is incorrect
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Endpoint Data Buffers
The three data buffers are used to hold data for both IN and OUT transactions. Each data buffer is 8 bytes long. The reset values
of the Endpoint Data Registers are unknown. Unlike past enCoRe parts the USB data buffers are only accessible in the I/O space
of the processor.
Table 82 . Endpoint 0 Data (EP0DATA) [0x50-0x57] [R/W]
Bit # 76543210
Field Endpoint 0 Data Buffer [7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown
The Endpoint 0 buffer is comprised of 8 bytes located at address 0x50 to 0x57
Table 83. Endpoint 1 Data (EP1DATA) [0x58-0x5F] [R/W]
Bit # 76543210
Field Endpoint 1 Data Buffer [7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown
The Endpoint 1buffer is comprised of 8 bytes located at address 0x58 to 0x5F
Table 84 . Endpoint 2 Data (EP2DATA) [0x60-0x67] [R/W]
Bit # 76543210
Field Endpoint 2 Data Buffer [7:0]
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown
The Endpoint 2 buffer is comprised of 8 bytes located at address 0x60 to 0x67
CYRF69313
Document #: 001-66503 Rev. *B Page 59 of 78
USB Mode Tables
Mode Column
The 'Mode' column contains the mnemonic names given to the
modes of the endpoint. The mode of the endpoint is determined
by the four-bit binaries in the 'Encoding' column as discussed in
the following section. The Status IN and Status OUT represent
the status IN or OUT stage of the control transfer.
Encoding Colu mn
The contents of the 'Encoding' column represent the Mode
Bits [3:0] of the Endpoint Mode Registers (Table 80 and
Table 81). The endpoint modes determine how the SIE responds
to different tokens that the host sends to the endpoints. For
example, if the Mode Bits [3:0] of the Endpoint 0 Mode Register
are set to '0001' , which is NAK IN/OUT mod e, the SIE sends an
ACK handshake in response to SETUP tokens and NAK any IN
or OUT tokens.
SETUP, IN, and OUT Columns
Depending on the mode specified in the 'Encoding' column, the
'SETUP', 'IN', and 'OUT' columns contain the SIE's responses
when the endpoint receives SETUP, IN, and OUT tokens,
respectively.
A 'Check' in the Out column means that upon receiving an OUT
token the SIE checks to see whether the OUT is of zero length
and has a Data T oggle (Data1/0) of 1. If these conditions are true,
the SIE responds with an ACK. If any of the above conditions is
not met, the SIE responds with either a STALL or Ignore.
A 'TX Count' entry in the IN column means that the SIE transmits
the number of bytes specified in the Byte Count Bit [3:0] of the
Endpoint Count Register (Table 79) in response to any IN token.
Mode Encoding SETUP IN OUT Comments
DISABLE 0000 Ignore Ignore Ignore Ignore all USB traffic to this endpoint. Used by Data and
Control endpoints
NAK IN/OUT 0001 Accept NAK NAK NAK IN and OUT token. Control endpoint only
STATUS OUT
ONLY 0010 Accept STALL Check STALL IN and ACK zero byte OUT. Control endpoint only
STALL IN/OUT 0011 Accept STALL STA LL STALL IN and OUT token. Control endpoint only
ST ATUS IN ONL Y 0110 Accept TX0 byte ST ALL ST ALL OUT and send zero byte data for IN token. Control
endpoint only
ACK OUT –
STATUS IN 1011 Accept TX0 byte ACK ACK the OUT token or send zero byte data for IN token.
Control endpoint only
ACK IN –
STATUS OUT 1111 Accept TX Count Check Respond to IN data or Status OUT. Control endpoint only
NAK OUT 1000 Ignore Ignore NAK Send NAK handshake to OUT token. Data endpoint only
ACK OUT (ST ALL =
0) 1001 Ignore Ignore ACK This mode is changed by the SIE to mode 1000 on issu-
ance of ACK handshake to an OUT. Data endpoint only
ACK OUT (ST ALL =
1) 1001 Ignore Ignore STALL STALL the OUT transfer
NAK IN 1100 Ignore NAK Ignore Send NAK handshake for IN token. Data endpoint only
ACK IN (STALL = 0) 1101 Ignore TX Count Ignore This mode is changed by the SIE to mode 1100 after re-
ceiving ACK handshake to an IN data. Data endpoint only
ACK IN (STALL = 1) 1101 Ignore STALL Ignore STALL the IN transfer . Data endpoint only
Reserved 0101 Ignore Ignore Ignore These modes are not supported by SIE. Firmware should
not use this mode in Control and Data endpoints
Reserved 0111 Ignore Ignore Ignore
Reserved 1010 Ignore Ignore Ignore
Reserved 0100 Ignore Ignore Ignore
Reserved 1110 Ignore Ignore Ignore
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Details of Mode for Differing Traffic Conditions
Control Endpoint
SIE Bus Event SIE EP0 Mode Register EP0 Count Register EP0 Interrupt Comments
Mode Token Count Dval D0/1 Response S I O A MODE DTOG DVAL COUNT FIFO
DISABLED
0000 x x x x Ignore All
STALL_IN_OUT
0011 SETUP >10 x x junk Ignore
0011 SETUP <=10 invalid x junk Ignore
0011 SETUP <=10 valid x ACK 1 1 0001 update 1 update data Yes ACK SETUP
0011 IN x x x STALL Stall IN
0011 OUT >10 x x Ignore
0011 OUT <=10 invalid x Ignore
0011 OUT <=10 valid x STALL Stall OUT
NAK_IN_OUT
0001 SETUP >10 x x junk Ignore
0001 SETUP <=10 invalid x junk Ignore
0001 SETUP <=10 valid x ACK 1 1 0001 update 1 update data Yes ACK SETUP
0001 IN x x x NAK NAK IN
0001 OUT >10 x x Ignore
0001 OUT <=10 invalid x Ignore
0001 OUT <=10 valid x NAK NAK OUT
ACK_IN_STATUS_OUT
1111 SETUP >10 x x junk Ignore
1111 SETUP <=10 invalid x junk Ignore
1111 SETUP <=10 valid x ACK 1 1 0001 update 1 update data Yes ACK SETUP
1111 IN x x x TX Host Not ACK'd
1111 IN x x x TX 1 1 0001 Yes Host ACK'd
1111 OUT >10 x x Ignore
1111 OUT <=10 invalid x Ignore
1111 OUT <=10, <>2 valid x STALL 001 1 Yes Bad Status
1111 OUT 2 valid 0 STALL 0011 Yes Bad Status
1111 OUT 2 valid 1 ACK 1 1 0010 1 1 2 Yes Good Status
STATUS_OUT
0010 SETUP >10 x x junk Ignore
0010 SETUP <=10 invalid x junk Ignore
0010 SETUP <=10 valid x ACK 1 1 0001 update 1 update data Yes ACK SETUP
0010 IN x x x STALL 0011 Yes Stall IN
0010 OUT >10 x x Ignore
0010 OUT <=10 invalid x Ignore
0010 OUT <=10, <>2 valid x S TALL 0011 Yes Bad Status
0010 OUT 2 valid 0 STALL 0011 Yes Bad Status
0010 OUT 2 valid 1 ACK 1 1 1 1 2 Yes Good Status
ACK_OUT_STATUS_IN
1011 SETUP >10 x x junk Ignore
1011 SETUP <=10 invalid x junk Ignore
1011 SETUP <=10 valid x ACK 1 1 0001 update 1 update data Yes ACK SETUP
1011 IN x x x TX 0 Host Not ACK'd
1011 IN x x x TX 0 1 1 0011 Yes Host ACK'd
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Document #: 001-66503 Rev. *B Page 61 of 78
1011 OUT >10 x x junk Ignore
1011 OUT <=10 invalid x junk Ignore
1011 OUT <=10 valid x ACK 1 1 0001 update 1 update data Yes Good OUT
STATUS_IN
0110 SETUP >10 x x junk Ignore
0110 SETUP <=10 invalid x junk Ignore
0110 SETUP <=10 valid x ACK 1 1 0001 update 1 update data Yes ACK SETUP
0110 IN x x x TX 0 Host Not ACK'd
0110 IN x x x TX 0 1 1 0011 Yes Host ACK'd
0110 OUT >10 x x Ignore
0110 OUT <=10 invalid x Ignore
0110 OUT <=10 valid x STALL 0011 Yes Stall OUT
Data Out Endpoints
SIE Bus Event SIE EP0 Mode Register EP0 Count Register EP0 Interrupt Comments
Mode Token Count Dval D0/1 Response S I O A MODE DTOG DVAL COUNT FIFO
ACK OUT (STALL Bit = 0)
1001 IN x x x Ignore
1001 OUT >MAX x x junk Ignore
1001 OUT <=MAX invalid invalid junk Ignore
1001 OUT <=MAX valid valid ACK 1 1000 update 1 update data Yes ACK OUT
ACK OUT (STALL Bit = 1)
1001 IN x x x Ignore
1001 OUT >MAX x x Ignore
1001 OUT <=MAX invalid invalid Ignore
1001 OUT <=MAX valid valid STALL Stall OUT
NAK OUT
1000 IN x x x Ignore
1000 OUT >MAX x x Ignore
1000 OUT <=MAX invalid invalid Ignore
1000 OUT <=MAX valid valid NAK If Enabled NAK OUT
Data In Endpoints
SIE Bus Event SIE EP0 Mode Register EP0 Count Register EP0 Interrupt Comments
Mode Token Count Dval D0/1 Response S I O A MODE DTOG DVAL COUNT FIFO
ACK IN (STALL Bit = 0)
1101 OUT x x x Ignore
1101 IN x x x Host Not ACK'd
1101 IN x x x TX 1 1100 Yes Host ACK'd
ACK IN (STALL Bit = 1)
1101 OUT x x x Ignore
1101 IN x x x STALL Stall IN
NAK IN
1100 OUT x x x Ignore
1100 IN x x x NAK If Enabled NAK IN
Details of Mode for Differing Traffic Conditions (continued)
Control Endpoint
SIE Bus Event SIE EP0 Mode Register EP0 Count Register EP0 Interrupt Comments
Mode Token Count Dval D0/1 Response S I O A MODE DTOG DVAL COUNT FIFO
CYRF69313
Document #: 001-66503 Rev. *B Page 62 of 78
Register Summary
Addr Name 7 6 5 4 3 2 1 0 R/W Default
00 P0DATA P0.7 Reserved Reserved P0.4/INT2 P0.3/INT1 Reserved P0.1 Reserved b--bbb-- 00000000
01 P1DATA P1.7 P1.6/SMI
SO P1.5/SMO
SI P1.4/SCLK P1.3/SSEL P1.2 P1.1/D– P1.0/D+ bbbbbbbb 00000000
02 P2DATA Res P2.1–P2.0 bbbbbbbb 00000000
06 P01CR Reserved Int Enable Int Act
Low TTL Thresh High Sink Open Drain Pull-up
Enable Output
Enable --bbbbbb 00000000
08–09 P03CR–
P04CR Reserved Reserved Int Act
Low TTL Thresh Reserved Open Drain Pull-up
Enable Output
Enable --bbbbbb 00000000
0C P07CR Reserved Int
Enable Int Act
Low TTL Thresh Reserved Open Drain Pull-up
Enable Output
Enable -bbbbbbb 00000000
0D P10CR Reserved Int
Enable Int Act
Low Reserved 5 K pull-up
enable Output
Enable -bb----b 00000000
0E P11CR Reserved Int
Enable Int Act
Low Reserved Open Drain Reserved Output
Enable -bb--b-b 00000000
0F P12CR CLK
Output Int
Enable Int Act
Low TTL Thresh Reserved Open Drain Pull-up
Enable Output
Enable bbbbbbbb 00000000
10 P13CR Reserved Int
Enable Int Act
Low 3.3 V Drive High Sink Open Drain Pull-up
Enable Output
Enable -bbbbbbb 00000000
11–13 P14CR–
P16CR SPI Use Int
Enable Int Act
Low 3.3 V Drive High Sink Open Drain Pull-up
Enable Output
Enable bbbbbbbb 00000000
14 P17CR Reserved Int
Enable Int Act
Low TTL Thresh High Sink O pen Drain Pull-up
Enable Output
Enable -bbbbbbb 00000000
15 P2CR Reserved Int
Enable Int Act
Low TTL Thresh Reserved Open Drain Pull-up
Enable Output
Enable -bbbbbbb 00000000
20 FRTMRL Free-Running Timer [7:0] bbbbbbbb 00000000
21 FRTMRH Free-Running Timer [15:8] bbbbbbbb 00000000
26 PITMRL Prog Interval Timer [7:0] bbbbbbbb 00000000
27 PITMRH Reserved Prog Interval Timer [11:8] ----bbbb 00000000
28 PIRL Prog Interval [7:0] bbbbbbbb 00000000
29 PIRH Reserved Prog Interva l [11 : 8] ----bbbb 00000000
30 CPUCLKCR Reserved -------- 00010000
31 ITMRCLKCR TCAPCLK Divider TCAPCLK Select ITMRCLK Divider ITMRCLK Select bbbbbbbb 10001111
32 CLKIOCR Reserved Reserved CLKOUT Select ---bbbbb 00000000
34 IOSCTR foffset[2:0] Gain[4:0] bbbbbbbb 000ddddd
35 XOSCTR Reserved Reserved Reserved Mode ---bbb-b 000ddd0d
36 LPOSCTR 32 kHz
Low
Power
Reserved 32 kHz Bias Trim [1:0] 32 kHz Freq Trim [3:0] b-bbbbbb dddddddd
39 OSCLCKCR Reserved Fine T une
Only USB
Osclock
Disable
------bb 00000000
3C SPIDATA SPIData[7:0] bbbbbbbb 00000000
3D SPICR Swap LSB First Comm Mode CPOL CPHA SCLK Select bbbbbbbb 00000000
40 USBCR USB
Enable Device Address[6:0] bbbbbbbb 00000000
41 EP0CNT Data
Toggle Data Valid Reserved Byte Count[3:0] bbbbbbbb 00000000
42 EP1CNT Data
Toggle Data Valid Reserved Byte Count[3:0] bbbbbbbb 00000000
43 EP2CNT Data
Toggle Data Valid Reserved Byte Count[3:0] bbbbbbbb 00000000
44 EP0MODE Setup
rcv’d IN rcv’d OUT rcv’d ACK’d trans Mode[3:0] ccccbbbb 00000000
45 EP1MODE Stall Reserved NA K In t
Enable Ack’d trans Mode[3:0] b-bcbbbb 00000000
46 EP2MODE Stall Reserved NA K In t
Enable Ack’d trans Mode[3:0] b-bcbbbb 00000000
50–57 EP0DATA Endpoint 0 Data Buffer [7:0] bbbbbbbb ????????
58–5F EP1DATA Endpoint 1 Data Buffer [7:0] bbbbbbbb ????????
60–67 EP2DATA Endpoint 2 Data Buffer [7:0] bbbbbbbb ????????
CYRF69313
Document #: 001-66503 Rev. *B Page 63 of 78
LEGEND
In the R/W column,
b = Both Read and Write
r = Read Only
w = Write Only
c = Read/Clear
? = Unknown
d = calibration value. Should not change during normal use
74 USBXCR USB
Pull-up
Enable
Reserved USB Force
State b------b 00000000
DA INT_CLR0 GPIO Port
1Sleep
Timer INT1 GPIO Port
0SPI
Receive SPI Transmit INT0 POR bbbbbbbb 00000000
DB INT_CLR1 Reserved Prog
Interval
Timer
1-ms
Timer USB Active USB Reset USB EP2 USB EP1 USB EP0 -bbbbbbb 00000000
DC INT_CLR2 Reserved Reserved Reserved GP IO Port 2 Reserved INT2 16-bit
Counter
Wrap
Reserved -bbbbbb- 00000000
DE INT_MSK3 ENSWINT Reserved b------- 00000000
DF INT_MSK2 Reserved Reserved Reserved GPIO P ort 2
Int Enable Reserved INT2
Int Enable 16-bit
Counter
Wrap
Int Enable
Reserved ---bbbb- 00000000
E0 INT_MSK0 GPIO Port
1
Int Enable
Sleep
Timer
Int Enable
INT1
Int Enable GPIO Port 0
Int Enable SPI
Receive
Int Enable
SPI Transmit
Int Enable INT0
Int Enable POR
Int Enable bbbbbbbb 00000000
E1 INT_MSK1 Reserved Prog
Interval
Timer
Int Enable
1-ms
Timer
Int Enable
USB Active
Int Enable USB Reset
Int Enable USB EP2
Int Enable USB EP1
Int Enable USB EP0
Int Enable bbbbbbbb 00000000
E2 INT_VC Pending Interrupt [7:0] bbbbbbbb 00000000
E3 RESWDT Reset Watchdog Timer [7:0] wwwwwwww 00000000
-- CPU_A Temporary Register T1 [7:0] -------- 00000000
-- CPU_X X[7:0] -------- 00000000
-- CPU_PCL Program Counter [7:0] -------- 00000000
-- CPU_PCH Program Counter [1 5: 8 ] -------- 00000000
-- CPU_SP Stack Poin te r [7: 0] -------- 00000000
-CPU_F Reserved XOI Super Carry Zero Global IE ---brwww 00000010
FF CPU_SCR GIES Reserved WDRS PORS Sleep Reserved Reserved Stop r-ccb--b 00010000
1E0 OSC_CR0 Reserved No Buzz Sleep Timer [1:0] CPU Speed [2:0] --bbbbbb 00000000
1E3 PORCR Reserved PORLEV[1:0] Reserved --bb-bbbb 00000000
1E4 VLTCMP Reserved PPOR ------rr 00000000
1EB ECO_TR Sleep Duty Cycle [1:0] Reserved bb------ 00000000
Register Summary (continued)
Addr Name 7 6 5 4 3 2 1 0 R/W Default
CYRF69313
Document #: 001-66503 Rev. *B Page 64 of 78
Radio Function Register Descriptions
All registers are read and writeable, except where noted. Registers may be written to or read from either individually or in sequential
groups. A single-byte read or write reads or writes from the addressed register . Incrementing burst read and write is a sequence that
begins with an address, and then reads or writes to/from each register in address order for as long as clocking continues. It is possible
to repeatedly read (poll) a single register using a non-incrementing burst read. These registers are managed and configured over SPI
by the user firmware running in the microcontroller function.
Tab le 85. Register Map Summ ary
Address Mnemonic b7 b6 b5 b4 b3 b2 b1 b0 Default[4] Access[4]
0x00 CHANNEL_ADR Not Used Channel -1001000 -bbbbbbb
0x01 TX_LENGTH_ADR TX Length 00000000 bbbbbbbb
0x02 TX_CTRL_ADR TX GO TX CLR TXB15
IRQEN TXB8
IRQEN TXB0
IRQEN TXBERR
IRQEN TXC
IRQEN TXE
IRQEN 00000011 bbbbbbbb
0x03 TX_CFG_A DR Not Used Not Used DATA CODE
LENGTH RSVD Data mode PA SETTING --000101 --bbbbbb
0x04 TX_IRQ_STATUS_ADR OS
IRQ RSVD TXB15
IRQ TXB8
IRQ TXB0
IRQ TXBERR IRQ T XC
IRQ TXE
IRQ 10111000 rrrrrrrr
0x05 RX_CTRL_ADR RX GO RSVD RXB16
IRQEN RXB8
IRQEN RXB1
IRQEN RXBERR
IRQEN RXC
IRQEN RXE
IRQEN 00000111 bbbbbbbb
0x06 RX_CFG_ADR AGC EN LNA ATT HILO FAST TURN
EN Not Used RXOW EN VLD EN 10010-10 bbbbb-bb
0x07 RX_IRQ_STATUS_ADR RXOW
IRQ SOFDET
IRQ RXB16
IRQ RXB8
IRQ RXB1
IRQ RXBERR IRQ RXC
IRQ RXE
IRQ 00000000 brrrrrrr
0x08 RX_STATUS_ADR RX ACK PKT ERR EOP ERR CRC0 Bad CRC RX Cod e RX Data Mode 00001--- rrrrrrrr
0x09 RX_COUNT_A DR RX Count 00000000 rrrrrrrr
0x0A RX_LENGTH_ADR RX Length 00000000 rrrrrrrr
0x0B PWR_CTRL_ADR The firmware should set “00010000” to this register while initiating 10100000 bbb-bbbb
0x0C XTAL_CTRL_ADR XOUT FN XSIRQ EN Not Used Not Used FREQ 000--100 bbb--bbb
0x0D IO_CFG_ADR IRQ OD IRQ POL MISO OD XOUT OD RSVD RSVD SPI 3PIN IRQ GPIO 00000000 bbbbbbbb
0x0E GPIO_CTRL_ADR XOUT OP MISO OP RSVD IRQ OP XOUT IP MISO IP RSVD IRQ IP 0000---- bbbbrrrr
0x0F XACT_CFG_ADR ACK EN Not Used FRC END END STATE ACK TO 1-000000 b-bbbbbb
0x10 FRAMING_CFG_ADR SOP EN SOP LEN LEN EN SOP TH 10100101 bbbbbbbb
0x11 DATA32_THOLD_ADR Not Used Not Used Not Used Not Used TH32 ----0100 ----bbbb
0x12 DATA64_THOLD_ADR Not Used Not Used Not Used TH64 ---01010 ---bbbbb
0x13 RSSI_ADR SOP Not Used LNA RSSI 0-100000 r-rrrrrr
0x14 EOP_CTRL_ADR[9] HEN HINT EOP 10100100 bbbbbbbb
0x15 CRC_SEED_LSB_ADR CRC SEED LSB 00000000 bbbbbbbb
0x16 CRC_ SEED_MSB_ADR CRC SEED MSB 00000000 bbbbbbbb
0x17 TX_CRC_LSB_ADR CRC LSB -------- rrrrrrrr
0x18 TX_CRC_MSB_ADR CRC MSB -------- rrrrrrrr
0x19 RX_CRC_LSB_ADR CRC LSB 11111111 rrrrrrrr
0x1A RX_CRC_MSB_ADR CRC MSB 11111111 rrrrrrrr
0x1B TX_OFFSET_LSB_ADR STRIM LSB 00000000 bbbbbbbb
0x1C TX_OFFSET_MSB_ADR Not Used Not Used Not Used Not Used STRIM MSB ----0000 ----bbbb
0x1D MODE_OVERRIDE_ADR RSVD RSVD FRC SEN FRC AWAKE Not Used Not Used RST 00000--0 wwwww--w
0x1E RX_OVERRIDE_ADR ACK RX RXTX DLY MAN RXACK FRC RXDR DIS CRC0 DIS RXCRC ACE Not Used 0000000- bbbbbbb-
0x1F TX_OVERRIDE_ADR ACK TX FRC PRE RSVD MAN
TXACK OVRD ACK DIS TXCRC RSVD TX INV 00000000 bbbbbbbb
0x27 CLK_OVERRIDE_ADR RSVD RSVD RSVD RSVD RSVD RSVD RXF RSVD 00000000 wwwwwwww
0x28 CLK_EN_ADR RSVD RSVD RSVD RSVD RSVD RSVD RXF RSVD 00000000 wwwwwwww
0x29 RX_ABORT_ADR RSVD RSVD ABORT EN RSVD RSVD RSVD RSVD RSVD 00000000 wwwwwwww
0x32 AUTO_CAL_TIME_ADR AUTO_CAL_TIME_MAX 00000011 wwwwwwww
0x35 AUTO_CAL_OFFSET_ADR AUTO_CAL_OFFSET_MINUS_4 00000000 wwwwwwww
0x39 ANALOG_CTRL_ADR RSVD RSVD RSVD RSVD RSVD RSVD RSVD ALL SLOW 00000000 wwwwwwww
Register Files
0x20 TX_BUFFER_ADR TX Buffer File -------- wwwwwwww
0x21 RX_ BUFFER_ADR RX Buffer File -------- rrrrrrrr
0x22 SOP_CODE_ADR SOP Co de File Note 5 bbbbbbbb
0x23 DATA_CODE_ADR Data Code File Note 6 bbbbbbbb
0x24 PREAMBLE_ADR Preamble File Note 7 bbbbbbbb
0x25 MFG_ID_ADR MFG ID File NA rrrrrrrr
Notes
4. b = read/write; r = read only; w = write only; ‘-’ = not used, default value is undefined.
5. SOP_CODE_ADR default = 0x17FF9E213690C782.
6. DATA_CODE_ADR default = 0x02F9939702FA5CE3012BF1DB0132BE6F.
7. PREAMBLE_ADR default = 0x333302
8. Registers must be configured or accessed only when the radio is in IDLE or SLEEP mode.The GPIOs,RSSI registers can be accessed in Active Tx and Rx mode.
9. EOP_CTRL_ADR[6:4] should never have the value of “000” i.e. EOP Hint Symbol count should never be “0”.
CYRF69313
Document #: 001-66503 Rev. *B Page 65 of 78
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User gui d el i ne s are not tested.
Storage Temperature................... ... ............–40 °C to +90 °C
Ambient Temperature with Power Applied......0 °C to +70 °C
Supply Voltage on any power supply
pin relative to VSS.........................................–0.3 V to +3.9 V
DC Voltage to Logic Inputs[10] ........... ... .–0.3 V to VIO +0.3 V
DC Voltage applied to Outputs
in High Z State....................................... –0.3 V to VIO +0.3 V
Static Discharge V oltage (Digital)[11].........................>2000 V
Static Discharge V oltage (RF)[11]............................... 1100 V
Latch up Current......................................+200 mA, –200 mA
Ground Voltage.................................................................0 V
FOSC (Crystal Frequency)...........................12 MHz ±30 ppm
Notes
10.It is permissible to connect voltages above VIO to inputs through a series resisto r l i miting input current to 1 mA. AC timing not guarante ed.
11. Human Body Model (HBM).
12.Includes current drawn while starting crystal, starting synthesizer, transmitting packet (including SOP and CRC16), changing to receive mode, and receiving
ACK handshake. Device is in sleep exce pt during this transaction.
DC Characteristics (T = 25 C)
Parameter Description Conditions Min Typ Max Unit
Radio Function Operating Voltages (For RF activity, Vcc = Vbat = 3.0 V to 3.6 V)
VBAT Battery voltage 0 C – 70 C2.7 –3.6 V
VIO VIO Voltage 2.7 –3.6 V
VCC VCC Voltage 0 C – 70 C2.7 –3.6 V
MCU Function Operating Voltages
VDD_MICRO1 Operating voltage N o U S B a c t i v i t y,
CPU speed < 12 MHz 4.0 – 5.25 V
VDD_MICRO2 Operating voltage USB activity, CPU speed <
12 MHz. Flash programming 4.35 – 5.25 V
Device Current (For total current consumption in different modes, for example Radio, active, MCU, sleep, etc., add Radio
Function Current and MCU Function Current)
IDD (GFSK)[12] Average IDD, 1 Mbps, slow channel PA = 5, 2-way, 4 bytes/10 ms –10.87 –mA
IDD (32-8DR)[12] Average IDD, 250 kbps, fast channel PA = 5, 2-way, 4 bytes/10 ms –11.2 –mA
ISB Sleep Mode IDD Radio function and MCU function
in Sleep mode –40.1 –µA
Radio Function Current (VDD_Micro = 5.0 V, MCU sleep)
IDLE ICC Radio Off, XTAL Active XOUT disabled –2.1 –mA
Isynth ICC during Synth Start –9.8 –mA
TX ICC ICC during transmit PA = 5 (–5 dBm) –22.4 –mA
TX ICC ICC during transmit PA = 6 (0 dBm) –27.7 –mA
RX ICC ICC during receive LNA off, ATT on –20.2 –mA
RX ICC ICC during receive LNA on, ATT off –23.4 –mA
MCU Function Current (VDD_Micro = 5.0 V)
IDD_MICRO1 VDD_MICRO operating supply current No GPIO loading, 6 MHz – 10 – mA
ISB1 Standby current Internal Oscillators, Bandgap,
Flash, CPU Clock, Time r Clock,
USB Clock all disabled
– 4 10 µA
USB Interface
VON Static output High 15 K ± 5% Ohm to VSS 2.8 – 3.6 V
VOFF Static output Low RUP is enabled – – 0.3 V
VDI Differential input sensitivity 0.2 – – V
VCM Differential input common mode range 0.8 – 2.5 V
CYRF69313
Document #: 001-66503 Rev. *B Page 66 of 78
VSE Single ended receiver threshold 0.8 – 2 V
CIN Transceiver capacitance – – 20 pF
IIO Hi-Z State data line leakage 0 V < VIN < 3.3 V –10 – 10 µA
Radio Function GPIO Int erfa ce
VOH1 Output High voltage condition 1 At IOH = –100.0 µA VIO – 0.1 VIO – V
VOH2 Output High voltage condition 2 At IOH = –2.0 mA VIO – 0.4 VIO – V
VOL Output Low voltage At IOL = 2.0 mA – 0 0.4 V
VIH Input High voltage 0.76 VIO – VIO V
VIL Input Low voltage 0 – 0.24 VIO V
IIL Input leakage current 0 < VIN < VIO –1 0.26 +1 µA
CIN Pin Input capacitance except XTAL, RFN, RFP, RFBIAS –3.5 10 pF
MCU Function GPIO Interface
RUP Pull-up resistance 4 – 12 K
VICR Input threshold voltage Low, CMOS
mode Low to High edg e 40% – 65% VCC
VICF Input threshold voltage Low, CMOS
mode High to Low edg e 30% – 55% VCC
VHC Input hysteresis voltage, CMOS mode High to Low edge 3% – 10% VCC
VILTTL Input Low voltage, TTL mode IO-pin Supply = 2.9–3.6 V – – 0.8 V
VIHTTL Input High voltage, TTL mode IO-pin Supply = 4.0–5.5 V 2.0 – – V
VOL1 Output Low voltage, High drive[13] IOL1 = 50 mA – – 0.8 V
VOL2 Output Low voltage, High drive[13] IOL1 = 25 mA – – 0.4 V
VOL3 Output Low voltage, Low drive[13] IOL2 = 8 mA – – 0.4 V
VOH Output High voltage[13] IOH = 2 mA VCC – 0.5 – – V
DC Characteristics (T = 25 C) (continued)
Parameter Description Conditions Min Typ Max Unit
Note
13.Except for pins P1.0, P1.1 in GPIO mode.
CYRF69313
Document #: 001-66503 Rev. *B Page 67 of 78
RF Characteristics
Notes
14.Exceptions F/3 and 5C/3.
Table 86. Radio Parameters
Parameter Description Conditions Min Typ Max Unit
RF Frequency Range Subject to regulations. 2.400 – 2.497 GHz
Receiver (T = 25 °C, VCC = Vbat = 3.0 V, fOSC = 12.000 MHz, BER < 10–3)
Sensitivity 250 kbps 32-8DR BER 1E-3 – –90 – dBm
Sensitivity GFSK BER 1E-3, ALL SLOW = 1 – –84 – dBm
LNA gain – 22.8 – dB
ATT gain ––31.7 – dB
Maximum received signal LNA On –15 –6 – dBm
RSSI value for PWRin –60 dBm LNA On – 21 – Count
RSSI slope – 1.9 – dB/Count
Interference Performance (CER 1E-3)
Co-channel Interference rejection
Carrier-to-Interference (C/I) C = –60 dBm, v 9 – dB
Adjacent (±1 MHz) channel selectivity C/I 1 MHz C = –60 dBm – 3 – dB
Adjacent (±2 MHz) channel selectivity C/I 2 MHz C = –60 dBm – –30 – dB
Adjacent (> 3 MHz) channel selectivity C/I > 3 MHz C = –67 dBm – –38 – dB
Out-of-Band Blocking 30 MHz–12.7 5 MHz[14] C = –67 dBm – –30 – dBm
Intermodulatio n C = –64 dBm, f = 5,10 MHz – –36 – dBm
Receive Spurious Emission
800 MHz 100 kHz ResBW – –79 – dBm
1.6 GHz 100 kHz ResBW – –71 – dBm
3.2 GHz 100 kHz ResBW – –65 – dBm
Transmitter (T = 25 °C, VCC = Vbat =3.0 V, fOSC = 12.000 MHz)
Maximum RF transmit power PA = 6 –2 0 +2 dBm
Maximum RF transmit power PA = 5 –7 –5 –3 dBm
Maximum RF transmit power PA = 0 – –35 – dBm
RF power control range – 39 – dB
RF power range control step size Six steps, monotonic – 5.6 – dB
Frequency deviation Min P N Code Pattern 10101010 – 270 – kHz
Frequency deviation Max PN Code Pattern 11110000 – 323 – k Hz
Error vector magnitude (FSK error) >0 dBm – 10 – %rms
Occupied bandwidth –6 dBc, 100 kHz ResBW 500 876 – kHz
Transmit Spurious Emission (PA = 6)
In-band spurious second channel power (±2 MHz) – –38 – dBm
In-band spurious third channel power (>3 MHz) – –44 – dBm
Non-harmonically related spurs (8.000 GHz) – –38 – dBm
Non-harmonically related spurs (1.6 GHz) – –34 – dBm
Non-harmonically related spurs (3.2 GHz) – –47 – dBm
Harmonic spurs (Second Harmonic) – –43 – dBm
Harmonic spurs (Third Harmonic) – –48 – dBm
CYRF69313
Document #: 001-66503 Rev. *B Page 68 of 78
AC Test Lo ads and Waveforms for Digital Pins
Figure 18. AC Test Loads and Waveforms for Digital Pins
Fourth and Greater Harmonics – –59 – dBm
Power Management (Crystal PN# eCERA GF-1200008)
Crystal start to 10 ppm – 0.7 1.3 ms
Crystal start to IRQ XSIRQ EN = 1 – 0.6 ms
Synth Settle Slow channel s – – 270 µs
Synth Settle Medium channels – – 180 µs
Synth Settle Fast channels – – 100 µs
Link turnaround time GFSK – – 30 µs
Link turnaround time 250 kbps – – 62 µs
Max packet length < 60 ppm crystal-to-crystal – – 40 bytes
Table 86. Radio Parameters (continued)
Parameter Description Conditions Min Typ Max Unit
90%
10%
VCC
GND
90%
10%
ALL INPUT PULSES
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
OUTPUT RTH
Equivalent to:
VTH
THÉVENIN EQUIVALENT
Rise time: 1 V/ns Fall time: 1 V/ns
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
Max Typical
Parameter Unit
R1 1071
R2 937
RTH 500
VTH 1.4 V
VCC 3.00 V
VCC
OUTPUT
R1
R2
AC Test Loads DC Test Load
CYRF69313
Document #: 001-66503 Rev. *B Page 69 of 78
AC Characteristics
Parameter Description Conditions Min Typical Max Unit
Clock
FIMO Internal main oscillator frequency No USB present
With USB present 22.8
23.64 –25.2
24.36 MHz
MHz
FILO Internal low-power oscillator Normal Mode
Low Power Mode 29.44
35.84 – 37.12
47.36 KHz
KHz
3.3 V Regulator
VORIP Output ripple voltage 45 – 55 %
USB Driver
TR1 Transition rise time CLOAD = 200 pF 75 – – ns
TR2 Transition rise time CLOAD = 600 pF – – 300 ns
TF1 Transition fall time CLOAD = 200 pF 75 – – ns
TF2 Transition fall time CLOAD = 600 pF – – 300 ns
TRRise/Fall time matching 80 – 125 %
VCRS Output signal crossover voltage 1.3 – 2.0 V
USB Data Timing
TDRATE Low speed data rate Ave. Bit Rate (1.5 Mbps ± 1.5%) 1.4775 – 1.5225 Mbps
TDJR1 Receiver data jitter tolerance To next transition –75 – 75 ns
TDJR2 Receiver data jitter tolerance To pair transition –45 – 45 ns
TDEOP Differential to EOP transition skew –40 – 100 ns
TEOPR1 EOP width at receiver Rejects as EOP – – 330 ns
TEOPR2 EOP width at receiver Accept as EOP 675 – – ns
TEOPT Source EOP width 1.25 – 1.5 s
TUDJ1 Differential driver jitter To next transition –95 – 95 ns
TUDJ2 Differential driver jitter To pair transition –95 – 95 ns
TLST Width of SE0 during different transition – – 210 ns
Non-USB Mode Driver Characteristics
TFPS2 SDATA/SCK transition fall time 50 – 300 ns
SPI Timing
TSMCK SPI master clock rate FCPUCLK/6 – – 2 MHz
TSSCK SPI slave clock rate – – 2.2 MHz
TSCKH SPI clock high time High for CPOL = 0, Low for CPOL = 1 125 – – ns
TSCKL SPI clock low time Low for CPOL = 0, High for CPOL = 1 125 – – ns
TMDO Master data output time[15] SCK to data valid –25 – 50 ns
TMDO1 Master data output time,
First bit with CPHA = 0 Time before leading SCK edge 100 – – ns
TMSU Master input data setup time 50 – – ns
TMHD Master input data hold time 50 – – ns
TSSU Slave input data setup time 50 – – ns
TSHD Slave input data hold time 50 – – ns
TSDO Slave data output time SCK to data valid – – 100 ns
TSDO1 Slave data output time,
First bit with CPHA = 0 Time after SS LOW to data valid – – 100 ns
TSSS Slave select setup time Before first SCK edge 150 – – ns
TSSH Slave select hold time After last SCK edge 150 – – ns
Note
15.In Master mode first bit is available 0.5 SPICLK cycle before Master clock edge available on the SCLK pin.
CYRF69313
Document #: 001-66503 Rev. *B Page 70 of 78
Figure 19. Clock Timing
Figure 20. USB Data Signal Timing
Figure 21. Clock Timing
Figure 22. USB Data Signal Timing
CLOCK
TCYC
TCL
TCH
90%
10%
90%
10%
D
DTRTF
Vcrs
Voh
Vol
CLOCK
TCYC
TCL
TCH
90%
10%
90%
10%
D
DTRTF
Vcrs
Voh
Vol
CYRF69313
Document #: 001-66503 Rev. *B Page 71 of 78
Figure 23. Receiver Jitte r Tolerance
Figure 24. Differential to EOP Transition Skew and EOP Width
Figure 25. Differential Data Jitter
Differential
Data Lines
Pair ed
Transitions
N * TPERIOD + TJR2
T
PERIOD
Consecutive
Transitions
N * TPERIOD + TJR1
TJR
TJR1
TJR2
T
PERIOD
Differential
Data Lines
Crossover
Point
C rosso ver Point
Extended
Source EO P Width: TEOPT
Receiver EOP W idth: TEOPR1, T EOPR2
Diff. Da ta to
SE0 S kew
N * TPERIOD + TDEOP
T
PERIOD
Differential
Data Lines
Crossover
Points
Paired
Transitions
N * TPERIOD + TxJR2
Consecutive
Transitions
N * TPERIOD + TxJR1
CYRF69313
Document #: 001-66503 Rev. *B Page 72 of 78
Figure 26. SPI Master Timing, CPHA = 1
Figure 27. SPI Slave Timing, CPHA = 1
MSB
TMSU
LSB
TMHD
TSCKH
TMDO
SS
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
MISO
(SS is under firmware control in SPI Master mode)
TSCKL
MSB LSB
MSB
TSSU
LSB
TSHD
TSCKH
TSDO
SS
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
MISO
TSCKL
TSSS TSSH
MSB LSB
CYRF69313
Document #: 001-66503 Rev. *B Page 73 of 78
Figure 28. SPI Master Timing, CPHA = 0
Figure 29. SPI Slave Timing, CPHA = 0
MSB
TMSU
LSB
TMHD
TSCKH
TMDO1
SS
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
MISO
(SS is under firmware control in SPI Master mode)
TSCKL
TMDO
LSBMSB
MSB
TSSU
LSB
TSHD
TSCKH
TSDO1
SS
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
MISO
TSCKL
TSDO
LSBMSB
TSSS TSSH
CYRF69313
Document #: 001-66503 Rev. *B Page 74 of 78
Ordering Code Definitions
Ordering Information
Package Ordering Part Number
40-pin Pb-free Punch-QFN 6 × 6 mm CYRF69313-40 LFXC
40-pin Pb-free Sawn-QFN 6 × 6 mm CYRF69313-40LTXC
CY
M arketing code: RF =
W ireless (radio frequency)
product line
RF XXXXX
Part num ber
Com pany ID: C Y = Cypress
40 LF/T
40-pin Q FN package
F = Punch, T = Sawn
C
Tem perature range:
Commercial
X
X = Pb-free
CYRF69313
Document #: 001-66503 Rev. *B Page 75 of 78
Package Handling
Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving
the factory. A label on the packaging has details about actual bake temp erature and the minimum bake time to remove this
moisture.The maximum bake time is the aggregate time that the parts are exposed to the bake temperature. Exceeding this exposure
time may degrade device reliability.
Package Diagram
Figure 30. 40-Pin Pb-free Punch-QFN 6 × 6 mm
Tab le 87. Package Handling
Parameter Description Min Typ Max Unit
TBAKETEMP Bake Temperature 125 see package label °C
tBAKETIME Bake Time see package label 24 hours
PAD
EXPOSED
SOLDERABLE
001-12917 *C
CYRF69313
Document #: 001-66503 Rev. *B Page 76 of 78
Figure 31. 40-Pin Pb-free Sawn-QFN 6 ×6 mm
001-44328 *F
CYRF69313
Document #: 001-66503 Rev. *B Page 77 of 78
Acronyms Document Conventions
Units of Measure
Table 88. Acronyms Used in this Document
Acronym Description
ACK Acknow ledge (packet received, no errors)
BER Bit error rate
BOM Bill of materials
CMOS complementary metal oxide semiconductor
CRC cyclic redundancy check
FEC forward error correction
FER frame error rate
GFSK Gaussian frequency-shift keying
HBM Human body model
ISM Industrial, scientific, and medical
IRQ interrupt request
MCU microcontrol ler unit
NRZ non return to zero
PLL phase-locked loop
QFN Q uad flat no-leads
RSSI received signal strength indication
RF radio frequency
Rx receive
Tx transmit
Table 89. Units of Measure
Symbol Unit of Measure
°C degree Celsius
dB decibels
dBc decibel relative to carrier
dBm decibel-milliwatt
Hz hertz
KB 1024 bytes
Kbit 1024 bits
kHz kilohertz
kkilohm
MHz megahertz
Mmegaohm
Amicroampere
smicrosecond
Vmicrovolt
Vrms microvolts root-mean-square
Wmicrowatts
mA milliampere
ms millisecond
mV millivolt
nA nanoampere
ns nanosecond
nV nanovolt
ohm
pp peak-to-peak
ppm parts per million
ps picosecond
sps samples per second
Vvolt
Document #: 001-66503 Rev. *B Revised February 28, 2012 Page 78 of 78
All products and company names mentioned in this document may be the trademarks of their respective holders.
CYRF6931
© Cypress Semico nducto r Co rpor ation , 2011-2012. The informati on con ta ined her ein is subje ct to cha nge w ithou t noti ce. C ypress S emiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply an y license under patent or other rights. Cypres s pro d ucts ar e not war ran t ed no r int e nded to be used fo r
medical, life supp or t, l if e savin g, cr it ical control or saf ety ap pl ic at io ns, unless pursuant to a n exp re ss wr i tte n ag re em en t w it h C ypress. Fu rthermore, Cypress does not auth ori ze i t s pr o ducts for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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Document Title: CYRF69313 Programmable Radio-on-Chip LPstar
Document Number: 001-66503
Revision ECN Orig. of
Change Submission
Date Description of Change
** 3188093 NXZ/KKCN 04/05/ 11 New advance da tasheet.
*A 3333406 KPMD 08/01/2011 Removed Advance status from the datasheet.
Post to external web.
*B 3532316 KKCN 02/28/2012 Updated Ordering Information (CYRF69313-40LTXC) and Ordering Code
Definitions.
Updated Package Diagram (001-44328).
Added Package Handling .
