M24L416256DA-55TIG - Elite Semiconductor Memory Technology, Inc.

ESMT

M24L416256DA

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008

Revision: 1.5 1/15

PSRAM 4-Mbit (256K x 16) Pseudo Static RAM

Features

• Advanced low-power architecture

•High speed: 55 ns, 60 ns and 70 ns

•Wide voltage range: 2.7V to 3.6V

•Typical active current: 1 mA @ f = 1 MHz

•Low standby power

•Automatic power-down when deselected

Functional Description

The M24L416256DA is a high-performance CMOS pseudo

static RAM (PSRAM) organized as 256K words by 16 bits that

supports an asynchronous memory interface. This device

features advanced circuit design to provide ultra-low active

current. This is ideal for portable applications such as cellular

telephones. The device can be put into standby mode

reducing power consumption dramatically when deselected

( 1CE HIGH, CE2 LOW or both BHE and BLE are HIGH).

The input/output pins (I/O0 through I/O15) are placed in a

high-impedance state when: deselected ( 1CE HIGH, CE2

LOW, OE is HIGH), or during a write operation (Chip

Enabled and Write Enable WE LOW).

Reading from the device is accomplished by asserting the

Chip Enables ( 1CE LOW and CE2 HIGH) and Output

Enable( OE ) LOW while forcing the Write Enable ( WE ) HIGH.

If Byte Low Enable ( BLE ) is LOW, then data from the memory

location specified by the address pins A0 through A17 will

appear on I/O0 to I/O7. If Byte High Enable ( BHE ) is LOW,

then data from memory will appear on I/O8 to I/O15. See the

Truth Table for a complete description of read and write

modes.

ESMT

M24L416256DA

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008

Revision: 1.5 2/15

Pin Configuration[3, 4, 5]

44-pin TSOPII

Top View

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

A4

A3

A2

A1

A0

CE1

I/O0

I/O1

I/O2

I/O3

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

A5

A6

A7

OE

BHE

BLE

I/O15

I/O14

I/O13

I/O12

V

CC

V

SS

I/O4

I/O5

I/O6

I/O7

WE

A16

A15

A14

A13

A12

V

SS

V

CC

I/O11

I/O10

I/O9

I/O8

CE2

A8

A9

A10

A11

A17

ESMT

M24L416256DA

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008

Revision: 1.5 3/15

Product Portfolio

Power Dissipation

Operating, ICC (mA)

VCC Range(V)

f = 1 MHz f = fMAX

Standby, ISB2 (µA)

Product

Min. Typ. Max.

Speed

(ns)

Typ.[2] Max. Typ.[2] Max. Typ.[2] Max.

55

60

14 22

M24L416256DA 2.7 3.0 3.6

70

1 5

8 15

17 40

Notes:

2.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC (typ)

and TA = 25°C.

3.Ball H1, G2, H6 are the address expansion pins for the 8-Mb, 16-Mb, and 32-Mb densities, respectively.

4.NC “no connect”—not connected internally to the die.

5.DNU (Do Not Use) pins have to be left floating or tied to VSS to ensure proper application.

ESMT

M24L416256DA

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008

Revision: 1.5 4/15

Maximum Ratings

(Above which the useful life may be impaired. For user

guide-lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied ..............................................–55°C to +125°C

Supply Voltage to Ground Potential ................−0.4V to 4.6V

DC Voltage Applied to Outputs

in High-Z State[6, 7, 8] .......................................−0.4V to 3.7V

DC Input Voltage[6, 7, 8] ....................................−0.4V to 3.7V

Output Current into Outputs (LOW) ............................20 mA

Static Discharge Voltage ......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current ....................................................> 200 mA

Operating Range

Range Ambient Temperature (TA) VCC

Extended −25°C to +85°C 2.7V to 3.6V

Industrial −40°C to +85°C 2.7V to 3.6V

DC Electrical Characteristics (Over the Operating Range) -55, 60, 70

Parameter Description Test Conditions Min. Typ.[2] Max.

Unit

VCC Supply Voltage 2.7 3.0 3.6 V

VOH Output HIGH

Voltage IOH = −0.1 mA VCC – 0.4 V

VOL Output LOW

Voltage IOL = 0.1 mA 0.4 V

VIH Input HIGH

Voltage 0.8 * VCC V

CC + 0.4 V

VIL Input LOW

Voltage F = 0 -0.4 0.62 V

IIX Input Leakage

Current GND ≤ V

IN ≤ Vcc -1 +1 µA

IOZ Output Leakage

Current

GND ≤ V

OUT

≤

Vcc, Output

Disabled -1 +1 µA

f = fMAX = 1/tRC

14 for –55

14 for –60

08 for –70

22 for –55

22 for –60

15 for –70

ICC VCC Operating

Supply Current

f = 1 MHz

VCC = 3.6V,

IOUT = 0 mA,

CMOS level 1 for all speeds 5 for all speeds

mA

ISB1

Automatic 1CE

Power-down

Current —CMOS

Inputs

1CE ≥ V

CC − 0.2V, CE2

≤

0.2V, VIN ≥ V

CC − 0.2V, VIN

≤

0.2V, f = fMAX(Address and Data

Only),f = 0 ( OE , WE ,BHE and

BLE )

150 250 µA

ISB2

Automatic 1CE

Power-down

Current —CMOS

Inputs

1CE ≥ V

CC − 0.2V, CE2

≤

0.2V, VIN ≥ V

CC − 0.2V or VIN

≤ 0.2V, f = 0, VCC = 3.6V

17 40 µA

Capacitance[9]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance 8 pF

COUT Output Capacitance

TA = 25°C, f = 1 MHz

VCC = VCC(typ) 8 pF

Thermal Resistance[9]

Parameter Description Test Conditions VFBGA Unit

θJA Thermal Resistance (Junction to Ambient) 55 °C/W

θJC Thermal Resistance (Junction to Case)

Test conditions follow standard test

methods and procedures for measuring

thermal impedance, per EIA/JESD51. 17 °C/W

Notes:

6.VIH(MAX) = VCC + 0.5V for pulse durations less than 20 ns.

7.VIL(MIN) = –0.5V for pulse durations less than 20 ns.

8.Overshoot and undershoot specifications are characterized and are not 100% tested.

9.Tested initially and after design or process changes that may affect these parameters.

ESMT

M24L416256DA

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008

Revision: 1.5 5/15

AC Test Loads and Waveforms

Parameters 3.0V VCC Unit

R1 22000 Ω

R2 22000 Ω

RTH 11000 Ω

VTH 1.50 V

Switching Characteristics (Over the Operating Range)[10]

–55 –60 –70

Prameter Description Min. Max. Min. Max. Min. Max. Unit

Read Cycle

tRC Read Cycle Time 55[14] 60 70 ns

tAA Address to Data Valid 55 60 70 ns

tOHA Data Hold from Address Change 5 8 10 ns

tACE 1CE LOW and CE2 HIGH to Data Valid 55 60 70 ns

tDOE OE LOW to Data Valid 25 25 35 ns

tLZOE OE LOW to Low Z[11, 12] 5 5 5 ns

tHZOE OE HIGH to High Z[11, 12] 25 25 25 ns

tLZCE 1CE LOW and CE2 HIGH to Low Z[11,

12]

5 5 5 ns

tHZCE 1CE HIGH and CE2 LOW to High Z[11,

12]

25 25 25 ns

tDBE BLE /BHE LOW to Data Valid 55 60 70 ns

tLZBE BLE /BHE LOW to Low Z[11, 12] 5 5 5 ns

tHZBE BLE /BHE HIGH to High-Z[11, 12] 10 10 25 ns

tSK [14] Address Skew 0 5 10 ns

Write Cycle[13]

tWC Write Cycle Time 55 60 70 ns

tSCE 1CE LOW and CE2 HIGH to Write End 45 45 60 ns

tAW Address Set-up to Write End 45 45 55 ns

tHA Address Hold from Write End 0 0 0 ns

tSA Address Set-up to Write Start 0 0 0 ns

Notes:

10. Test conditions assume signal transition time of 1 V/ns or higher, timing reference levels of VCC(typ)/2, input pulse levels of 0V

to VCC(typ), and output loading of the specified IOL/IOH and 30-pF load capacitance.

11. tHZOE, tHZCE, tHZBE and tHZWE transitions are measured when the outputs enter a high-impedance state.

12. High-Z and Low-Z parameters are characterized and are not 100% tested.

13. The internal write time of the memory is defined by the overlap of WE , 1CE = VIL, CE2 = VIH, BHE and/or BLE =VIL. All

signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input

set-up and hold timing should be referenced to the edge of the signal that terminates write.

14. To achieve 55-ns performance, the read access should be CE controlled. In this case tACE is the critical parameter and tSK is

satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable

within 10 ns after the start of the read cycle.

ESMT

M24L416256DA

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008

Revision: 1.5 6/15

Switching Characteristics (Over the Operating Range)[10] (continued)

–55 –60 –70

Prameter Description Min. Max. Min. Max. Min. Max. Unit

tPWE WE Pulse Width 40 40 45 ns

tBW BLE /BHE LOW to Write End 50 50 55 ns

tSD Data Set-up to Write End 25 25 25 ns

tHD Data Hold from Write End 0 0 0 ns

tHZWE WE LOW to High Z[11, 12] 25 25 25 ns

tLZWE WE HIGH to Low Z[11, 12] 5 5 5 ns

Switching Waveforms

Read Cycle 1 (Address Transition Controlled)[14, 15, 16]

Read Cycle 2 (OE Controlled)[14, 16]

Notes:

15.Device is continuously selected. OE , CE = VIL.

16. WE is HIGH for Read Cycle.

ESMT

M24L416256DA

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008

Revision: 1.5 7/15

Switching Waveforms (continued)

Write Cycle No. 1(WE Controlled)[12, 13, 17, 18, 19]

Notes:

17.Data I/O is high impedance if OE > VIH.

18.If Chip Enable goes INACTIVE simultaneously with WE =HIGH, the output remains in a high-impedance state.

19.During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.

ESMT

M24L416256DA

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008

Revision: 1.5 8/15

Switching Waveforms (continued)

Write Cycle 2 ( 1CE or CE2 Controlled)[12, 13, 17, 18, 19]

Write Cycle 3 (WE Controlled, OE LOW)[18, 19]

ESMT

M24L416256DA

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008

Revision: 1.5 9/15

Switching Waveforms (continued)

Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[18, 19]

ESMT

M24L416256DA

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008

Revision: 1.5 10/15

Avoid Timing

ESMT Pseudo SRAM has a timing which is not supported at read operation, If your system has multiple invalid address signal

shorter than tRC during over 15μs at read operation shown as in Abnormal Timing, it requires a normal read timing at leat during

15μs shown as in Avoidable timing 1 or toggle 1CE to high (≧tRC) one time at least shown as in Avoidable Timing 2.

Abnormal Timing

Avoidable Timing 1

Avoidable Timing 2

CE1

15μs

≧

WE

Address

＜

t

RC

CE1

15μs

≧

WE

Address

t

≧

RC

CE1

15μs

≧

WE

Address

＜

t

RC

t

≧

RC

ESMT

M24L416256DA

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008

Revision: 1.5 11/15

Truth Table[20]

1CE CE2 WE OE BHE BLE Inputs/Outputs Mode Power

H X X X X X High Z Deselect/Power-down Standby (ISB)

X L X X X X High Z Deselect/Power-down Standby (ISB)

X X X X H H High Z Deselect/Power-down Standby (ISB)

L H H L L L Data Out (I/O0–I/O15) Read (Upper Byte and Lower Byte) Active (ICC)

L H H L H L

Data Out (I/O0–I/O7);

I/O8–I/O15 in High Z Read (Upper Byte only) Active (ICC)

L H H L L H

Data Out (I/O8–I/O15);

I/O0–I/O7 in High Z Read (Lower Byte only) Active (ICC)

L H H H L L High Z Output Disabled Active (ICC)

L H H H H L High Z Output Disabled Active (ICC)

L H H H L H High Z Output Disabled Active (ICC)

L H L X L L Data In (I/O0–I/O15) Write (Upper Byte and Lower Byte) Active (ICC)

L H L X H L

Data In (I/O0–I/O7);

I/O8–I/O15 in High Z Write (Lower Byte Only) Active (ICC)

L H L X L H

Data In (I/O8–I/O15);

I/O0–I/O7 in High Z Write (Upper Byte Only) Active (ICC)

Note:

20.H = Logic HIGH, L = Logic LOW, X = Don’t Care.

Ordering Information

Speed (ns) Ordering Code Package Type Operating Range

55 M24L416256DA-55BEG 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free) Extended

60 M24L416256DA-60BEG 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free) Extended

70 M24L416256DA-70BEG 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free) Extended

55 M24L416256DA-55TEG 44-pin TSOPII (Pb-Free) Extended

60 M24L416256DA-60TEG 44-pin TSOPII (Pb-Free) Extended

70 M24L416256DA-70TEG 44-pin TSOPII (Pb-Free) Extended

55 M24L416256DA-55BIG 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free) Industrial

60 M24L416256DA-60BIG 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free) Industrial

70 M24L416256DA-70BIG 48-ball Very Fine Pitch BGA (6.0 x 8.0 x 1.0 mm) (Pb-Free) Industrial

55 M24L416256DA-55TIG 44-pin TSOPII (Pb-Free) Industrial

60 M24L416256DA-60TIG 44-pin TSOPII (Pb-Free) Industrial

70 M24L416256DA-70TIG 44-pin TSOPII (Pb-Free) Industrial

ESMT

M24L416256DA

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008

Revision: 1.5 12/15

Package Diagram

48-ball VFBGA (6 x 8 x 1 mm)

ESMT

M24L416256DA

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008

Revision: 1.5 13/15

44-LEAD TSOP(II) PSRAM(400mil)

Symbol Dimension in mm Dimension in inch

Min Norm Max Min Norm Max

A

1.20

0.047

A1 0.05

0.15 0.002

0.006

A2 0.95 1.00 1.05 0.037 0.039 0.042

B 0.30

0.45 0.012

0.018

B1 0.30 0.35 0.40 0.012 0.014 0.016

C 0.12

0.21 0.005

0.008

C1 0.10

0.16 0.004

0.006

D 18.28 18.41 18.54 0.720 0.725 0.730

ZD 0.805 REF 0.0317 REF

E 11.56 11.76 11.96 0.455 0.463 0.471

E1 10.03 10.16 10.29 0.395 0.400 0.4

L 0.40 0.59 0.69 0.016 0.023 0.027

L1 0.80 REF 0.031 REF

e 0.80 BSC 0.0315 BSC

θ °0 °8 °0 °8

ESMT

M24L416256DA

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008

Revision: 1.5 14/15

Revision History

Revision Date Description

1.0 2007.07.04 Original

1.1 2007.11.20

Modify the descriptive error for standby mode, tHZWE and tLZWE

description

1.2 2007.11.22

Modify tHZBE and tLZBE descriptive and restore tHZWE and tLZWE

description

1.3 2008.02.27

1.Add 44-pin TSOPII package

2. Add Avoid timing

1.4 2008.03.24 Add I-grade for TSOPII package

1.5 2008.07.04

1. Move Revision History to the last

2. Modify voltage range 2.7V~3.3V to 2.7V~3.6V

3. Add Industrial grade for BGA package

ESMT

M24L416256DA

Elite Semiconductor Memory Technology Inc. Publication Date: Jul. 2008

Revision: 1.5 15/15

Important Notice

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without the prior permission of ESMT.

The contents contained in this document are believed to be accurate at the time of

publication. ESMT assumes no responsibility for any error in this document, and reserves

the right to change the products or specification in this document without notice.

The information contained herein is presented only as a guide or examples for the

application of our products. No responsibility is assumed by ESMT for any infringement of

patents, copyrights, or other intellectual property rights of third parties which may result

from its use. No license, either express , implied or otherwise, is granted under any

patents, copyrights or other intellectual property rights of ESMT or others.

Any semiconductor devices may have inherently a certain rate of failure. To minimize risks

associated with customer's application, adequate design and operating safeguards against

injury, damage, or loss from such failure, should be provided by the customer when

making application designs.

ESMT's products are not authorized for use in critical applications such as, but not limited

to, life support devices or system, where failure or abnormal operation may directly affect

human lives or cause physical injury or property damage. If products described here are to

be used for such kinds of application, purchaser must do its own quality assurance testing

appropriate to such applications.