E n n n n n n 28F016XD 16-MBIT (1 MBIT x 16) DRAM-INTERFACE FLASH MEMORY 85 ns Access Time (t RAC) Supports both Standard and FastPage-Mode Accesses n n Multiplexed Address Bus RAS# and CAS# Control Inputs n n No-Glue Interface to Many Memory Controllers SmartVoltage Technology User-Selectable 3.3V or 5V V CC User-Selectable 5V or 12V V PP 0.33 MB/sec Write Transfer Rate x16 Architecture n n n 56-Lead TSOP Type I Package Backwards-Compatible with 28F008SA Command Set 2 A Typical Deep Power-Down Current 1 mA Typical I CC Active Current in Static Mode 32 Separately-Erasable/Lockable 64-Kbyte Blocks 1 Million Erase Cycles per Block State-of-the-Art 0.6 m ETOXTM IV Flash Technology Intel's 28F016XD 16-Mbit flash memory is a revolutionary architecture which is the ideal choice for designing truly revolutionary high-performance products. Combining its DRAM-like read performance and interface with the intrinsic nonvolatility of flash memory, the 28F016XD eliminates the traditional redundant memory paradigm of shadowing code from a slow nonvolatile storage source to a faster execution memory, such as DRAM, for improved system performance. The innovative capabilities of the 28F016XD enable the design of direct-execute code and mass storage data/file flash memory systems. The 28F016XD's DRAM-like interface with a multiplexed address bus, flexible VCC and VPP voltages, power saving features, extended cycling, fast program and read performance, symmetrically-blocked architecture, and selective block locking provide a highly flexible memory component suitable for resident flash component arrays on the system board or SIMMs. The DRAM-like interface with RAS# and CAS# control inputs allows for easy migration to flash memory in existing DRAM-based systems. The 28F016XD's dual read voltage allows the same component to operate at either 3.3V or 5.0V VCC. Programming voltage at 5.0V VPP minimizes external circuitry in minimal-chip, space critical designs, while the 12.0V VPP option maximizes program/erase performance. The x16 architecture allows optimization of the memory-to-processor interface. Its high read performance combined with flexible block locking enable both storage and execution of operating systems/application software and fast access to large data tables. The 28F016XD is manufactured on Intel's 0.6 m ETOX IV process technology. December 1996 Order Number: 290533-004 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F016XD may contain design defects or errors known as errata. Current characterized errata are available upon request. *Third-party brands and names are the property of their respective owners. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-879-4683 COPYRIGHT (c) INTEL CORPORATION, 1996 CG-041493 E 28F016XD FLASH MEMORY CONTENTS PAGE 1.0 INTRODUCTION ......................................... 5 1.1 Product Overview...................................... 5 2.0 DEVICE PINOUT......................................... 6 2.1 Lead Descriptions ..................................... 9 3.0 MEMORY MAPS ....................................... 11 3.1 Extended Status Registers Memory Map ........................................ 12 4.0 4.1 4.2 4.3 4.4 4.5 4.6 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS.......... 13 Bus Operations ....................................... 13 28F008SA--Compatible Mode Command Bus Definitions.................... 14 28F016XD--Enhanced Command Bus Definitions ..................................... 15 Compatible Status Register .................... 16 Global Status Register ............................ 17 Block Status Register.............................. 18 5.0 ELECTRICAL SPECIFICATIONS ............. 19 5.1 Absolute Maximum Ratings..................... 19 5.2 Capacitance............................................ 20 5.3 Transient Input/Output Reference Waveforms........................................... 21 5.4 DC Characteristics (VCC = 3.3V 0.3V).............................. 22 5.5 DC Characteristics (VCC = 5.0V 0.5V).............................. 25 PAGE AC Characteristics (VCC = 3.3V 0.3V)..............................28 Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) ....28 Read Cycle...............................................28 Write Cycle ...............................................29 Read-Modify-Write Cycle..........................30 Fast Page Mode Cycle .............................30 Fast Page Mode Read-Modify-Write Cycle ........................................................30 Refresh Cycle...........................................31 Misc. Specifications ..................................31 5.7 AC Characteristics (VCC = 5.0V 0.5V)..............................33 Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) ....33 Read Cycle...............................................34 Write Cycle ...............................................35 Read-Modify-Write Cycle..........................35 Fast Page Mode Cycle .............................35 Fast Page Mode Read-Modify-Write Cycle ........................................................36 Refresh Cycle...........................................36 Misc. Specifications ..................................37 5.8 AC Waveforms ........................................38 5.9 Power-Up and Reset Timings..................50 5.10 Erase and Word Program Performance ..51 5.6 6.0 MECHANICAL SPECIFICATIONS ............52 APPENDIX A: Device Nomenclature and Ordering Information .....................................53 APPENDIX B: Additional Information...............54 3 E 28F016XD FLASH MEMORY REVISION HISTORY Number 4 Description -001 Original Version -002 Removed support of the following features: * All page buffer operations (read, write, programming, Upload Device Information) * Command queuing * Software Sleep and Abort * Erase All Unlocked Blocks * Device Configuration command Changed definition of "NC." Removed "No internal connection to die" from description. Added "xx" to Upper Byte of Command (Data) Definition in Sections 4.2 and 4.3. Modified parameters "V" and "I" of Section 5.1 to apply to "NC" pins. Increased IPPS (VPP Read Current) for VPP > VCC to 200 A at VCC = 3.3V/5.0V. Changed VCC = 5.0V DC Characteristics (Section 5.5) marked with Note 1 to indicate that these currents are specified for a CMOS rise/fall time (10% to 90%) of <5 ns and a TTL rise/fall time of <10 ns. Corrected "RP# high to RAS# going low" to be a "Min" specification at V CC = 3.3V/5.0V. Increased Typical "Word/Block Program Times" (tWHRH1/tWHRH3) for VPP = 5.0V: tWHRH1 from 24.0 s to 35.0 s and t WHRH3 from 0.8 sec to 1.2 sec at V CC = 3.3V tWHRH1 from 16.0 s to 25.0 s and t WHRH3 from 0.6 sec to 0.85 sec at V CC = 5.0V Changed "Time from Erase Suspend Command to WSM Ready" spec name to "Erase Suspend Latency Time to Read;" modified typical values and added Min/Max values at VCC =3.3/5.0V and VPP =5.0/12.0V (Section 5.10). Minor cosmetic changes throughout document. -003 Added 3/5# pin to Pinout Configuration (Figure 2), Product Overview (Section 1.1) and Lead Descriptions (Section 2.1) Modified Block Diagram (Figure 1): Removed Address/Data Queues, Page Buffers, and Address Counter; Added 3/5# pin Added 3/5# pin to Test Conditions of ICC2 and ICC5 Specifications Modified Power-Up and Reset Timings (Section 5.9) to include 3/5# pin: Removed t5VPH and t 3VPH specifications; Added t PLYL, tPLYH, tYLPH, and tYHPH specifications Corrected TSOP Mechanical Specification A1 from 0.50 mm to 0.050 mm (Section 6.0) Minor cosmetic changes throughout document. -004 Updated DC Specifications ICC3, ICC4, ICC6, ICC7, ICCD and IPPES Updated AC Specifications tCAS(min), tRCD(max) and tCWD(min) E 1.0 INTRODUCTION The documentation of the Intel 28F016XD flash memory device includes this datasheet, a detailed user's manual, and a number of application notes and design tools, all of which are referenced in Appendix B. The datasheet is intended to give an overview of the chip feature-set and of the operating AC/DC specifications. The 16-Mbit Flash Product Family User's Manual provides complete descriptions of the user modes, system interface examples and detailed descriptions of all principles of operation. It also contains the full list of software algorithm flowcharts, and a brief section on compatibility with the Intel 28F008SA. Significant 28F016XD feature revisions occurred between datasheet revisions 290533-001 and 290533-002. These revisions center around removal of the following features: * All page buffer operations (read, write, programming, Upload Device Information) * Command queuing * Software Sleep and Abort * Erase all Unlocked Blocks * Device Configuration command In addition, a significant 28F016XD change occurred between datasheet revisions 290532-002 and 290532-003. This change centers around the addition of a 3/5# pin to the device's pinout configuration. Figure 2 shows the 3/5# pin assignment for the TSOP Type 1 package. Intel recommends that all customers obtain the latest revisions of 28F016XD documentation. 1.1 Product Overview The 28F016XD is a high-performance, 16-Mbit (16,777,216-bit) block erasable, nonvolatile random access memory, organized as 1 Mword x 16. The 28F016XD includes thirty-two 32-KW (32,768 word) blocks. A chip memory map is shown in Figure 3. The implementation of a new architecture, with many enhanced features, will improve the device operating characteristics and result in greater product reliability and ease-of-use as compared to 28F016XD FLASH MEMORY other flash memories. Significant features of the 28F016XD include: * No-Glue Interface to Memory Controllers * Improved Word Program Performance * SmartVoltage Technology Selectable 3.3V or 5.0V VCC Selectable 5.0V or 12.0V VPP * Block Program/Erase Protection The 28F016XD's multiplexed address bus with RAS# and CAS# inputs allows for a "No Glue" interface to many existing in-system memory controllers. As such, 28F016XD-based SIMMs (72-pin JEDEC Standard) offer attractive advantages over their DRAM counterparts in many applications. For more information on 28F016XDbased SIMM designs, see the application note referenced at the end of this datasheet. The 28F016XD incorporates SmartVoltage technology, providing VCC operation at both 3.3V and 5.0V and program and erase capability at VPP = 12.0V or 5.0V. Operating at VCC = 3.3V, the 28F016XD consumes less than 60% of the power consumption at 5.0V VCC, while 5.0V VCC provides the highest read performance capability. VPP = 5.0V operation eliminates the need for a separate 12.0V converter, while VPP = 12.0V maximizes program/erase performance. In addition to the flexible program and erase voltages, the dedicated VPP gives complete code protection with VPP VPPLK. A 3/5# input pin configures the device's internal circuitry for optimal 3.3V or 5.0V read/program operation. A Command User Interface (CUI) serves as the system interface between the microprocessor or microcontroller and the internal memory operation. Internal Algorithm Automation allows word programs and block erase operations to be executed using a Two-Write command sequence to the CUI in the same way as the 28F008SA 8Mbit FlashFileTM memory. Software Locking of Memory Blocks is an added feature of the 28F016XD as compared to the 28F008SA. The 28F016XD provides selectable block locking to protect code or data such as direct-executable operating systems or application code. Each block has an associated nonvolatile lock-bit which determines the lock status of the 5 E 28F016XD FLASH MEMORY block. In addition, the 28F016XD has a master Write Protect pin (WP#) which prevents any modifications to memory blocks whose lock-bits are set. Writing of memory data is performed in word increments typically within 6 s (12.0V VPP)--a 33% improvement over the 28F008SA. A block erase operation erases one of the 32 blocks in typically 0.6 sec (12.0V VPP), independent of the other blocks, which is about a 65% improvement over the 28F008SA. Each block can be written and erased a minimum of 100,000 cycles. Systems can achieve one million Block Erase Cycles by providing wearleveling algorithms and graceful block retirement. These techniques have already been employed in many flash file systems and hard disk drive designs. All operations are started by a sequence of Write commands to the device. Three types of Status Registers (described in detail later in this datasheet) and a RY/BY# output pin provide information on the progress of the requested operation. The following Status Registers are used to provide device and WSM information to the user : * A Compatible Status Register (CSR) which is 100% compatible with the 28F008SA FlashFile memory Status Register. The CSR, when used alone, provides a straightforward upgrade capability to the 28F016XD from a 28F008SAbased design. * A Global Status Register (GSR) which also informs the system of overall Write State Machine (WSM) status. * 32 Block Status Registers (BSRs) which provide block-specific status information such as the block lock-bit status. The GSR and BSR memory maps are shown in Figure 4. The 28F016XD incorporates an open drain RY/BY# output pin. This feature allows the user to OR-tie many RY/BY# pins together in a multiple memory configuration such as a Resident Flash Array. The 28F016XD is specified for a maximum fast page mode cycle time of 65 ns (tPC,R) at 5.0V operation (4.75V to 5.25V) over the commercial temperature range (0C to +70C). A corresponding maximum fast page mode cycle time of 75 ns at 3.3V (3.0V to 3.6V and 0C to +70C) is achieved for reduced power consumption applications. The 28F016XD incorporates an Automatic Power Saving (APS) feature, which substantially reduces the active current when the device is in static mode of operation (addresses not switching). In APS mode, the typical ICC current is 1 mA at 5.0V (3.0 mA at 3.3V). A deep power-down mode of operation is invoked when the RP# (called PWD# on the 28F008SA) pin transitions low. This mode brings the device power consumption to less than 2.0 A, typically, and provides additional write protection by acting as a device reset pin during power transitions. A reset time of 300 ns (5.0V VCC operation) is required from RP# switching high until dropping RAS#. In the deep power-down state, the WSM is reset (any current operation will abort) and the CSR, GSR and BSR registers are cleared. A CMOS standby mode of operation is enabled when RAS# and CAS# transition high and RP# stays high with all input control pins at CMOS levels. In this mode, the device typically draws an ICC standby current of 70 A at 5.0V V CC. The 28F016XD is available in a 56-Lead, 1.2 mm thick, 14 mm x 20 mm TSOP Type I package. This form factor and pinout allow for very high board layout densities. 2.0 DEVICE PINOUT The 28F016XD 56-Lead TSOP Type I pinout configuration is shown in Figure 2. 6 E 28F016XD FLASH MEMORY DQ DQ 8-15 Output Buffer 0-7 Output Buffer Input Buffer Input Buffer I/O Logic Output Multiplexer ID Register VCC Data Register CSR RAS# ESRs CAS# CUI OE# WP# Y Decoder Y Gating/Sensing WSM X Decoder 64-Kbyte Block 31 RY/BY# Address Register 64-Kbyte Block 30 CAS# WE# RP# 64-Kbyte Block 1 RAS# Input Buffer/ Address De-Mux 64-Kbyte Block 0 A 0-9 Data Comparator Program/Erase Voltage Switch VPP 3/5# V CC GND 0533_01 Figure 1. 28F016XD Block Diagram Architectural Evolution Includes Multiplexed Address Bus, SmartVoltage Technology, and Extended Registers 7 E 28F016XD FLASH MEMORY 3/5# GND NC A9 A8 A7 A6 A5 VCC RAS# CAS# NC NC GND VPP RP# NC NC NC NC GND NC NC A4 A3 A2 A1 A0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 E28F016XD 56-LEAD TSOP PINOUT 14 mm x 20 mm TOP VIEW 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 WP# WE# OE# RY/BY# DQ 15 DQ 7 DQ 14 DQ 6 GND DQ 13 DQ 5 DQ 12 DQ 4 VCC GND DQ 11 DQ 3 DQ 10 DQ 2 VCC DQ 9 DQ 1 DQ 8 DQ 0 NC VCC NC NC 0533_02 Figure 2. 28F016XD 56-Lead TSOP Type I Pinout Configuration 8 E 28F016XD FLASH MEMORY 2.1 Lead Descriptions Symbol A0-A9 DQ0-DQ15 RAS# CAS# RP# OE# WE# RY/BY# WP# Type Name and Function INPUT MULTIPLEXED ROW/COLUMN ADDRESSES: Selects a word within one of thirty-two 32-Kword blocks. Row (upper) addresses are latched on the falling edge of RAS#, while column (lower) addresses are latched on the falling edge of CAS#. INPUT/OUTPUT DATA BUS: Inputs data and commands during CUI write cycles. Outputs array, identifier or status data (DQ0-7) in the appropriate read mode. Floated when the chip is de-selected or the outputs are disabled. INPUT ROW ADDRESS STROBE: Latches row address information on inputs A9-0 when RAS# transitions low. A subsequent CAS# low transition initiates 28F016XD read or program operations. INPUT COLUMN ADDRESS STROBE: Latches column address information on inputs A9-0 when CAS# transitions low. When preceded by a RAS# low transition, CAS# low initiates 28F016XD read or program operations, along with OE# and WE#. Subsequent CAS# low transitions, with RAS# held low, enable fast page mode reads/programs INPUT RESET/POWER-DOWN: RP# low places the device in a deep powerdown state. All circuits that consume static power, even those circuits enabled in standby mode, are turned off. When returning from deep power-down, a recovery time of 300 ns at 5.0V VCC is required to allow these circuits to power-up. When RP# goes low, the current WSM operation is terminated, and the device is reset. All Status Registers return to ready (with all status flags cleared). Exit from deep power-down places the device in read array mode. INPUT OUTPUT ENABLE: Gates device data through the output buffers when low in combination with RAS# and CAS# low. The outputs float to tri-state off when OE# is high. OE# can be tied to GND if not controlled by the system memory controller. RAS# and CAS# high override OE# low. WE# low also overrides OE# low. INPUT WRITE ENABLE: Controls access to the CUI, Data Register and Address Register. WE# is active low and initiates programs in combination with RAS# and CAS# low. WE# low overrides OE# low. RAS# and CAS# high override WE# low. OPEN DRAIN READY/BUSY: Indicates status of the internal WSM. When low, it OUTPUT indicates that the WSM is busy performing an operation. RY/BY# floating indicates that the WSM is ready for new operations, erase is suspended, or the device is in deep power-down mode. This output is always active (i.e., not floated to tri-state off when OE#, RAS# or CAS# are high). INPUT WRITE PROTECT: Erase blocks can be locked by writing a nonvolatile lock-bit for each block. When WP# is low, those locked blocks as reflected by the Block-Lock Status bits (BSR.6), are protected from inadvertent data programs or erases. When WP# is high, all blocks can be written or erased regardless of the state of the lock-bits. The WP# input buffer is disabled when RP# transitions low (deep power-down mode). 9 E 28F016XD FLASH MEMORY 2.1 Lead Descriptions (Continued) Type Name and Function 3/5# Symbol INPUT VPP SUPPLY VCC SUPPLY GND SUPPLY 3.3/5.0 VOLT SELECT: 3/5# high configures internal circuits for 3.3V operation. 3/5# low configures internal circuits for 5.0V operation. NOTE: Reading the array with 3/5# high in a 5.0V system could damage the device. Reference the power-up and reset timings (Section 5.9) for 3/5# switching delay to valid data. PROGRAM/ERASE POWER SUPPLY (12.0V 0.6V, 5.0V 0.5V): For erasing memory array blocks or writing words into the flash array. V PP = 5.0V 0.5V eliminates the need for a 12.0V converter, while connection to 12.0V 0.6V maximizes program/erase performance. NOTE: Successful completion of program and erase attempts is inhibited with VPP at or below 1.5V. Program and erase attempts with VPP between 1.5V and 4.5V, between 5.5V and 11.4V, and above 12.6V produce spurious results and should not be attempted. DEVICE POWER SUPPLY (3.3V 0.3V, 5.0V 0.5V): To switch 3.3V to 5.0V (or vice versa), first ramp V CC down to GND, and then power to the new VCC voltage. Do not leave any power pins floating. GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins floating. NO CONNECT: Lead may be driven or left floating. NC 10 E 28F016XD FLASH MEMORY 3.0 MEMORY MAPS A [19-0] FFFFF F8000 F7FFF F0000 EFFFF E8000 E7FFF E0000 DFFFF D8000 D7FFF D0000 CFFFF C8000 C7FFF C0000 BFFFF B8000 B7FFF B0000 A8FFF A8000 A7FFF A0000 9FFFF 98000 97FFF 90000 8FFFF 88000 87FFF 80000 7FFFF 78000 77FFF 70000 6FFFF 68000 67FFF 60000 5FFFF 58000 57FFF 50000 4FFFF 48000 47FFF 40000 3FFFF 38000 37FFF 30000 2FFFF 28000 27FFF 20000 1FFFF 18000 17FFF 10000 0FFFF 08000 07FFF 00000 32-Kword Block 31 32-Kword Block 30 32-Kword Block 29 32-Kword Block 28 32-Kword Block 27 32-Kword Block 26 32-Kword Block 25 32-Kword Block 24 32-Kword Block 23 32-Kword Block 22 32-Kword Block 21 32-Kword Block 20 32-Kword Block 19 32-Kword Block 18 32-Kword Block 17 32-Kword Block 16 32-Kword Block 15 32-Kword Block 14 32-Kword Block 13 32-Kword Block 12 32-Kword Block 11 32-Kword Block 10 32-Kword Block 9 32-Kword Block 8 32-Kword Block 7 32-Kword Block 6 32-Kword Block 5 32-Kword Block 4 32-Kword Block 3 32-Kword Block 2 32-Kword Block 1 32-Kword Block 0 0533_03 NOTE: The upper 10 bits (A19-10) reflect 28F016XD addresses A9-0, latched by RAS#. The lower 10 bits (A9-0) reflect 28F016XD addresses A9-0, latched by CAS#. Figure 3. 28F016XD Memory Map 11 E 28F016XD FLASH MEMORY 3.1 Extended Status Registers Memory Map A 19-0 FFFFFH RESERVED F8003H RESERVED GSR F8002H RESERVED BSR31 F8001H RESERVED RESERVED F8000H 07FFFH RESERVED 00003H RESERVED GSR 00002H RESERVED BSR0 00001H RESERVED RESERVED 00000H 0533_04 NOTE: The upper 10 bits (A19-10) reflect 28F016XD addresses A9-0, latched by RAS#. The lower 10 bits (A9-0) reflect 28F016XD addresses A9-0, latched by CAS#. Figure 4. Extended Status Registers Memory Map 12 E 28F016XD FLASH MEMORY 4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS 4.1 Bus Operations Notes RP# RAS# CAS# OE# WE# DQ0-15 RY/BY# Row Address Latch Mode 1,2,9 VIH VIH X X X X Column Address Latch 1,2,9 VIH VIL X X X X Read 1,2,7 VIH VIL VIL VIL VIH DOUT X Output Disable 1,6,7 VIH VIL VIL VIH VIH High Z X Standby 1,6,7 VIH VIH VIH X X High Z X Deep Power-Down 1,3 VIL X X X X High Z VOH Manufacturer ID 4,8 VIH VIL VIL VIL VIH 0089H VOH Device ID 4,8 VIH VIL VIL VIL VIH 66A8H VOH 1,5,6 VIH VIL VIL X VIL DIN X Write NOTES: 1. X can be VIH or VIL for address or control pins except for RY/BY#, which is either VOL or VOH, or High Z or DOUT for data pins depending on whether or not OE# is active. 2. RY/BY# output is open drain. When the WSM is ready, erase is suspended or the device is in deep power-down mode, RY/BY# will be at VOH if it is tied to VCC through a resistor. RY/BY# at VOH is independent of OE# while a WSM operation is in progress. 3. RP# at GND 0.2V ensures the lowest deep power-down current. 4. A0 (latched by CAS#) at VIL provides the Manufacturer ID code. A0 (latched by CAS#) at VIH provides the Device ID code. All other addresses (row and column) should be set to zero. 5. Commands for erase, data program, or lock-block operations can only be completed successfully when VPP = VPPH1 or VPP = VPPH2. 6. While the WSM is running, RY/BY# stays at VOL until all operations are complete. RY/BY# goes to VOH when the WSM is not busy or in erase suspend mode. 7. RY/BY# may be at VOL while the WSM is busy performing various operations (for example, a Status Register read during a program operation). 8. The 28F016XD shares an identical device identifier with the 28F016XS. 9. Row (upper) addresses are latched via inputs A0-9 on the falling edge of RAS#. Column (lower) addresses are latched via inputs A0-9 on the falling edge of CAS#. Row addresses must be latched before column addresses are latched. 13 E 28F016XD FLASH MEMORY 4.2 28F008SA--Compatible Mode Command Bus Definitions First Bus Cycle Command Notes Read Array Second Bus Cycle Oper Addr Data(4) Oper Addr Data(4) Write X xxFFH Read AA AD Intelligent Identifier 1 Write X xx90H Read IA ID Read Compatible Status Register 2 Write X xx70H Read X CSRD Clear Status Register 3 Write X xx50H Word Program Write X xx40H Write PA PD Alternate Word Program Write X xx10H Write PA PD Block Erase/Confirm Write X xx20H Write BA xxD0H Erase Suspend/Resume Write X xxB0H Write X xxD0H ADDRESS AA = Array Address BA = Block Address IA = Identifier Address PA = Program Address X = Don't Care DATA AD = Array Data CSRD = CSR Data ID = Identifier Data PD = Program Data NOTES: 1. Following the Intelligent Identifier command, two read operations access the manufacturer and device signature codes. 2. The CSR is automatically available after device enters data program, erase, or suspend operations. 3. Clears CSR.3, CSR.4 and CSR.5. Also clears GSR.5 and all BSR.5, BSR.4 and BSR.2 bits. See Status Register definitions. 4. The upper byte of the data bus (D8-15) during command writes is a "Don't Care." 14 E 28F016XD FLASH MEMORY 4.3 28F016XD--Enhanced Command Bus Definitions First Bus Cycle Command Read Extended Status Register Oper Addr Data(3) Oper Addr Data(3) 1 Write X xx71H Read RA GSRD BSRD Write X xx77H Write BA xxD0H Write X xx97H Write X xxD0H Lock Block/Confirm Upload Status Bits/Confirm Second Bus Cycle Notes 2 ADDRESS DATA BA = Block Address AD = Array Data RA = Extended Register Address BSRD = BSR Data PA = Program Address GSRD = GSR Data X = Don't Care NOTES: 1. RA can be the GSR address or any BSR address. See Figure 4 for the Extended Status Register memory map. 2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the actual lock-bit status. 3. The upper byte of the data bus (D8-15) during command writes is a "Don't Care." 15 E 28F016XD FLASH MEMORY 4.4 Compatible Status Register WSMS ESS ES DWS VPPS R R R 7 6 5 4 3 2 1 0 NOTES: CSR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy RY/BY# output or WSMS bit must be checked to determine completion of an operation (erase, erase suspend, or data program) before the appropriate Status bit (ESS, ES or DWS) is checked for success. CSR.6 = ERASE-SUSPEND STATUS 1 = Erase Suspended 0 = Erase In Progress/Completed CSR.5 = ERASE STATUS 1 = Error In Block Erasure 0 = Successful Block Erase If DWS and ES are set to "1" during an erase attempt, an improper command sequence was entered. Clear the CSR and attempt the operation again. CSR.4 = DATA-WRITE STATUS 1 = Error in Data Program 0 = Data Program Successful CSR.3 = VPP STATUS 1 = VPP Error Detect, Operation Abort 0 = VPP OK The VPPS bit, unlike an A/D converter, does not provide continuous indication of VPP level. The WSM interrogates VPP's level only after the Data Program or Erase command sequences have been entered, and informs the system if V PP has not been switched on. VPPS is not guaranteed to report accurate feedback between VPPLK(max) and VPPH1(min), between VPPH1(max) and VPPH2(min) and above VPPH2(max). CSR.2-0 = RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use; mask them out when polling the CSR. 16 E 28F016XD FLASH MEMORY 4.5 Global Status Register WSMS OSS DOS R 7 6 5 4 GSR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy R R R R 3 2 1 0 NOTES: RY/BY# output or WSMS bit must be checked to determine completion of an operation (block lock, suspend, Upload Status Bits, erase or data program) before the appropriate Status bit (OSS or DOS) is checked for success. GSR.6 = OPERATION SUSPEND STATUS 1 = Operation Suspended 0 = Operation in Progress/Completed GSR.5 = DEVICE OPERATION STATUS 1 = Operation Unsuccessful 0 = Operation Successful or Currently Running GSR.4-0 = RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use; mask them out when polling the GSR. 17 E 28F016XD FLASH MEMORY 4.6 Block Status Register BS BLS BOS R 7 6 5 4 BSR.7 = BLOCK STATUS 1 = Ready 0 = Busy R VPPS VPPL R 3 2 1 0 NOTES: RY/BY# output or BS bit must be checked to determine completion of an operation (block lock, suspend, erase or data program) before the appropriate Status bits (BOS, BLS) is checked for success. BSR.6 = BLOCK LOCK STATUS 1 = Block Unlocked for Program/Erase 0 = Block Locked for Program/Erase BSR.5 = BLOCK OPERATION STATUS 1 = Operation Unsuccessful 0 = Operation Successful or Currently Running BSR.2 = VPP STATUS 1 = VPP Error Detect, Operation Abort 0 = VPP OK BSR.1 = VPP LEVEL 1 = VPP Detected at 5.0V 10% 0 = VPP Detected at 12.0V 5% BSR.1 is not guaranteed to report accurate feedback between the VPPH1 and VPPH2 voltage ranges. Programs and erases with VPP between VPPLK(max) and VPPH1 (min), between VPPH1(max) and VPPH2(min), and above VPPH2(max) produce spurious results and should not be attempted. BSR.1 was a RESERVED bit on the 28F016SA. BSR.4,3,0 = RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use; mask them out when polling the BSRs. 18 E 28F016XD FLASH MEMORY 5.0 ELECTRICAL SPECIFICATIONS NOTICE: This is a production datasheet. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. *WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. 5.1 Absolute Maximum Ratings* Temperature Under Bias ....................0C to +80C Storage Temperature ...................-65C to +125C VCC = 3.3V 0.3V Systems Sym Parameter Notes Min Max Units Test Conditions Ambient Temperature TA Operating Temperature, Commercial 1 0 70 C VCC VCC with Respect to GND 2 -0.2 7.0 V VPP VPP Supply Voltage with Respect to GND 2,3 -0.2 14.0 V V Voltage on any Pin (except VCC,VPP) with Respect to GND 2,5 -0.5 VCC + 0.5 V I Current into any Non-Supply Pin 5 30 mA IOUT Output Short Circuit Current 4 100 mA VCC = 5.0V 0.5V Systems Sym Parameter Notes Min Max Units Test Conditions Ambient Temperature TA Operating Temperature, Commercial 1 0 70 C VCC VCC with Respect to GND 2 -0.2 7.0 V VPP VPP Supply Voltage with Respect to GND 2,3 -0.2 14.0 V V Voltage on any Pin (except VCC,VPP) with Respect to GND 2,5 -2.0 7.0 V I Current into any Non-Supply Pin 5 30 mA IOUT Output Short Circuit Current 4 100 mA NOTES: 1. Operating temperature is for commercial product defined by this specification. 2. Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <20 ns. Maximum DC voltage on input/output pins is VCC + 0.5V which, during transitions, may overshoot to VCC + 2.0V for periods <20 ns. 3. Maximum DC voltage on VPP may overshoot to +14.0V for periods <20 ns. 4. Output shorted for no more than one second. No more than one output shorted at a time. 5. This specification also applies to pins marked "NC." 19 E 28F016XD FLASH MEMORY 5.2 Capacitance For a 3.3V 0.3V System: Sym Parameter Notes Typ Max Units Test Conditions CIN Capacitance Looking into an Address/Control Pin 1 6 8 pF TA = +25C, f = 1.0 MHz COUT Capacitance Looking into an Output Pin 1 8 12 pF TA = +25C, f = 1.0 MHz CLOAD Load Capacitance Driven by Outputs for Timing Specifications 50 pF 1,2 For 5.0V 0.5V System: Sym Parameter Notes Typ Max Units Test Conditions CIN Capacitance Looking into an Address/Control Pin 1 6 8 pF TA = +25C, f = 1.0 MHz COUT Capacitance Looking into an Output Pin 1 8 12 pF TA = +25C, f = 1.0 MHz CLOAD Load Capacitance Driven by Outputs for Timing Specifications 100 pF 1,2 NOTE: 1. Sampled, not 100% tested. 2. To obtain iBIS models for the 28F016XD, please contact your local Intel/Distribution Sales Office. 20 E 28F016XD FLASH MEMORY 5.3 Transient Input/Output Reference Waveforms 2.4 2.0 INPUT 2.0 OUTPUT TEST POINTS 0.8 0.45 0.8 0533_05 AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0." Input timing begins at VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns. Figure 5. Transient Input/Output Reference Waveform for VCC = 5.0V 0.5V(1) 3.0 INPUT 1.5 TEST POINTS 1.5 OUTPUT 0.0 0533_06 AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.5V. Input rise and fall times (10% to 90%) <10 ns. Figure 6. Transient Input/Output Reference Waveform for VCC = 3.3V 0.3V(2) NOTES: 1. Testing characteristics for 28F016XD-85. 2. Testing characteristics for 28F016XD-95. 21 E 28F016XD FLASH MEMORY 5.4 DC Characteristics VCC = 3.3V 0.3V, T A = 0C to +70C 3/5# = Pin Set High for 3.3V Operations Sym Parameter Notes Typ Max Unit Test Condition 1,4,5 50 70 mA VCC Standby Current 1,5 1 4 mA ICC3 VCC RAS#-Only Refresh Current 1,5 50 80 mA ICC4 VCC Fast Page Mode Word Read Current 1,4,5 40 70 mA ICC5 VCC Standby Current 1,5 70 130 A ICC6 VCC CAS#-beforeRAS# Refresh Current 1,5 40 15 mA ICC7 VCC Standby Current (Self Refresh Mode) 1,5 40 10 mA ILI Input Load Current 1 1 A ILO Output Leakage Current 1 10 A ICCD VCC Deep PowerDown Current 1 10 A VCC = VCC Max RAS#, CAS# = VIL RAS#, CAS#, Addr. Cycling @ tRC = min IOUT = 0 mA Inputs = TTL or CMOS VCC = VCC Max RAS#, CAS#, RP# = V IH WP#, 3/5# = VIL or VIH VCC = VCC Max CAS# = VIH RAS# = VIL RAS#, Addr. Cycling @ tRC = min Inputs = TTL or CMOS VCC = VCC Max RAS#, CAS# = VIL CAS#, Addr. Cycling @ tPC = min IOUT = 0 mA Inputs = VIL or VIH VCC = VCC Max RAS# CAS# RP# = VCC 0.2V WP#, 3/5# = VCC 0.2V or GND 0.2V VCC = VCC Max CAS#, RAS# = VIL CAS#, RAS#, Addr. Cycling @ tRC = min Inputs = TTL or CMOS VCC = VCC Max RAS#, CAS# = VIL IOUT = 0 mA Inputs = VIL or VIH VCC = VCC Max VIN = VCC or GND VCC = VCC Max VOUT = VCC or GND RP# = GND 0.2V ICC1 VCC Word Read Current ICC2 22 Min 2 E 28F016XD FLASH MEMORY 5.4 DC Characteristics (Continued) VCC = 3.3V 0.3V, T A = 0C to +70C 3/5# = Pin Set High for 3.3V Operations Sym Parameter Notes Min ICCW ICCE ICCES IPPS IPPD IPPW IPPE IPPES VCC Word Program Current VCC Block Erase Current VCC Erase Suspend Current VPP Standby/Read Current VPP Deep PowerDown Current VPP Word Program Current VPP Block Erase Current Typ Max Unit Test Condition 8 12 mA 8 17 mA 6 12 mA 9 17 mA 1,2 1 4 mA 1 1 10 A VPP = 12.0V 5% Program in Progress VPP = 5.0V 10% Program in Progress VPP = 12.0V 5% Block Erase in Progress VPP = 5.0V 10% Block Erase in Progress RAS#, CAS# = VIH Block Erase Suspended VPP VCC 1 30 0.2 200 5 A A VPP > VCC RP# = GND 0.2V 1,6 10 15 mA 15 25 mA 4 10 mA 14 20 mA 30 200 A VPP = 12.0V 5% Program in Progress VPP = 5.0V 10% Program in Progress VPP = 12.0V 5% Block Erase in Progress VPP = 5.0V 10% Block Erase in Progress Block Erase Suspended 0.8 VCC + 0.3 0.4 V V 1,6 1,6 1,6 1 VIL VIH VPP Erase Suspend Current Input Low Voltage Input High Voltage VOL Output Low Voltage 6 VOH1 Output High Voltage 6 2.4 V VOH2 6 V VPPLK 3,6 VCC0.2 0.0 3 4.5 3 11.4 VPP Erase/Program Lock Voltage VPPH1 VPP during Program/ Erase Operations VPPH2 VPP during Program/ Erase Operations VLKO VCC Erase/Program Lock Voltage 6 6 -0.3 2.0 2.0 V 1.5 V 5.0 5.5 V 12.0 12.6 V VCC = VCC Min IOL = 4.0 mA VCC = VCC Min IOH = -2.0 mA VCC = VCC Min IOH = -100 A V 23 28F016XD FLASH MEMORY E NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 3.3V, VPP = 12.0V or 5.0V, T = +25C. 2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of ICCES and ICC1/ICC4. 3. Block erases, word programs and lock block operations are inhibited when VPP = VPPLK and not guaranteed in the ranges between VPPLK(max) and VPPH1(min), between VPPH1(max) and VPPH2(min) , and above VPPH2(max). 4. Automatic Power Saving (APS) reduces ICC1 and ICC4 to 3.0 mA typical in static operation. 5. CMOS inputs are either VCC 0.2V or GND 0.2V. TTL inputs are either VIL or VIH. 6. Sampled, but not 100% tested. Guaranteed by design. 24 E 28F016XD FLASH MEMORY 5.5 DC Characteristics VCC = 5.0V 0.5V, T A = 0C to +70C 3/5# = Pin Set Low for 5.0V Operations Sym Parameter Notes Min Typ Max Unit 1,4,5 90 120 mA Test Condition ICC1 VCC Word Read Current ICC2 VCC Standby Current 1,5 2 4 mA ICC3 VCC RAS#-Only Refresh Current 1,5 90 145 mA ICC4 VCC Fast Page Mode Word Read Current 1,4,5 80 130 mA ICC5 VCC Standby Current 1,5 70 130 A ICC6 VCC CAS#-beforeRAS# Refresh Current 1,5 50 15 mA ICC7 VCC Standby Current (Self Refresh Mode) 1,5 50 10 mA ILI Input Load Current 1 1 A VCC = VCC Max VIN = VCC or GND ILO Output Leakage Current 1 10 A VCC = VCC Max VOUT = VCC or GND ICCD VCC Deep Power-Down Current 1 10 A RP# = GND 0.2V 2 VCC = VCC Max RAS#, CAS# = VIL RAS#, CAS#, Addr. Cycling @ tRC = min IOUT = 0 mA Inputs = TTL or CMOS VCC = VCC Max RAS#, CAS#, RP# = V IH WP#, 3/5# = VIL or VIH VCC = VCC Max CAS# = VIH RAS# = VIL RAS#, Addr. Cycling @ tRC = min Inputs = TTL or CMOS VCC = VCC Max RAS#, CAS# = VIL CAS#, Addr. Cycling @ tPC = min IOUT = 0 mA Inputs = VIL or VIH VCC = VCC Max RAS#,CAS#,RP# = VCC 0.2V WP#, 3/5# = VCC 0.2V or GND 0.2V VCC = VCC Max CAS#, RAS# = VIL CAS#, RAS#, Addr. Cycling @ tRC = min Inputs = TTL or CMOS VCC = VCC Max RAS#, CAS# = VIL IOUT = 0 mA Inputs = VIL or VIH 25 E 28F016XD FLASH MEMORY 5.5 DC Characteristics (Continued) VCC = 5.0V 0.5V, T A = 0C to +70C 3/5# = Pin Set Low for 5.0V Operations Sym ICCW ICCE ICCES IPPS Parameter VCC Word Program Current VCC Block Erase Current VCC Erase Suspend Current VPP Standby/Read Notes Min Typ Max Unit 25 35 mA 25 40 mA 18 25 mA 20 30 mA 1,2 2 4 mA 1 1 10 A 30 200 A VPP > VCC 1 0.2 5 A RP# = GND 0.2V 1,6 7 12 mA 17 22 mA 5 10 mA 16 20 mA 30 200 A VPP = 12.0V 5% Word Program in Progress VPP = 5.0V 10% Word Program in Progress VPP = 12.0V 5% Block Erase in Progress VPP = 5.0V 10% Block Erase in Progress Block Erase Suspended 1,6 1,6 Current IPPD IPPW IPPE VPP Deep Power-Down Current VPP Word Program Current VPP Block Erase Current 1,6 IPPES VPP Erase Susp.Current 1 VIL Input Low Voltage 6 -0.5 0.8 V VIH Input High Voltage 6 2.0 V VOL Output Low Voltage 6 VCC + 0.5 0.45 VOH1 Output High Voltage 6 0.85 VCC V 6 VCC- 0.4 V 3,6 0.0 3 4.5 3 11.4 VOH2 VPPLK VPP Erase/Program Lock Voltage VPPH1 VPP during Program/Erase Operations VPPH2 VPP during Program/Erase Operations VLKO VCC Erase/Program Lock Voltage 26 2.0 V 1.5 V 5.0 5.5 V 12.0 12.6 V V Test Condition VPP = 12.0V 5% Word Program in Progress VPP = 5.0V 10% Word Program in Progress VPP = 12.0V 5% Block Erase in Progress VPP = 5.0V 10% Block Erase in Progress RAS#, CAS# = VIH Block Erase Suspended VPP VCC VCC = VCC Min IOL = 5.8 mA VCC = VCC Min IOH = -2.5 mA VCC = VCC Min IOH = -100 A E 28F016XD FLASH MEMORY NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0V, VPP = 12.0V or 5.0V, T = +25C. These currents are specified for a CMOS rise/fall time (10% to 90%) of <5 ns and a TTL rise/fall time of <10 ns. 2. ICCES is specified with the device de-selected. If the device is read while in Erase Suspend mode, current draw is the sum of ICCES and ICC1/ICC4. 3. Block erases, word programs and lock block operations are inhibited when VPP = VPPLK and not guaranteed in the ranges between VPPLK(max) and VPPH1(min), between VPPH1(max) and VPPH2(min), and above VPPH2(max). 4. Automatic Power Saving (APS) reduces ICC1 and ICC4 to 1 mA typical in static operation. 5. CMOS inputs are either VCC 0.2V or GND 0.2V. TTL inputs are either VIL or VIH. 6. Sampled, not 100% tested. Guaranteed by design. 27 E 28F016XD FLASH MEMORY 5.6 AC Characteristics(11) VCC = 3.3V 0.3V, T A = 0C to +70C Read, Program, Read-Modify-Program and Refresh Cycles (Common Parameters) Versions Sym Parameter 28F016XD-95 Notes Min Units Max tRP RAS# precharge time 10 ns tCP CAS# precharge time 15 ns tASR Row address set-up time 9 0 ns tRAH Row address hold time 9 15 ns tASC Column address set-up time 9 0 ns tCAH Column address hold time 9 20 ns tAR Column address hold time referenced to RAS# 3,9 35 ns tRAD RAS# to column address delay time 8,9 15 tCRP CAS# to RAS# precharge time tOED OE# to data delay tDZO 15 ns 10 ns 10 30 ns OE# delay time from data-in 10 0 ns tDZC CAS# delay time from data-in 10 0 ns tT Transition time (rise and fall) 10 2 4 ns Read Cycle Versions Sym Parameter 28F016XD-95 Notes Min Units Max tRC(R) Random read cycle time 105 tRAS(R) RAS# pulse width (reads) 95 ns tCAS(R) CAS# pulse width (reads) 45 ns tRCD(R) RAS# to CAS# delay time (reads) 15 50 ns tRSH(R) RAS# hold time (reads) 30 ns tCSH(R) CAS# hold time (reads) 95 ns tRAC Access time from RAS# 1,8 95 ns tCAC Access time from CAS# 1,2 40 ns tAA Access time from column address 8 75 ns tOEA OE# access time 40 ns 28 1 ns E 28F016XD FLASH MEMORY Read Cycle (Continued) Versions Sym Parameter 28F016XD-95 Notes Min Units Max tROH RAS# hold time referenced to OE# 40 ns tRCS Read command setup time 5 ns tRCH Read command hold time referenced to CAS# 6,10 0 ns tRRH Read command hold time referenced to RAS# 6,10 0 ns tRAL Column address to RAS# lead time 9 15 ns tCAL Column address to CAS# lead time 9 75 ns tCLZ CAS# to output in Low-Z 0 ns tOH Output data hold time 0 ns tOHO Output data hold time from OE# 0 ns tOFF Output buffer turn-off delay tOEZ Output buffer turn off delay time from OE# tCDD CAS# to data-in delay time 4 30 ns 30 ns 30 ns Write Cycle Versions Sym Parameter 28F016XD-95 Notes Min Units Max tRC(W) Random write cycle time 90 tRAS(W) RAS# pulse width (writes) 80 ns tCAS(W) CAS# pulse width (writes) 65 ns tRCD(W) RAS# to CAS# delay time (writes) 15 15 ns tRSH(W) RAS# hold time (writes) 65 ns tCSH(W) CAS# hold time (writes) 80 ns tWCS Write command set-up time 0 ns tWCH Write command hold time 15 ns tWCR Write command hold time referenced to RAS# 30 ns tWP Write command pulse width 15 ns tRWL Write command to RAS# lead time 65 ns tCWL Write command to CAS# lead time 65 ns tDS Data-in set-up time 7,9 0 ns tDH Data-in hold time 7,9 15 ns tDHR Data-in hold time referenced to RAS# 3,9 30 ns 1 5 3 ns 29 E 28F016XD FLASH MEMORY Read-Modify-Write Cycle Versions Sym Parameter 28F016XD-95 Units Notes Min Max 10 200 ns tRWC Read-modify-write cycle time tRWD RAS# to WE# delay time 5,10 125 ns tCWD CAS# to WE# delay time 5,10 75 ns tAWD Column address to WE# delay time 5,9,10 105 ns tOEH OE# command hold time 10 15 ns Fast Page Mode Cycle Versions Sym Parameter 28F016XD-95 Notes Min Units Max tPC(R) Fast page mode cycle time (reads) 75 ns tPC(W) Fast page mode cycle time (writes) 80 ns tRASP(R) RAS# pulse width (reads) 95 ns tRASP(W) RAS# pulse width (writes) 80 ns tCPA Access time from CAS# precharge 85 ns tCPW WE# delay time from CAS# precharge tCPRH(R) tCPRH(W) 10 0 ns RAS# hold time from CAS# precharge (reads) 75 ns RAS# hold time from CAS# precharge (writes) 80 ns Fast Page Mode Read-Modify-Write Cycle Versions Sym tPRWC 30 Parameter Fast page mode read-modify-write cycle time 28F016XD-95 Notes Min 10 170 Units Max ns E 28F016XD FLASH MEMORY Refresh Cycle Versions Sym 28F016XD-95 Units Parameter Notes Min Max tCSR CAS# set-up time (CAS#-before-RAS# refresh) 10 10 ns tCHR CAS# hold time (CAS#-before-RAS# refresh) 10 10 ns tWRP WE# setup time (CAS#-before-RAS# refresh) 10 10 ns tWRH WE# hold time (CAS#-before-RAS# refresh) 10 10 ns tRPC RAS# precharge to CAS# hold time 10 10 ns tRASS RAS# pulse width (self-refresh mode) 10 0 ns tRPS RAS# precharge time (self-refresh mode) 10 10 ns tCPN CAS# precharge time (self-refresh mode) 10 10 ns tCHS CAS# hold time (self-refresh mode) 10 0 ns Refresh Versions Sym tREF Parameter Refresh period 28F016XD-95 Notes Min Max 10 Units ms Misc. Specifications Versions Parameter 28F016XD-95 Units Notes Min Max RP# high to RAS# going low 10 480 ns RP# set-up to WE# going low 10 480 ns VPP set-up to CAS# high at end of write cycle 10 100 ns WE# high to RY/BY# going low 10 RP# hold from valid status register data and RY/BY# high 10 0 ns VPP hold from valid status register data and RY/BY# high 10 0 ns 100 ns 31 28F016XD FLASH MEMORY NOTES: E 1. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point. 2. Assumes that tRCD tRCD(max). 3. tAR, tWCR, tDHR are referenced to tRAD(max). 4. tOFF(max) defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 5. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If tWCS tWCS(min) the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD tCWD(min), tRWD tRWD(min), tAWD tAWD(min), then the cycle is a read-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions are satisfied, the condition of the data out is indeterminate. 6. Either tRCH or tRRH must be satisfied for a read cycle. 7. These parameters are referenced to the CAS# leading edge in early write cycles and to the WE# leading edge in readwrite cycles. 8. Operation within the tRAD(max) limit ensures that tRAC(max) can be met, tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit, then the access time is controlled by tAA. 9. Refer to command definition tables for valid address and data values. 10. Sampled, but not 100% tested. Guaranteed by design. 11. See AC Input/Output Reference Waveforms for timing measurements. 32 E 28F016XD FLASH MEMORY 5.7 AC Characteristics(11) VCC = 5.0V 0.5V, T A = 0C to +70C Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) Versions Sym Parameter 28F016XD-85 Notes Min Units Max tRP RAS# precharge time 10 ns tCP CAS# precharge time 15 ns tASR Row address set-up time 9 0 ns tRAH Row address hold time 9 15 ns tASC Column address set-up time 9 0 ns tCAH Column address hold time 9 20 ns tAR Column address hold time referenced to RAS# 3,9 35 ns tRAD RAS# to column address delay time 8,9 15 tCRP CAS# to RAS# precharge time 10 ns tOED OE# to data delay 10 30 ns tDZO OE# delay time from data-in 10 0 ns tDZC CAS# delay time from data-in 10 0 ns tT Transition time (rise and fall) 10 2 15 4 ns ns 33 E 28F016XD FLASH MEMORY Read Cycle Versions Sym Parameter 28F016XD-85 Notes Min Units Max tRC(R) Random read cycle time 95 tRAS(R) RAS# pulse width (reads) 85 ns tCAS(R) CAS# pulse width (reads) 35 ns tRCD(R) RAS# to CAS# delay time (reads) 15 50 ns tRSH(R) RAS# hold time (reads) tCSH(R) CAS# hold time (reads) tRAC Access time from RAS# 1,8 85 ns tCAC Access time from CAS# 1,2 35 ns tAA Access time from column address 8 65 ns tOEA OE# access time 35 ns tROH RAS# hold time referenced to OE# 35 ns tRCS Read command setup time 5 ns tRCH Read command hold time referenced to CAS# 6,10 0 ns tRRH Read command hold time referenced to RAS# 6,10 0 ns tRAL Column address to RAS# lead time 9 15 ns tCAL Column address to CAS# lead time 9 65 ns tCLZ CAS# to output in Low-Z 10 0 ns tOH Output data hold time 10 0 ns tOHO Output data hold time from OE# 10 0 ns tOFF Output buffer turn-off delay 4,10 30 ns tOEZ Output buffer turn off delay time from OE# 10 30 ns tCDD CAS# to data-in delay time 10 34 1 ns 30 ns 85 30 ns ns E 28F016XD FLASH MEMORY Write Cycle Versions Sym Parameter 28F016XD-85 Notes Min Units Max tRC(W) Random write cycle time 75 tRAS(W) RAS# pulse width (writes) 65 ns tCAS(W) CAS# pulse width (writes) 50 ns tRCD(W) RAS# to CAS# delay time (writes) 15 15 ns tRSH(W) RAS# hold time (writes) tCSH(W) CAS# hold time (writes) tWCS Write command set-up time tWCH Write command hold time tWCR Write command hold time referenced to RAS# tWP 1 ns 50 ns 65 ns 0 ns 15 ns 30 ns Write command pulse width 15 ns tRWL Write command to RAS# lead time 50 ns tCWL Write command to CAS# lead time 50 ns tDS Data-in set-up time 7,9 0 ns tDH Data-in hold time 7,9 15 ns tDHR Data-in hold time referenced to RAS# 3,9 30 ns 5 3 Read-Modify-Write Cycle Versions Sym Parameter 28F016XD-85 Units Notes Min Max 10 175 ns tRWC Read-modify-write cycle time tRWD RAS# to WE# delay time 5,10 115 ns tCWD CAS# to WE# delay time 5,10 65 ns tAWD Column address to WE# delay time 5,9,10 100 ns tOEH OE# command hold time 10 15 ns Fast Page Mode Cycle Versions Sym Parameter 28F016XD-85 Notes Min Units Max tPC(R) Fast page mode cycle time (reads) 65 ns tPC(W) Fast page mode cycle time (writes) 65 ns 35 E 28F016XD FLASH MEMORY Fast Page Mode Cycle Continued Versions Sym Parameter 28F016XD-85 Notes Min Max Units tRASP(R) RAS# pulse width (reads) 85 ns tRASP(W) RAS# pulse width (writes) 65 ns tCPA Access time from CAS# precharge 70 ns tCPW WE# delay time from CAS# precharge tCPRH(R) tCPRH(W) 10 0 ns RAS# hold time from CAS# precharge (reads) 65 ns RAS# hold time from CAS# precharge (writes) 65 ns Fast Page Mode Read-Modify-Write Cycle Versions Sym tPRWC Parameter Fast page mode read-modify-write cycle time 28F016XD-85 Notes Min 10 145 Units Max ns Refresh Cycle Versions Sym 28F016XD-85 Units Parameter Notes Min tCSR CAS# set-up time (CAS#-before-RAS# refresh) 10 10 Max ns tCHR CAS# hold time (CAS#-before-RAS# refresh) 10 10 ns tWRP WE# setup time (CAS#-before-RAS# refresh) 10 10 ns tWRH WE# hold time (CAS#-before-RAS# refresh) 10 10 ns tRPC RAS# precharge to CAS# hold time 10 10 ns tRASS RAS# pulse width (self-refresh mode) 10 0 ns tRPS RAS# precharge time (self-refresh mode) 10 10 ns tCPN CAS# precharge time (self-refresh mode) 10 10 ns tCHS CAS# hold time (self-refresh mode) 10 0 ns Refresh Versions Sym tREF 36 Parameter Refresh period 28F016XD-85 Notes 10 Min Units Max ms E 28F016XD FLASH MEMORY Misc. Specifications Versions Parameter 28F016XD-85 Units Notes Min Max RP# high to RAS# going low 10 300 ns RP# set-up to WE# going low 10 300 ns VPP set-up to CAS# high at end of write cycle 10 100 ns WE# high to RY/BY# going low 10 RP# hold from valid status register data and RY/BY# high 10 0 ns VPP hold from valid status register data and RY/BY# high 10 0 ns 100 ns NOTES: 1. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point. 2. Assumes that tRCDtRCD(max). 3. tAR, tWCR, tDHR are referenced to tRAD(max). 4. tOFF(max) defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 5. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If tWCStWCS(min) the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWDtCWD(min), tRWDtRWD(min), tAWDtAWD(min), then the cycle is a read-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions are satisfied, the condition of the data out is indeterminate. 6. Either tRCH or tRRH must be satisfied for a read cycle. 7. These parameters are referenced to the CAS# leading edge in early write cycles and to the WE# leading edge in readwrite cycles. 8. Operation within the tRAD(max) limit ensures that tRAC(max) can be met, tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit, then the access time is controlled by tAA. 9. Refer to command definition tables for valid address and data values. 10. Sampled, but not 100% tested. Guaranteed by design. 11. See AC Input/Output Reference Waveforms for timing measurements. 37 E 28F016XD FLASH MEMORY 5.8 AC Waveforms t RC t RAS t RP RAS# t CSH t CRP t RCD t RSH t CAS tT CAS# t RAD t RAL t CAL t ASR Address t RAH t ASC Row t CAH Column t RRH t RCS WE# t RCH t DZC t CDD OPEN Din t DZO t OED t OEA OE# tAA t CAC t OEZ tOHO tOFF tOH t RAC Dout Dout : Don't Care 0533-07 Figure 7. AC Waveforms for Read Operations 38 E 28F016XD FLASH MEMORY t t RC t RAS RP RAS# t t t t CSH t RCD t T CRP RSH CAS CAS# t Address ASR t t RAH ASC Row t CAH Column t t WCS WCH WE# t Din t DS DH Din OPEN Dout OE# : Don't Care : Don't Care t _ t WCS (min) 0528_08 WCS > Figure 8. AC Waveforms for Early Write Operations 39 E 28F016XD FLASH MEMORY t t RC t RAS RP RAS# t t t t CSH t RCD t T CRP RSH CAS CAS# t Address ASR t t RAH ASC Row t CAH Column t t RCS CWL t t WE# t t DZC t DZO OE# Dout DS DH Din t QED t t WP t OPEN Din RWL t QEH QEZ CLZ Invalid Dout : Don't Care 0533_09 Figure 9. AC Waveforms for Delayed Write Operations 40 E 28F016XD FLASH MEMORY t RWC t t RAS RP RAS# t t t RCD t CAS CRP T CAS# t t Address ASR t RAD t RAH t ASC Row CAH Column t t RCS t t t CWD AWD RWD CWL t RWL t WP WE# t DZC t t DS OPEN Din Din t OED t DZO DH t OEH t OEA OE# t t AA t RAC Dout t CAC t OEZ OHO Dout t CLZ : Don't Care 0533_10 Figure 10. AC Waveforms for Read-Modify-Write Operations 41 E 28F016XD FLASH MEMORY t RASP t t CPRH RP RAS# tT t t t CSH t RCD t CAS t PC t CP t CAS RSH t CP t CRP CAS CAS# t t t t ASR t RAD t RAH t CAL ASC t t CAH CAL ASC t RAL t t ASC CAH t CAL CAH Address Row Column 2 Column 1 t t RCS t RCH Column N t RRH RCH t RCH WE# t t DCZ t t CDD DCZ t CDD t t DZO t t OED DZO t CDD OPEN OPEN OPEN Din t DCZ t OED QED DZO OE# t t RAC t t t Dout t OH t AA OEA t CAC CLZ CPA t AA t OHO t OEZ Dout 1 t t OH t t OFF CLZ OEA t CAC OEZ Dout 2 t CPA t AA t OEA t OHO t CAC t OFF t CLZ t t OHO t t OH OFF QEZ Dout N : Don't Care 0533_11 Figure 11. AC Waveforms for Fast Page Mode Read Operations 42 E 28F016XD FLASH MEMORY t t RASP RP RAS# t T t t t CSH t RCD CAS t t PC t CP CAS t RSH t CP CAS t RP CAS# t Address ASR t RAH t Row ASC t t CAH Column 1 t WCS t ASC t t CAH Column 2 WCH t WCS t WCH ASC t CAH Column N t WCS t WCH WE# t Din DS t t DH DS t DH Din 2 Din 1 t DS t DH Din N OPEN Dout OE# : Don't Care : Don't Care t t WCS >= WCS (min) 0533_12 Figure 12. AC Waveforms for Fast Page Mode Early Write Operations 43 E 28F016XD FLASH MEMORY t RASP t RP RAS# t t T t t CP CSH t RCD t t CP t PC t CAS t CAS RSH CAS CAS# t t t t Address RAD ASR t RAH Row t ASC ASC t CAH Column 1 t t t ASC t CAH CAH Column 2 t CWL t RCS Column N t CWL t RCS CWL t RCS RWL WE# t t t DZC t WP t DS t DH t DZC t t DZC t t DS Din N Din 2 t DZO t OED WP DH DH DZO t t DS Din 1 Din t WP OED OEH DZO t t OED OEH t OEH OE# t t CLZ t t CLZ t OEZ CLZ t OEZ OEZ Dout : Don't Care Invalid Dout Invalid Dout Invalid Dout 0533_13 Figure 13. AC Waveforms for Fast Page Mode Delayed Write Operations 44 E 28F016XD FLASH MEMORY t RASP t RP RAS# t t T t t t RCD PRWC t t CP t CAS CRP CP t CAS CAS CAS# t t t Address RAD t ASR t ASC t RAH t CAH RWD CWL AWD t t CWD t t Column N t t RCS t t CWL t CWD WP CAH t CPW AWD CWL t RWL CWD RCS t WP WP RCS t DZC t t DZC DS t DH t DS t DH Din 2 Din t t t CPW t AWD WE# t t ASC CAH Column 2 t t t t Column 1 Row t ASC t DZO t t t DS t DH Din N Din 2 t DZO DZO t OED t DZC OEH t OEA t OED t CPA t OED t OEH t OEA OEH OEA OE# t t CAC t AA t t CLZ OHO t t t CAC t AA t CLZ OHOt t OEZ CAC t AA t OHO CLZ t OEZ OEZ Dout : Don't Care Dout 1 Dout 2 Dout 3 0533_14 Figure 14. AC Waveforms for Fast Page Mode Read-Modify-Write Operations 45 E 28F016XD FLASH MEMORY t t RC t RAS RP RAS# t T t t RPC CRP CAS# t Address ASR t RAH ROW t OFF OPEN Dout OE#,WE# : Don't Care : Don't Care 0533_15 Figure 15. AC Waveforms for RAS#-Only Refresh Operations 46 E 28F016XD FLASH MEMORY t t t RP t RC t RAS t RP RAS RC t RP RAS# t t T t RPC t CP t CSR t t CHR t RPC t CP t CSR CRP CHR CAS# t t WRH t WRP t WRP WRH WE# Address t Dout OFF OPEN OE#: Don't Care : Don't Care 0533_16 Figure 16. AC Waveforms for CAS#-before-RAS# Refresh Operations 47 E 28F016XD FLASH MEMORY t t t RC t RAS RP t t RC RAS t RP t RC RAS t RP RAS# t T t t t RSH CHR t CRP RCD CAS# t t ASR t Address t RAD RAH t t ASC RAL CAH Column Row t t RCS RRH t RCH WE# t t DZC CDD Din t t DZO t QED OEA OE# t CAC t t RAC t Dout t AA t CLZ OFF t QEZ t OHO OH Dout : Don't Care 0533_17 Figure 17. AC Waveforms for Hidden Refresh Operations 48 E 28F016XD FLASH MEMORY t RAS# t t RASS RPS RPC t CPN t t CSR CHS CAS# t OFF HI-Z On 0533_18 Figure 18. AC Waveforms for Self-Refresh Operations 49 E 28F016XD FLASH MEMORY 5.9 Power-Up and Reset Timings VCC POWER-UP RP# (P) t YHPH t YLPH 3/5# 5.0V (Y) t PLYL 4.5V 3.3V VCC 0V (3V,5V) t PL5V 0533_19 Figure 19. VCC Power-Up and RP# Reset Waveforms Symbol tPLYL Parameter Notes Min Max Units RP# Low to 3/5# Low (High) 0 s 3/5# Low (High) to RP# High 0 s 0 s tPLYH tYLPH tYHPH tPL5V tPL3V RP# Low to VCC at 4.5V (Minimum) RP# Low to VCC at 3.0V (Min) or 3.6V (Max) 2 NOTES: For Read Timings following Reset, see sections 5.6 and 5.7. 1. The tYLPH and/or tYHPH times must be strictly followed to guarantee all other read and write specifications for the 28F016XD 2. The power supply may start to switch concurrently with RP# going low. 50 E 28F016XD FLASH MEMORY 5.10 Erase and Word Program Performance(3,4) VCC = 3.3V 0.3V, V PP = 5.0V 0.5V, T A = 0C to +70C Symbol Parameter Notes Min Typ(1) Max Units tWHRH1 Word Program Time 2,5 TBD 35.0 TBD s tWHRH3 Block Program Time 2,5 TBD 1.2 TBD sec Block Erase Time 2,5 TBD 1.4 TBD sec 1.0 12.0 75.0 s Notes Min Typ(1) Max Units 9 TBD s Erase Suspend Latency Time to Read VCC = 3.3V 0.3V, V PP = 12.0V 0.6V, T A = 0C to +70C Symbol Parameter tWHRH1 Word Program Time 2,5 5 tWHRH3 Block Program Time 2,5 TBD 0.3 1.0 sec 2 0.3 0.8 10 sec 1.0 9.0 55.0 s Notes Min Typ(1) Max Units Block Erase Time Erase Suspend Latency Time to Read VCC = 5.0V 0.5V, V PP = 5.0V 0.5V, T A = 0C to +70C Symbol Parameter tWHRH1 Word Program Time 2,5 TBD 25.0 TBD s tWHRH3 Block Program Time 2,5 TBD 0.85 TBD sec Block Erase Time 2,5 TBD 1.0 TBD sec 1.0 9.0 55.0 s Min Typ(1) Max Units Erase Suspend Latency Time to Read VCC = 5.0V 0.5V, V PP = 12.0V 0.6V, T A = 0C to +70C Symbol Parameter Notes tWHRH1 Word Program Time 2,5 4.5 6 TBD s tWHRH3 Block Program Time 2,5 TBD 0.2 1.0 sec 2 0.3 0.6 10 sec 1.0 7.0 40.0 s Block Erase Time Erase Suspend Latency Time to Read NOTES: 1. +25C, and nominal voltages. 2. Excludes system-level overhead. 3. These performance numbers are valid for all speed versions. 4. Sampled, but not 100% tested. Guaranteed by design. 5. Please contact Intel's Application Hotline or your local sales office for more information for current TBD information. 51 E 28F016XD FLASH MEMORY 6.0 MECHANICAL SPECIFICATIONS 048928.eps Figure 20. Mechanical Specifications of the 28F016XD 56-Lead TSOP Type I Package Family: Thin Small Out-Line Package Symbol Millimeters Minimum Nominal A A1 Maximum 1.20 0.050 A2 0.965 0.995 1.025 b 0.100 0.150 0.200 c 0.115 0.125 0.135 D1 E 18.20 18.40 18.60 13.80 14.00 14.20 e 0.50 D 19.80 20.00 20.20 L 0.500 0.600 0.700 N 56 0 3 Y Z 52 Notes 5 0.100 0.150 0.250 0.350 E 28F016XD FLASH MEMORY APPENDIX A DEVICE NOMENCLATURE AND ORDERING INFORMATION Product line designator for all Intel Flash products E 2 8 F 0 1 6 XD - 8 5 Random Access Time (tRAC) at 5V VCC ns) Package E = TSOP Device Density 016 = 16 Mbit Device Type D = DRAM-Interface Product Family X = Fast Flash 0533_21 Valid Combinations Order Code VCC = 3.3V 0.3V, 50 pF load, 1.5V I/O Levels(1) VCC = 5.0V 10%, 100 pF load, TTL I/O Levels(1) E28F016XD 85 E28F016XD-95 E28F016XD-85 NOTE: 1. See Section 5.3 for Transient Input/Output Reference Waveforms. 53 28F016XD FLASH MEMORY APPENDIX B ADDITIONAL INFORMATION(1,2) Order Number E Document/Tool 297372 16-Mbit Flash Product Family User's Manual 292092 AP-357 Power Supply Solutions for Flash Memory 292123 AP-374 Flash Memory Write Protection Techniques 292126 AP-377 16-Mbit Flash Product Family Software Drivers, 28F016SA/SV/XD/XS 292131 AP-384 Designing with the 28F016XD 292163 AP-610 Flash Memory In-System Code and Data Update Techniques 292168 AP-614 Adapting DRAM Based Designs for the 28F016XD 292152 AB-58 28F016XD-Based SIMM Designs 292165 AB-62 Compiled Code Optimizations for Flash Memories 294016 ER-33 ETOXTM Flash Memory Technology--Insight to Intel's Fourth Generation Process Innovation 297508 FLASHBuilder Utility Contact Intel/Distribution Sales Office 28F016XD Benchmark Utility Contact Intel/Distribution Sales Office Flash Cycling Utility Contact Intel/Distribution Sales Office 28F016XD iBIS Models Contact Intel/Distribution Sales Office 28F016XD VHDL/Verilog Models Contact Intel/Distribution Sales Office 28F016XD TimingDesigner* Library Files Contact Intel/Distribution Sales Office 28F016XD Orcad and ViewLogic Schematic Symbols NOTE: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel's World Wide Web home page at http://www.Intel.com for technical documentation and tools. 54