DATA SH EET
Product specification
Supersedes data of 1998 Mar 17 2002 Oct 02
INTEGRATED CIRCUITS
74LVC16373A; 74LVCH16373A
16-bit D-type transparent latch with
5 V tolerant inputs/outputs (3-state)
2002 Oct 02 2
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state) 74LVC16373A;
74LVCH16373A
FEATURES
•5 V tolerant inputs/outputs for interfacing with 5V logic
•Wide supply voltage range from 1.2 to 3.6 V
•Complies with JEDEC standard no. 8-1A
•CMOS low power consumption
•MULTIBYTETM flow-through standard pin-out
architecture
•Low inductance multiple power and ground pins for
minimum noise and ground bounce
•Direct interface with TTL levels
•All data inputs have bus hold (74LVCH16373A only)
•High-impedance when VCC =0V.
DESCRIPTION
The 74LVC(H)16373A is a 16-bit D-type transparent latch
featuring separate D-type inputs for each latch and 3-state
outputs for bus oriented applications. One Latch Enable
(LE) input and one Output Enable (OE) are provided for
each octal. Inputs can be driven from either 3.3 or 5 V
devices. In 3-state operation, outputs can handle 5 V.
These features allow the use of these devices in a mixed
3.3 and 5 V environment.
The 74LVC(H)16373A consists of 2 sections of eight
D-typetransparentlatcheswith3-statetrueoutputs.When
LE is HIGH, data at the Dn inputs enter the latches. In this
condition the latches are transparent, i.e., a latch output
will change each time its corresponding D-input changes.
WhenLEisLOWthelatches storetheinformationthat was
present at the D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the eight latches are available at the outputs.
When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the
state of the latches.
The 74LVCH16373A bus hold data inputs eliminates the
need for external pull up resistors to hold unused inputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr=t
f≤2.5 ns
Note
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD=C
PD ×VCC2×fi+Σ(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacity in pF;
VCC = supply voltage in Volts;
Σ(CL×VCC2×fo) = sum of the outputs.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
tPHL/tPLH propagation delay: CL= 50 pF; VCC = 3.3 V
Dn to Qn 3.0 ns
LE to Qn 3.4 ns
CIinput capacitance 5.0 pF
CPD power dissipation per latch VCC = 3.3 V; note 1 26 pF
2002 Oct 02 3
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state) 74LVC16373A;
74LVCH16373A
ORDERING INFORMATION
TYPE NUMBER TEMPERATURE RANGE PACKAGE
PINS PACKAGE MATERIAL CODE
74LVC16373ADL −40 to +85 °C 48 TSSOP-48 plastic SOT370-1
74LVC16373ADGG −40 to +85 °C 48 TSSOP-48 plastic SOT362-1
74LVCH16373ADL −40 to +85 °C 48 TSSOP-48 plastic SOT370-1
74LVCH16373ADGG −40 to +85 °C 48 TSSOP-48 plastic SOT362-1
PINNING
PIN SYMBOL DESCRIPTION
11
OE output enable input (active
LOW)
2, 3, 5, 6, 8,
9, 11, 12 1Q0 to 1Q7 data inputs/outputs
4, 10, 15,
21, 28, 34,
39, 45
GND ground (0 V)
7, 18, 31,
42 VCC supply voltage
13, 14, 16,
17, 19, 20,
22, 23
2Q0 to 2Q7 data inputs/outputs
24 2OE output enable input
(active LOW)
25 2LE latch enable input
(active HIGH)
36, 35, 33,
32, 30, 29,
27, 26
2D0 to 2D7 data inputs
47, 46, 44,
43, 41, 40,
38, 37
1D0 to 1D7 data inputs
48 1LE latch enable input (active
HIGH)
handbook, halfpage
MGU767
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
26
25
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
1Q0
1Q1
GND
1Q2
1Q3
VCC
1Q4
1Q5
GND
1Q6
1Q7
2Q0
2Q1
GND
2Q2
2Q3
VCC
2Q4
2Q5
GND
2Q6
2Q7
2OE
1D0
1D1
GND
1D2
1D3
VCC
1D4
1D5
GND
1D6
1D7
2D0
2D1
GND
2D2
2D3
VCC
2D4
2D5
GND
2D6
2D7
2LE
1OE 1LE
Fig.1 Pin configuration.
2002 Oct 02 4
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state) 74LVC16373A;
74LVCH16373A
handbook, full pagewidth
MGU769
2LE
D
LATCH
9
Q
2OE
to 7 other channels
LE LE
2Q02D0
1LE
D
LATCH
1
Q
1OE
to 7 other channels
LE LE
1Q01D0
Fig.2 Logic diagram.
handbook, halfpage
MGU768
1Q0
1Q1
1LE 2LE
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1OE
47
46
48 25
44
43
41
40
38
37
2
3
1
5
6
8
9
11
12
24
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
36
35
33
32
30
29
27
26
13
14
16
17
19
20
22
23
2OE
Fig.3 Logic symbol.
handbook, halfpage
23
MGU770
37 12
11
9
8
6
5
47
46
44
43
41
40
38
1D7
1D0
1D1
1D2
1D3
1D4
1D5
1D6
2
3
1Q7
1Q6
1Q5
1Q4
1Q3
1Q2
1Q0
1Q1
26
22
20
19
17
16
36
35
33
32
30
29
27
2D5
2D0
2D1
2D2
2D3
2D4
13
14
2Q5
2Q4
2Q3
2Q2
2Q1
2Q0
24
25 2EN
1OE 11EN
1LE
2OE
2LE
48 C3
C4
3D 1
4D 2
2D7
2D6
2Q7
2Q6
Fig.4 Logic symbol (IEEE/IEC).
2002 Oct 02 5
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state) 74LVC16373A;
74LVCH16373A
handbook, halfpage
to internal circuit
MGU771
VCC
data input
Fig.5 Bus hold circuit.
FUNCTION TABLE
Per section of eight bits; note 1
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
OPERATING MODES INPUT INTERNAL
LATCHES OUTPUTS
Q0 TO Q7
OE LE Dn
Enable and read register (transparent mode) L H L L L
LHHHH
Latch and read register L L l L L
LLhHH
Latch register and disable outputs H L l L Z
HLhHZ
2002 Oct 02 6
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state) 74LVC16373A;
74LVCH16373A
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V);
note 1.
Notes
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “Recommended
operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage for maximum speed performance 2.7 3.6 V
for low voltage applications 1.2 3.6 V
VIinput voltage 0 5.5 V
VOoutput voltage output HIGH or LOW state 0 VCC V
output 3-state 0 5.5 V
Tamb operating ambient
temperature in free-air −40 +85 °C
tr,t
finput rise and fall times VCC = 1.2 to 2.7 V 0 20 ns/V
VCC = 2.7 to 3.6 V 0 10 ns/V
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VCC supply voltage −0.5 −+6.5 V
IIK input diode current VI<0 −−50 −V
VIinput voltage note 2 −0.5 −+6.5 V
IOK output diode current VO>V
CC or VO<0 −±50 −V
VOoutput voltage output HIGHor LOW state;
note 2 −0.5 −VCC + 0.5 V
output 3-state; note 2 −0.5 −+6.5 V
IOoutput source or sink current VO= 0 to VCC −±50 −mA
ICC, IGND VCC or GND current −±100 −mA
Tstg storage temperature −65 −+150 °C
Ptot power dissipation per package
SO above 70 °C derates
linearly with 8 mW/K −500 −mW
SSOP and TSSOP above 60 °C derates
linearly with 8 mW/K −500 −mW
2002 Oct 02 7
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state) 74LVC16373A;
74LVCH16373A
DC CHARACTERISTICS
Over recommended operating conditions; voltages are referenced to GND (ground=0V).
Notes
1. All typical values are measured at VCC = 3.3 V and Tamb =25°C.
2. For bus hold parts, the bus hold circuit is switched off when VI>V
CC allowing 5.5 V on the input terminal.
3. Valid for data inputs of bus hold parts (LVCH16373A) only.
4. The specified sustaining current at the data input holds the input below the specified VI level.
5. The specified overdrive current at the data input forces the data input to the opposite logic input state.
SYMBOL PARAMETER
TEST CONDITIONS Tamb (°C)
UNIT
OTHER VCC (V) −40 to +85
MIN. TYP.(1) MAX.
VIH HIGH-level input voltage 1.2 VCC −−V
2.7 to 3.6 2.0 −−V
V
IL LOW-level input voltage 1.2 −−GND V
2.7 to 3.6 −−0.8 V
VOH HIGH-level output
voltage VI=V
IH or VIL; IO=−12 mA 2.7 VCC −0.5 −−V
V
I
=V
IH or VIL; IO=−100 µA 3.0 VCC −0.2 VCC −V
VI=V
IH or VIL; IO=−18 mA 3.0 VCC −0.6 −−V
V
I
=V
IH or VIL; IO=−24 mA 3.0 VCC −0.8 −−V
V
OL LOW-level output voltage VI=V
IH or VIL; IO= 12 mA 2.7 −−0.40 V
VI=V
IH or VIL; IO= 100 µA 3.0 −−0.20 V
VI=V
IH or VIL; IO= 24 mA 3.0 −−0.55 V
ILI input leakage current VI= 5.5 V or GND; note 2 3.6 −±0.1 ±5µA
IOZ 3-state output OFF-state
current VI=V
IH or VIL;
VO= 5.5 Vor GND 3.6 −0.1 ±5µA
Ioff power off leakage current Vior VO= 5.5 V 0 −−±10 µA
ICC quiescent supply current VI=V
CC or GND; IO= 0 3.6 −0.1 20 µA
∆ICC additional quiescent
supply current per input
pin
VI=V
CC −0.6 V; IO= 0 2.7 to 3.6 −5 500 µA
IBHL bus hold LOW sustaining
current VI= 0.8 V; notes 3 and 4 3.0 75 −−µA
I
BHH busholdHIGHsustaining
current VI= 2.0 V; notes 3 and 4 3.0 −75 −−µA
I
BHLO bus hold LOW overdrive
current notes 3 and 5 3.6 500 −−µA
I
BHHO bus hold HIGH overdrive
current notes 3 and 5 3.6 −500 −−µA
2002 Oct 02 8
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state) 74LVC16373A;
74LVCH16373A
AC CHARACTERISTICS
GND = 0 V; tr=t
f= 2.5 ns; CL= 50 pF; RL= 500 Ω.
Note
1. Typical values are measured at VCC = 3.3 V and Tamb =25°C.
SYMBOL PARAMETER WAVEFORMS
Tamb (°C)
UNIT−40 to +85
MIN. TYP. MAX.
VCC = 1.2 V
tPHL/tPLH propagation delay Dn to Qn see Figs 6 and 10 −12 −ns
tPHL/tPLH propagation delay LE to Qn see Figs 7 and 10 −14 −ns
tPZH/tPZL 3-state output enable time OE to Qn see Figs 9 and 10 −18 −ns
tPHZ/tPLZ 3-state output enable time OE to Qn see Figs 9 and 10 −11 −ns
tWLE pulse width HIGH see Fig.7 −−−ns
tsu set-up time Dn to LE see Fig.8 −−−ns
thhold time Dn to LE see Fig.8 −−−ns
VCC = 2.7 V
tPHL/tPLH propagation delay Dn to Qn see Figs 6 and 10 1.5 −5.7 ns
tPHL/tPLH propagation delay LE to Qn see Figs 7 and 10 1.5 −5.8 ns
tPZH/tPZL 3-state output enable time OE to Qn see Figs 9 and 10 1.5 −6.5 ns
tPHZ/tPLZ 3-state output enable time OE to Qn see Figs 9 and 10 1.5 −6.4 ns
tWLE pulse width HIGH see Fig.7 3 −−ns
tsu set-up time Dn to LE see Fig.8 1.7 −−ns
thhold time Dn to LE see Fig.8 1.2 −−ns
VCC = 3.3 ±0.3 V; note1
tPHL/tPLH propagation delay Dn to Qn see Figs 6 and 10 1.5 3.0 4.7 ns
tPHL/tPLH propagation delay LE to Qn see Figs 7 and 10 1.5 3.4 4.8 ns
tPZH/tPZL 3-state output enable time OE to Qn see Figs 9 and 10 1.5 3.5 5.5 ns
tPHZ/tPLZ 3-state output enable time OE to Qn see Figs 9 and 10 1.5 3.9 5.4 ns
tWLE pulse width HIGH see Fig.7 3 2.0 −ns
tsu set-up time Dn to LE see Fig.8 +1.7 −0.1 −ns
thhold time Dn to LE see Fig.8 1.2 0.1 −ns
2002 Oct 02 9
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state) 74LVC16373A;
74LVCH16373A
AC WAVEFORMS
handbook, halfpage
MGU772
Dn input
Qn output
tPHL tPLH
GND
VI
VM
VMVM
VOH
VOL
Fig.6 Input (Dn) to output (Qn) propagation delays.
VM= 1.5 V at VCC ≥2.7 V.
VM= 0.5VCC at VCC < 2.7 V.
VOL and VOH are the typical output voltage drop that occur with the output load.
handbook, halfpage
MGU773
LE input
Qn output
tPHL tPLH
tW
VMVM
VOH
VI
GND
VOL
VMVMVM
Fig.7 Latch enable input (LE) pulse width, and the latch enable input to output (Qn) propagation delays.
VM= 1.5 V at VCC ≥2.7 V.
VM= 0.5VCC at VCC < 2.7 V.
VOL and VOH are the typical output voltage drop that occur with the output load.
2002 Oct 02 10
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state) 74LVC16373A;
74LVCH16373A
handbook, full pagewidth
MGU774
thth
tsu
tsu
VM
VM
VI
GND
VI
GND
LE input
Dn input
Fig.8 Data set-up and hold times for the Dn input to the LE input.
VM= 1.5 V at VCC ≥2.7 V.
VM= 0.5VCC at VCC < 2.7 V.
VOL and VOH are the typical output voltage drop that occur with the output load.
The shaded areas indicate when the input is permitted to change for predictable performance.
handbook, full pagewidth
MGU775
tPLZ
tPHZ
outputs
disabled outputs
enabled
VY
VX
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
OE input
VI
VOL
VOH
VCC
VMVM
GND
GND
tPZL
tPZH
VM
VM
Fig.9 3-state enable and disable times.
VM= 1.5 V at VCC ≥2.7 V.
VM= 0.5VCC at VCC < 2.7 V.
VX=V
OL + 0.3 V at VCC ≥2.7 V.
VX=V
OL + 0.1VCC at VCC < 2.7 V.
VY=V
OH −0.3 V at VCC ≥2.7 V.
VY=V
OH −0.1VCC at VCC < 2.7 V. VOL and VOH are the typical output voltage drop that occur with the output load.
2002 Oct 02 11
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state) 74LVC16373A;
74LVCH16373A
handbook, full pagewidth
open
GND
2 × VCC
VCC
VIN VOUT
MGU776
D.U.T.
CL
RT
RL
500 Ω
RL
500 Ω
PULSE
GENERATOR
S1
Fig.10 Load circuitry for switching times.
TEST S1
tPLH/tPHL open
tPLZ/tPZL 2xV
CC
tPHZ/tPZH GND
VCC VI
<2.7 V VCC
2.7 to 3.6 2.7 V
Definitions for test circuits:
RL= Load resistor.
CL= Load capacitance including jig and probe capacitance.
RT= Termination resistance should be equal to the output impedance Zo of the pulse generator.
2002 Oct 02 12
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state) 74LVC16373A;
74LVCH16373A
PACKAGE OUTLINES
UNIT A
1
A
2
A
3
b
p
cD
(1)
E
(1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm 0.4
0.2 2.35
2.20 0.25 0.3
0.2 0.22
0.13 16.00
15.75 7.6
7.4 0.635 1.4 0.25
10.4
10.1 1.0
0.6 1.2
1.0 0.85
0.40 8
0
o
o
0.18 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT370-1 95-02-04
99-12-27
(1)
w
M
b
p
D
H
E
E
Z
e
c
v
M
A
X
A
y
48 25
MO-118
24
1
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
pin 1 index
0 5 10 mm
scale
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1
A
max.
2.8
2002 Oct 02 13
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state) 74LVC16373A;
74LVCH16373A
UNIT A1A2A3bpcD
(1) E(2) eH
ELL
pQZywvθ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm 0.15
0.05 0.2
0.1 8
0
o
o
0.1
DIMENSIONS (mm are the original dimensions).
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
SOT362-1 95-02-10
99-12-27
wM
θ
A
A1
A2
D
Lp
Q
detail X
E
Z
e
c
L
X
(A )
3
0.25
124
48 25
y
pin 1 index
b
H
1.05
0.85 0.28
0.17 0.2
0.1 12.6
12.4 6.2
6.0 0.5 1 0.25
8.3
7.9 0.50
0.35 0.8
0.4
0.08
0.8
0.4
p
EvMA
A
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1
A
max.
1.2
0
2.5
5 mm
scale
MO-153
2002 Oct 02 14
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state) 74LVC16373A;
74LVCH16373A
SOLDERING
Introduction to soldering surface mount packages
Thistextgivesa very briefinsighttoacomplextechnology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certainsurfacemount ICs,butitisnot suitable forfinepitch
SMDs. In these situations reflow soldering is
recommended.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
totheprinted-circuitboardby screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
Wave soldering
Conventional single wave soldering is not recommended
forsurfacemount devices(SMDs)orprinted-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
•Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
•For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
•Forpackageswith leadsonfoursides,the footprint must
be placed at a 45°angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2002 Oct 02 15
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state) 74LVC16373A;
74LVCH16373A
Suitability of surface mount IC packages for wave and reflow soldering methods
Notes
1. FormoredetailedinformationontheBGApackagesrefer to the
“(LF)BGAApplicationNote
”(AN01026);orderacopy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
PACKAGE(1) SOLDERING METHOD
WAVE REFLOW(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable
HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN,
HVSON, SMS not suitable(3) suitable
PLCC(4), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(4)(5) suitable
SSOP, TSSOP, VSO not recommended(6) suitable
2002 Oct 02 16
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state) 74LVC16373A;
74LVCH16373A
DATA SHEET STATUS
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For datasheets describing multiple type numbers, the highest-level product status determines the data sheet status.
LEVEL DATA SHEET
STATUS(1) PRODUCT
STATUS(2)(3) DEFINITION
I Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
DEFINITIONS
Short-form specification The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseoratanyother conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentation orwarrantythatsuch applicationswillbe
suitable for the specified use without further testing or
modification.
DISCLAIMERS
Life support applications These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductorscustomers usingorsellingtheseproducts
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
2002 Oct 02 17
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state) 74LVC16373A;
74LVCH16373A
NOTES
2002 Oct 02 18
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state) 74LVC16373A;
74LVCH16373A
NOTES
2002 Oct 02 19
Philips Semiconductors Product specification
16-bit D-type transparent latch with 5 V
tolerant inputs/outputs (3-state) 74LVC16373A;
74LVCH16373A
NOTES
© Koninklijke Philips Electronics N.V. 2002 SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Philips Semiconductors – a worldwide compan y
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Printed in The Netherlands 613508/05/pp20 Date of release: 2002 Oct 02 Document order number: 9397 750 10037
