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P/N:PM1097 REV. 1.3, NOV. 07, 2006
FEATURES
• Word organization
- (16,777,216 + 1,048,576Note) by 8 bits
• P age size
- (512 + 16Note) by 8 bits
• Block size
- (16,384 + 512Note) by 8 bits
Note : Underlined parts are redundancy and fixed to
all FFH.
• Operation mode
- READ mo de (1), READ mode (2), READ mode (3),
RESET
• Operating supply v o ltage : VCC = 2.7~3.6V
MX23J12840
128M-BIT NAND INTERFACE XtraROMTM
• Access Time
- Memo ry cell array to starting address : 7 us (MAX.)
- Read cycle time : 50 ns (MAX.)
- RE access time : 35 ns (MAX.)
• Operating supply current
- During read : 30 mA (MAX.) (50 ns cycle operatio n)
- During standby (CMOS) : 40 uA (MAX.)
• Package T ype
- 48-pin TSOP(I) (12mmx20mm)
• XtraROMTM : factory pre-programmed ROM with
Macro nix NBitTM techno logy , suppo rting short TAT
• Process
- 0.15um
PIN DESCRIPTION
SYMBOL PIN NAME
I/O0~I/O7 Address Input/Command Inputs/
Data Outputs
CLE Command Latch Enable
ALE Address Latch Enable
WE Write Enable
RE Read Enable
CE Chip Enable
RB READY, /BUSY pin
VCC Supply Voltage
NC No Connection
GND Ground
PIN CONFIGURATIONS
48 TSOP
NC
NC
NC
NC
NC
GND
RB
RE
CE
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
NC
NC
VCC
GND
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
NC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MX23J12840
(Normal Type)
ORDER INFORMATION
Part No. Package Grade
MX23J12840TC-50G 48 pin TSOP (Pb-free, RoHS) Co mmercial
MX23J12840TC-50 48 pin TSOP Co mmercial
MX23J12840TI-50G 48 pin TSOP (Pb-free, RoHS) Industrial
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P/N:PM1097 REV. 1.3, NOV. 07, 2006
MX23J12840
BLOCK DIAGRAM
Input/Output Buffer
Command
Register
READ Contorol Circuit Memory Cell Matrix
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Control Logic
X-Decoder
CE
CLE
ALE
WE
RE
VCC
RB (Open-drain)
Sense Amplifier
Y-Selector
Data Register Circuit
Address
Register
READY/BUSY
Control Circuit
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P/N:PM1097 REV. 1.3, NOV. 07, 2006
MX23J12840
MEMORY MAP
•The start address (SA) during read operation is specified divided into three areas using three types of read
commands.
- In read mode (1), start address (SA) is set in area (A).
- In read mode (2), start address (SA) is set in area (B).
- In read mode (3), start address (SA) is set in area (C).
One page consists of a total of 528 bytes broken down into 512 bytes (main memory) and 16 bytes (redundancy).
One block consists of 32 pages.
Caution The data of area (C) is redundancy, which is not programmable and is fix ed to all FFH.
1 Block
=32 Pages
512 Bytes
(Main memory) 16 Bytes
(Redundancy)
0 . . . 255
0
1
2
.
.
30
31
.
.
.
.
.
.
.
.
.
32,765
32,766
32,767
256
1 Page=528 Bytes
. . . 511 . 527
1,024 Blocks
=32,768 Pages
(B)(A) (C)
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P/N:PM1097 REV. 1.3, NOV. 07, 2006
MX23J12840
Operation Modes
Command input, address input, and serial read are all perfor med from I/O pins, and the respective statuses are
controlled b y the CLE, ALE, WE, RE, and CE signals.
Operation mode during serial read
Mode CLE ALE CE W E RE I/O0 - I/O7
Data output L L L H L Data output
Output Hi-Z L L L H H Hi-Z
Standby L L H H x Hi-Z
Operation mode
Mode CLE ALE CE WE RE
Command input cycle H L L H
Address input cycle L H L H
Serial read cycle L L L H
Remark ´ : VIH or VIL
Command
input cycle Address input cycle Serial read cycle
Busy
CLE
CE
WE
RE
I/O0~
I/O7
RB
ALE
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P/N:PM1097 REV. 1.3, NOV. 07, 2006
MX23J12840
Operation Commands
The following six operation settings are possible by inputting commands from I/O pins.
I/O Pin Correspondence Table during Address Input Cycle (Address Setting)
(1) When 00H o r 01H command is set [Read mode (1), Read mode (2)]
Command I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
1st address cycle A7 A6 A5 A4 A3 A2 A1 A0
2nd address cycle A16 A15 A14 A13 A12 A11 A10 A9
3rd address cycle X A23 A22 A21 A20 A19 A18 A1 7
(2) When 50H command is set [Read mo de (3)]
Command I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
1st address cycle X X X X A3 A2 A1 A0
2nd address cycle A16 A15 A14 A13 A12 A11 A10 A9
3rd address cycle X A23 A22 A21 A20 A19 A18 A1 7
Remarks
1. A0 to A23 are internal addresses.
2. Internal address A8 is set internally with command 00H or 01H.
3 . When 50H co mmand is set [read mo de (3)], the I/O4, I/O5, I/O6, and I/O7 inputs o f the 1st address cycle are VIH
or VIL.
Command Hex I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Command receivable
during Busy
Read mode(1) 00 LLLLLLLL
Read mode(2) 01 LLLLLLLH
Read mode(3)Note1 50 LHLHLLLL
Reset Note2 FF HHHHHHHH
Notes:
1. The data o utput in read mo de (3) is all FFH.
2. The o nly command that can be executed when the device is Busy is the reset co mmand. Do not set any o f the o ther
commands while the device is Busy.
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P/N:PM1097 REV. 1.3, NOV. 07, 2006
MX23J12840
Electrical Specifications
Absolute Maximum Ratings
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent
damage. The device is not meant to be operated under conditions outside the limits described in the operational
section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect
device reliability.
Parameter Symbol Condition Rating Unit
Supply voltage VCC -0.5 to +4.6 V
Input voltage VI -0.3 to VCC+0.3 V
Input / Output voltage VI/O -0.3 to VCC+0.3 (< 4.6) V
Operating ambient temperature TA -40 to 85 °C
Sto r age temperature Tstg -65 to +150 °C
Capacitance (TA = 25°°
°°
°C)
P arameter Symbol Test condition MIN. TYP. MAX. Unit
Input capacitance CI f = 1 MHz 10 pF
Output capacitance CO 10 pF
DC Characteristics (TA = -40 to 85°°
°°
°C, VCC = 2.7~3.6V)
P arameter Symbol T est conditions MIN. TYP. MAX. Unit
High lev el input vo ltage VIH 2.0 VCC+0.3 V
Low le v el input vo ltage VIL -0.3 +0.8 V
High level output voltage VOH IOH =-400uA 2.4 V
Low lev el output voltage VOL IOL = 2.1 mA 0.4 V
Input leakage current ILI VI = 0 V to VCC ±10 uA
Output leakage current ILO VO = 0 V to VCC ±10 uA
P o w er supply current in read ICCO1 CE = VIL, IOUT =0 mA, 30 mA
tCYCLE = 50 ns
Standby current (CMOS) ICCS2 CE = VCC-0.2 V 4 0 uA
RB pin output current IOL(RB) VOL = 0.4 V 8 mA
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P/N:PM1097 REV. 1.3, NOV. 07, 2006
MX23J12840
Parameter Symbol MIN. TYP. MAX. Unit
CLE setup time tCLS 0 ns
CLE hold time tCLH 10 ns
CE setup time tCS 0 ns
CE hold time tCH 10 ns
Write pulse width tWP 25 ns
ALE setup time tALS 0 ns
ALE hold time tALH 10 ns
Data setup time tDS 20 ns
Data hold time tDH 10 ns
Write cycle time tWC 50 ns
WE high hold time tWH 15 ns
Ready to RE falling edge tRR 20 ns
Read pulse width tRP 35 ns
Read cycle time tRC 50 ns
RE access time (serial data access) tREA 35 ns
CE high hold time for last address in serial read cycle tCEH 100 ns
RE high to o utput Hi-Z tRHZ 10 30 ns
CE high to output Hi-Z tCHZ 20 ns
RE high hold time tREH 15 ns
Output Hi-Z to RE falling edge tIR 0 ns
WE high to RE low tWHR 30 ns
Memo ry cell array to starting address t R 7 us
WE high to Busy tWB 200 ns
ALE low to RE low (read cycle) tAR2 50 ns
RE last clock rising edge to Busy (in sequential read) tRB 20 0 ns
CE high to Ready (when interrupted by CE in read mode) tCRYNote 1us
Device reset time tRST 6 us
AC Characteristics (TA = -40 to 85°°
°°
°C, VCC = 2.7~3.6V)
Note :tCRY (time from CE to Ready) depends on the pull-up resister of the RB pin.
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P/N:PM1097 REV. 1.3, NOV. 07, 2006
MX23J12840
AC Test Conditions
1.5V1.5V Test points
Input Waveform (Rise/Fall Time < 5ns)
1.5V1.5V Test points
Output Waveform
Output Load : 1 TTL + 100pF
Input Pulse Levels : 0.4 ~ 2.4V
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P/N:PM1097 REV. 1.3, NOV. 07, 2006
MX23J12840
READ CYCLE TIMING CHART (1)
(In case of read mode (1))
Remarks:
1. Start address (SA) specification when read is performed with co mmand 00H. N: 0 to 255
2. The time (tCRY) from CE high lev el until Busy is cancelled depends on the pull-up register o f the RB output pin.
tCLS tCLH
tDS
tDS tDH
tDH tDH tDH
Access
page M
tDS tDS
tWC
tAR2
tRC
tRP
tWB tREH
tRB
Output Page M Data
tRHZ
tRHZ
tREA
tRR tRC
tCEH
tCRY
tCHZ
tALH tALS tWP tWH tALH
tRtCS
CLE
CE
00H A0-A7 A9-A16 A17-A24
DOUT
N N+1 527
DOUT DOUT
WE
RE
I/O0~
I/O7
RB
ALE
tDH
tDS
A25
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P/N:PM1097 REV. 1.3, NOV. 07, 2006
MX23J12840
READ CYCLE TIMING CHART (2)
(In case of read mode (2))
Remarks
1. Start address (SA) specification when read is performed with co mmand 01H. N: 0 to 255
2. The time (tCRY) from CE high lev el until Busy is cancelled depends on the pull-up register o f the RB output pin.
tCLS tCLH
tDS
tDS tDH
tDH tDH tDH
Access
page M
tDS tDS
tWC
tAR2
tRC
tRP
tWB tREH
tRB
Output Page M Data
tRHZ
tRHZ
tREA
tRR tRC
tCEH
tCRY
tCHZ
tALH tALS tWP tWH tALH
tRtCS
CLE
CE
01H A0-A7 A9-A16 A17-A24 DOUT
256+N 256+N+1 527
DOUT DOUT
WE
RE
I/O0~
I/O7
RB
ALE
tDH
tDS
A25
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P/N:PM1097 REV. 1.3, NOV. 07, 2006
MX23J12840
READ CYCLE TIMING CHART (3)
(In case of read mode (3))
Remarks
1. Start address (SA) specification when read is performed with command 50H. N: 0 to 15
2. The start address o f area C (redundancy data) is specified with A0 tp A3 during the 1st address cycle. At this time,
A4 to A7 are Don't Care.
3. The time (tCRY) from CE high lev el until Busy is cancelled depends on the pull-up register o f the RB output pin.
tCLS tCLH
tDS
tDS tDH
tDH tDH tDH
Access
page M
tDS tDS
tWC
tAR2
tRC
tRP
tWB tREH
tRB
Output Page M Data
tRHZ
tRHZ
tREA
tRR tRC
tCEH
tCRY
tCHZ
tALH tALS tWP tWH tALH
tRtCS
CLE
CE
50H A0-A3 A9-A16 A17-A24
DOUT
512+N 512+N+1 527
DOUT DOUT
WE
RE
I/O0~
I/O7
RB
ALE
tDH
tDS
A25
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P/N:PM1097 REV. 1.3, NOV. 07, 2006
MX23J12840
Sequential Read
In read modes (1), (2), and (3), when a command (00H, 01H, 50H) is input and an address specified, if it is in the
block that includes the address that was specified first, the address is automatically incremented and the read
o peration is co ntinuo usly perf o rmed until the last address in the same blo c k, by inputting the RE# clock. At this time ,
a Busy period (tR) occurs after the last address is accessed in a page.
Note :To perfor m read again after reading the 527th byte of data of the last page of block, stop the read operation once, and
then restart the read operation by inputting again the read command and an address.
Relationship Between Command and Start Address (SA) during Sequential Read
•When the "00H" command is set, the start address (SA) is set to area (A).
•When the "01H" command is set, the start address (SA) is set to area (B).
•When the "50H" command is set, the start address (SA) is set to area (C).
(A) (B) (C)
256
1block
=32 pages
0
SA
512 527
Sequential read mode (1)
(When "00H" command is input) Sequential read mode (2)
(When "01H" command is input) Sequential read mode (3)
(When "50H" command is input)
Note
Note : When the "50H" command is set, only the (C) area (redundancy data part) is continuously read.
(A) (B) (C)
256
SA
512 527
(A) (B) (C)
256
SA
512 527
Busy
Address
input
Command
input
RB
00H
tR
Busy
tR
Busy
In same block
(Maximum of 32 pages)
tR
Busy
tR
Busy
tCRY
Note
Note
Busy
tR
Page M
data output Page M+1
data output Output of in last page
in block Data output
Address
input
01H
50H
Command
input
01H
00H
50H
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P/N:PM1097 REV. 1.3, NOV. 07, 2006
MX23J12840
SEQUENTIAL READ CYCLE TIMING CHART(1)
(In case of read mode (1))
Remarks
1.Start address (SA) specification when read is performed with command 00H. N:0 to 255.
tCLS tCLH
tDS
tDS tDH
tDH tDH tDH
Access
page M Access
page M+1
tDS tDS
tWC
tAR2
tRC
tRP
tWB tREH tR
tRB
Output Page M Data Output page M+1 data
tRR
tRHZ
tREA
tRR tRC
tALH tALS tWP tWH tALH
tRtCS
CLE
CE
00H A0-A7 A9-A16 A17-A24
DOUT
N N+1 527 0
DOUT DOUT DOUT
1
DOUT
WE
RE
I/O0~
I/O7
RB
ALE
tDH
tDS
A25
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P/N:PM1097 REV. 1.3, NOV. 07, 2006
MX23J12840
SEQUENTIAL READ CYCLE TIMING CHART(2)
(In case of read mode (2))
Remarks
1.Start address (SA) specification when read is performed with command 01H. N:0 to 255.
tCLS tCLH
tDS
tDS tDH
tDH tDH tDH
Access
page M Access
page M+1
tDS tDS
tWC
tAR2
tRC
tRP
tWB tREH tR
tRB
Output Page M Data Output page M+1 data
tRR
tRHZ
tREA
tRR tRC
tALH tALS tWP tWH tALH
tRtCS
CLE
CE
01H A0-A7 A9-A16 A17-A24 DOUT
256+N 256+N+1 527 0
DOUT DOUT DOUT
1
DOUT
WE
RE
I/O0~
I/O7
RB
ALE
tDH
tDS
A25
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P/N:PM1097 REV. 1.3, NOV. 07, 2006
MX23J12840
SEQUENTIAL READ CYCLE TIMING CHART(3)
(In case of read mode (3))
Remarks
1.Start address (SA) specification when read is performed with co mmand 50H. N:0 to 15.
tCLS tCLH
tDS
tDS tDH
tDH tDH tDH
Access
page M Access
page M+1
tDS tDS
tWC
tAR2
tRC
tRP
tWB tREH tR
tRB
Output Page M Data Output page M+1 data
tRR
tRHZ
tREA
tRR tRC
tALH tALS tWP tWH tALH
tRtCS
CLE
CE
50H A0-A3 A9-A16 A17-A24 DOUT
512+N 512+N+1 527 512
DOUT DOUT DOUT
513
DOUT
WE
RE
I/O0~
I/O7
RB
ALE
tDH
tDS
A25
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P/N:PM1097 REV. 1.3, NOV. 07, 2006
MX23J12840
Reset Cycle Timing Char t
tCLS tCLH
tCS tCH
tALS
tDS tDH
tWB
tALH
tRST
tWP
CLE
CE
FFH
WE
ALE
RB
I/O0~
I/O7
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P/N:PM1097 REV. 1.3, NOV. 07, 2006
MX23J12840
[Usage Cautions]
(1) Rated operation
Operation using timing other than shown in the timing charts is no t guaranteed.
(2) Commands that can be input
The o nly co mmands that can be input are 00H, 01H, 50H, and FFH. Do no t input any o ther co mmands .
If o ther commands are input, the subsequent operatio n is not guaranteed.
(3) Command limitations during Busy period
Do not input commands other than the reset command (FFH) dur ing the Busy period. If a command is input
during the Busy period, the subsequent operation is not guaranteed.
(4) Cautions regarding RE clock
•Following the last RE clock, do not input the RE clock until the RB pin changes from Busy to Ready.
•Do not input the RE clock other than during data output.
(5) Cautions upon power application
Since the state o f the device is undetermined upon power o n, input high level to the CE pin and execute the reset
command following power on.
(6) Cautions during read mode
•P erf orm address input immediately following command input. If address input is done witho ut perf orming co m-
mand input first, the correct data cannot be output because the o peration mode is undetermined.
•To ex ecute the read mo de after the read mode has been sto pped with the reset co mmand (FFH) and CE, input
again a command and address.
(7) Busy output following access of last address in page in read mode
After the access to the last address in a page, if the delay (tRHCH) from RE to CE is 30 ns or less, the Ready
status is maintained and Busy is not output by k eeping CE high level for a set period (tCEH).
tCEH
tRHCH
527526
CE
RE
RB
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P/N:PM1097 REV. 1.3, NOV. 07, 2006
MX23J12840
PACKAGE INFORMATION
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P/N:PM1097 REV. 1.3, NOV. 07, 2006
MX23J12840
REVISION HISTORY
Revision # Description Page Date
1.0 1. Changed standby current from 100uA to 40uA P1,6 AUG/16/2005
2. Removed "Advanced Information" P1
1.1 1. Added "Order Information" P1 SEP/06/2005
1.2 1. Removed tWHC P7 OCT/28/2005
2. Mo dified "Read cycle timing chart" and "Sequential read cycle timing P 9~ 11
char t" P13~15
1.3 1. Added statement P20 NO V/07/2006
MX23J12840
MACRONIX INTERNATIONAL CO., LTD .
Headquarters:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
Europe Office :
TEL:+32-2-456-8020
FAX:+32-2-456-8021
Hong Kong Office :
TEL:+86-512-6258-0888
FAX:+86-512-6258-6799
Japan Office :
Kawasaki Office :
TEL:+81-44-246-9100
FAX:+81-44-246-9105
Technical Support Center :
TEL:+81-44-246-9875
FAX:+81-44-246-9951
Singapore Office :
TEL:+65-6346-5505
FAX:+65-6348-8096
Taipei Office :
TEL:+886-2-2509-3300
FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-262-8887
FAX:+1-408-262-8810
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
Macro nix's products are no t designed, manufactured, o r intended for use fo r any high risk applications in which the
failure of a single component could cause death, personal injury, severe physical damage, or other substantial
harm to persons or proper ty, such as life-support systems, high temperature automotive, medical, aircraft and
military applicatio n. Macro nix and its suppliers will not be liable to you and/o r any third party fo r any claims, injuries
o r damages that may be incurred due to use o f Macro nix's pro ducts in the prohibited applicatio ns.
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