1/28January 2006
M24C16, M24C08
M24C04, M24C02, M24C01
16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I²C Bus EEPROM
FEATURES SUMMARY
■Two-Wire I²C Serial Interface
Supports 400kHz Protocol
■Single Supply Voltage:
– 2.5 to 5.5V for M24Cxx-W
– 1.8 to 5.5V for M24Cxx-R
■Write Control Input
■BYTE and PAGE WRITE (up to 16 Bytes)
■RANDOM and SEQUENTIAL READ Modes
■Self-Timed Programming Cycle
■Automatic Address Incrementing
■Enhanced ESD/Latch-Up Protection
■More than 1 Million Erase/Write Cycles
■More than 40-Year Data Retention
■Packages
– ECOPACK® (RoHS compliant)
Table 1. Product List
Figure 1. Pack ag e s
Reference Part Number
M24C16 M24C16-W
M24C16-R
M24C08 M24C08-W
M24C08-R
M24C04 M24C04-W
M24C04-R
M24C02 M24C02-W
M24C02-R
M24C01 M24C01-W
M24C01-R
PDIP8 (BN)
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
TSSOP8 (DS)
3x3mm² body size (MSOP)
UFDFPN8 (MB)
2x3mm² (MLP)
M24C16, M24C08, M24C04, M24C02, M24C01
2/28
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. 8-Pin Package Connections (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Data (SDA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. Device Select Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Supply voltag e (V CC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operating supply voltage VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Internal Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Power-down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5. Maximum RP Value versus Bus Parasitic Capacitance (C) for an I²C Bus . . . . . . . . . . . 6
Figure 6. I²C Bus Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Device Select Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DEVICE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Stop Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Write Mode Sequences with WC=1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Byte Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. Write Mode Sequences with WC=0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. Write Cycle Polling Flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Minimizing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10.Read Mode Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Random Address Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Acknowledge in Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3/28
M24C16, M24C08, M24C04, M24C02, M24C01
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Operating Conditions (M24Cxx-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. Operating Conditions (M24Cxx-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. DC Characteristics (M24Cxx-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. DC Characteristics (M24Cxx-W, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10. DC Characteristics (M24Cxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 11. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 12. Input Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 13. AC Characteristics (M24Cxx-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 14. AC Characteristics (M24Cxx-R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12.AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 21
Table 15. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data. . . . . . . . . . 21
Figure 14.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . 22
Table 16. SO8 narrow – 8 lead Plastic Small Outline, 150 mils bod y width,
Package Mechanical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 15.UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm²,
Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 17. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm²,
Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 16.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 24
Table 18. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 24
Figure 17.TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² b ody size,
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 19. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size,
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 20. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 21. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
M24C16, M24C08, M24C04, M24C02, M24C01
4/28
SUMMARY DESCRIPTION
These I²C-compatible electrically erasable pro-
grammable memory (EEPROM) devices are orga-
nized as 2048/1024/512/256/128 x 8 (M24C16,
M24C08, M24C04, M24C02 and M24C01).
In order to meet environmental requirements, ST
offers these devices in ECOPACK® packages.
ECOPACK® packages are Lead-free and RoHS
compliant.
ECOPACK is an ST trademark. ECOPACK speci-
fications are available at: www.st.com.
Figure 2. Logic Diagram
I²C uses a two-wire serial interface, comprising a
bi-directional data line and a clock line. The devic-
es carry a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I²C bus definition.
The device behave s as a slave in the I² C prot ocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are initiat-
ed by a St art condition, generate d by the bus mas-
ter. The Start condition is followed by a Device
Select Code and Read/Write bit (RW) (as de-
scribed in Table 3.), terminated by an acknowl-
edge bit.
When writing data to the memory, the device in-
serts an acknowledge bit during the 9th bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after a n Ack for Wr ite, and af ter a
NoAck for Read.
Table 2. Signal Names
Figure 3. 8-Pin Package Co nnections (Top View)
Note: 1. NC = Not Connecte d
2. See PACKAGE MECHANICAL section for package dimensions, and ho w to identify pin-1.
AI02033
3
E0-E2 SDA
VCC
M24Cxx
WC
SCL
VSS
E0, E1, E2 Chip Enable
SDA Serial Data
SCL Serial Clock
WC Write Control
VCC Supply Voltage
VSS Ground
SDAVSS SCL
WC
VCC
/ E2
AI02034E
M24Cxx
1
2
3
4
8
7
6
5
/ E2/ E2/ E2NC / E1
/ E1/ E1/ NCNC / E0
/ E0/ NC/ NCNC /1Kb
/2Kb/4Kb/8Kb16Kb
5/28
M24C16, M24C08, M24C04, M24C02, M24C01
SIGNAL DESCRIPTION
Serial Clock (SCL)
This input signal is used to strobe all data in and
out of the device. In applications where this signal
is used by slave devices to synchronize the bus to
a slower clock, the bus m aster must have an op en
drain output, and a pull-up resistor can be con-
nected from Serial Clock (SCL) to VCC. (Figure 5.
indicates how the value of the pull-up resistor can
be calculated). In most applications, though, this
method of synchronization is not employed, and
so the pull-up resistor is not necessary, provided
that the bus master has a push-pull (rather than
open drain) output.
Serial Data (SDA)
This bi-directional signal is used to transfer d ata in
or out of the device. It is an open drain output that
may be wire-OR’ed with other open drain or open
collector signals on the bus. A pull up resistor must
be connected from Serial Dat a (SDA) to VCC. (Fig-
ure 5. indicates how the value of the pull-up resis-
tor can be calculated).
Chip Enable (E0, E1, E2)
These inpu t signals are used to se t the value that
is to be looked for on the thr ee least significant bits
(b3, b2, b1) of the 7-bit Device Select Cod e. These
inputs must be t ied to VCC or VSS, to establish the
Device Select Code as shown in Figure 4.
Figure 4. Device Select Code
Write Control (WC). This input signal is useful
for protecting the entire contents of the memory
from inadvertent write operations. Write opera-
tions are disabled to the entire memory array when
Write Control (WC) is driven High. When uncon-
nected, the signal is internally read as VIL, and
Write operations are allowed.
When Write Control (WC) is driven High, Device
Select and Address bytes are acknowledged,
Data bytes are not acknowledged.
Supply voltage (VCC)
Operating supply voltage VCC. Prior to select-
ing the memory and issuing instructions to it, a val-
id and stable VCC voltage must be applied: this
voltage must be a DC voltage within the specified
[VCC(min), VCC(max)] range, as defined in Table
6. and Table 7. In or der to secure a stable DC sup-
ply voltage, it is recommended to decouple the
VCC line with a suitable capacitor (usually of the
order of 10nF to 100nF) close to the VCC/VSS
package pins.
The VCC voltage must remain stable and valid until
the end of the transmission of the instruction and,
for a Write instruction, until the completion of the
internal write cycle (tW).
Internal Device Reset. In order to prevent inad-
vertent Write operations during Power-up, a Pow-
er On Reset (POR) circuit is included. At Power-up
(continuous rise of VCC), the device does not re-
spond to any instruction until V CC has reached the
Power On Reset threshold voltage (this threshold
is lower than the minimum VCC operating voltage
defined in Table 6. and Table 7.).
When VCC has passed the POR threshold, the de-
vice is reset and in the Standby Power mode
Power-down. At Power-down (where VCC de-
creases continuously), as soon as V CC drops from
the operating voltage range below the Power On
Reset threshold voltage, the device stops re-
sponding to any instruction sent to it.
During Power-down, the d evice must be deselect-
ed and in the Standby Power mode (that is there
should be no internal Write cycle in progress).
Ai11650
VCC
M24Cxx
VSS
Ei
VCC
M24Cxx
VSS
Ei
M24C16, M24C08, M24C04, M24C02, M24C01
6/28
Figure 5. Maximu m RP Value versus Bus Parasitic Capa citance (C) for an I²C Bus
Figure 6. I²C Bus Protocol
AI01665b
VCC
C
SDA
RP
MASTER
RP
SCL C
100
0
4
8
12
16
20
C (pF)
Maximum RP value (kΩ)
10 1000
fc = 400kHz
fc = 100kHz
SCL
SDA
SCL
SDA
SDA
START
Condition
SDA
Input SDA
Change
AI00792B
STOP
Condition
123 789
MSB ACK
START
Condition
SCL 123 789
MSB ACK
STOP
Condition
7/28
M24C16, M24C08, M24C04, M24C02, M24C01
Table 3. Device Select Code
Note: 1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared a gainst the res pective external pins on the memory device.
3. A10, A9 and A8 represent most significant bits of the address.
Device Type Identifier1Chip Enable2,3 RW
b7 b6 b5 b4 b3 b2 b1 b0
M24C01 Select Code 1 0 1 0 E2 E1 E0 RW
M24C02 Select Code 1 0 1 0 E2 E1 E0 RW
M24C04 Select Code 1 0 1 0 E2 E1 A8 RW
M24C08 Select Code 1 0 1 0 E2 A9 A8 RW
M24C16 Select Code 1 0 1 0 A10 A9 A8 RW
M24C16, M24C08, M24C04, M24C02, M24C01
8/28
DEVICE OPERATION
The device supports the I²C protocol. This is sum-
marized in Figure 6.. Any device that sends data
on to the bus is defined to be a transmitter, and
any device that reads the data to be a receiver.
The device that cont rols the data transfer is known
as the bus master, and the other as the slave de-
vice. A data transfer can only be initiated by the
bus master, which will also provide the serial clock
for synchronizati on. The M24Cxx device is always
a slave in all communication.
Start Condition
Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The device continuously
monitors (except during a Write cycle) Serial Data
(SDA) and Serial Clock (SCL) f or a Start condition,
and will not respond unless one is given.
Stop Condition
Stop is identified by a rising edge of Serial Data
(SDA) while Serial Clock (SCL) is stable and driv-
en High. A Stop condition terminates communica-
tion between the device and the bus master. A
Read command that is followed by NoAck can be
followed by a Stop condition to force the device
into the Stand-by mode. A Stop condition at the
end of a Writ e command triggers the in ternal Write
cycle.
Acknowledge Bit (ACK)
The acknowledge bit is used to indicate a success-
ful byte transfer. The bus transmitter, whether it be
bus master or slave device, releases Serial Data
(SDA) after sending eight bits of data. During the
9th clock pulse period, the receiver pulls Serial
Data (SDA) Low to acknowledge t he receipt of the
eight data bits.
Data Input
During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must chan ge only when Serial Clock (SCL) is driv-
en Low.
Memory Addressing
To start communication between the bus master
and the slave device, the bus master must initiate
a Start condition. Following this, the bus master
sends the Device Select Code, shown in Table 3.
(on Serial Data (SDA), most significant bit first).
The Device Select Code cons ists of a 4-bit Device
Type Identifier, and a 3-bit Chip Enable “Address”
(E2, E1, E0). To address the me mory array, t he 4-
bit Device Type Identifier is 1010b.
Each device is given a unique 3-bit code on the
Chip Enable (E0, E1, E2) in puts. When the Device
Select Code is received, the device only r esponds
if the Chip Enable Address is the same as the val-
ue on the Chip Enable (E0, E1, E2) inputs. How-
ever, those devices with larger memo ry capacities
(the M24C16, M24C08 and M24C04) need more
address bits. E0 is not available for use o n devices
that need to use address line A8; E1 is not avail-
able for devices that need to use address line A9,
and E2 is not available for devices that need to use
address line A10 (see Figure 3. and Table 3. for
details). Using the E0, E1 and E2 inputs, up to
eight M24C02 (or M24C01), four M24C04, two
M24C08 or one M24C16 devices ca n be co nne ct-
ed to one I²C bus. In each case, and in the hybrid
cases, this gives a total memory capacity of
16 Kbits, 2 KBytes (except where M24C01 devic-
es are used).
The 8th bit is the Read/Write bit (RW). This bit is
set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code, the
corresponding device gives an acknowledgment
on Serial Data (S DA) during the 9th bit time . If the
device does not match the Device Select code, it
deselects itself f rom the bus, an d goes into Stand-
by mode.
9/28
M24C16, M24C08, M24C04, M24C02, M24C01
Table 4. Operating Modes
Note: 1. X = VIH or VIL.
Figure 7. Write Mode Sequences with WC=1 (data write inhibited)
Mode RW bit WC (1) Bytes Initial Sequence
Current Address Read 1 X 1 START, Device Select, RW = 1
Random Address Read 0X1START, De vice Select, RW = 0, Address
1 X reSTART, Device Select, RW = 1
Sequential Read 1 X ≥ 1 Similar to Current or Random Address Read
Byte Write 0 VIL 1 START, Device Select, RW = 0
Page Write 0 VIL ≤ 16 START, Device Select, RW = 0
STOP
START
Byte Write DEV SEL BYTE ADDR DATA IN
WC
START
Page Write DEV SEL BYTE ADDR DATA IN 1 DATA IN 2
WC
DATA IN 3
AI02803C
Page Write
(cont'd)
WC (cont'd)
STOP
DATA IN N
ACK ACK NO ACK
R/W
ACK ACK NO ACK NO ACK
R/W
NO ACK NO ACK
M24C16, M24C08, M24C04, M24C02, M24C01
10/28
Write Operations
Following a Start condition the bus master sends
a Device Select Code with the Read/Write bit
(RW) reset to 0. The de vice acknowledges this, as
shown in Figure 8. , an d wa its for an ad dress byte .
The device responds to the address byte with an
acknowledge bit, and then waits for the data byte.
When the bus master generates a Stop condition
immediately after the Ack bit (in the “10th bit” time
slot), either at the end of a Byte Write or a Page
Write, the internal Write cycle is triggered. A Stop
condition at any other time slot does not trigger the
internal Write cycle.
During the in ternal Write cycle, Serial Data (SDA)
and Serial Clock (SCL) are ignored, and the de-
vice does not respond to any requests.
Byte Write
After the Device Select code and the address byte,
the bus master sends one data byte. If the ad-
dressed location is Wr ite-protect ed, by Write Con -
trol (WC) being driven High (during the period from
the Start condition until the end of the address
byte), the device replies to the data byte with
NoAck, as shown in Figure 7., and the location is
not modified. If, instead, the addressed location is
not Write-protected, the device replies with Ack.
The bus master terminat es the transf er by gener-
ating a Stop condition, as shown in Figure 8..
Page Write
The Page Write mode allows up to 16 bytes to be
written in a single Write cycle, provided that they
are all located in the same page in the memory:
that is, the most significant memory address bits
are the same. If more bytes are sent than will fit up
to the end of the page, a condition known as ‘roll-
over’ occurs. This should be avoided, as data
starts to become over written in an implement ation
dependent way.
The bus master sends from 1 to 16 bytes of data,
each of which is acknowledged by the device if
Write Control (WC) is Low. If the addressed loca-
tion is Write-protected, by Write Control (WC) be-
ing driven High (during the period from the Start
condition until the end of the address byte), the de-
vice replies to the data bytes with NoAck, as
shown in Figure 7., and t he locations ar e not mod-
ified. After each byte is transferred, the internal
byte address counter (the 4 least significant ad-
dress bits only) is increm ented. The transfer is te r-
minated by the bus master generating a Stop
condition.
11/28
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 8. Write Mode Sequences with WC=0 (data write enabled)
STOP
START
BYTE WRITE DEV SEL BYTE ADDR DATA IN
WC
START
PAGE WRITE DEV SEL BYTE ADDR DATA IN 1 DATA IN 2
WC
DATA IN 3
AI02804B
PAGE WRITE
(cont'd)
WC (cont'd)
STOP
DATA IN N
ACK
R/W
ACK ACK
ACK ACK ACK ACK
R/W
ACKACK
M24C16, M24C08, M24C04, M24C02, M24C01
12/28
Figure 9. Write Cycle Polling Flowchart using ACK
Minimizing System Delays by Polling On ACK
During the internal Write cycle, the device discon-
nects itself from the bus, and writes a copy of the
data from its internal latches to the memory cells.
The maximum Write time (tw) is shown in Table
13. and Table 14., but the typical time is shorter.
To make use of this, a polling sequence can be
used by the bus master.
The sequence, as shown in Figure 9., is:
– Initial condition: a Write cycle is in progress.
– Step 1: the bus master issues a Start condition
followed by a Device Select Code (the first
byte of the new ins tru ct ion ).
– Step 2: if the device is busy with the internal
Write cycle, no Ack will be returned and the
bus master goes back to St ep 1 . If the d evice
has terminated the internal Write cycle, it
responds with an Ack, ind i ca tin g that the
device is ready to receive the second part of
the instruction (the f irst byte of t his instructi on
having been sent during Step 1).
WRITE Cycle
in Progress
AI01847C
Next
Operation is
Addressing the
Memory
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
YES
NO
YESNO
ReSTART
STOP
DATA for the
WRITE Operation DEVICE SELECT
with RW = 1
Send Address
and Receive ACK
First byte of instruction
with RW = 0 already
decoded by the device
YESNO START
Condition
Continue the
WRITE Operation Continue the
Random READ Operation
13/28
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 10. Read Mode Sequences
Note: The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 3rd bytes) must be identical.
Read Operations
Read operations are performed independently of
the state of the Write Control (WC) signal.
The device has an internal addre ss co unter which
is incremented eac h tim e a byt e is read .
Random Address Read
A dummy Write is first performed to load the ad-
dress into this address counter (as shown in Fig-
ure 10.) but without sending a Stop condition.
Then, the bus master sends another Start condi-
tion, and repeats the De vice Select Code, with the
Read/Write bit (RW ) set to 1. The device acknowl-
edges this, and outputs the contents of the ad-
dressed byte. The bus master must not
acknowledge the byte, and terminates the transfer
with a Stop condition.
Current Address Read
For the Current Address Read operation, following
a Start condition, the bus master on ly sends a De-
vice Select Code with the Read/ Writ e bit (RW) set
to 1. The device acknowledges this, and outputs
the byte addressed by the internal address
counter. The counter is then incremented. The bus
master terminates the transfer with a Stop condi-
START
DEV SEL * BYTE ADDR
START
DEV SEL DATA OUT 1
AI01942
DATA OUT N
STOP
START
CURRENT
ADDRESS
READ DEV SEL DATA OUT
RANDOM
ADDRESS
READ
STOP
START
DEV SEL * DATA OUT
SEQUENTIAL
CURRENT
READ
STOP
DATA OUT N
START
DEV SEL * BYTE ADDR
SEQUENTIAL
RANDOM
READ
START
DEV SEL * DATA OUT 1
STOP
ACK
R/W
NO ACK
ACK
R/W
ACK ACK
R/W
ACK ACK ACK NO ACK
R/W
NO ACK
ACK ACK
R/W
ACK ACK
R/W
ACK NO ACK
M24C16, M24C08, M24C04, M24C02, M24C01
14/28
tion, as sho wn in Figure 10., without acknowledg-
ing the byte.
Sequential Read
This operation can be used after a Current Ad-
dress Read or a Random Address Read. The bus
master does acknowledge the data byte output,
and sends additional clock pulses so that the de-
vice continues to output the next byte in sequence.
To terminate the stream of bytes, the bus master
must not acknowledge the last byte, and must
generate a St op condition, as shown in Figure 10..
The output data comes f rom consecutive address-
es, with the internal address counter autom atically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’,
and the device continues to output data from
memory address 00h.
Acknowledge in Read Mode
For all Read commands, the device waits, after
each byte read, for an acknowledgment during the
9th bit time. If the bus master does not drive Serial
Data (SDA) Low during this time, the device termi-
nates the data transfer and switches to its Stand-
by mode.
INITIAL DELIVERY STATE
The device is delivered with all bits in the memory
array set to 1 (eac h byte contains F Fh).
15/28
M24C16, M24C08, M24C04, M24C02, M24C01
MAXIMUM RATING
Stressing the device outside the ratings listed in
Table 5. may cause pe rmanent damage t o the de-
vice. These are stress ratings only, and operation
of the device at these, or any other conditions out-
side those indicated in the Operating sections of
this specification, is not implied. Exposure to Ab-
solute Maximum Rating conditions for extended
periods may affect device reliability. Refer also to
the STMicroelectronics SURE Program and other
relevant quality documents.
Table 5. Absolute Maximum Rat ings
Note: 1. TLEAD max must not be applied for more than 10s.
2. AEC-Q10 0-002 (compliant with JEDEC Std JESD22-A11 4A, C1=100pF, R1=1500Ω, R2=500Ω).
Symbol Parameter Min. Max. Unit
TAAm bient Operating Temperature –40 130 °C
TSTG Storage Temperature –65 150 °C
TLEAD PDIP-Specific Lead Temperature during Soldering 260(1) °C
VIO Input or Output range –0.50 6.5 V
VCC Supply Voltage –0.50 6.5 V
VESD Electrostatic Discharge Voltage (Human Body model) (2) –4000 4000 V
M24C16, M24C08, M24C04, M24C02, M24C01
16/28
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 6. Operating Conditions (M24Cxx-W)
Table 7. Operating Conditions (M24Cxx-R)
Table 8. DC Characteristics (M24Cxx-W, Device Grade 6)
Note: 1. The voltage source driving only E0, E1 and E2 inputs must provide an impedance of less than 1kOhm.
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 2.5 5.5 V
TAAmbient Operating Temperature (Device Grade 6) –40 85 °C
Ambient Operating Temperature (Device Grade 3) –40 125 °C
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 1.8 5.5 V
TAAmbient Operating Temperature –40 85 °C
Symbol Parameter Test Condition
(in addition to those in Table 6.)Min. Max. Unit
ILI Input Leakage Current
(SCL, SDA, E0, E1,and E2) VIN = VSS or VCC ± 2 µA
ILO Output Leakage Current VOUT = VSS or VCC, SDA in Hi-Z ± 2 µA
ICC Supply Current VCC=5V, fc=400kH z (rise/fall time < 30ns) 2mA
VCC =2.5V, fc=400kHz (rise/f all time < 30ns) 1mA
ICC1 Stand-by Supply Current VIN = VSS or VCC, for 2.5V < VCC = < 5.5V 1µA
VIL Input Low Voltage (1) –0.45 0.3VCC V
VIH Input High Voltage (1) 0.7VCC VCC+1 V
VOL Output Low Voltage IOL = 2.1mA when VCC = 2.5V or
IOL = 3mA when VCC = 5.5V 0.4 V
17/28
M24C16, M24C08, M24C04, M24C02, M24C01
Table 9. DC Characteristics (M24Cxx-W, Device Grade 3)
Note: 1. The voltage source driving only E0, E1 and E2 inputs must provide an impedance of less than 1kOhm.
Table 10. DC Characteristics (M24Cxx-R)
Note: 1. The voltage source driving only E0, E1 and E2 inputs must provide an impedance of less than 1kOhm.
Table 11. AC Measurement Conditions
Symbol Parameter Test Condition
(in addition to those in Table 6.)Min. Max. Unit
ILI Input Leakage Current
(SCL, SDA, E0, E1,and E2) VIN = VSS or VCC ± 2 µA
ILO Output Leakage Current VOUT = VSS or VCC, SDA in Hi-Z ± 2 µA
ICC Supply Current VCC=5V, fC=400kHz (rise/fall time < 30ns) 3mA
VCC =2.5V, fC=400kHz
(rise/fall time < 30ns) 3mA
ICC1 Stand-by Supply Current VIN = VSS or VCC, VCC = 5 V 5µA
VIN = VSS or VCC, VCC = 2.5 V 2µA
VIL Input Low Voltage (1) –0.45 0.3VCC V
VIH Input High Voltage (1) 0.7VCC VCC+1 V
VOL Output Low Voltage IOL = 2.1mA when VCC = 2.5V or
IOL = 3mA when VCC = 5.5V 0.4 V
Symbol Parameter Test Condition
(in addition to those in Table 7.)Min. Max. Unit
ILI Input Leakage Current
(SCL, SDA, E0, E1,and E2) VIN = VSS or VCC ± 2 µA
ILO Output Leakage Current VOUT = VSS or VCC, SDA in Hi-Z ± 2 µA
ICC Supply Current VCC =1.8V, fc=400kHz (rise/fall time < 30ns) 0.8 mA
ICC1 Stand-by Supply Current VIN = VSS or VCC, 1.8V < VCC < 5.5V 1µA
VIL Input Low Voltage (1) 2.5 V ≤ VCC –0.45 0.3 VCC V
1.8 V ≤ VCC < 2.5 V –0.45 0.25 VCC V
VIH Input High Voltage (1) 0.7VCC VCC+1 V
VOL Output Low Voltage IOL = 0.7 mA, VCC = 1.8 V 0.2 V
Symbol Parameter Min. Max. Unit
CLLoad Capacitance 100 pF
Input Rise and Fall Times 50 ns
Input Levels 0.2VCC to 0.8VCC V
Input and Output Timing Reference Levels 0.3VCC to 0.7VCC V
M24C16, M24C08, M24C04, M24C02, M24C01
18/28
Figure 11. AC Measurement I/O Waveform
Table 12. Input Parameters
Note: 1. TA = 25°C, f = 400kHz
2. Sampled onl y, not 100% tested.
Symbol Parameter1,2 Test Condition Min. Max. Unit
CIN Input Capacitance (SDA) 8 pF
CIN Input Capacitance (other pins) 6 pF
ZWCL WC Input Impedance VIN < 0.3 V 15 70 kΩ
ZWCH WC Input Impedance VIN > 0.7VCC 500 kΩ
tNS Pulse width ignored
(Input Filter on SCL and SDA) Single glitch 100 ns
AI00825B
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Input and Output
Timing Reference Levels
Input Levels
19/28
M24C16, M24C08, M24C04, M24C02, M24C01
Table 13. AC Characteristics (M24Cxx-W)
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled onl y, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. Previous de vic es beari n g the pr oces s l ett er “L ” i n the pa ckage mar kin g gu ara nt ee a max i mum wri te time of 10 ms. Fo r mo re in for -
mation about t hese devices a nd their device identification, please ask you r ST Sales Offi ce for Process C hange Notices PCN MPG/
EE/0061 and 0062 (PCEE0061 and PCEE0062).
Table 14. AC Characteristics (M24Cxx-R)
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled onl y, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. This is preliminary information.
Test conditions specified in Table 6. and Table 11.
Symbol Alt. Parameter Min. Max. Unit
fCfSCL Clock Frequency 400 kHz
tCHCL tHIGH Clock Pulse Width High 600 ns
tCLCH tLOW Clock Pulse Width Low 1300 ns
tDL1DL2 2tFSDA Fall Time 20 300 ns
tDXCX tSU:DAT Data In Set Up Time 100 ns
tCLDX tHD:DAT Data In Hold Time 0 ns
tCLQX tDH Data Out Hold Time 200 ns
tCLQV 3tAA Clock Low to Next Data Valid (Access Time) 200 900 ns
tCHDX 1tSU:STA Start Condition Set Up Time 600 ns
tDLCL tHD:STA Start Condition Hold Time 600 ns
tCHDH tSU:STO Stop Condition Set Up Time 600 ns
tDHDL tBUF Time between Stop Condition and Next Start Condition 1300 ns
tW 4tWR Write Time 5 ms
Test conditions specified in Table 7. and Table 10.
Symbol Alt. Parameter Min. 4Max. 4Unit
fCfSCL Clock Frequency 400 kHz
tCHCL tHIGH Clock Pulse Width High 600 ns
tCLCH tLOW Clock Pulse Width Low 1300 ns
tDL1DL2 2tFSDA Fall Time 20 300 ns
tDXCX tSU:DAT Data In Set Up Time 100 ns
tCLDX tHD:DAT Data In Hold Time 0 ns
tCLQX tDH Data Out Hold Time 200 ns
tCLQV 3tAA Clock Low to Next Data Valid (Access Time) 200 900 ns
tCHDX 1tSU:STA Start Condition Set Up Time 600 ns
tDLCL tHD:STA Start Condition Hold Time 600 ns
tCHDH tSU:STO Stop Condition Set Up Time 600 ns
tDHDL tBUF Time between Stop Condition and Next Start Condition 1300 ns
tWtWR Write Time 10 ms
M24C16, M24C08, M24C04, M24C02, M24C01
20/28
Figure 12. AC Waveforms
SCL
SDA In
SCL
SDA Out
SCL
SDA In
tCHCL
tDLCL
tCHDX
START
Condition
tCLCH
tDXCXtCLDX
SDA
Input
SDA
Change tCHDH tDHDL
STOP
Condition
Data Valid
tCLQV tCLQX
tCHDH
STOP
Condition
tCHDX
START
Condition
Write Cycle
tW
AI00795C
START
Condition
21/28
M24C16, M24C08, M24C04, M24C02, M24C01
PACKAGE MECHANICAL
Figure 13. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline
Note: Drawing is not to scale.
Table 15. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
Symbol millimeters inches
Typ. Min. Max. Typ. Min. Max.
A 5.33 0.210
A1 0.38 0.015
A2 3.30 2.92 4.95 0.130 0.115 0.195
b 0.46 0.36 0.56 0.018 0.014 0.022
b2 1.52 1.14 1.78 0.060 0.045 0.070
c 0.25 0.20 0.36 0.010 0.008 0.014
D 9.27 9.02 10.16 0.365 0.355 0.400
E 7.87 7.62 8.26 0.310 0.300 0.325
E1 6.35 6.10 7.11 0.250 0.240 0.280
e2.54––0.100––
eA 7.62 – – 0.300 – –
eB 10.92 0.430
L 3.30 2.92 3.81 0.130 0.115 0.150
PDIP-B
A2
A1
A
L
be
D
E1
8
1
c
eA
b2
eB
E
M24C16, M24C08, M24C04, M24C02, M24C01
22/28
Figure 14. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline
Note: 1. Drawing is not to scale.
2. The ‘1’ that appears in the top vie w of the package shows the position of pin 1 and the ‘ N ’ indicates the total number of pins.
Table 16. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width,
Package Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
A2 1.10 1.65 0.043 0.065
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
ddd 0.10 0.004
E 3.80 4.00 0.150 0.157
e1.27– –0.050– –
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035
α0° 8° 0° 8°
N (number of
pins) 88
SO-A
E
8
ddd
Be
A
D
C
LA1 α
1
H
h x 45˚
A2
23/28
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 15. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm²,
Outline
Note: 1. Drawing is not to scale.
2. The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to VSS. It must not be allowed to be connected to
any other voltage or signal line on the PCB, for example during the soldering process.
3. The circle in the top view of the package indicates the position of pin 1.
Table 17. UFDFPN8 (MLP8) 8- lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm²,
Data
Symbol millimeters inches
Typ. Min. Max. Typ. Min. Max.
A 0.55 0.50 0.60 0.022 0.020 0.024
A1 0.00 0.05 0.000 0.002
b 0.25 0.20 0.30 0.010 0.008 0.012
D 2.00 0.079
D2 1.55 1.65 0.061 0.065
ddd 0.05 0.002
E 3.00 0.118
E2 0.15 0.25 0.006 0.010
e0.50– –0.020– –
L 0.45 0.40 0.50 0.018 0.016 0.020
L1 0.15 0.006
L3 0.30 0.012
N (number of
pins) 88
D
E
UFDFPN-01
A
A1 ddd
L1
eb
D2
L
E2
L3
M24C16, M24C08, M24C04, M24C02, M24C01
24/28
Figure 16. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline
Note: 1. Drawing is not to scale.
2. The circle in the top view of the package indicates the position of pin 1.
Table 18. TSSOP8 – 8 le ad Thin Shrink Small Outli ne, Package Mechanical Data
Symbol millimeters inches
Typ. Min. Max. Typ. Min. Max.
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 1.000 0.800 1.050 0.0394 0.0315 0.0413
b 0.190 0.300 0.0075 0.0118
c 0.090 0.200 0.0035 0.0079
CP 0.100 0.0039
D 3.000 2.900 3.100 0.1181 0.1142 0.1220
e 0.650 – – 0.0256 – –
E 6.400 6.200 6.600 0.2520 0.2441 0.2598
E1 4.400 4.300 4.500 0.1732 0.1693 0.1772
L 0.600 0.450 0.750 0.0236 0.0177 0.0295
L1 1.000 0.0394
α0° 8° 0° 8°
TSSOP8AM
1
8
CP
c
L
EE1
D
A2A
α
eb
4
5
A1
L1
25/28
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 17. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size,
Package Outline
Note: 1. Drawing is not to scale.
2. The circle in the top view of the package indicates the position of pin 1.
Table 19. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size,
Mechanical Data
Symbol millimeters inches
Typ. Min. Max. Typ. Min. Max.
A 1.100 0.0433
A1 0.050 0.150 0.0020 0.0059
A2 0.850 0.750 0.950 0.0335 0.0295 0.0374
b 0.250 0.400 0.0098 0.0157
c 0.130 0.230 0.0051 0.0091
D 3.000 2.900 3.100 0.1181 0.1142 0.1220
E 4.900 4.650 5.150 0.1929 0.1831 0.2028
E1 3.000 2.900 3.100 0.1181 0.1142 0.1220
e 0.650 – – 0.0256 – –
CP 0.100 0.0039
L 0.550 0.400 0.700 0.0217 0.0157 0.0276
L1 0.950 0.0374
α0° 6° 0° 6°
TSSOP8BM
1
8
CP
c
L
EE1
D
A2A
α
eb
4
5
A1
L1
M24C16, M24C08, M24C04, M24C02, M24C01
26/28
PART NUMBERING
Table 20. Ordering Information Scheme
Note: 1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Cer-
tified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy.
2. Used only for Device Grade 3.
For a list of available options (speed, package,
etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Of-
fice.
The category of second Level Interconnect is
marked on the package and on the inner box label,
in compliance with JEDEC Standar d JESD97. The
maximum ratings related to soldering conditions
are also marked on the inner box label.
Example: M24C16 – W DW 3 T P /W
Device Type
M24 = I2C serial access EEPROM
Device Function
16 = 16 Kbit (2048 x 8)
08 = 8 Kbit (1024 x 8)
04 = 4 Kbit (512 x 8)
02 = 2 Kbit (256 x 8)
01 = 1 Kbit (128 x 8)
Operating Vo ltage
W = VCC = 2.5 to 5.5V (400 kHz)
R = VCC = 1.8 to 5.5V (400 kHz)
Package
BN = PDIP8
MN = SO8 (150 mil width)
MB = UDFDFPN8 (MLP8)
DW = TSSOP8 (169 mil width)
DS = TSSOP8 (3x3mm² body size, MSOP8)
Device Grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
3 = Device tested with High Reliability Certified Flow1.
Automotive temperature range (–40 to 125 °C)
Option
T = Tape and Reel Packing
Plating Technology
blank = Standard SnPb plating
P or G = ECOPACK® (RoHS compliant)
Process2
/W or /S = F6SP36%
27/28
M24C16, M24C08, M24C04, M24C02, M24C01
REVISION HISTORY
Table 21. Document Revision History
Date Version Description of Revision
10-Dec-1999 2.4 TSSOP8 Turned-Die package removed (p 2 and order information)
Lead temperature added for TSSOP8 in table 2
18-Apr-2000 2.5 Labelling change to Fig-2D, correction of values for ‘E’ and main caption for Tab-13
05-May-2000 2.6 Extr a labelling to Fig-2D
23-Nov-2000 3.0 SBGA package information removed to an annex document
-R range changed to being the -S range, and the new -R range added
19-Feb-2001 3.1
SBGA package information put back in this document
Lead Soldering Temperature in the Absolute Maximum Ratings table amended
Write Cycle Polling Flow Chart using ACK illustration updated
References to PSDIP changed to PDIP and Package Mechanical data updated
W ording brought in to line with standard glossary
20-Apr-2001 3.2 Revision of DC and AC characteristics fo r the -S series
08-Oct-2001 3.3 Ball numbers added to the SBGA connections and package mechanical illustrations
09-Nov-2001 3.4 Specification of Test Condition for Leakage Currents in the DC Characteristics table
improved
30-Jul-2002 3.5 Document reformatted using new template. SBGA5 package removed
TSSOP8 (3x3mm² body size) package (MSOP8) added. -L voltage r ange added
04-Feb-2003 3.6 Document title spelt out more fully. “W”-marked devices with tw=5ms added.
05-May-2003 3.7 -R voltage range upgraded to 400kHz working, and no longer preliminary data.
5V voltage range at temperature range 3 (-xx3) no longer preliminary data.
-S voltage r ange removed. -Wxx3 voltage+temp ranged added as preliminary data.
07-Oct-2003 4.0 Table of contents, and Pb-free options added. Minor wording changes in Summar y
Description, Power-On Reset, Memory Addressing, Read Operations. VIL(min) improved to
-0.45V. tW(max) value for -R voltage range corrected.
17-Mar-2004 5.0
MLP package added. Absolute Maximum Ratings for VIO(min) and VCC(min) changed.
Soldering temperature information clarified for RoHS compliant devices. Device grade
infor m ation clarified. Process identification letter “G” information added. 2.2-5.5V range is
removed, and 4.5-5.5V range is now Not for New Design
7-Oct-2005 6.0 Product List summary table added. AEC-Q100-002 compliance. Device Grade informaton
clarified. Updated Device internal reset section, Figure 4., Figure 5., Table 14. and Table
20. Added Ecopack® information. Updated tW=5ms for the M24Cxx-W.
17-Jan-2006 7.0
Pin numbers removed from silhouettes (see Figure 1., Packages). Internal Device Reset
paragraph moved to below Supply voltage (VCC). Supply voltage (VCC) added below
SIGNAL DESCRIPTION. Test conditions for VOL updated in Table 8. and Table 9. SO8N
package specifications updated (see Table 16.)
New definition of ICC1 over the whole VCC range (see Tables 8, 9 and 10).
M24C16, M24C08, M24C04, M24C02, M24C01
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