W83303AD/W83303AG
Nuvoton
Advanced ACPI Controller
W83303AD/W83303AG
W83303AD/W83303AG
W83303AD/AG
Data Sheet Revision History
Pages Dates Version Version
on Web Main Contents
1 N.A. N.A.
All of the versions before 0.50 are for internal
use.
2 N.A. 10/25/04 0.5 N.A. First published preliminary versio n.
3 N.A. 12/20/04 0.51 N.A. Add part no of W8303AG with Pb-free
package.
4 12,13,14 1/09/06 0.52 N.A. Modified the application circuit.
5
6
7
8
Please note that all data and specifications are subject to change without notice. All the trademarks of
products and companie s mentioned in this data sheet belong to their respe ctive o wne rs.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or
systems where malfunction of these products can reasonably be expected to result in
personal injury. Nuvoton customers using or selling these products for use in such
applications do so at their own risk and agree to fully indemnify Nuvoton for any
damages resulting from such improper use or sales.
W83303AD/W83303AG
Publication Release Date: Jan. 9, 2006
- 1 - Revision 0.52
1. GENERAL FUNCTION DESCRIPTION
y Provides Voltages
− 5V Active/Sleep (5VDUAL)
− Programmable 5VDL/5VSTR/5VCC for USB Devices(5VUSB)
− 3.3V Active/Sleep (3.3VDUAL)
− Programmable Dual-Chan nels RAM Active/Sleep (VSTR) for DDR
− Auto-detective 2.6VSTR/1.8VSTR for DDR/DDRII Voltage
− Two Programmable Linear Regulators and one Linear Regulator Ranging 1.2V~5.00V for
Over-Clocking Application
− 1.2V VCCVID for Intel® P4 CPU or FSB_VTT for Grandsdale
− 1.5V VPCI Voltage
y Supports VRGOOD signal for Intel® P4 CPU Power Good Control
y Supports RSMRST# Signal Control
y Provides Signals for ATX Power Supply PS_ON# Control
y I2C Interface
y Selectable I2C Address
y Internal Charge Pump Support Up to 9.5VSB
y Drive All N-Channel MOSFET
y Soft Start
y Under-Voltage Monitoring for 3VDUAL, VPCI and VRAM Channel s
W83303AD/W83303AG
2. W83303AD/AG PIN-OUT
LR1_DRV
VCC
VPCI_SEN
VPCI_DRV
AGND
CHRPMP
C2
C1
5VSB
1.2V_DRV
1.2V_SEN
VRGOOD
S3#
S5#
I2C_DATA
I2C_CLK
RSMRST#
PWM_MODE
LR3_SEN
LR3_DR V
AGND
5VUSB
5VSBDRV
3V/5VDRV
1 2 3 4 5 6 7 8 9 10 11 12
13
14
15
16
17
18
19
20
21
22
23
24
36 35 34 33 32 31 30 29 28 27 26 25
48
47
46
45
44
43
42
41
40
39
38
37
LR1_SEN
LR2_DRV
LR2_SEN
DDRDET#
FAULT#
PS_IN#
PW_BUT#
PS_OUT#
DGND
PWR_OK
A0
D5VSB
AGND
VRAM_DRV1
I_SEN1
VRAM_SEN
VRAM_DRV2
I_SEN2
5VSB
ISET
SS
VCC3
3.3VSB_DRV
3.3V_SEN
W83303AD/AG
- 2 -
W83303AD/W83303AG
Publication Release Date: Jan. 9, 2006
- 3 - Revision 0.52
3. PIN DESCRIPTIONS
NO NAME I/O FUNCTION DESCRIPTION
1 S3# I
2 S5# I
SYSTEM ACPI CONTROL SIGNALS
3 I2C_DATA I/O
4 I2C_CLK I
I2C Interface, and the default ID value are defined as 5CH (0101 110X) as
well as 5EH (0101 111X), and X is used to control read/write.
5 RSMRST# OD
A signal to indicate 3VDUAL power status. The signal will be issued after
82ms delay when the level of 3VDUAL higher than 2.8 V
6 PWM_MODE I
0=Internal RAM for Linear Mode;
1= external RAM for PWM Mode
7 LR3_SEN I
8 LR3_DRV O
Linear Regulators ranging form 1.2V to 5V and can be adjusted by
external resistors
9 AGND P Power ground
10 5VUSB O
11 5VSBDRV O
12 5VDRV O
Power switch for USB devises provides a programmable Voltage
(5VDUAL/5VSTR/ 5VCC) for USB devices. It can be set by register CR00
13 3.3V_SEN I
14 3.3VSB_DRV O
3.3VDUAL Voltage regulator
15 VCC3 P Power 3.3Vcc
16 SS I
Soft-Start pin. Attach a capacitor to this pin to determine the soft-start rate;
and the slew-rate of SS is set by adjust the capacity of the external
capacitor.
17 ISET I
A
ttached a specific external resistor to determine the internal reference
current.
18 5VSB P Power Pin
19 I_SEN2 I
20 VRAM_DRV2 O
21 VRAM_SEN I
22 I_SEN1 I
23 VRAM_DRV1 O
2 channels of VSTR output for DDR or DDRII with internal current sharing
design to balance the current on the channels. In which I_SEN1 & I_SEN2
pins should be connected together to 5VSB or 3VDUAL if only one
channel used. The DDR or DDRII determine by DDRDET#. If DDRDET#
=0 VRAM=DDR(2.6V) ; DDRDET#=1 VRAM=DDRII(1.8V).
24 AGND P Power ground
25 VRGOOD OD
The signal is applied for the Intel® Northwood CPU using; it’s a signal to
declare the CPU VID status.
W83303AD/W83303AG
- 4 -
Pin Descriptions, continued
NO NAME I/O FUNCTION DESCRIPTION
26 1.2V_SEN I
27 1.2V_DRV O
1.2VCC voltage regulator for Intel® P4 CPU application.
28 5VSB P Power Pin
29 C1 I
30 C2 I
31 CHRPMP P
Charge pump pins. It supports 10mA driving current and insures output
voltage 9V or above.
32 AGND P
Power pin
33 VPCI_DRV O
34 VPCI_SEN I
1.5V Voltage Regulator for PCI Express. If this power plane won’t be
used, the VPCI_SEN must be connected to 3VDUAL to avoid the fault
trigger of LUV event.
35 VCC P Power pin
36 LR1_DRV O
37 LR1_SEN I
38 LR2_DRV O
39 LR2_SEN I
Linear Regulators ranging form 1.2V to 5V and can be adjusted by
external resistors
40 DDRDET# I
A signal to indicate type of DDRRAM that plugged- in; low means 2.6V for
DDR and high means 1.8V for DDRII.
41 FAULT# I
Fault event be monitored; the chip shut the ATX power supply down
directly by control the PS_ON# signal as long as the fault events are
triggered.
42 PS_IN# Power on signal. Low active.
43 PW_BUT# I System PW_BUT for power sequen ce monitoring.
44 PS_OUT# O Pin to control ATX power supply.
45 DGND P Power ground.
46 PWR_OK I Power good input signal of ATX power supply.
47 A0 I I2C address selecting pin.
48 D5VSB P Power pin.
*VRGOOD & TYPEDET# can endure 0-12V level voltage.
W83303AD/W83303AG
4. INTERNAL BLOCK DIAGRAM
C2 S3#
PWR_OK
VPCI_DRV
VPCI_SEN
Reset
Integrated
Circuit
Charge
Pump Control
Circuit 3.3VDL
5VDL
5VUSB
VRAM
I2C
PCI express 1.5V
Soft Start
1.2V
VCCVID
Control
Register
RSMRST#
3.3V_SEN
3.3V_DRV
5VSBDRV
5VUSB
VRAM_DRV1
I_SEN11
VRAM_SEN1
VRAM_DRV2
I_SEN2
PS_IN#
FAULT#
PW_BUT#
PS_OUT#
VRGOOD
1.2V_DRV
1.2V_SEN
SS
1.20V
5VDRV
ISET Reference
Current
C1 CHRPMP S5# DDRDET#
LR_DRV1
LR_SEN1 LR_SEN2
LR_DRV2
A0
I2C_DATA
I2C_CLK
LR_SEN3
LR_DRV3
EXT_RAM
Publication Release Date: Jan. 9, 2006
- 5 - Revision 0.52
W83303AD/W83303AG
- 6 -
5. I2C COMMUNICATION PROTOCOL
The W83303AD/AG serial protocol accepts byte write, byte read operation from the controller. For the
byte write and byte read operations, the system controller can access individual indexed bytes. The
byte write and byte read protocol is outlined in following table. Besides, the slave receiver address is
0101 1110(5Eh).
BYTE WRITE BYTE READ
BIT DESCRIPTION BIT DESCRIPTION
1 Start 1 Start
2:8 Slave address – 7 bits 2:8 Slave address – 7 bits
9 Write 9 Write
10 Acknowledge from Slave 10 Acknowledge from slave
11:18
Command Code – 8 bits
‘1xxxxxx’ stands for byte
operation bit[6:0] of the command
code represents the offset of the
byte to be accessed
11:18
Command Code – 8 bits
‘1xxxxxx’ stands for byte operation
bit[6:0] of the command code
represents the offset of the byte to
be accessed
19 Acknowledge from slave 19 Acknowledge from slave
20:27 Data byte – 8 bits 20 Repeat start
28 Acknowledge from slave 21:27 Slave address – 7bits
29 Stop 28 Read
29 Acknowledge from slave
30:37 Data byte from slave – 8bits
38 Not Acknowledge
39 Stop
W83303AD/W83303AG
6. REGISTER DESCRIPTION
6.1 CR00 (5VUSB Setting Register, Default 0x00h, Read/Write)
Publication Release Date: Jan. 9, 2006
- 7 - Revision 0.52
6.2 CR01 (VPCI Voltage Setting Register, Default 0x00h, Read/Write)
Bit7~3: Reserved
BIT2 BIT1 BIT0 VAGP OUTPUT
0 0 0 1.50V
0 0 1 1.55V
0 1 0 1.60V
0 1 1 1.65V
1 0 0 1.70V
1 0 1 1.80V
1 1 0 1.90V
1 1 1 2.00V
6.3 CR02 (VRAM Voltage Setting Register, Default x000 0000 b, Read/Write)
Bit7 is reserved for signal DDRDET# Setting (Dynamic detect)
DDRDET#=H bit7=1 DDRII type, DDRDET#=L bit7=0 DDRI type.
Bit3,2, 1 and 0 are applied for DDRRAM output adjusting.
BIT7 BIT3 BIT2 BIT1 BIT0 VRAM OUTPUT
0 0 0 0 0 2.60V
0 0 0 0 1 2.50V
0 0 0 1 0 2.55V
0 0 0 1 1 2.65V
0 0 1 0 0 2.70V
0 0 1 0 1 2.80V
0 0 1 1 0 2.90V
0 0 1 1 1 3.00V
0 1 0 0 0 3.10V
0 1 0 0 1 3.20V
BIT1 BIT0 SUPPORT ACPI STATE
0 1 S0, S3
0 0 S0, S3, S5
1 1 S0
W83303AD/W83303AG
- 8 -
BIT7 BIT3 BIT2 BIT1 BIT0 VRAM OUTPUT
1 0 0 0 1 1.75V
1 0 0 1 0 1.85V
1 0 0 1 1 1.90V
1 0 1 0 0 1.95V
1 0 1 0 1 2.00V
1 0 1 1 0 2.05V
1 0 1 1 1 2.10V
1 1 0 0 0 2.20V
1 1 0 0 1 2.30V
6.4 CR03 (Linear Regulator 1,2 Voltage Setting Register, Default 0x 00h,
Read/Write)
VLR1: Bit2, 1 and 0 are applied for output voltage adjusting.
BIT2 BIT1 BIT0 PERCENTAGE OF VOLTAGE INCREASE
0 0 0 +0%
0 0 1 +2%
0 1 0 +4%
0 1 1 +8%
1 0 0 +12%
1 0 1 +16%
VLR2 : Bit2, 1 and 0 are applied for output voltage adjusting.
BIT6 BIT5 BIT4 PERCENTAGE OF VOLTAGE INCREASE
0 0 0 +0%
0 0 1 +2%
0 1 0 +4%
0 1 1 +8%
1 0 0 +12%
1 0 1 +16%
6.5 CR04 Chip ID
Power on default [7:0] = 1010,0001 b
Bit Name Read/Write Description
7-0 CHIPID[7:0] Read Only Nuvoton Chip ID number. Read this register will return
0xa1h for W83303AD/AG.
6.6 CR05 (Linear-Under-Voltage Setting Register) default 0x07
W83303AD/W83303AG
Publication Release Date: Jan. 9, 2006
- 9 - Revision 0.52
Bit0, 1 and 2 are applied for Linear-Under-Voltage Protection functions e nable/disable.
BIT0 1/0 Enable/disable VPCI LUV, default value=1
BIT1 1/0 Enable/disable VRAM LUV, default value=1
BIT2 1/0 Enable/disable Dual3.3V LUV, default value =1
BIT3 1/0 Enable/disable RSRMST# restart as release latching fault or LUV event
Default value = 0 (disable)
BIT4 1/0 Enable/disable Power Button release latching fault event.
Default value = 0 (disable)
BIT5 1/0 Enable/disable Power Button release latching LUV event.
Default value = 0 (disable)
6.7 CR06 Version ID
Power on default [7:0] = 0000,0000 b
Bit Name Read/Write Description
7-0 CHIPID[7:0] Read Only
Nuvoton Version ID number. Read this register will
return 0x00h for W83303AD/AG.
W83303AD/W83303AG
- 10 -
7. ELECTRICAL SPECIFICATION
7.1 AC CHARACTERISTICS
Vcc=5V
±
5 %, TA = 0
°
C to +70
°
C
PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS
VPCI Linear Regulator
Nominal Output Voltage 1.50 V CR01(bit2~0)=000
Regulation 4 %
Under-Voltage Falling
Threshold 70 %
VPCI_DRV Output Voltage 8 V I(VPCI_DRV) <
0.3mA
Vref Voltage Reference
Nominal Output Voltage 1.152 1.2 1.248 Iload < 1mA
1.2V Linear Regulator
Nominal Output Voltage 1.152 1.2 1.248 V
VRGood delay 2 mS After
1.2V_SEN>1.1V
VRAM Regulator
Nominal Output Voltage 2.60 V CR02(bit7)=0
Nominal Output Voltage 1.80 V CR02(bit7)=1
Regulation 4 %
Under-Voltage Falling
Threshold 70 %
MAX VRAM_DRV Output
Voltage 8 V
I(VRAM_DRV) <
0.3mA
Increase percentage of Linear Regula tor _1,2 ou tput voltage (% )
Nominal Output Voltage 0 %
Nominal Output Voltage 2 %
Nominal Output Voltage 4 %
Nominal Output Voltage 8 %
Nominal Output Voltage 12 %
Nominal Output Voltage 16 %
Soft Start Source current
Soft start current 20 uA
W83303AD/W83303AG
Publication Release Date: Jan. 9, 2006
- 11 - Revision 0.52
AC CHARACTERISTICS, continued
5VDUAL Switch Controller
5VDRV Output High
Voltage 9 Cap Loading
5VSBDRV Output High
Voltage 9 Cap Loading
5VUSB Output High
Voltage 9 Cap Loading
5VUSB SS Sourcing
Current 2.5 uA @ Soft-start
3.3VDUAL
Under-Voltage Falling
Threshold 70 %
MAX 3VSBDRV Output
Voltage 9 V
I(3VSBDRV) <
0.3mA
Charge Pump
Charge Pump Frequen cy 200 KHz
Charge Pump Voltage 9.5
W83303AD/W83303AG
8. APPLICATION CIRCUIT
8.1 Linear Mode
VCC5
VCC3
C26
10U
VTT
A0=LOW, I2C Add=0X5CH
C33
1000U
VRGOOD
S3#
5VSB
5VSB
C24
1000U
C20
1000U
3VDUAL
A0 DDRDET#
VRAM
C23
1000U
VCC3
VLR3=1.2X(R8+R10)/ R10
5VSB
Q3MOSFET N 2
13
VCC3
DDRDET#
R1
4.7K
Q9
MOSFET N
Q6MOSFET N
3VDUAL
5VUSB
5VDUAL
C17
1000U
C14
10U
Q12
MOSFET N
R4
R
R20 1K
R2
4.7K
DUAL/VSB/VSTR/VCC
R18 4.7K
5VSB
R8
R
Q4 NMOS
R9
4.7K S5#
C6
10U
A0=HIGH, I2C Add=0X5EH
C19
10U
VLR2=1.2X(R4+R5)/ R5
C9
1000U
C36
1000U
C18 0.1U
LR3_DRV
R16
1K
DDRDET#
R5
R
C7
10U
5VSB
RSMRST#
W5VSB
R11 1K
C42
1000U
PS_OUT#(to ATX)
Q7
MOSFET N
C40
0.1U
W5VSB
5VSB
W5VSB
A0
C5
1000U
R19
1K C39
1n
C2
0.1U
SDA
VRAM
C1
10U
Q5MOSFET N 2
13
A0
C10
0.1U
C3
0.1U
R21 1K
Q10
MOSFET N
SCL
5VDUAL
C15 0.1U
DUAL/VSB/VSTR/VCC
VCC5
R22
1K
VCC3
C32
1000U
C25
10U
1.2V
R13
100K
Q8
MOSFET N 2
13
PWR_OK(from ATX)
VRAM
R7
R
C21
1000U
C12
1000U
5VSB
C37
0.1U
C41
0.1U
3VDUAL
W83303AD
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
36
35
34
33
32
31
30
29
28
27
26
25
37
38
39
40
41
42
43
44
45
46
47
48
S3#
S5#
I2C_DATA
I2C_CLK
RSMRST#
PWM_MODE
LR3_SEN
LR3_DRV
AGND
5VUSB
5VSBDRV
3V/5VDRV
AGND
VRAM_DRV1
I_SEN1
VRAM_SEN
VRAM_DRV2
I_SEN2
5VSB
ISET
SS
VCC3
3.3VSB_DRV
3.3V_SEN
LR1_DRV
VCC
VPCI_SEN
VPCI_DRV
AGND
CHRPMP
C2
C1
5VSB
1.2V_DRV
1.2V_SEN
VRGOOD
LR1_SEN
LR2_DRV
LR2_SEN
DDRDET#
FAULT#
PS_IN#
PW_BUT#
PS_OUT#
DGND
PWR_OK
A0
D5VSB
R14 4m
R6
R
R15 4m
C38
1500U
DDRDET#=HIGH, VRAM=1.8V
W5VSB
C34
0.1U
C27
10U
FAULT#
LR3_DRV
DUAL/VSB/VSTR/VCC
C13
0.1U
U1
W83310S-R2/DS
1
2
3
4 5
6
7
8
VIN
GND
VREF
VOUT VCNTL
VCNTL
VCNTL
VCNTL
C22
0.1U
C30
0.33U
R3
5
C31
10U
VCC3/1.2V
VPCI
Q11
MOSFET N
2
13
3VDUAL
5VSB
C16
1000U
C35
1000U
PS_IN#
C29
1000U
R12
4.7K
Q2
MOSFET N
R17 4.7K
Q1
MOSFET N
C4
1000U
C8
1000U
DDRDET#=LOW, VRAM=2.6V
R10
R
VLR1=1.2X(R6+R7)/ R7
C11
1000U
C28
1000U
- 12 -
W83303AD/W83303AG
8.2 PWM Mode
3VDUAL
C24
10U
C3
0.1U
A0=LOW, I2C Add=0X5CH
5VUSB
C31
1000U
W5VSB
A0=HIGH, I2C Add=0X5EH
R4
R
Q6
MOSFET N 2
13
Q3MOSFET N 2
13
R16
4.7K
Q1
MOSFET N
W5VSB
C4
1000U
VRAM
VCC3
5VSB
C6
10U
5VSB
R17
100K
Q8
MOSFET N
C9
1000U
W83303AD
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
36
35
34
33
32
31
30
29
28
27
26
25
37
38
39
40
41
42
43
44
45
46
47
48
S3#
S5#
I2C_DATA
I2C_CLK
RSMRST#
PWM_MODE
LR3_SEN
LR3_DRV
AGND
5VUSB
5VSBDRV
3V/5VDRV
AGND
VRAM_DRV1
I_SEN1
VRAM_SEN
VRAM_DRV2
I_SEN2
5VSB
ISET
SS
VCC3
3.3VSB_DRV
3.3V_SEN
LR1_DRV
VCC
VPCI_SEN
VPCI_DRV
AGND
CHRPMP
C2
C1
5VSB
1.2V_DRV
1.2V_SEN
VRGOOD
LR1_SEN
LR2_DRV
LR2_SEN
DDRDET#
FAULT#
PS_IN#
PW_BUT#
PS_OUT#
DGND
PWR_OK
A0
D5VSB
R2
4.7K
3VDUAL
R9
R
C14
10U SDA
R10
R
R14 4.7K
VRAM
5VSB
FAULT#
C13
0.1U
C27
1500U
VLR1=1.2X(R7+R9)/ R9 R5 4.7K
C26
0.1U
R13
R
C17 0.1U
Q9
MOSFET N
2
13
C20
1000U
C5
1000U
5VSB
C35
2000U
5VSB
Q5MOSFET N
SCL
R6
R
C33
0.1U
C10
0.1U
VRGOOD
A0
PS_IN#
VCC3
C23
1000U
R7
R
C7
10U
C21
0.1U
DUAL/VSB/VSTR/VCC
S5#
DDRDET#=HIGH, VRAM=1.8V
R8 4.7KVLR3=1.2X(R10+R113)/ R13
PS_OUT#(to ATX)
C22
1000U
U1
W83310S-R2/DS
1
2
3
4 5
6
7
8
VIN
GND
VREF
VOUT VCNTL
VCNTL
VCNTL
VCNTL
R18
1K
C38
0.1U
C32
0.1U
VCC3
C19
1000U
LR3_DRV
VCC3/1.2V
R12
4.7K
DDRDET#
R11
4.7K S3#
C15
0.1U
PWR_OK(from ATX)
1.2V
C2
0.1U
A0
R19
1K
DDRDET#
5VDUAL
R20
1K
W5VSB
5VSB
C29
1n
C34
0.1U
A0
3VDUAL
DUAL/VSB/VSTR/VCC
Q4MOSFET N 2
13
C37
1000U
C12
1000U
Q7
MOSFET N
RSMRST# C16 0.1U
R1
4.7K C1
10U
R3
5
VRAM_REF
VTT
C28
0.33U
5VSB
LR3_DRV
C25
10U
VPCI_REF
C18
10U
C30
1000U
DDRDET#
VLR2=1.2X(R4+R6)/ R6
Q2
MOSFET N
R15 4.7K
VCC5
DDRDET#=LOW, VRAM=2.6V
DUAL/VSB/VSTR/VCC
C11
1000U
C36
1000U
5VDUAL
5VSB
C8
1000U
VCC5
W5VSB
Publication Release Date: Jan. 9, 2006
- 13 - Revision 0.52
W83303AD/W83303AG
VRAM
U3
W83320S
1
2
3
4
5
6
7 8
9
10
11
12
13
14
LGATE
VDD
VDDA
PWOK
GNDA
SS
COMP FB
VREF
BG_REF
BOOT
HGATE
GND
ISEN
5VDUAL
C55
2.2U
C63
0.22u
C56
2.2U
VRAM_REF
C46
0.1U 5VDUAL
L3 3.3U
C50
1000U
C48
0.22U
VPCI
C51 (OPT)
VPCI
VCC5
C54
0.22U
C45
6.8n
C39
0.22U
C59
2000U
C60
6.8n
VCC5
R31 10VCC5
D2
SCHOTTKY
R24
2.2
C66 (OPT)
R34
2.2
R33
4.7K
R36
49.9K C64
2000U
C52
2.2n
VCC5
Q12
NMOS
VPCI_REF
R35 33
C42
2.2U
R40
(OPT)
C61
0.1U
C40
2.2U
R38
(OPT)
C41
2.2U
VRAM
R27
100k
R37
100k
C47
0.1U
C43
2000U
R29
5.1K(1%)
R26
49.9K
R23
4.7K
C65
1000U
Q13
NMOS
C67
2.2n
R21 10
C68
(OPT)
L1 3.3U
R28
(OPT)
C62
0.1U
L2 1.5U
5VDUAL
D1
SCHOTTKY
R25 33
L4 1.5U
C53
(OPT)
C49
2000U
R39
5.1k
5VDUAL
U2
W83320S
1
2
3
4
5
6
7 8
9
10
11
12
13
14
LGATE
VDD
VDDA
PWOK
GNDA
SS
COMP FB
VREF
BG_REF
BOOT
HGATE
GND
ISEN
R32 5.6K
C58
2000U
R22 5.6K
Q11
NMOS
C57
2.2U
C44
2000U
R30
5.1K(1%)
Q10
NMOS
- 14 -
W83303AD/W83303AG
9. ORDERING INSTRUCTION
PART NO. PACKAGE REMARKS
W83303AD 48-pin LQFP
W83303AG 48-pin LQFP Pb-free package
10. HOW TO READ THE TOP MARKING
inbond
W83303AD
214658302
410GBR
A
inbond
W83303AG
214658302
410GBR
A
1st Line: Nuvoton Logo
2nd Line: Part No W83303AD, W83303AG (Pb-free package)
3rd Line: Wafer production serial number
4th Line: tracking code 410GBRA
410：Date code, 410 means package was made in ’04 week 10
G：Assembly ID, G means GR, A means ASE…etc.
B：Chip Version, A means version A, B means version B
RA：Nuvoton internal use
Publication Release Date: Jan. 9, 2006
- 15 - Revision 0.52
W83303AD/W83303AG
11. PACKAGE DIMENSION
Y
SEATING PLANE
D
E
D
H
e
b
A
2
A
1 12
48
A
1
36 25
37 24
H
13
L1
c
Controlling dimension: Millimeters
0.10
0
7
0
0.004
1.00
0.75
0.600.45
0.039
0.030
0.024
0.018
9.10
9.00
8.90
0.358
0.354
0.350
0.50
0.20
0.25
1.45
1.40
0.10
0.15
1.35
0.008
0.010
0.0570.055
0.026
7.10
7.00
6.90
0.280
0.276
0.272
0.004
0.006
0.053
Symbol Min Nom Max Max
No
m
Mi
n
Dimension in inch Dimension in mm
A
b
c
D
e
H D
H E
L
Y
0
A
A
L
1
1
2
E
0.008
0.006 0.15
0.20
0.020 0.35 0.65
0.100.05
0.002 0.004 0.006 0.15
7.00
6.90
0.280
0.276
0.272
0.014
7.10
9.10 9.00
8.900.358
0.354
0.350
7
W83303AD/W83303AG
Important Notice
Nuvoton products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, or for other applications intended to support or sustain life.
Furthermore, Nuvoton products are not intended for applications wherein failure of Nuvoton
products could result or lead to a situation wherein personal injury, death or severe property
or environmental damage could occur.
Nuvoton customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Nuvoton for any damages resulting from such improper
use or sales.
Publication Release Date: Jan. 9, 2006
- 17 - Revision 0.52