W83303AD/W83303AG Nuvoton Advanced ACPI Controller W83303AD/W83303AG W83303AD/W83303AG W83303AD/AG Data Sheet Revision History Pages Dates Version Version on Web Main Contents N.A. All of the versions before 0.50 are for internal use. 1 N.A. 2 N.A. 10/25/04 0.5 N.A. First published preliminary version. 3 N.A. 12/20/04 0.51 N.A. Add part no of W8303AG with Pb-free package. 4 12,13,14 1/09/06 0.52 N.A. Modified the application circuit. 5 6 7 8 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nuvoton for any damages resulting from such improper use or sales. W83303AD/W83303AG 1. GENERAL FUNCTION DESCRIPTION y y y y y y y y y y Provides Voltages - 5V Active/Sleep (5VDUAL) - Programmable 5VDL/5VSTR/5VCC for USB Devices(5VUSB) - 3.3V Active/Sleep (3.3VDUAL) - Programmable Dual-Channels RAM Active/Sleep (VSTR) for DDR - Auto-detective 2.6VSTR/1.8VSTR for DDR/DDRII Voltage - Two Programmable Linear Regulators and one Linear Regulator Ranging 1.2V~5.00V for Over-Clocking Application - 1.2V VCCVID for Intel(R) P4 CPU or FSB_VTT for Grandsdale - 1.5V VPCI Voltage Supports VRGOOD signal for Intel(R) P4 CPU Power Good Control Supports RSMRST# Signal Control Provides Signals for ATX Power Supply PS_ON# Control I2C Interface Selectable I2C Address Internal Charge Pump Support Up to 9.5VSB Drive All N-Channel MOSFET Soft Start Under-Voltage Monitoring for 3VDUAL, VPCI and VRAM Channels -1- Publication Release Date: Jan. 9, 2006 Revision 0.52 W83303AD/W83303AG LR1_DRV VCC VPCI_SEN VPCI_DRV AGND CHRPMP C2 C1 5VSB 1.2V_DRV 1.2V_SEN VRGOOD 2. W83303AD/AG PIN-OUT 36 35 34 33 32 31 30 29 28 27 26 25 LR1_SEN 37 24 AGND LR2_DRV 38 23 VRAM_DRV1 LR2_SEN 39 22 I_SEN1 DDRDET# 40 21 VRAM_SEN FAULT# 41 20 VRAM_DRV2 PS_IN# 42 19 I_SEN2 PW_BUT# 43 18 5VSB PS_OUT# 44 17 ISET DGND 45 16 SS PWR_OK 46 15 VCC3 A0 47 14 3.3VSB_DRV D5VSB 48 13 3.3V_SEN I2C_CLK RSMRST# 8 9 10 11 12 3V/5VDRV I2C_DATA 7 5VSBDRV S5# 6 5VUSB 5 AGND 4 LR3_DR V 3 LR3_SEN 2 PWM_MODE 1 S3# W83303AD/AG -2- W83303AD/W83303AG 3. PIN DESCRIPTIONS NO NAME I/O FUNCTION DESCRIPTION 1 S3# I 2 S5# I 3 I2C_DATA 4 I2C_CLK 5 RSMRST# OD 6 PWM_MODE I 7 LR3_SEN I 8 LR3_DRV 9 AGND P Power ground 10 5VUSB O 11 5VSBDRV O 12 5VDRV O 13 3.3V_SEN I 14 3.3VSB_DRV O 15 VCC3 16 SS I Soft-Start pin. Attach a capacitor to this pin to determine the soft-start rate; and the slew-rate of SS is set by adjust the capacity of the external capacitor. 17 ISET I Attached a specific external resistor to determine the internal reference current. 18 5VSB 19 I_SEN2 I 20 VRAM_DRV2 O 21 VRAM_SEN I 22 I_SEN1 I 23 VRAM_DRV1 O 24 AGND 25 VRGOOD SYSTEM ACPI CONTROL SIGNALS I/O I2C Interface, and the default ID value are defined as 5CH (0101 110X) as I well as 5EH (0101 111X), and X is used to control read/write. A signal to indicate 3VDUAL power status. The signal will be issued after 82ms delay when the level of 3VDUAL higher than 2.8V 0=Internal RAM for Linear Mode; 1= external RAM for PWM Mode Linear Regulators ranging form 1.2V to 5V and can be adjusted by O external resistors Power switch for USB devises provides a programmable Voltage (5VDUAL/5VSTR/ 5VCC) for USB devices. It can be set by register CR00 3.3VDUAL Voltage regulator P Power 3.3Vcc P Power Pin 2 channels of VSTR output for DDR or DDRII with internal current sharing design to balance the current on the channels. In which I_SEN1 & I_SEN2 pins should be connected together to 5VSB or 3VDUAL if only one channel used. The DDR or DDRII determine by DDRDET#. If DDRDET# =0 VRAM=DDR(2.6V) ; DDRDET#=1 VRAM=DDRII(1.8V). P Power ground OD The signal is applied for the Intel(R) Northwood CPU using; it's a signal to declare the CPU VID status. -3- Publication Release Date: Jan. 9, 2006 Revision 0.52 W83303AD/W83303AG Pin Descriptions, continued NO NAME I/O FUNCTION DESCRIPTION 26 1.2V_SEN I 27 1.2V_DRV O 28 5VSB 29 C1 I 30 C2 I 31 CHRPMP P 32 AGND P 33 VPCI_DRV 34 VPCI_SEN 35 VCC 36 LR1_DRV O 37 LR1_SEN I 38 LR2_DRV Linear Regulators ranging form 1.2V to 5V and can be adjusted by O external resistors 39 LR2_SEN I 40 DDRDET# I A signal to indicate type of DDRRAM that plugged- in; low means 2.6V for DDR and high means 1.8V for DDRII. 41 FAULT# I Fault event be monitored; the chip shut the ATX power supply down directly by control the PS_ON# signal as long as the fault events are triggered. 42 PS_IN# 43 PW_BUT# I 44 PS_OUT# O Pin to control ATX power supply. 45 DGND 46 PWR_OK I Power good input signal of ATX power supply. 47 A0 I I2C address selecting pin. 48 D5VSB 1.2VCC voltage regulator for Intel(R) P4 CPU application. P Power Pin Charge pump pins. It supports 10mA driving current and insures output voltage 9V or above. Power pin O 1.5V Voltage Regulator for PCI Express. If this power plane won't be used, the VPCI_SEN must be connected to 3VDUAL to avoid the fault I trigger of LUV event. P Power pin Power on signal. Low active. System PW_BUT for power sequence monitoring. P Power ground. P Power pin. *VRGOOD & TYPEDET# can endure 0-12V level voltage. -4- W83303AD/W83303AG 4. INTERNAL BLOCK DIAGRAM PWR_OK C1 C2 CHRPMP PW_BUT# S5# S3# DDRDET# RSMRST# PS_IN# FAULT# PS_OUT# Reset Integrated Circuit VRGOOD 3.3V_SEN Charge Pump Control Circuit 5VUSB 1.2V_SEN SS ISET VPCI_DRV 3.3V_DRV 5VDL 1.2V VCCVID 1.2V_DRV 3.3VDL Control Register Soft Start 5VDRV 5VSBDRV 5VUSB VRAM_DRV1 I_SEN11 Reference Current VRAM_SEN1 VRAM 1.20V VRAM_DRV2 I_SEN2 PCI express 1.5V VPCI_SEN EXT_RAM I2C LR_SEN1 LR_SEN2 LR_DRV1 LR_SEN3 LR_DRV2 LR_DRV3 -5- Publication Release Date: Jan. 9, 2006 Revision 0.52 I2C_CLK I2C_DATA A0 W83303AD/W83303AG 5. I2C COMMUNICATION PROTOCOL The W83303AD/AG serial protocol accepts byte write, byte read operation from the controller. For the byte write and byte read operations, the system controller can access individual indexed bytes. The byte write and byte read protocol is outlined in following table. Besides, the slave receiver address is 0101 1110(5Eh). BYTE WRITE BYTE READ BIT DESCRIPTION BIT DESCRIPTION 1 Start 1 Start 2:8 Slave address - 7 bits 2:8 Slave address - 7 bits 9 Write 9 Write 10 Acknowledge from Slave 10 Acknowledge from slave 11:18 Command Code - 8 bits `1xxxxxx' stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed 11:18 Command Code - 8 bits `1xxxxxx' stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed 19 Acknowledge from slave 19 Acknowledge from slave 20:27 Data byte - 8 bits 20 Repeat start 28 Acknowledge from slave 21:27 Slave address - 7bits 29 Stop 28 Read 29 Acknowledge from slave 30:37 Data byte from slave - 8bits 38 Not Acknowledge 39 Stop -6- W83303AD/W83303AG 6. REGISTER DESCRIPTION 6.1 CR00 (5VUSB Setting Register, Default 0x00h, Read/Write) 6.2 BIT1 BIT0 SUPPORT ACPI STATE 0 1 S0, S3 0 0 S0, S3, S5 1 1 S0 CR01 (VPCI Voltage Setting Register, Default 0x00h, Read/Write) Bit7~3: Reserved 6.3 BIT2 BIT1 BIT0 VAGP OUTPUT 0 0 0 1.50V 0 0 1 1.55V 0 1 0 1.60V 0 1 1 1.65V 1 0 0 1.70V 1 0 1 1.80V 1 1 0 1.90V 1 1 1 2.00V CR02 (VRAM Voltage Setting Register, Default x000 0000 b, Read/Write) Bit7 is reserved for signal DDRDET# Setting (Dynamic detect) DDRDET#=H bit7=1 DDRII type, DDRDET#=L bit7=0 DDRI type. Bit3,2, 1 and 0 are applied for DDRRAM output adjusting. BIT7 BIT3 BIT2 BIT1 BIT0 VRAM OUTPUT 0 0 0 0 0 2.60V 0 0 0 0 1 2.50V 0 0 0 1 0 2.55V 0 0 0 1 1 2.65V 0 0 1 0 0 2.70V 0 0 1 0 1 2.80V 0 0 1 1 0 2.90V 0 0 1 1 1 3.00V 0 1 0 0 0 3.10V 0 1 0 0 1 3.20V -7- Publication Release Date: Jan. 9, 2006 Revision 0.52 W83303AD/W83303AG BIT7 BIT3 BIT2 BIT1 BIT0 VRAM OUTPUT 1 0 0 0 1 1.75V 1 0 0 1 0 1.85V 1 0 0 1 1 1.90V 1 0 1 0 0 1.95V 1 0 1 0 1 2.00V 1 0 1 1 0 2.05V 1 0 1 1 1 2.10V 1 1 0 0 0 2.20V 1 1 0 0 1 2.30V 6.4 CR03 (Linear Regulator 1,2 Voltage Setting Register, Default 0x00h, Read/Write) VLR1: Bit2, 1 and 0 are applied for output voltage adjusting. BIT2 BIT1 BIT0 PERCENTAGE OF VOLTAGE INCREASE 0 0 0 +0% 0 0 1 +2% 0 1 0 +4% 0 1 1 +8% 1 0 0 +12% 1 0 1 +16% VLR2 : Bit2, 1 and 0 are applied for output voltage adjusting. 6.5 BIT6 BIT5 BIT4 PERCENTAGE OF VOLTAGE INCREASE 0 0 0 +0% 0 0 1 +2% 0 1 0 +4% 0 1 1 +8% 1 0 0 +12% 1 0 1 +16% CR04 Chip ID Power on default [7:0] = 1010,0001 b Bit Name Read/Write Description 7-0 CHIPID[7:0] Read Only Nuvoton Chip ID number. Read this register will return 0xa1h for W83303AD/AG. 6.6 CR05 (Linear-Under-Voltage Setting Register) default 0x07 -8- W83303AD/W83303AG Bit0, 1 and 2 are applied for Linear-Under-Voltage Protection functions enable/disable. BIT0 1/0 Enable/disable VPCI LUV, default value=1 BIT1 1/0 Enable/disable VRAM LUV, default value=1 BIT2 1/0 Enable/disable Dual3.3V LUV, default value=1 BIT3 1/0 Enable/disable RSRMST# restart as release latching fault or LUV event Default value = 0 (disable) BIT4 1/0 Enable/disable Power Button release latching fault event. Default value = 0 (disable) BIT5 1/0 Enable/disable Power Button release latching LUV event. Default value = 0 (disable) 6.7 CR06 Version ID Power on default [7:0] = 0000,0000 b Bit Name Read/Write Description 7-0 CHIPID[7:0] Read Only Nuvoton Version ID number. Read this register will return 0x00h for W83303AD/AG. -9- Publication Release Date: Jan. 9, 2006 Revision 0.52 W83303AD/W83303AG 7. ELECTRICAL SPECIFICATION 7.1 AC CHARACTERISTICS Vcc=5V 5 %, TA = 0C to +70C PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS V CR01(bit2~0)=000 VPCI Linear Regulator Nominal Output Voltage 1.50 Regulation 4 Under-Voltage Falling Threshold VPCI_DRV Output Voltage 70 % % 8 V I(VPCI_DRV) < 0.3mA Vref Voltage Reference Nominal Output Voltage 1.152 1.2 1.248 1.152 1.2 1.248 Iload < 1mA 1.2V Linear Regulator Nominal Output Voltage V 2 mS After 1.2V_SEN>1.1V Nominal Output Voltage 2.60 V CR02(bit7)=0 Nominal Output Voltage 1.80 V CR02(bit7)=1 VRGood delay VRAM Regulator Regulation 4 Under-Voltage Falling Threshold MAX VRAM_DRV Output Voltage 70 8 % % V Increase percentage of Linear Regulator _1,2 output voltage (%) Nominal Output Voltage 0 % Nominal Output Voltage 2 % Nominal Output Voltage 4 % Nominal Output Voltage 8 % Nominal Output Voltage 12 % Nominal Output Voltage 16 % 20 uA Soft Start Source current Soft start current - 10 - I(VRAM_DRV) < 0.3mA W83303AD/W83303AG AC CHARACTERISTICS, continued 5VDUAL Switch Controller 5VDRV Output High Voltage 9 Cap Loading 5VSBDRV Output High Voltage 9 Cap Loading 5VUSB Output High Voltage 9 Cap Loading 5VUSB SS Sourcing Current 2.5 uA 70 % @ Soft-start 3.3VDUAL Under-Voltage Falling Threshold MAX 3VSBDRV Output Voltage 9 V I(3VSBDRV) < 0.3mA Charge Pump Charge Pump Frequency Charge Pump Voltage 200 KHz 9.5 - 11 - Publication Release Date: Jan. 9, 2006 Revision 0.52 W83303AD/W83303AG 8. APPLICATION CIRCUIT 8.1 Linear Mode 5VSB 5VSB DUAL/VSB/VSTR/VCC R1 4.7K 5VSB R3 W5VSB R2 4.7K Q1 MOSFET N 5 C2 0.1U C3 0.1U C1 10U VLR2=1.2X(R4+R5)/ R5 C4 C5 1000U 1000U DUAL/VSB/VSTR/VCC DDRDET# FAULT# PS_IN# R4 R PS_OUT#(to ATX) PWR_OK(from ATX) DUAL/VSB/VSTR/VCC C6 10U VLR1=1.2X(R6+R7)/ R7 W5VSB A0 C7 10U R6 R C10 0.1U 1 VLR3=1.2X(R8+R10)/ R10 Q2 MOSFET N R5 R C8 1000U C9 1000U MOSFET N Q3 2 5VSB 5VDUAL S3# S5# SDA SCL R9 4.7K R10 R RSMRST# R11 1K 1 C14 10U 5VUSB LR3_DRV MOSFET N Q5 3 2 C20 1000U C21 1000U 1 2 3 4 5 6 7 8 9 10 11 12 S3# S5# I2C_DATA I2C_CLK RSMRST# PWM_MODE LR3_SEN LR3_DRV AGND 5VUSB 5VSBDRV 3V/5VDRV W83303AD LR1_DRV VCC VPCI_SEN VPCI_DRV AGND CHRPMP C2 C1 5VSB 1.2V_DRV 1.2V_SEN VRGOOD C25 10U VCC5 C13 0.1U 36 35 34 33 32 31 30 29 28 27 26 25 VCC3 NMOS C15 0.1U C18 0.1U VCC3 C16 1000U MOSFET N Q6 1.2V VRGOOD R12 4.7K C22 0.1U C23 1000U VCC3/1.2V C24 1000U 3VDUAL Q7 MOSFET N Q8 MOSFET N C33 1000U VRAM Q11 C30 R13 100K 3VDUAL C28 1000U 2 3 MOSFET N Q10 3 MOSFET N 2 Q9 C26 10U R14 4m C27 10U 1 VCC3 1 5VDUAL Q12 MOSFET N MOSFET N 3VDUAL C31 10U 0.33U C34 0.1U VCC3 C35 C36 1000U 1000U C37 0.1U W5VSB VRAM VRAM 3VDUAL U1 1 C38 1500U 2 3 R19 1K C17 1000U C19 10U W5VSB 5VSB VCC5 R16 1K VPCI Q4 13 14 15 16 17 18 19 20 21 22 23 24 5VSB C32 1000U R7 R D5VSB A0 PWR_OK DGND PS_OUT# PW_BUT# PS_IN# FAULT# DDRDET# LR2_SEN LR2_DRV LR1_SEN R8 R 3.3V_SEN 3.3VSB_DRV VCC3 SS ISET 5VSB I_SEN2 VRAM_DRV2 VRAM_SEN I_SEN1 VRAM_DRV1 AGND C12 1000U 48 47 46 45 44 43 42 41 40 39 38 37 LR3_DRV 3 C11 1000U C39 1n 4 VIN VCNTL GND VCNTL VREF VCNTL VOUT VCNTL W83310S-R2/DS A0=HIGH, I2C Add=0X5EH 8 R17 A0 7 R18 5VSB 4.7K DDRDET# 5VSB 6 A0=LOW, I2C Add=0X5CH DDRDET#=LOW, VRAM=2.6V 5 R20 C40 0.1U A0 VTT C41 R22 0.1U 1K DDRDET#=HIGH, VRAM=1.8V 4.7K C42 1000U - 12 - 1K R21 DDRDET# 1K C29 1000U R15 4m W83303AD/W83303AG 8.2 PWM Mode 5VSB 5VSB DUAL/VSB/VSTR/VCC R1 4.7K 5VSB R3 W5VSB R2 4.7K Q1 MOSFET N 5 C2 0.1U C3 0.1U C1 10U VLR2=1.2X(R4+R6)/ R6 C4 C5 1000U 1000U DUAL/VSB/VSTR/VCC DDRDET# FAULT# PS_IN# R4 R PS_OUT#(to ATX) PWR_OK(from ATX) DUAL/VSB/VSTR/VCC C6 10U R5 Q2 MOSFET N R6 R A0 C7 10U R7 R C10 0.1U 1 VLR3=1.2X(R10+R113)/ R13 A0=HIGH, I2C Add=0X5EH VLR1=1.2X(R7+R9)/ R9 W5VSB C8 1000U C9 1000U R8 R12 4.7K R13 R 5VUSB S3# S5# SDA SCL RSMRST# LR3_DRV MOSFET N Q4 3 2 C19 1000U R9 R 48 47 46 45 44 43 42 41 40 39 38 37 R11 4.7K 1 C14 10U D5VSB A0 PWR_OK DGND PS_OUT# PW_BUT# PS_IN# FAULT# DDRDET# LR2_SEN LR2_DRV LR1_SEN R10 R 1 2 3 4 5 6 7 8 9 10 11 12 S3# S5# I2C_DATA I2C_CLK RSMRST# PWM_MODE LR3_SEN LR3_DRV AGND 5VUSB 5VSBDRV 3V/5VDRV W83303AD 3.3V_SEN 3.3VSB_DRV VCC3 SS ISET 5VSB I_SEN2 VRAM_DRV2 VRAM_SEN I_SEN1 VRAM_DRV1 AGND C12 1000U 5VDUAL 4.7K A0 LR3_DRV 5VSB 3 C11 1000U 5VSB A0=LOW, I2C Add=0X5CH MOSFET N Q3 2 4.7K A0 C20 1000U 36 35 34 33 32 31 30 29 28 27 26 25 C13 0.1U DDRDET#=HIGH, VRAM=1.8V VPCI_REF C16 C17 C21 0.1U 13 14 15 16 17 18 19 20 21 22 23 24 5VSB LR1_DRV VCC VPCI_SEN VPCI_DRV AGND CHRPMP C2 C1 5VSB 1.2V_DRV 1.2V_SEN VRGOOD VCC5 C15 0.1U 0.1U 0.1U R14 4.7K DDRDET# VCC3 5VSB MOSFET N Q5 C18 10U W5VSB DDRDET#=LOW, VRAM=2.6V 1.2V R15 VRGOOD 4.7K DDRDET# R16 4.7K C22 1000U C23 1000U VCC3/1.2V VRAM C24 10U 5VSB VRAM 2 MOSFET N Q7 MOSFET N Q8 3 Q6 MOSFET N C30 1000U C31 1000U C26 0.1U R17 100K Q9 1 R18 1K C27 1500U C28 2 3 2 3 5VDUAL C25 10U 1 VCC3 1 VCC5 3VDUAL MOSFET N 3VDUAL U1 VRAM_REF R19 1K C29 1n 4 VIN VCNTL GND VCNTL VREF VCNTL VOUT VCNTL W83310S-R2/DS 3VDUAL 0.33U 8 7 6 5 C32 0.1U VTT C33 0.1U C34 R20 0.1U 1K VCC3 C36 C37 1000U 1000U C35 2000U C38 0.1U W5VSB - 13 - Publication Release Date: Jan. 9, 2006 Revision 0.52 W83303AD/W83303AG VRAM VRAM 5VDUAL R21 10 5VDUAL R23 4.7K C40 C41 2.2U 2.2U NMOS Q10 L1 R22 5.6K C39 0.22U U2 1 2 3 4 5 6 7 C46 0.1U LGATE VDD VDDA PWOK GNDA SS COMP ISEN GND HGATE BOOT BG_REF VREF FB 14 13 12 11 10 9 8 C52 2.2n C43 2000U C44 2000U C45 6.8n 5VDUAL NMOS Q11 VRAM_REF L2 R25 33 5VDUAL 1.5U R26 W83320S C51 R24 2.2 C42 2.2U D1 SCHOTTKY 3.3U C47 0.1U C48 0.22U 49.9K C49 2000U C50 1000U (OPT) R28 (OPT) R27 100k C53 (OPT) R29 5.1K(1%) R30 5.1K(1%) VPCI VPCI VCC5 R31 10 VCC5 R33 4.7K C55 C56 2.2U 2.2U NMOS Q12 L3 R32 5.6K C54 0.22U U3 1 2 3 4 5 6 7 C61 0.1U LGATE VDD VDDA PWOK GNDA SS COMP ISEN GND HGATE BOOT BG_REF VREF FB 14 13 12 11 10 9 8 C67 2.2n C58 2000U C60 6.8n VCC5 NMOS Q13 VPCI_REF L4 R35 33 VCC5 1.5U R36 W83320S C66 R34 2.2 C57 2.2U D2 SCHOTTKY 3.3U C62 0.1U 49.9K (OPT) R38 (OPT) R37 100k R40 (OPT) R39 5.1k - 14 - C68 (OPT) C63 0.22u C64 2000U C65 1000U C59 2000U W83303AD/W83303AG 9. ORDERING INSTRUCTION PART NO. PACKAGE W83303AD 48-pin LQFP W83303AG 48-pin LQFP REMARKS Pb-free package 10. HOW TO READ THE TOP MARKING inbond W83303AD 214658302 410GBRA inbond W83303AG 214658302 410GBRA 1st Line: Nuvoton Logo 2nd Line: Part No W83303AD, W83303AG (Pb-free package) 3rd Line: Wafer production serial number 4th Line: tracking code 410GBRA 410Date code, 410 means package was made in '04 week 10 GAssembly ID, G means GR, A means ASE...etc. BChip Version, A means version A, B means version B RANuvoton internal use - 15 - Publication Release Date: Jan. 9, 2006 Revision 0.52 W83303AD/W83303AG 11. PACKAGE DIMENSION HD D A 36 A 2 25 37 24 48 13 A 1 HE E 1 b e 12 c SEATING PLANE L Y L1 Controlling dimension: Millimeters Symbol Dimension in inch Dimension in mm No Max m Min Nom Max Mi n 0.002 0.004 0.006 0.05 0.053 0.055 0.057 1.35 1.40 1.45 0.006 0.008 0.010 0.15 0.20 0.25 c 0.004 0.006 0.008 0.10 0.15 0.20 D 0.272 0.276 0.280 6.90 7.00 7.10 E 0.272 0.276 0.280 6.90 7.00 7.10 0.014 0.020 0.026 0.35 0.50 0.65 D 0.350 0.354 0.358 8.90 9.00 9.10 E 0.350 0.354 0.358 8.90 9.00 9.10 0.018 0.024 0.030 0.45 0.60 0.75 A A A 1 2 b e H H L L 1 Y 0 0.15 1.00 0.039 0.10 0.004 0 0.10 7 0 7 W83303AD/W83303AG Important Notice Nuvoton products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Furthermore, Nuvoton products are not intended for applications wherein failure of Nuvoton products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nuvoton for any damages resulting from such improper use or sales. - 17 - Publication Release Date: Jan. 9, 2006 Revision 0.52