DEMO MANUAL DC178 HIGH SPEED ADC LTC1418 (200ksps) 14-Bit A/D Converter Demo Board DESCRIPTIO U The LTC 1418 is a 4s, 200ksps sampling A/D converter that draws 15mW. The LTC1418 demo board provides the user with a way to evaluate the LTC1418 A/D converter. The LTC1418 is equipped to handle serial or parallel data transfer. The demo board allows the user to select the desired interface. In addition, the LTC1418 demo board is intended to illustrate the layout and bypassing techniques required to obtain optimum performance from this part. The LTC1418 demo board is designed to be easy to use and requires only 7V to 15V supplies, a conversionstart signal and an analog input signal (single-ended or differential). As shown in the Board Photo, the LTC1418 is a very space-efficient solution for A/D users. Combining a 14-bit A/D, sample-and-hold and reference in a single SO package allows all the data acquisition circuitry, including the bypass capacitors, to be placed in an area of only 0.22 inch2 when operating on split supplies and only 0.2 inch2 with single-supply operation. This manual shows how to use the demo board. Included are timing diagrams, power supply requirements and analog input range information. Additionally, a schematic, parts list, drawings and dimensions of all the PC board layers are included. An explanation of the layout and bypass strategies used in this board is also included, so that anyone designing a PC board using the LTC1418 will be able to get the maximum performance from the device. The LTC1418 and its demo board are intended for, but not limited to, signal acquisition and processing, high resolution and industrial data acquisition applications and battery-powered equipment, especially those that benefit from a 2.048V input range. Gerber files for this circuit board are available. Call the LTC factory. Some key features of this demo board include: * Proven 200ksps 14-bit ADC surface mount layout * Actual ADC footprint is only 0.22 inch2 including bypass capacitors * 81.5dB SINAD and - 94dB THD with a 100kHz fullscale sine wave input , LTC and LT are registered trademarks of Linear Technology Corporation. W U U TYPICAL PERFOR A CE CHARACTERISTICS A D BOARD PHOTO 4096 Point FFT of LTC1418 Demo Board 0 fSAMPLE = 200kHz fIN = 97.509765kHz SFDR = 94.29 SINAD = 81.4 AMPLITUDE (dB) -20 -40 -60 -80 -100 -120 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY (kHz) 1418 F02b 1 J7 J5 JP5A JP5B 1 2 3 SER/PAR CS SHDN HC14 U7A R16 75 C8 1F 16V JP2 JP4 DGND JP5C VOUT LT1121-5 3 DGND HC14 U7B C13 10F 16V C11 2200pF R15 75 GND TABGND D15 2 4 SS12 VIN R19 51 R18 10k R17 10k 1 U2 4 1 2 5 4 6 VSS HC14 U7C C4 0.1F 8 C14 0.1F + 19 1 EN2 EN1 R20 10k 2 1 VSS 13 10 20 4 7 U8B U8 74HC244 U8F 9 SINGLE DUAL 74HC244 U8E 74HC244 11 D6 D7 D8 D9 D10 16 1 B13 B00 B01 B02 B03 B04 15 B05 13 B06 12 B07 B04 B03 B02 B01 B00 EXTCLKIN SCLK CLKOUT DOUT 14 17 3 18 U8C 12 6 74HC244 U8H 74HC244 R23 100k VLOGIC B06 B07 B08 B09 2 U8G DGND U8D 8 74HC244 15 74HC244 U8A 74HC244 13 B11 10 B09 B10 B12 B10 9 5 VSS Q6 Q7 D6 D7 J8-6 J8-2 J8-1 J8-3 J8-4 J8-5 HEADER 6-PIN HC14 12 7 GND U7 HC14 14 VCC VLOGIC Q5 Q4 Q3 Q2 Q1 Q0 D5 D4 D3 D2 D1 D0 0E U6 74HC574 Q7 Q6 D7 Q5 D6 Q4 Q3 Q2 Q1 Q0 D5 D4 D3 D2 D1 D0 0E D06 D07 D08 D09 D10 D11 D12 D13 D05 D04 D03 D02 D01 D00 C6 15pF R21 1k 12 13 14 15 16 17 18 19 12 13 14 15 16 17 18 19 C1 22F 10V U5 74HC574 U7F 9 8 7 6 5 4 3 2 11 B11 8 11 B08 1 9 8 B05 6 5 7 B04 B03 4 3 B01 B02 2 11 B00 1 D14 SS12 B12 EXT/INT VOUT 3 7 JP6 SUPPLY SELECT BUSY VIN U1 LT1175-5 TAB GND B[00:13] 4 2 B13 -VIN J1 -7V TO -15V 6 D5 SER/PAR 16 (EXTCLKIN) D4 VDD 17 (SCLK) D3 BUSY 18 (CLKOUT) D2 VSS 19 (DOUT) D1 AGND 20 (EXT/INT) D0 DGND SHDN RD CONVST CS D11 D12 D13 C15 0.1F VLOGIC U4 LTC1418ACG C7 0.1F REFCOMP VREF AIN- AIN+ C5 10F 3 16V 14 5 27 26 28 21 22 23 24 25 4 3 2 1 C10 10F 10V VLOGIC VLOGIC 74HC244 C9 10F 16V VCC C3 0.1F 1 U3 7 LT1363 - 6 VCC V- 3 R14 20 0.125W C12 0.1F 3 + V+ 2 VOUT JP7 C2 22F 10V JP3 R22 1M + VCC NOTES: UNLESS OTHERWISE SPECIFIED 1. ALL RESISTOR VALUES IN OHMS, 1/10W, 5% 2. ALL CAPACITOR VALUES IN F, 25V, 20% AND IN pF, 50V, 10% VLOGIC CLK A- A+ AGND J2 J4 GND +VIN J3 7V TO 15V + 2 VCC 9 11 HC14 U7D HC14 U7E D[00:13] 8 10 D13 D3 D03 R3 RDY D13 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 D13 D12 D11 J6-12 J6-11 J6-14 JP1 LED D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 DGND J6-18 DC178 * SCHEMATIC HEADER 18-PIN BUSY VREF AIN - AIN+ 9 8 7 6 5 4 3 2 1 LTC1418ACG TOP VIEW 15 D5 16 D4 17 D3 18 D2 19 D1/(DOUT) 20 D0 21 SER/PAR 22 SHDN 23 RD 24 CONVST 25 CS 26 BUSY 27 VSS 28 VDD LTC1418ACG SW PACKAGE 28-LEAD PLASTIC SO DGND 14 D6 13 D7 12 D8 11 D9 10 D10 D11 D12 D13 AGND REFCOMP RDY (PARALLEL) D13 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 J6-17 J6-16 J6-15 J6-2 J6-1 J6-4 J6-3 J6-6 J6-5 J6-8 J6-7 J6-10 J6-9 D9 D8 D7 D6 D5 D10 J6-13 D13 R13 D12 R12 D11 R11 D10 R10 D09 R9 D08 R8 D07 R7 D06 R6 D05 R5 D4 D2 D02 R2 D04 R4 D1 D0 D01 R1 D00 R0, 1k LTC1418 Demonstration Board Features Analog Input Signal Buffer, 200ksps Parallel and Serial Data Output 14-Bit ADC, Data Latches and LED Binary Data Display. Latched Conversion Data is Available on the 18-Pin Header, J6 DEMO MANUAL DC178 HIGH SPEED ADC U W W PACKAGE AND SCHEMATIC DIAGRAMS DEMO MANUAL DC178 HIGH SPEED ADC PARTS LIST REFERENCE DESIGNATOR C1, C2 C3, C4, C7, C12, C14, C15 C5, C9, C10, C13 C6 C8 C11 D0-D13 D14, D15 J1-J3 J4, J5, J7 J6 J8 JP1 JP2-JP4 JP5 JP6, JP7 R0-R13, R21 R14 R15, R16 R17, R18, R20 R19 R22 R23 U1 U2 U3 U4 U5, U6 U7 U8 QUANTITY 2 6 4 1 1 1 14 2 3 3 1 1 1 3 1 2 15 1 2 3 2 1 1 1 1 1 1 2 1 1 6 4 4 2 PART NUMBER TAJC226M010R 08053C104MAT1A DESCRIPTION 22F 10V 20% Tantalum Capacitor 0.1F 25V 20% X7R Capacitor VENDOR AVX AVX TELEPHONE (803) 946-0690 (803) 946-0362 1210YG106ZAT1A 08055A150KAT1A 0805YG105ZAT1A 08053A222KAT1A SML-LX0805SRC-TR SS12-PKG11 575-4 112404 3201S-18G1 3201S-06G1 2802S-02-G2 JL-100-25-T 2202S-06-G2 2802S-03-G2 CR10-102J-M CR18-200J-M CR10-750J-M CR10-510J-M CR10-510J-M CR10-510J-M CR10-510J-M LT1175CST-5 LT1121CST-5 LT1363CS8 LTC1418ACG MC74HC574ADT MC74HC14ADT MC74HC244ADT CCIJ2MM-138-G 10F 16V Y5V Capacitor 15pF 50V 10% NPO Capacitor 1F 16V Y5V Capacitor 2200pF 25V 10% NPO Capacitor 2.1V 15mA Super Red SMT Led 20V 1A SMA Schottky Diode Standard Banana Jack Connector 50 PCB-Vertical BNC Connector 0.100cc 18-Pin 2-Row Header Connector 0.100cc 3-Pin 2-Row Header Connector 2mm 2-Pin Jumper 0.100cc 22-AWG Wire Jumper 2mm 3-Pin 2-Row Jumper 2mm 3-Pin Jumper 1k 1/10W 5% Chip Resistor 20 1/8W 5% Chip Resistor 75 1/10W 5% Chip Resistor 10k 1/10W 5% Chip Resistor 51 1/10W 5% Chip Resistor 1M 1/10W 5% Chip Resistor 100k 1/10W 5% Chip Resistor - 5V SO-8 IC Regulator 5V S0T-223 IC Regulator SO-8 IC Op Amp 14-Bit SOL-28 IC ADC MSOP-20 IC Octal D Flip Flop MSOP-14 IC Hex Inverter Schmitt MSOP-20 IC Octal Buffer 2mm SHUNT #4-40 1/4" SCREW #4-40 1/2" Nylon Hex STANDOFF 0.100cc SHUNT AVX AVX AVX AVX Lumex General Inst Keystone CONNEX COMM CON COMM CON COMM CON Samtec COMM CON COMM CON TAD TAD TAD TAD TAD TAD TAD LTC LTC LTC LTC Motorola Motorola Motorola COMM CON Any Keystone COMM CON (803) 946-0362 (803) 946-0362 (803) 946-0362 (803) 946-0362 (847) 359-2790 (516) 847-3000 (718) 956-8900 (805) 378-6464 (818) 301-4200 (818) 301-4200 (818) 301-4200 (800) 726-8329 (818) 301-4200 (818) 301-4200 (800) 508-1521 (800) 508-1521 (800) 508-1521 (800) 508-1521 (800) 508-1521 (800) 508-1521 (800) 508-1521 (408) 432-1900 (408) 432-1900 (408) 432-1900 (408) 432-1900 (800) 441-2447 (800) 441-2447 (800) 441-2447 (818) 301-4200 CCIJ335-138-G (718) 956-8900 (818) 301-4200 U OPERATIO OPERATING THE BOARD provides 5V for analog and digital circuitry and the MC79L05 regulator (U1) provides - 5V for the A/D and buffer. Powering the Board To use the demo board, apply 7V to 15V at 200mA to the banana jacks J1 and J3 and 0V (GND) to J2. Be careful to observe the correct polarity. Onboard regulators provide 5V to the LTC1418. An LT (R) 1121-5 regulator (U2) The Analog Input The LTC1418 has a unique feature not found on previous ADCs: differential inputs with good common mode rejection from DC to over 5MHz. Although this feature is 3 DEMO MANUAL DC178 HIGH SPEED ADC U OPERATIO extremely valuable for rejecting noise and measuring differential signals, the board can also be used to evaluate the LTC1418 in single-ended mode (with the "-" input grounded). A simple jumper selection at JP4 allows evaluation in either mode. Differential (bipolar) analog signals are applied to the LTC1418 demo board using BNC connectors J4 (noninverting + input) and J5 (inverting - input). The analog signal input range is 2.048V when operating on 5V and 0V to 4.096V when using a single 5V supply. + - The LTC1418 A IN (noninverting) and A IN (inverting) inputs have a common mode range of VSS to VDD. The full-scale differential between the signals applied to AIN+ and AIN- is 2.048V. For example, when a 1.5V signal is applied to the AIN- input, the negative-to-positive full-scale input range of AIN+ is - 0.548V to 3.548V, corresponding to an output code of 10 0000 0000 0000 to 01 1111 1111 1111. The demo board is delivered with jumpers JP2 and JP4 closed and jumper JP6 set for dual supply. This configures the board for a 2.048V input signal centered around ground and applied to J4 (AIN+). For unipolar inputs (0V to 4.096V) set JP6 to single-supply and open JP4. The board includes a recommended lowpass filter (R15, R16 and C11) across the differential inputs. With the component values shown, the cutoff frequency (fs) is: 1 = 482kHz 2(150)(0.0022F) LT1363 demonstrates how to properly drive the LTC1418. When using the LT1363, open JP2 and close JP4 and JP3. Optimum performance is achieved using a signal source that has low output impedance, is low noise and has low distortion. Signal generators, such as the B & K Type 1051 Sine Generator, give excellent results. Further, this generator can be configured to operate referenced to a master clock signal, as shown in Figure 1. REFERENCE FREQUENCY IN BRUEL & KJAER TYPE 1051 SINE GENERATOR 4 VIN J4 LTC1418 14-BIT A/D DEMO BOARD HEWLETT PACKARD HP3326A REFERENCE GENERATOR FREQUENCY OUT CLOCK J7 J6 1-14 DOUT HEWLETT PACKARD HP1663A LOGIC ANALYZER CONVST CLK DC178 * F01 Figure 1. Typical Setup for LTC1418 Demo Board CONVST BUSY DATA READY These values can be altered to meet other circuit and inputsignal requirements. For lower bandwidth input signals, increase the value of C11. For undersampling applications that take advantage of the input circuitry's wide bandwidth, decrease the capacitance of C11. The best way to observe the performance of the LTC1418 is to drive it directly from a low impedance signal source. However, since some applications involve high output impedance sources, the board also has provisions for an onboard LT1363 high speed operational amplifier. The LT1363, operating as a noninverter buffer, provides the LTC1418 with a fast settling, low impedance signal that allows the input voltage to fully settle before starting a conversion. The buffer is recommended if the source impedance of the input signal is greater than 930. The OUT DC178 * F02 Figure 2. Timing Diagram <420ns >40ns GOOD CONVST BUSY DATA READY DC178 * F03 Figure 3. Alternative Timing Diagram DEMO MANUAL DC178 HIGH SPEED ADC U OPERATIO Applying the Conversion Start Signal A conversion is initiated by a falling edge on the CONVST input (BNC J7). The CONVST input uses TTL or CMOS levels. As shown in Figure 2, CONVST should remain low until the conversion is completed or returned high within 420ns of the negative-going edge, as shown in Figure 3. During a conversion, transitions on the CONVST input can cause errors in the conversion data. configuration are active only when a logic low is applied to the CS and RD pins. The data outputs are in a high impedance state for any other logic combination on the CS and RD pins. Table 1 is a summary of the configurations and connections for the four serial modes. Figures 4 through 7 are timing diagrams for the serial interface. Refer to the LTC1418 data sheet for more details on the serial interface modes. DATA OUTPUT INTERFACE PARALLEL INTERFACE The LTC1418 features a versatile data interface that connects to a parallel or serial data bus. The SER/PAR pin configures the LTC1418 for the desired interface. The SER/PAR pin is accessed through jumper JP5A. For onboard control, shorting JP5A applies a logic low to the SER/PAR pin, configuring the LTC1418 for parallel data. Opening JP5A applies a logic high to the SER/PAR pin through R20, which is connected to 5V. This logic high reconfigures the LTC1418's data outputs for a serial bus, changing the function of Pin 16 through Pin 20 from parallel data outputs to a serial data interface. The remaining data outputs are placed in a high impedance state. Select the desired interface by opening JP5A and applying the appropriate logic level to JP5A, Pin 2. The SER/PAR logic signal source must be able to sink current to ground through a 10k resistor (R20). The data outputs of either Applying a logic low to the SER/PAR pin configures the LTC1418 for a parallel data bus. The LTC1418's pins 20 through 15 and pins 13 through 6 correspond to parallel bits D0 to D5 and D6 to D13. These data bits are found on J6, Pin 1 through Pin 14, along with an end of conversion signal (RDY) on Pin 16. For performing an AC test using FFTs that require unsigned binary, the MSB is inverted and available on J6, Pin 15 (D13). SERIAL INTERFACE Serial Data Output During a Conversion In the two modes that follow, the serial data, beginning with the MSB, is present on DOUT (Pin 19 on the LTC1418 and Pin 4 on J8) during the conversion. Since the BUSY signal is a logic low during conversions, it can serve as a frame signal in applications using DSPs. Table 1. Serial Data Mode Configuration and Connection Summary Data During Conversion Inputs/Outputs EXT/INT SCLK Signal RD Internal Conversion and Serial Data Clocks Short J8-5 to J8-6 CONVST Signal External Conversion and Serial Data Clocks Internal Conversion and External Serial Data Clocks J8-5 Open Short J8-5 to J8-6 J8-5 Open Short J8-1 to J8-3 Apply External Clock Source to J8-1 Apply External Read Signal to JP7-2 Leave JP7-1 and JP7-3 Unconnected Apply External Clock Source to J8-2 Present on J8-3 Apply External Clock Source to J8-2 Present on J8-3 Apply to J7 DOUT Present on J8-4 BUSY Present on J6-17 SER/PAR External Conversion and Serial Data Clocks Short JP7-2 to JP7-3 EXTCLKIN CLKOUT Data After Conversion Open JP5A For Serial Operation CS Close JP5B SHDN Close JP5C 5 DEMO MANUAL DC178 HIGH SPEED ADC U OPERATIO Internal Conversion and Serial Data Shift Clocks DOUT is on J8-4 The mode shown in Figure 4 uses the LTC1418's internal conversion clock signal to shift out the conversion result on the DOUT pin. This mode uses the least wiring (just four lines, CONVST, BUSY, CLKOUT and DOUT) and requires no external clocks. The DOUT pin's output state (high impedance or active) is controlled by BUSY's logic state. While BUSY is a logic low, the serial data is shifted out on the DOUT pin (J8, Pin 4). The LTC1418 is configured for this mode by making the following connections: BUSY is on J6-17 External Conversion and Serial Data Shift Clocks CS = GND (close JP5B) The mode shown in Figure 5 uses an external clock signal to clock conversions and serial data. As in the previous mode, this mode also uses the least wiring (just four lines, CONVST, BUSY, EXTCLKIN and DOUT). The DOUT pin's output state (high impedance or active) is controlled by BUSY's logic state. While BUSY is a logic low, the serial data is shifted out on the DOUT pin (J8, Pin 4). The LTC1418 is configured for this mode by making the following connections: SHDN = VLOGIC (close JP5C) SER/PAR = VLOGIC (open JP5A) EXT/INT = GND (short J8-5 to J8-6) CS = GND (close JP5B) SCLK = CLKOUT (short J8-1 to J8-3) SHDN = VLOGIC (close JP5C) RD = BUSY (connect JP7-2 to JP7-3) EXT/INT = VLOGIC (nothing connected to J8-5) CONVST signal is applied to J7 SCLK = EXTCLKIN (short J8-1 to J8-2) CLKOUT is on J8-3 RD = BUSY (connect JP7-2 to JP7-3) SER/PAR = VLOGIC (open JP5A) CONVST 24 CONVST BUSY RD SCLK BUSY (= RD) 26 23 LTC1418 CLKOUT DOUT EXT/INT P OR DSP (CONFIGURED AS SLAVE) OR SHIFT REGISTER 17 18 CLKOUT ( = SCLK) 19 DOUT 20 CS 25 (SAMPLE N) t5 CS = EXT/INT = 0 (SAMPLE N + 1) CONVST t13 t6 t8 HOLD BUSY (= RD) SAMPLE HOLD t10 1 2 3 4 5 6 7 8 9 D13 D12 D11 D10 D9 D8 D7 D6 D5 10 11 12 13 14 15 16 1 2 3 D13 D12 D11 CLKOUT (= SCLK) t7 DOUT Hi-Z D4 D3 D2 D1 D0 FILL ZEROS D13 Hi-Z DATA (N - 1) tCONV DATA N t11 Figure 4. Internal Conversion Clock Selected. Data Transferred During Conversion Using the ADC Clock Output as a Master Shift Clock (SCLK Driven from CLKOUT). 6 178 F04 DEMO MANUAL DC178 HIGH SPEED ADC U OPERATIO CONVST signal is applied to J7 interface (BUSY, RD, CLKOUT and DOUT). The LTC1418 is configured for this mode by making the following connections: EXTCLKIN = signal from external clock source DOUT is on J8-4 SER/PAR = VLOGIC (open JP5A) BUSY is on J6-17 CS = GND (close JP5B) Serial Data Output After Conversion SHDN = VLOGIC (close JP5C) The two serial modes that follow potentially offer the best AC performance because error-producing switching noise is eliminated during conversion, since external clocks are inactive. In these modes, the serial data is available on DOUT (Pin 19 on the LTC1418 and Pin 4 on J8) after the conversion is completed. It begins with the MSB and can be shifted out anytime after the BUSY signal's logic low to logic high transition. The RD signal must be a logic low while clocking the data. It can serve as a frame signal in applications using DSPs. EXT/INT = GND (short J8-5 to J8-6) Internal Conversion Clock and External Data Clock External Conversion Clock and External Data Clock The mode shown in Figure 6 uses the internal clock signal for conversions and an external clock to shift the serial data. This mode adds just one more line to the serial The mode shown in Figure 7 uses an external clock signal to clock conversions and serial data. Although this mode has the most serial interface connections, it is also the CONVST 24 CONVST BUSY RD EXTCLKIN SCLK = signal from external serial shift-clock source (applied to J8-1) RD = external RD signal source is applied to JP7-2 (remove any shorts from JP7) CONVST signal is applied to J7 DOUT is on J8-4 BUSY is on J6-17 BUSY (= RD) 26 23 16 EXTCLKIN ( = SCLK) P OR DSP LTC1418 SCLK DOUT EXT/INT 17 DOUT 19 20 5V CS 25 (SAMPLE N) t5 CS = 0, EXT/INT = 5 (SAMPLE N + 1) CONVST t13 t6 t8 HOLD BUSY (= RD) SAMPLE HOLD t10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 D12 D11 EXTCLKIN (= SCLK) t7 DOUT Hi-Z D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FILL ZEROS D13 Hi-Z D13 DATA (N - 1) tCONV DATA N t11 178 F05 Figure 5. External Conversion Clock Selected. Data Transferred During Conversion Using the External Clock (External Clock Drives Both EXTCLKIN and SCLK). 7 DEMO MANUAL DC178 HIGH SPEED ADC U OPERATIO most versatile and flexible. By using two separate clocks (one clocks the conversion and another clocks the serial data), the conversion speed can be optimized for an application's requirements (source impedance, bandwidth, power dissipation, etc). The speed of the serial data can be set to what is needed by the processor, independent of the conversion clock. Conversely, this mode can be simplified by using the same clock signal for the conversion and data retrieval. This mode uses BUSY, RD, EXTCLKIN, CLKOUT and DOUT. The LTC1418 is configured for this mode by making the following connections: CONVST signal is applied to J7 EXTCLKIN = signal from external conversion clock signal source (applied to J8-2) DOUT is on J8-4 BUSY is on J6-17 Reading the Output Data The ADC's parallel data outputs are buffered by the two 74HC574 latches and are available on connector J6. The latches drive the LEDs and connector J6. In a practical circuit, latches are not required unless the ADC is tied to a noisy data bus. (Refer to the LTC1418 data sheet for details on different digital interface modes.) SER/PAR = VLOGIC (open JP5A) CS = GND (close JP5B) SHDN = VLOGIC (close JP5C) The output data format of the LTC1418 is two's complement. The data can be converted to offset binary by using D13 (J6-15) instead of D13. Offset binary is used when an FFT is to be performed on the sampled data. A Data Ready line (J6, Pin 16) is provided to latch the DOUT word. DOUT is valid on the rising edge of Data Ready. Two ground lines EXT/INT = VLOGIC (nothing connected to J8-5) SCLK = signal from external serial shift-clock source (applied to J8-1) RD = external RD signal source is applied to JP7-2 (remove any shorts from JP7) CONVST 24 CONVST BUSY RD SCLK 26 INT 23 C0 17 SCK P OR DSP LTC1418 DOUT EXT/INT 19 MISO 20 CS 25 t5 CS = EXT/INT = 0 CONVST t13 t6 t8 SAMPLE HOLD BUSY t9 t12 RD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCLK t10 Hi-Z DOUT D13 12 11 10 9 t11 8 7 6 5 4 3 2 1 0 FILL ZEROS Hi-Z (SAMPLE N) tCONV DATA N Figure 6. Internal Conversion Clock Selected. Data Transferred After Conversion Using an External SCLK. BUSY Indicates End of Conversion 8 178 F06 DEMO MANUAL DC178 HIGH SPEED ADC U OPERATIO these lines externally driven if desired. See the LTC1418 data sheet for details on driving these lines. are provided on the connector and should be connected to the receiving system's ground. The LTC1418 DOUT word can be acquired with a logic analyzer. Conversion data can be stored on a disk and easily transferred to a PC by using a logic analyzer that has a PC compatible floppy drive (such as an HP1663A). Once the data is transferred to a PC, use programs such as MathCAD or Excel to calculate FFTs. Use the FFTs to obtain LTC1418 AC specifications, such as signal-to-noise ratio and total harmonic distortion. LAYOUT A well-designed printed circuit board layout incorporating the LTC1418 uses separate analog and digital ground planes. Except for connecting them near U4's Pin 24, completely isolate the ground planes from each other. Additionally, they should not overlap if they are on different printed circuit board layers. Connecting the LTC1418 analog (AGND) and digital (DGND) pins to the analog ground plane ensures the lowest noise operation. The demonstration board layout (section titled "PCB Layout and Film") shows the best way to configure and connect the ground planes. To ensure maximum ground plane efficiency, especially for the analog ground plane, it is important to minimize plane-breaking traces. LEDs D0 to D13 provide a visual display of the LTC1418 digital output word. D0 and D13 display the logic state of the LSB and MSB, respectively. Remove jumper JP1 to disable the LEDs, reducing supply current consumption up to 37mA. Driving CS, RD and SHDN Pins Jumpers for SHDN, RD and CS (JP5A to JP5C) are shorted for normal operation. The jumpers can be removed and CONVST 24 16 CONVST EXTCLKIN BUSY CLKOUT 26 INT 23 RD C0 P OR DSP LTC1418 17 SCLK DOUT EXT/INT SCK 19 20 MISO 5V CS 25 1 CS = 0, EXT/INT = 5 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 EXTCLKIN t5 t7 CONVST t13 t6 t8 SAMPLE HOLD BUSY t9 t12 RD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D13 12 11 10 9 8 7 6 5 SCLK t10 Hi-Z DOUT t11 4 3 2 1 0 FILL ZEROS Hi-Z (SAMPLE N) tCONV DATA N 178 F07 Figure 7. External Conversion Clock Selected. Data Transferred After Conversion Using an External SCLK. BUSY Indicates End of Conversion 9 DEMO MANUAL DC178 HIGH SPEED ADC POWER SUPPLY CONNECTIONS AND BYPASSING Analog and digital positive supply pins, AVDD and DVDD respectively, are connected at the device and to the 5V supply with a single trace. The negative supply pin (VSS) is connected to the -5V supply. The best performance is achieved by careful attention to proper bypassing. Bypass VDD to the analog ground plane with a 10F monolithic ceramic capacitor. Bypass VSS to the analog ground plane with its own 10F monolithic ceramic capacitor. The internal voltage reference requires a 10F monolithic ceramic capacitor connected between the REFCOMP pin and the analog ground plane. This bypass capacitor is necessary because the LTC1418 internal reference requires a bypass capacitor of at least 1F for stable operation. Reference noise can be reduced even further by using a 1F monolithic ceramic capacitor connected between the VREF pin and the analog ground plane. As with all high accuracy, high resolution circuits, the best performance is achieved by minimizing the lead length of the bypass capacitors. Table 2. Functional Description of User Configurable Jumpers JUMPER JUMPER NAME JP1 LED Enable JP2 AIN+ Shorted for Unbuffered Operation. Open When Using the Noninverting Input Buffer. See JP3 JP3 Noninverting Input Buffer Bypass Open for Normal Operation. Short for Buffered Input Signals and Open JP2 - JP4 AIN JP5A SER/PAR JP5B CS JP5C SHDN JUMPER CONNECTION Shorting Enables LED Operation. Opening Disables LED Operation Shorted for Single-Ended Operation. Open for Differential Input Signals Shorted for Parallel Interface Operation. Open for Serial Interface Operation. Shorted for Normal Operation. Open to Externally Drive the CS Pin. Shorted for Normal Operation. Open to Externally Drive the SHDN Pin with a Logic Low for Shutdown Mode or with a Logic High for Normal Operation. Table 3. Input and Output Pin Functional Description INPUT/OUTPUT PIN INPUT/OUTPUT PIN FUNCTION E1 AGND (Mounting Hole) J6-4 D11 E2 DGND (Mounting Hole) J6-5 D08 E3 DGND (Mounting Hole) J6-6 D09 E4 DGND (Mounting Hole) J6-7 D06 J1 Negative Supply Voltage: -7V to -15V at 100mA J6-8 D07 J6-9 D04 J2 Supply Ground J6-10 D05 J3 Positive Supply Voltage: 7V to 15V at 100mA J6-11 D02 J4 AIN+, Noninverting Input: 2.5V, Referenced to AIN-. Input Voltage Range: VSS to AVDD (DVDD). J6-12 D03 J6-13 D00 J6-14 D01 AIN-, Inverting Input: 2.5V, Referenced to AIN+. Input Voltage Range: VSS to AVDD (DVDD). J6-15 D13 (MSB) J6-16 RDY Output (Parallel End of Conversion) J6-17 Digital Ground J6-1 D12 J6-18 BUSY J6-2 D13 (MSB) J6-3 D10 J5 10 FUNCTION J7 Convert Start: 0V to 5V DEMO MANUAL DC178 HIGH SPEED ADC U W PCB LAYOUT A D FIL Component Side Silkscreen Component Side Component Side Soldermask Solder Side Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 11 DEMO MANUAL DC178 HIGH SPEED ADC U W PCB LAYOUT A D FIL Solder Side Soldermask Pastemask U PC FAB DRAWI G 3.00 B A A A B C F D NOTES: UNLESS OTHERWISE SPECIFIED 1. MATERIALS: FR4 OR EQUIVALENT EPOXY, 2 OZ COPPER CLAD THICKNESS 0.062 0.006 TOTAL OF 2 LAYERS 2. FINISH: ALL PLATED HOLES 0.001 MIN/0.0015 MAX COPPER PLATE ELECTRODEPOSITED TIN-LEAD COMPOSITION BEFORE REFLOW, SOLDER MASK OVER BARE COPPER (SMOBC) 3. SOLDER MASK: BOTH SIDES USING LPI OR EQUIVALENT 4. SILKSCREEN: USING WHITE OR NONCONDUCTIVE EPOXY INK 5. ALL DIMENTIONS IN INCHES F D SYMBOL DIAMETER NUMBER OF HOLES A 0.210 3 B 0.120 4 C 0.070 2 D 0.060 12 E D D 3.00 F D D E D D E C D F B 12 D E D D F E 0.045 27 F 0.035 20 UNMARKED E E E E E E B Linear Technology Corporation 0.015 78 TOTAL HOLES 146 DC178 * FAB DWG dc178f LT/TP 1298 500 * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 FAX: (408) 434-0507 www.linear-tech.com LINEAR TECHNOLOGY CORPORATION 1998