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Data Sheet 1998-08 Preliminary

ttp://www.siemens.de

semiconductor/

C163-L

Revision History: 1998-08 Preliminary

Previous Releases: 12.95 Advance Information

Page Subjects

--- 3 V specification introduced.

2 Ordering codes removed.

3 Pin description corrected (pin 16, 17, 21, 40).

24 SSCBR removed.

26, 27 Revised description of Absolute Maximum Ratings and Operating Conditions.

36 PLL description reworked.

39, 47 t22 updated.

55 t35, t36, t59 updated.

61 t200, t203, t204, t209 updated.

Edition 1998-08

Published by Siemens AG, Bereich Halbleiter,

Marketing-Kommunikation

Balanstraße 73, D- 81541 München

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Components used in life-support devices or systems must be express ly authorized for such purpose!

Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2

with the expr ess writ te n appro val o f the Se mic onduct or Grou p of Si emen s AG.

1 A critical component is a component used in a life-support device or system whose failure can reasonably be

expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device

or system.

2 Life support devices or systems are intended (a) to be implanted in the human body , or (b) to support and/or maintain

and sustain human life. If the

fail

it is re asona ble t o assume t hat the h ealt h of the user ma

be endan

ered.

●High Performance 16-bit CPU with 4-Stage Pipeline

– 80 ns Instruction Cycle Time at 25 MHz CPU Clock

– 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit)

– Enhanced Boolean Bit Manipulation Facilities

– Additional Instructions to Support HLL and Operating Systems

– Register-Based Design with Multiple Variable Register Banks

– Single-Cycle Context Switching Support

– 16 MBytes Total Linear Address Space for Code and Data

– 1024 Bytes On-Chip Special Function R egister Area

●16-Priority-Level Interrupt System with 20 Sources, Sample-Rate down to 40 ns

●8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via

Peripheral Event Controller (PEC)

●Clock Generation via on-chip PLL (1:1.5/2/2.5/3/4/5), via prescaler or via direct clock input

●On-Chip Memory Modules

– 1 KBytes On-Chip Internal RAM (IRAM)

●On-Chip Peripheral Modules

– Two Multi-Functional General Purpose Timer Units with 5 Timers

– Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)

●Up to 16 MBytes External Address Space for Code and Data

– Programmable External Bus C haracteristics for Different Address Ranges

– Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit Data Bus Width

– Five Programmable Chip-Select Signals

– Hold- and Hold-Acknow ledge Bus Arbitration Support

●Idle and Power Down Modes

●Programmable Watchdog Timer and Oscillator Watchdog

●Up to 77 General Purpose I/O Lines

●High Speed Operation with 5 V Supply up to 25 MHz

●Low Power Operation with 3 V Supply up to 12 MHz

●Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler

Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer

Disassemblers, Programming Boards

●100-Pin TQFP Package (Thin QFP)

This document describes the SAB-C163-LF, the SAB-C163-L25F and the SAF-C163-L25F.

For simplicity all versions are referred to by the term C163-L throughout this document.

C166-Family of

High-Performance CMOS 16-Bit Microcontrollers

Preliminary

C163-L 16-Bit Microcontroller

C163-L

1 1998-08

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C163-L

Introduction

The C163-L is a derivative of the Siemens C166 family of 16-bit single-chip CMOS microcontrollers.

It combines high CP U performance (up to 1 2.5 millio n instructio ns per second ) with high p eripheral

functionality and enhanced IO-capabilities.

Figure 1

Logic Symbol

The C163-L can be operated from a 5 V power supply as well as from a 3 V power supply (25 MHz

versions C163-L25F only). Wi thin the standard s upply volta ge range of VDD = 4.5 - 5.5 V it delivers

its maximum performance at CPU clock frequencies of up to 25 MHz. Within the reduced supply

voltage range of VDD = 2.7 - 3.6 V it provides low power operation for energy sensi tive applic ations

at CPU clock frequencies of up to 12 MHz (PLL operation is not supported in this case).

Ordering Information

The ordering code for Siemens microcontrollers provides an exact reference to the required

product. This ordering code identifies:

●the derivative itself, ie. its function set

●the specified temperature range

●the package

●the type of delivery.

For the available ordering codes for the C163-L please refer to the

„Product Information Microcontrollers“, which summarizes all avail able microcontrolle r variants.

C163-L

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C163-L

Note: The ordering codes for Mask-ROM versions are defi ned for each product after verificati on of

the respective ROM code.

Pin Configuration TQFP Package

(top view)

Figure 2

P5.12/T6IN

P5.11/T5EUD

P5.10/T6EUD

P2.15/EX7IN

P2.14/EX6IN

P2.13/EX5IN

P2.12/EX4IN

P2.11/EX3IN

P2.10/EX2IN

P2.9/EX1IN

P2.8/EX0IN

P6.7/BREQ

P6.6/HLDA

P6.5/HOLD

P6.4/CS4

P6.3/CS3

P6.2/CS2

P6.1/CS1

P6.0/CS0

NMI

RSTOUT

RSTIN

VDD

VSS

P1H.7/A15

100

C163-L

P1H.6/A14

P1H.5/A13

P1H.4/A12

P1H.3/A11

P1H.2/A10

VSS

VDD

P1H.1/A9

P1H.0/A8

P1L.7/A7

P1L.6/A6

P1L.5/A5

P1L.4/A4

P1L.3/A3

P1L.2/A2

P1L.1/A1

P1L.0/A0

P0H.7/AD15

P0H.6/AD14

P0H.5/AD13

P0H.4/AD12

P0H.3/AD11

P0H.2/AD10

P0H.1/AD9

P0H.0/AD8

P5.13/T5IN

P5.14/T4EUD

P5.15/T2EUD

VSS

XTAL1

XTAL2

VDD

P3.0

P3.1/T6OUT

P3.2/CAPIN

P3.3/T3OUT

P3.4/T3EUD

P3.5/T4IN

P3.6/T3IN

P3.7/T2IN

P3.8

P3.9

P3.10/TxD0

P3.11/RxD0

P3.12/BHE/WRH

P3.13

P3.15/CLKOUT

P4.0/A16

P4.1/A17

P4.2/A18

P4.3/A19

VSS

VDD

P4.4/A20/SSPCE1

P4.5/A21/SSPCE0

P4.6/A22/SSPDAT

P4.7/A23/SSPCLK

WR/WRL

READY

ALE

VDD

VSS

OWE

P0L.0/AD0

P0L.1/AD1

P0L.2/AD2

P0L.3/AD3

P0L.4/AD4

P0L.5/AD5

P0L.6/AD6

P0L.7/AD7

VDD

VSS

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C163-L

Pin Definitions and Functions

Symbol Pin

Numb.

TQFP

Input

Out-

put

Function

P5.10

P5.11

P5.12

P5.13

P5.14

P5.15

100

Port 5 is a 6-bit input-only port with Schmitt-Trigger characteristics. The

pins of Port 5 also serve as timer inputs:

T6EUD GPT2 Timer T6 External Up/Down Control Input

T5EUD GPT2 Timer T5 External Up/Down Control Input

T6IN GPT2 Timer T6 Count Input

T5IN GPT2 Timer T5 Count Input

T4EUD GPT1 Timer T4 External Up/Down Control Input

T2EUD GPT1 Timer T2 External Up/Down Control Input

XTAL1

XTAL2

Input to the oscillator amplifier and input to the internal clock generator.

Output of the oscillator amplifier circuit.

To clock the dev ice from an external source, drive XTAL1, while leav ing

XTAL2 unconnected. Minimum and maximum high/low and rise/fall

times specified in the AC Characteristics must be observed.

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

P3.8

P3.9

P3.10

P3.11

P3.12

P3.13

P3.15

Port 3 is a 15-bit (P3.14 is missing) bidirectional I/O port. It is bit-wise

programmable for input or output via direction bits. For a pin configured

as input, the output driver is put into high-impedance state. Port 3

outputs can be configured as push/pull or open drain drivers.

Some Port 3 pins also serve for alternate functions:

T6OUT GPT2 Timer T6 Toggle Latch Output

CAPIN GPT2 Register CAPREL Capture Input

T3OUT GPT1 Timer T3 Toggle Latch Output

T3EUD GPT1 Timer T3 Ext.Up/Down Ctrl.Input

T4IN GPT1 Timer T4 Input for

Count/Gate/Reload/Capture

T3IN GPT1 Timer T3 Count/Gate Input

T2IN GPT1 Timer T2 Input for

Count/Gate/Reload/Capture

T×D0 ASC0 Clock/Data Output (Asyn./Syn.)

R×D0 ASC0 Data Input (Asyn.) or I/O (Syn.)

BHE Ext. Memory H igh Byte Enable Signal,

WRH Ext. Memory High Byte Write Strobe

CLKOUT System Clock Output (=CPU Clock)

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C163-L

P4.0

P4.1

P4.2

P4.3

P4.4

P4.5

P4.6

P4.7

Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for

input or output via direction bits. For a pin configured as input, the

output driver is put into high-impedance state.

In case of an external bus configuration, Port 4 can be used to output

the segment address lines and it provides the SSP interface lines:

A16 Least Significant S egment Address Line

A17 Segment Address Line

A18 Segment Address Line

A19 Segment Address Line

A20 Segment Address Line,

SSPCE1 SSP Chip Enable Line 1

A21 Segment Address Line,

SSPCE0 SSP Chip Enable Line 0

A22 Segment Address Line,

SSPDAT SSP Data Input/Output Line

A23 Most Significant Segment Addr. Line

SSPCLK SSP Clock Output Line

RD 33 O External Memory Read Strobe. RD is activated for every external

instruction or data read access.

WR/

WRL 34 O External Memory Write Strobe. In WR-mode this pin is activated for

every external data write access. In WRL -mode this pin is activated for

low byte data write accesses on a 16-bit bus, and for every data write

access on an 8-bit bus. See bit WRC FG in register SYSCON for mode

selection.

READY 35 I Ready Input. When the Ready function is enabled, a high level at this

pin during an external memory access will force the inserti on of memory

cycle time waitstates until the pin returns to a low level.

ALE 36 O Address Latch Enable Output. Can be used for latching the address

into external memory or an addre ss l atch i n the multiplexed bus modes.

EA 37 I External A ccess Enable pin. A low level at this pin during and after

Reset forces the C163-L to begin instruction execution out of external

memory. A high level forces execution out of the internal ROM. The

C163-L must have this pin tied to ‘0’.

Pin Definitions and Functions (cont’d)

Symbol Pin

Numb.

TQFP

Input

Out-

put

Function

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C163-L

PORT0

P0L.0-7

P0H.0-7 41 - 48

51 - 58

IO PORT0 consists of the tw o 8-bit bidirectional I/O ports P0L and P0H. It

is bit-wise programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-impedance state.

In case of an external bus configuration, PORT0 serves as the address

(A) and address/data (AD) bus in multiplexed bus modes and as the

data (D) bus in demultiplexed bus modes.

Demultiplexed bus modes:

Data Path Width: 8-bit 16-bit

P0L.0 – P0L.7: D0 – D7 D0 - D7

P0H.0 – P0H.7: I/O D8 - D15

Multiplexed bus modes:

Data Path Width: 8-bit 16-bit

P0L.0 – P0L.7: AD0 – AD7 AD0 - AD7

P0H.0 – P0H.7: A8 - A15 AD8 - AD15

PORT1

P1L.0-7

P1H.0-7 59 - 66

67, 68,

71 - 76

IO PORT1 consists of the tw o 8-bit bidirectional I/O ports P1L and P1H. It

is bit-wise programmable for input or output via direction bits. For a pin

configured as input, the output driver is put into high-impedance state.

PORT1 is used as the 16-bit address bus (A) in demultiplexed bus

modes and also after switching from a demultiplexed bus mode to a

multiplexed bus mode.

RSTIN 79 I Reset Input with Schmitt-Trigger characteristics. A low level at this pin

for a minimum of 2 CPU clock cycles while the oscillator is running

resets the C163-L. An internal pullup resistor permits power-on reset

using only a capacitor connected to VSS.

Note: To let the reset configuration of PORT0 settle and to let the

PLL lock a reset duration of ca. 1 ms is recommended.

RST

OUT 80 O Internal Reset Indication Output. This pin is set to a low level when the

part is executing either a hardware-, a software- or a watchdog timer

reset. RSTOUT remains low until the EINIT (end of initialization)

instruction is executed.

NMI 81 I Non-Maskable Interrupt Input. A high to low transition at this pin causes

the CPU to vector to the NMI trap routine. When the PWRDN (power

down) instruction is executed, the NMI pin must be low in order to force

the C163-L to go into power down mode. If NMI is high, when PWRDN

is executed, the part will continue to run in normal mode.

If not used, pin NMI should be pulled high externally.

Pin Definitions and Functions (cont’d)

Symbol Pin

Numb.

TQFP

Input

Out-

put

Function

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C163-L

P6.0

P6.1

P6.2

P6.3

P6.4

P6.5

P6.6

P6.7

I/O

Port 6 is an 8-bit bidirectional I/O port. It is bit-wise programmable for

input or output via direction bits. For a pin configured as input, the

output driver is put into high-impedance state. Port 6 outputs can be

configured as push/pull or open drain drivers.

The Port 6 pins also serve as bus interface signals:

CS0 Chip Select 0 Output

CS1 Chip Select 1 Output

CS2 Chip Select 2 Output

CS3 Chip Select 3 Output

CS4 Chip Select 4 Output

HOLD External Master Hold Request Input

HLDA Hold Acknowledge Output or Input

(Master mode: O, Slave mode: I)

BREQ Bus Request Output

P2.8

P2.9

P2.10

P2.11

P2.12

P2.13

P2.14

P2.15

Port 2 is an 8-bit bidirectional I/O port. It is bit-wise programmable for

input or output via direction bits. For a pin configured as input, the

output driver is put into high-impedance state. Port 2 outputs can be

configured as push/pull or open drain drivers.

The Port 2 pins also serve as fast external interrupt inputs:

EX0IN Fast External Interrupt 0 Input

EX1IN Fast External Interrupt 1 Input

EX2IN Fast External Interrupt 2 Input

EX3IN Fast External Interrupt 3 Input

EX4IN Fast External Interrupt 4 Input

EX5IN Fast External Interrupt 5 Input

EX6IN Fast External Interrupt 6 Input

EX7IN Fast External Interrupt 7 Input

OWE 40 I Oscillator Watchdog Enable. This pin enables the PLL when high or

disables it when low (e.g. to disable the OWD for testing purposes.

An internal pullup device holds this input high if nothing is driving it.

Note: The input voltage at pin OWE must not exceed 12.6 V.

For 3 V operation pin OWE must be driven low.

VDD 7, 28,

38, 49,

69, 78

- Digital Supply Voltage:

+ 5 V or +3 V during normal operation and idle mode.

≥ 2.5 V during power down mode

VSS 4, 27,

39, 50,

70, 77

- Digital Ground.

Pin Definitions and Functions (cont’d)

Symbol Pin

Numb.

TQFP

Input

Out-

put

Function

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C163-L

Functional Description

The architecture of the C163-L combines advantages of both RISC and CISC processors and of

advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an

overview of the different on-chip components and of the advanced, high bandwidth internal bus

structure of the C163-L.

Note: All time specifications refer to a CPU clock of 25/12 MHz for 5/3 V operation

(see definition in the AC Characteristics section).

Figure 3

Block Diagram

PLL

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C163-L

Memory Organization

The memory space of the C163-L is configured in a Von Neumann architecture which means that

code memory, data memory, registers and I/O ports are organized within the same linear address

space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise.

Particular portions of the on-chip memory have additionally been made directly bit addressable.

The C163-L is prepared to incorporate on-chip mask-programmable ROM, OTP or Flash memory

for code or constant data. C urrently no program memory is integrated.

1 KByte of on-chip RAM is provided as a storage for user defined variables, for the system stack,

general purpose register banks and even for code. A register bank can consist of up to 16 wordwide

(R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) so-called General Purpose Registers

(GPRs).

1024 bytes (2 * 512 bytes) of the address space are reserved for the Special Function Register

areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling

and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for

other/future members of the C166 family.

In order to meet the needs o f designs where more memory is required than is provi ded on c hip, u p

to 16 MBytes of external R AM and/or ROM can be connected to the microcontroller.

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C163-L

External Bus Controller

All of the external memory accesses are performed by a particular on-chip External Bus Controller

(EBC). It can be programmed either to Single Chip Mode when no external me mory is required, or

to one of four different external memory access modes, which are as follows:

– 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed

– 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed

– 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed

– 16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed

In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on

PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for

input/output.

Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-

State Time, Length of ALE and Read Write Delay) have been made programmable to allow the user

the adaption of a wide range of different types of memories and external peripherals.

In addition, up to 4 independent address windows may be defined (via register pairs ADDRSELx /

BUSCONx) which allow to access different resources with different bus characteristics. These

address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and

BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows

are controlled by BUSCON0.

Up to 5 external CS signals (4 windows plus default) can be generated in order to save external glue

logic. Access to very slow memories is supported via a particular ‘Ready’ function.

A HOLD/HLDA protocol is available for bus arbitration and allows to share external resources with

other bus masters. The bus arbitration is enabled by setting bit HLDEN in register SYSCON. After

setting HLDEN once, pins P6.7...P6.5 (BREQ, HLDA, HOLD) are automatically controlled by the

EBC. In Master Mode (default after reset) the HLDA pin is an output. By setting bit DP6.7 to ’1’ the

Slave Mode is selected where pin HLDA is switched to input. This allows to directly connect the

slave controller to another master controller without glue logic.

For applications which require less than 16 MBytes of external memory space, this address space

can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, tw o or no

address lines at all. It outputs all 8 address lines, if an address space of 16 MBytes is used.

Note: When the on-chip SSP Module is to be u sed th e segm ent address output on Port 4 must b e

limited to 4 bits (ie. A19...A16) in order to enable the alternate function of the SSP interface

pins.

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C163-L

Central Processing Unit (CPU)

The main core o f the CPU consists of a 4-stage instructi on pipeline, a 16-bit arithmetic and logic unit

(ALU) and dedicated SFRs. Additional hardware has been spent for a separate multipl y and d ivid e

unit, a bit-mask generator and a barrel shifter.

Based on these hard ware provisions, most of the C163-L’s instructions can be executed in just one

machine cycle which requires 80 ns at 25-MHz CPU clock. For example, shift and rotate instructions

are always processed during one machine cyc le independent of the number of bits to be shifted. All

multiple-cycle instructions have been optimized so that they can be executed very fast as well:

branches in 2 cycles, a 16 × 16 bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles.

Another pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution time of

repeatedly performed jumps in a loop from 2 cycles to 1 cycle.

Figure 4

CPU Block Diagram

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C163-L

The CPU disposes of an actual register context consisting of up to 16 wordwide GP Rs w hich are

physically allocated within the on-chip RAM area. A Context Pointer (CP) register determi nes the

base address of the active register bank to be accessed by the CPU at a time. The number of

a register bank may overlap others.

A system stack of up to 512 words is provided as a storage for temporary data. The system stack

is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP)

pointer value upon each stack access for the detection of a stack overflow or underflow.

The high perform ance offered by th e hardware implementatio n of the CPU can efficiently be utilized

by a programmer via the highly efficient C163-L instruction set which includes the following

instruction classes:

– Arithmetic Instructions

– Logical Instructions

– Boolean Bit Manipulation Instructions

– Compare and Loop Control Instructions

– Shift and Rotate Instructions

– Prioritize Instruction

– Data Movement Instructions

– System Stack Instructions

– Jump and Call Instructions

– Return Instructions

– System Control Instructions

– Miscellaneous Instructions

The basic in struction length is either 2 or 4 bytes. Possible operand types are bits, by tes and words.

A variety of direct, indirect or immediate addressing modes are provided to specify the required

operands.

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C163-L

Interrupt System

With an interrupt response time within a range from just 200 ns to 480 ns (in case of internal

program execution), the C163-L is capable of reacting very fast to the occurence of non-

deterministic events.

The architecture of the C163-L supports several mechanisms for fast and flexible response to

service requests that can be generated from various sources internal or external to the

microcontroller. Any of these interrupt requests can be programmed to being serviced by the

Interrupt Controller or by the Peripheral Event Controller (PEC).

In contrast to a standard interrupt service where the current program execution is suspended and

a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU

activity to perform a PEC service. A PEC service implies a single byte or word data transfer between

any two memory locations with an additional increment of either the PEC source or the destination

pointer. An individual PEC transfer counter is implicity decremented for each PEC service except

when performing in the continuous transfer mode. When this counter reaches zero, a standard

interrupt is performed to the corresponding source related vector location. PEC services are very

well suited, for example, for supporting the transmission or reception of blocks of data. The C163-

L has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities.

A separate control reg ister which contains an in terrupt request flag, an interrupt enable fl ag a nd an

interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each

source can be programmed to one of sixteen interrupt priority levels. Once having been accepted

by the CPU, an interrupt service ca n only be interrupted by a higher prioritize d service request. For

the standard interrupt processing, each of the possible interrupt sources has a dedicated vector

location.

Fast external interrupt inputs are provided to service external interrupts with high precision

requirements. Thes e fast interrupt inp uts feature programmabl e edge d etecti on (rising edge, fa lling

edge or both edges).

Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an

individual trap (interrupt) number.

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C163-L

The following table shows all of the possible C163-L interrupt sources and the corresponding

hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers:

Source of Interrupt or

PEC Service Request Request

Flag Enable

Flag Interrupt

Vector Vector

Location Trap

Number

External Interrupt 0 CC8IR CC8IE CC8INT 00’0060H18H

External Interrupt 1 CC9IR CC9IE CC9INT 00’0064 H19H

External Interrupt 2 CC10IR CC10IE CC10INT 00’0068H1AH

External Interrupt 3 CC11IR CC11IE CC11INT 00’006CH1BH

External Interrupt 4 CC12IR CC12IE CC12INT 00’0070H1CH

External Interrupt 5 CC13IR CC13IE CC13INT 00’0074H1DH

External Interrupt 6 CC14IR CC14IE CC14INT 00’0078H1EH

External Interrupt 7 CC15IR CC15IE CC15INT 00’007CH1FH

GPT1 Timer 2 T2IR T2IE T2INT 00’0088H22H

GPT1 Timer 3 T3IR T3IE T3INT 00’008CH23H

GPT1 Timer 4 T4IR T4IE T4INT 00’0090H24H

GPT2 Timer 5 T5IR T5IE T5INT 00’0094H25H

GPT2 Timer 6 T6IR T6IE T6INT 00’0098H26H

GPT2 CAPREL Register CRIR CRIE CRINT 00’009CH27H

ASC0 Transmit S0TIR S0TIE S0TINT 00’00A8H2AH

ASC0 Transmit Buffer S0TBIR S0TBIE S0TBINT 00’011CH47H

ASC0 Receive S0RIR S0RIE S0RINT 00’00ACH2BH

ASC0 Error S0EIR S0EIE S0EINT 00’00B0H2CH

SSP Interrupt XP1IR XP1IE XP1INT 00’0104H41H

PLL Unlock / OWD XP3IR XP3IE XP3INT 00’010CH43H

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C163-L

The C163-L also provides an excellent mechanism to identify and to process exceptions or error

conditions tha t arise during run-tim e, so-cal led ‘Hardware Trap s’. Ha rdware traps c ause im mediate

non-maskable system reaction which is similar to a standard interrupt service (branching to a

dedicated vector table location). The occurence of a hardware trap is additionally signified by an

individual bit in the trap fl ag register (TFR). Except when another higher prio ritized trap service is in

progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap

services can normally not be interrupted by standard or PEC interrupts.

The following table shows all of the possible exceptions or error conditions that can arise during run-

time:

Exception Condition Trap

Flag Trap

Vector Vector

Location Trap

Number Trap

Priority

Reset Functions:

Hardware Reset

Software Reset

Watchdog Timer Overflow

RESET

00’0000H

00H

III

Class A Hardware Traps:

Non-Maskable Interrupt

Stack Overflow

Stack Underflow

NMI

STKOF

STKUF

NMITRAP

STOTRAP

STUTRAP

00’0008H

00’0010H

00’0018H

02H

04H

06H

Class B Hardware Traps:

Undefined Opcode

Protected Instruction

Fault

Illegal Word Operand

Access

Illegal Instruction Access

Illegal External Bus

Access

UNDOPC

PRTFLT

ILLOPA

ILLINA

ILLBUS

BTRAP

00’0028H

0AH

Reserved [2CH – 3CH][0B

H – 0FH]

Software Traps

TRAP Instruction Any

[00’0000H –

00’01FCH]

in steps

of 4H

Any

[00H – 7FH]Current

CPU

Priority

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C163-L

General Purpose Timer (GPT) Unit

The GPT unit represents a very flexible multifunctional timer/counter structure which may be used

for many different time related tasks such as eve nt timing and counting, puls e width and duty cycle

measurements, pulse generation, or pulse multiplication.

The GPT unit incorpor ates five 16-bit timers which are organized in two separate modules, GPT1

and GPT2. Each timer in each mo dule m ay operate independently in a number of different modes,

or may be concatenated with another timer of the same module.

Each of the three tim ers T2, T3, T4 of module GPT1 can be c onfigured individu ally for one of three

basic modes of operation, which are Timer, Gated Timer, and Counter Mode. In Timer Mode, the

input clock for a timer is derived from the C PU clock, divided by a programmable prescaler, while

Counter Mode allows a timer to be clocked in reference to external events.

Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of

a timer is controlled b y the ‘gate’ lev el on an external input pin. For these purposes, each timer has

one associated p ort pin (TxIN) whi ch serves as g ate or c lock inpu t. The m axim um res oluti on of th e

timers in module GPT1 is 320 ns (@ 25 MHz CPU clock).

The count direction (up/down) for each timer is programmable by software or may additionally be

altered dynamically by an external signal on a port pin (TxEUD) to facilitate e. g. position tracking.

Figure 5

Block Diagram of GPT1

Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer over-flow/

underflow. The state of this latch may be output on port a pin (T3OUT) e.g. for time out monitoring

of external hardware components, or may be used internally to clock timers T2 and T4 for

measuring long time periods with high resolution.

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C163-L

In addition to their basic operating modes, timers T2 and T4 may be c onfigured as reload or capture

registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The

contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins

(TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or

by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to

alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM

signal, this signal can be constantly generated w ithout software intervention.

Figure 6

Block Diagram of GPT2

With its maximum resolution of 160 ns (@ 25 MHz), the GPT2 module provides precise event

control and time measurement. It includes two timers (T5, T6) and a capture/reload register

(CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via

a programmable prescaler or with external si gnals. The count direction (up/down) for each timer is

programmable by software or may additionally be altered dynamically by an external signal on a

port pin (TxEUD). Timer T6 has an output toggle latch (T6OTL) which changes its state on each

timer overflow/underflow. Concatenation of the timers is supported via T6OTL.

The state of thi s latch may be used to clock ti mer T5, or it may be output on a port pin (T6OUT). The

overflows/underflows of timer T6 can additionally be used to cause a reload from the CAPREL

transition on the corresponding port pin (CAPIN ), and timer T5 may optionally be cleared after the

capture procedure. This allows absolute time differences to be measured or pulse multiplication to

be performed without software overhead.

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C163-L

Parallel Ports

The C163-L provides up to 77 I/O lines which are organized into six input/output ports and one input

port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise)

programmable as inputs or outputs via directi on regis ters. The I/ O ports are true bidi rectional ports

which are switched to high impedance state when confi gured as inputs. The output drive rs of three

I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation via control

registers. During the internal reset, all port pins are configured as inputs.

All port lines have programmable alternate input or output functions associated with them. PORT0

and PORT1 may be used as address and data lines when acc essing external memory, while Port 4

outputs the additional segment address bits A23/19/17...A16 in systems where segmentation is

enabled to access more than 64 KBytes of memory. Port 6 provides opti onal bus arbitration signals

(BREQ, HLD A, HOLD) and chip select signals. Port 3 includes alternate functions of timers, serial

interfaces, the optional bus control signal BHE and the system clock output (CLKOUT). Port 5 is

used for timer control signals. All port lines that are not used for these alternate functions may be

used as general purpose I/O lines.

Serial Channels

Serial communication with other microcontrollers, processors, terminals or external peripheral

components is provided by two serial interfaces with different functionality, an Asynchronous/

Synchronous Serial Channel (ASC0) and a Synchronous Serial Port (SSP).

The ASC0 is upward compatible with the serial ports of the Siemens 8-bit microcontroller families

and supports full-duplex asynchronous communication at up to 781 KBaud and half-duplex

synchronous communication at up to 3.125 MBaud @ 25 MHz CPU clock.

A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning.

For transmission, reception and error handling 4 separate interrupt vectors are provided. In

asynchronous mod e, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and

terminated by one or two stop bits. For multiprocessor communication, a mechani sm to distinguis h

address from data bytes has been included (8-bit data plus wake up bit mode).

In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock

which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is

available for testing purposes.

A number of optional hardware error detection capabilities has been included to increase the

reliability of data transfers. A parity bit can automatically be generated on transmission or be

checked on reception. Framing error detection allows to recognize data frames with missing stop

bits. An overrun error will be generated, if the last character received has not been read out of the

receive buffer register at the time the reception of a new character is complete.

The SSP transmits 1...3 bytes or receives 1 byte after sending 1...3 bytes synchronously to a shift

clock which is ge nerated by the SSP. The SSP can start s hiftin g with the LSB or with the M SB an d

allows to select shi fting and latchi ng clock ed ges as well as the c lock polari ty. Up to two chip select

lines may be activated in order to direct data transfers to one or both of two peripheral devices.

One general interrupt vector is provided for the SSP.

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C163-L

Watchdog Timer

The Watchdog Timer repr esents on e of the fail-safe mechani sms whic h have been imp lemented to

prevent the controller from malfunctioning for longer periods of time.

The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time

interval until the EINIT (end of initialization ) instruction has been executed. Thus, the chip’s sta rt-up

procedure is always monitored. The software has to be designed to service the Watchdog Timer

before it overflows. If, due to hardware or software related failur es, the software fails to do so, the

Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low

in order to allow external hardware components to be reset.

The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128.

The high byte of the W atchdog Timer register can be set to a prespecified reload value (stored in

WDTREL) in order to allow further variation of the monitored time interval. Each time it is ser viced

by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals

between 20 µs and 336 ms can be monitored (@ 25 MHz). The default Watchdog Timer interval

after reset is 5.24 ms (@ 25 MHz).

Oscillator Watchdog

During direct drive o r prescale r operation the Oscillator Wa tchdog (OWD) monitors th e clock signal

generated by the on-chip oscillator (either with a crystal or via external clock drive). For this

operation the PLL provides a clock signal which is used to supervise transitions on the oscillator

clock. This PLL clock is independent from the XTAL1 clock. When the expected oscillator clock

transitions are missing the OWD activates the PLL Unlock / OWD interrupt node and supplies the

CPU with the PLL clock signal. Under these circumstances the PLL will oscillate with its basic

frequency.

A low level on pin OWE disables the PLL and the OWD’s interrupt output so the clock signal is

derived from the oscillator clock in any case.

Note: The CPU clock source is only switched back to the oscillator clock after a hardware reset.

For 3 V operation pin OWE must always be low (OWD disabled) as the PLL cannot deliver an

appropriate clock signal in this case.

For 5 V operation pin OWE should only be pulled low (PLL disabled) if direct drive or prescaler

operation is configured. All other configurations (PLL factors) result in direct drive operation.

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C163-L

Instruction Set Summary

The table below lists the instructions of the C163-L in a condensed way.

The various addressing modes that can be used with a specific instruction, the operation of the

instructions, parameters for conditional execution of instructions, and the opcodes for each

instruction can be found in the “C16x Family Instruction Set Manual”.

This document also provides a detailled description of each instruction.

Instruction Set Summary

Mnemonic Description Bytes

ADD(B) Add word (byte) operands 2 / 4

ADDC(B) Add word (byte) operands with Carry 2 / 4

SUB(B) Subtract word (byte) operands 2 / 4

SUBC(B) Subtract word (byte) operands with Carry 2 / 4

MUL(U) (Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2

DIV(U) (Un)Signed divide register MDL by direct GPR (16-/16-bit) 2

DIVL(U) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2

CPL(B) Complement direct word (byte) GPR 2

NEG(B) Negate direct word (byte) GPR 2

AND(B) Bitwise AND, (word/byte operands) 2 / 4

OR(B) Bitwise OR, (word/byte operands) 2 / 4

XOR(B) Bitwise XOR, (word/byte operands) 2 / 4

BCLR Clear direct bit 2

BSET Set direct bit 2

BMOV(N) Move (negated) direct bit to direct bit 4

BAND, BOR, BXOR AND/OR/XOR direct bit with direct bit 4

BCMP Compare direct bit to direct bit 4

BFLDH/L Bitwise modify masked high/low byte of bit-addressable

direct word memory with immediate data 4

CMP(B) Compare word (byte) operands 2 / 4

CMPD1/2 Compare word data to GPR and decrement GPR by 1/2 2 / 4

CMPI1/2 Compare word data to GPR and increment GPR by 1/2 2 / 4

PRIOR Determine number of shift cycles to normalize direct

word GPR and store result in direct word GPR 2

SHL / SHR Shift left/right direct w ord GPR 2

ROL / ROR Rotate left/right direct word GPR 2

ASHR Arithmetic (sign bit) shift right direct word GPR 2

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C163-L

MOV(B) Move word (byte) data 2 / 4

MOVBS Move byte operand to word operand with sign extension 2 / 4

MOVBZ Move byte operand to w ord operand. with zero extension 2 / 4

JMPA, JMPI, JMPR Jump absolute/indirect/relative if condition is met 4

JMPS Jump absolute to a code segment 4

J(N)B Jump relative if direct bit is (not) set 4

JBC Jump relative and clear bit if direct bit is set 4

JNBS Jump relative and set bit if direct bit is not set 4

CALLA, CALLI, CALLR Call absolute/indirect/relative subroutine if condition is met 4

CALLS Call absolute subroutine in any code segment 4

PCALL Push direct word register onto system stack and call

absolute subroutine 4

TRAP Call interrupt service routine via immediate trap number 2

PUSH, POP Push/pop direct word register onto/from system stack 2

SCXT Push direct word register onto system stack und update

RET Return from intra-segm ent subroutine 2

RETS Return from inter-segment subroutine 2

RETP Return from intra-segment subroutine and pop direct

word register from system stack 2

RETI Return from interrupt service subroutine 2

SRST Software Reset 4

IDLE Enter Idle Mode 4

PWRDN Enter Power Down Mode

(supposes NMI-pin being low) 4

SRVWDT Service Watchdog Timer 4

DISWDT Disable Watchdog Time r 4

EINIT Signify End-of-Initialization on RSTOUT-pin 4

ATOMIC Begin ATOMIC sequence 2

EXTR Begin EXTended Register sequence 2

EXTP(R) Begin EXTended Page (and Register) sequence 2 / 4

EXTS(R) Begin EXTended Segment (and Register) sequence 2 / 4

NOP Null operation 2

Instruction Set Summary (cont’d)

Mnemonic Description Bytes

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C163-L

Special Function Registers Overview

The following table lists all SFRs which are implemented in the C163-L in alphabetical order.

Bit-addressable SFRs are m arked with the letter “ b” in column “Name”. SFRs withi n the Extended

SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. Registers within

on-chip X-Peripherals (SSP) are marked with the letter “X” in column “Physical Address”.

An SFR can be specifi ed via its individu al mnemonic name . Depending on the selected addres sing

mode, an SFR can be accessed via its physi cal address (using the Data Page Pointers), or via its

short 8-bit address (without using the Data Page Pointers).

Special Function Registers Overview

Name Physical

Address 8-Bit

Address Description Reset

Value

ADDRSEL1 FE18H0CHAddress Select Register 1 0000H

ADDRSEL2 FE1AH0DHAddress Select Register 2 0000H

ADDRSEL3 FE1CH0EHAddress Select Register 3 0000H

ADDRSEL4 FE1EH0FHAddress Select Register 4 0000H

BUSCON0 b FF0CH86HBus Configuration Register 0 0XX0H

BUSCON1 b FF14H8AHBus Configuration Register 1 0000H

BUSCON2 b FF16H8BHBus Configuration Register 2 0000H

BUSCON3 b FF18H8CHBus Configuration Register 3 0000H

BUSCON4 b FF1AH8DHBus Configuration Register 4 0000H

CAPREL FE4AH25HGPT2 Capture/Reload Register 0000H

CC8IC b FF88HC4HEX0IN Interrupt Control Register 0000H

CC9IC b FF8AHC5HEX1IN Interrupt Control Register 0000H

CC10IC b FF8CHC6HEX2IN Interrupt Control Register 0000H

CC11IC b FF8EHC7HEX3IN Interrupt Control Register 0000H

CC12IC b FF90HC8HEX4IN Interrupt Control Register 0000H

CC13IC b FF92HC9HEX5IN Interrupt Control Register 0000H

CC14IC b FF94HCAHEX6IN Interrupt Control Register 0000H

CC15IC b FF96HCBHEX7IN Interrupt Control Register 0000H

CP FE10H08HCPU Context Pointer Register FC00H

CRIC b FF6AHB5HGPT2 CAPREL Interrupt Control Register 0000H

CSP FE08H04HCPU Code Segment Pointer Register (read only) 0000H

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C163-L

DP0L b F100HE80HP0L Direction Control Register 00H

DP0H b F102HE81HP0H Direction Control Register 00H

DP1L b F104HE82HP1L Direction Control Register 00H

DP1H b F106HE83HP1H Direction Control Register 00H

DP2 b FFC2HE1HPort 2 Direction Control Register 0000H

DP3 b FFC6HE3HPort 3 Direction C ontrol Register 0000H

DP4 b FFCAHE5HPort 4 Direction Control Register 00H

DP6 b FFCEHE7HPort 6 Direction Control Register 00H

DPP0 FE00H00HCPU Data Page Pointer 0 Register (10 bits) 0000 H

DPP1 FE02H01HCPU Data Page Pointer 1 Register (10 bits) 0001 H

DPP2 FE04H02HCPU Data Page Pointer 2 Register (10 bits) 0002 H

DPP3 FE06H03HCPU Data Page Pointer 3 Register (10 bits) 0003 H

EXICON b F1C0HEE0HExternal Interrupt Control Register 0000H

MDC b FF0EH87HCPU Multiply Divide Control Register 0000H

MDH FE0CH06HCPU Multiply Divi de Register – High Word 0000H

MDL FE0EH07HCPU Multiply Divi de Register – Low Word 0000H

ODP2 b F1C2HEE1HPort 2 Open Drain Control Register 0000H

ODP3 b F1C6HEE3HPort 3 Open Drain Control Register 0000H

ODP6 b F1CEHEE7HPort 6 Open Drain Control Register 00H

ONES FF1EH8FHConstant Value 1’s Register (read only) FFFFH

P0L b FF00H80HPort 0 Low Register (Lower half of PORT0) 00H

P0H b FF02H81HPort 0 High Register (Upper half of PORT0) 00H

P1L b FF04H82HPort 1 Low Register (Lower half of PORT1) 00H

P1H b FF06H83HPort 1 High Register (Upper half of PORT1) 00H

P2 b FFC0HE0HPort 2 Register 0000H

P3 b FFC4HE2HPort 3 Register 0000H

P4 b FFC8HE4HPort 4 Register (8 bi ts) 00H

P5 b FFA2HD1HPort 5 Register (read only) XXXXH

Special Function Registers Overview (cont’d)

Name Physical

Address 8-Bit

Address Description Reset

Value

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C163-L

P6 b FFCCHE6HPort 6 Register (8 bits) 00H

PECC0 FEC0H60HPEC Channel 0 Control Register 0000H

PECC1 FEC2H61HPEC Channel 1 Control Register 0000H

PECC2 FEC4H62HPEC Channel 2 Control Register 0000H

PECC3 FEC6H63HPEC Channel 3 Control Register 0000H

PECC4 FEC8H64HPEC Channel 4 Control Register 0000H

PECC5 FECAH65HPEC Ch annel 5 Control Register 0000H

PECC6 FECCH66HPEC Channel 6 Control Register 0000H

PECC7 FECEH67HPEC Ch annel 7 Control Register 0000H

PSW b FF10H88HCPU Program Status Word 0000H

RP0H b F108HE84HSystem Startup Configuration Register (Rd. only) XXH

S0BG FEB4H5AHSerial Channel 0 Baud Rate Generator Reload

S0CON b FFB0HD8HSerial Channel 0 Control Register 0000H

S0EIC b FF70HB8HSerial Channel 0 Error Interrupt Control Register 0000H

S0RBUF FEB2H59HSerial Channel 0 Receive Buffer Register

(read only) XXH

S0RIC b FF6EHB7HSerial Channel 0 Receive Interrupt Control

S0TBIC b F19CHECEHSerial Channel 0 Transmit Buffer Interrupt Control

S0TBUF FEB0H58HSerial Channel 0 Transmit Buffer Register

(write only) 00H

S0TIC b FF6CHB6HSerial Channel 0 Transmit Interrupt Control

SP FE12H09HCPU System Stack Pointer Register FC00H

SSPCON0 EF00HX--- SSP Control Register 0 0000H

SSPCON1 EF02HX--- SSP Control Register 1 0000H

SSPRTB EF04HX--- SSP Receive/Transmit Buffer XXXXH

SSPTBH EF06HX--- SSP Transmit Buffer High XXXXH

STKOV FE14H0AHCPU Stack Overflow Pointer Register FA00H

Special Function Registers Overview (cont’d)

Name Physical

Address 8-Bit

Address Description Reset

Value

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C163-L

1) The system c onfiguratio n is selected durin g res et .

2) Bit WDT R ind ic at es a wa tchdog timer triggered reset .

STKUN FE16H0BHCPU Stack Underflow Pointer Register FC00H

SYSCON b FF12H89HCPU System Configuration Register 0XX0H1)

T2 FE40H20HGPT1 Timer 2 Regi ster 0000H

T2CON b FF40HA0HGPT1 Timer 2 C ontrol Register 0000H

T2IC b FF60HB0HGPT1 Timer 2 Interrupt Control Register 0000H

T3 FE42H21HGPT1 Timer 3 Regi ster 0000H

T3CON b FF42HA1HGPT1 Timer 3 C ontrol Register 0000H

T3IC b FF62HB1HGPT1 Timer 3 Interrupt Control Register 0000H

T4 FE44H22HGPT1 Timer 4 Regi ster 0000H

T4CON b FF44HA2HGPT1 Timer 4 C ontrol Register 0000H

T4IC b FF64HB2HGPT1 Timer 4 Interrupt Control Register 0000H

T5 FE46H23HGPT2 Timer 5 Regi ster 0000H

T5CON b FF46HA3HGPT2 Timer 5 C ontrol Register 0000H

T5IC b FF66HB3HGPT2 Timer 5 Interrupt Control Register 0000H

T6 FE48H24HGPT2 Timer 6 Regi ster 0000H

T6CON b FF48HA4HGPT2 Timer 6 C ontrol Register 0000H

T6IC b FF68HB4HGPT2 Timer 6 Interrupt Control Register 0000H

TFR b FFACHD6HTrap Flag Register 0000H

WDT FEAEH57HWatchdog Timer Register (read only) 0000H

WDTCON FFAEHD7HWatchdog Timer Control Register 000XH 2)

XP1IC b F18EHEC7HSSP Interrupt Control Register 0000H

XP3IC b F19EHECFHPLL/OWD Interrupt Control Register 0000H

ZEROS b FF1CH8EHConstant Value 0’s Register (read only) 0000H

Special Function Registers Overview (cont’d)

Name Physical

Address 8-Bit

Address Description Reset

Value

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C163-L

Absolute Maximum Ratings

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at

these or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect device reliability.

During absolute maximum rating overload conditions (

IN>

DD or

IN<

SS) the voltage on

DD pins with respect to ground (

SS) must not exceed the values defined by the absolute

maximum ratings.

Parameter Symbol Limit Values Unit Notes

min. max.

Storage temperature TST -65 150 °C

Voltage on VDD pins with

respect to ground (VSS)VDD -0.5 6.5 V

Voltage on any pi n with

respect to ground (VSS)VIN -0.5 VDD+0.5 V

Input current on any pin

during overload condition -10 10 mA

Absolute sum of all input

currents during overload

condition

- |100| mA

Power dissipation PDISS -1.5 W

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C163-L

Operating Conditions

The following opera ting conditions must not be exc eeded in order to ensure corre ct operation of the

C163-L. All parameters specified in the following sections refer to these operating conditions,

unless otherwise noticed.

Note: Operation at reduced supply voltage is defined for the 25 MHz devices (SA*-C163L25F)

only.

Parameter Interpretation

The parameters listed in the following partly represent the characteristics of the C163-L and partly

its demands on the system. To aid in interpreting the parameters right, when evalua ting them for a

design, they are marked in column “Symbol”:

CC (Controller Characteristics):

The logic of the C163-L will provide signals with the respective timing characteristics.

SR (System Requirement):

The external system must provide signals with the respective timing characteristics to the C163-L.

1) Overload conditions occur if the standard operatings conditions are exceeded, ie. the voltage on any pin

exceeds the specified range (ie. VOV >V

DD+0.5V, except pin OWE, or VOV <V

SS-0.5V). The absolute sum of

input overload currents on all port pins may not exceed 50 mA. The supply voltage must remain within the

specified limits.

2) Not 100% te s te d, guaranteed by de s ign c haracterizat ion.

Parameter Symbol Limit Values Unit Notes

min. max.

Digital supply voltage VDD 4.5 5.5 V Active mode,

fCPUmax = 25 MHz

2.5 5.5 V PowerDown mode

Reduced digital supply

voltage VDD 2.7 3.6 V Active mode,

fCPUmax = 12 MHz

Digital ground voltage VSS 0 V R eference voltage

Overload current IOV -±5 mA Per pin 1) 2)

Absolute sum of overload

currents Σ|IOV|- 50 mA

Ambient temperature TA0 70 °C SAB-C163-L...

-40 85 °C SAF-C163-L...

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C163-L

DC Characteristics (Standard Supply Voltage Range)

(Operating Conditions apply)

Parameter Symbol Limit Values Unit Test Condition

min. max.

Input low voltage VIL SR – 0.5 0.2 VDD

– 0.1 V–

Input high voltage

(all except RSTIN and XTAL1) VIH SR 0.2 VDD

+ 0.9 VDD + 0.5 V –

Input high voltage RSTIN VIH1 SR 0.6 VDD VDD + 0.5 V –

Input high voltage XTAL1 VIH2 SR 0.7 VDD VDD + 0.5 V –

Output low voltage

(PORT0, PORT1, Port 4, ALE, RD,

WR, BHE, CLKOUT, RSTOUT)

VOL CC – 0.45 V IOL = 2.4 mA

Output low voltage

(all other outputs) VOL1 CC – 0.45 V IOL1 = 1.6 mA

Output high voltage

(PORT0, PORT1, Port 4, ALE, RD,

WR, BHE, CLKOUT, RSTOUT)

VOH CC 0.9 VDD

2.4 –

–V

VIOH = – 500 µA

IOH = – 2.4 mA

Output high voltage 1)

(all other outputs) VOH1 CC 0.9 VDD

2.4 –V

VIOH = – 250 µA

IOH = – 1.6 mA

Input leakage current (Port 5) IOZ1 CC – ±200 nA 0.45 V < VIN < VDD

Input leakage current (all other) IOZ2 CC – ±500 nA 0.45 V < VIN < VDD

RSTIN pullup resistor RRST CC 50 250 kΩ–

Read/Write inactive current 2) IRWH 3) –-40µAVOUT = 2.4 V

Read/Write active current 2) IRWL 4) -500 – µAVOUT = VOLmax

ALE inactive current 2) IALEL 3) –40µAVOUT = VOLmax

ALE active current 2) IALEH 4) 500 – µAVOUT = 2.4 V

Port 6 inactive current 2) IP6H 3) –-40µAVOUT = 2.4 V

Port 6 active current 2) IP6L 4) -500 – µAVOUT = VOL1max

PORT0 configuration current 2) IP0H 3) –-10µAVIN = VIHmin

IP0L 4) -100 – µAVIN = VILmax

XTAL1 input current IIL CC – ±20 µA0 V < VIN < VDD

Pin capacitance 5)

(digital inputs/outputs) CIO CC – 10 pF f = 1 MHz

TA = 25 °C

Power supply current

(at 5 V supply voltage) IDD5 – 10 +

3.5 * fCPU

mA RSTIN = VIL2

fCPU in [MHz] 6)

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C163-L

1) This specif ication is not valid for ou tputs which are swit ched to open drain mode. In this case th e respective

output will floa t an d th e vo lt age results from th e ex t ernal circuitry.

2) This specif ication is only valid during Reset, or during Hold- or Adap t-mode. Por t 6 pins are only affected, if

they are used for CS output and th e open drain func tio n is not enabled.

3) The maxim um current ma y be draw n while the respective signa l line remains ina ctiv e.

4) The minimum current must be drawn in order to drive the respective signal line active.

5) Not 100% te s te d, guaranteed by de s ign c haracterizat ion.

6) The supply current is a function of the operating frequency. This dependency is illustrated in the figure below.

These parameters are tested at VDDmax and maximum CPU clock with all outputs disconnected and all inputs

at VIL or VIH.

7) This para meter is tested including leakag e curren ts. All inputs (inc luding p ins con figured as inpu ts) at 0 V to

0.1 V or at VDD – 0.1 V to VDD, VREF = 0 V, all outputs (inc luding pins con fi gured as outpu ts) dis c onnected.

Idle mode supply current

(at 5 V supply voltage) IID5 –2 +

1.1 * fCPU

mA RSTIN = VIH1

fCPU in [MHz] 6)

Power-down mode supply current

(at 5 V supply voltage) IPD5 –50µAVDD = VDDmax 7)

Parameter Symbol Limit Values Unit Test Condition

min. max.

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DC Characteristics (Reduced Supply Voltage Range)

(Operating Conditions apply)

Parameter Symbol Limit Values Unit Test Condition

min. max.

Input low voltage VIL SR – 0.5 0.8 V –

Input high voltage

(all except RSTIN and XTAL1) VIH SR 1.8 VDD + 0.5 V –

Input high voltage RSTIN VIH1 SR 0.6 VDD VDD + 0.5 V –

Input high voltage XTAL1 VIH2 SR 0.7 VDD VDD + 0.5 V –

Output low voltage

(PORT0, PORT1, Port 4, ALE, RD,

WR, BHE, CLKOUT, RSTOUT)

VOL CC – 0.45 V IOL = 1.6 mA

Output low voltage

(all other outputs) VOL1 CC – 0.45 V IOL1 = 1.0 mA

Output high voltage

(PORT0, PORT1, Port 4, ALE, RD,

WR, BHE, CLKOUT, RSTOUT)

VOH CC 0.9 VDD –VIOH = – 500 µA

Output high voltage 1)

(all other outputs) VOH1 CC 0.9 VDD –VIOH = – 250 µA

Input leakage current (Port 5) IOZ1 CC – ±200 nA 0.45 V < VIN < VDD

Input leakage current (all other) IOZ2 CC – ±500 nA 0.45 V < VIN < VDD

RSTIN pullup resistor RRST CC 50 250 kΩ–

Read/Write inactive current 2) IRWH 3) –-10µAVOUT = 2.4 V

Read/Write active current 2) IRWL 4) -500 – µAVOUT = VOLmax

ALE inactive current 2) IALEL 3) –20µAVOUT = VOLmax

ALE active current 2) IALEH 4) 500 – µAVOUT = 2.4 V

Port 6 inactive current 2) IP6H 3) –-10µAVOUT = 2.4 V

Port 6 active current 2) IP6L 4) -500 – µAVOUT = VOL1max

PORT0 configuration current 2) IP0H 3) –-5µAVIN = VIHmin

IP0L 4) -100 – µAVIN = VILmax

XTAL1 input current IIL CC – ±20 µA0 V < VIN < VDD

Pin capacitance 5)

(digital inputs/outputs) CIO CC – 10 pF f = 1 MHz

TA = 25 °C

Power supply current

(at 3 V supply voltage) IDD3 – 10 +

1.5 * fCPU

mA RSTIN = VIL2

fCPU in [MHz] 6)

11Aug98@14:48h Intermediate Version

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