Atmel-8811C-SEEPROM-AT93C56B-66B-Auto-Datasheet_022016
Features
Medium-voltage and Standard-voltage Operation
VCC = 2.5V to 5.5V
Automotive Temperature Range -40C to 125C
User-selectable Internal Organization
2K: 256 x 8 or 128 x 16
4K: 512 x 8 or 256 x 16
3-wire Serial Interface
Sequential Read Operation
2MHz Clock Rate
Self-timed Write Cycle (5ms max)
High Reliability
Endurance: 1,000,000 Write Cycles
Data Retention: 100 Years
Lead-free/Halogen-free Devices Available
8-lead JEDEC SOIC and 8-lead TSSOP Packages
Description
The Atmel® AT93C56B/66B provides 2,048/4,096 bits of Serial Electrically
Erasable Programmable Read-Only Memory (EEPROM). The EEPROM is
organized as 128/256 words of 16 bits each when the ORG pin is connected to
VCC and 256/512 words of 8 bits each when it is tied to ground. The device is
optimized for use in many automotive applications where low-power and
low-voltage operations are essential. AT93C56B/66B is available in space-saving
8-lead JEDEC SOIC and 8-lead TSSOP packages.
AT93C56B/66B is enabled through the Chip Select (CS) pin and accessed via a
3-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift
Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and
the data is clocked out serially on the data output pin DO. The write cycle is
completely self-timed and no separate erase cycle is required before write. The
write cycle is only enabled when the part is in the Erase/Write Enable state. When
CS is brought high following the initiation of a write cycle, the DO pin outputs the
Ready/Busy status of the part.
AT93C56B/66B operates from 2.5V to 5.5V.
AT93C56B and AT93C66B
3-wire Automotive Temperature Serial EEPROM
2K (256 x 8 or 128 x 16) and 4K (512 x 8 or 256 x 16)
DATASHEET
AT93C56B/66B Automotive [DATASHEET]
Atmel-8811C-SEEPROM-AT93C56B-66B-Auto-Datasheet_022016
2
1. Pin Configuration and Pinouts
Figure 1. Pin Configurations
2. Absolute Maximum Ratings*
Pin Name Function
CS Chip Select
SK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
GND Ground
VCC Power Supply
ORG Internal Organization
DC Don’t Connect
Operating Temperature 55C to +125C
Storage Temperature 65C to +150C
Voltage on any pin
with respect to ground 1.0V to +7.0V
Maximum Operating Voltage . . . . . . . . . . . . . . . 6.25V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . .5.0mA
*Notice: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only
and functional operation of the device at these or
any other conditions beyond those indicated in
the operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability
8-lead TSSOP
(Top View)
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
DC
ORG
GND
1
2
3
4
CS
SK
DI
DO
8
7
6
5
VCC
DC
ORG
GND
8-lead SOIC
(Top View)
Note: Drawings are not to scale.
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3. Block Diagram
Figure 3-1. Block Diagram
Note: When the ORG pin is connected to VCC, the “x 16” organization is selected. When it is connected to ground,
the “x 8” organization is selected. If the ORG pin is left unconnected and the application does not load the input
beyond the capability of the internal 1m pullup, then the “x 16” organization is selected.
Address
Decoder
Output
Buffer
Memory Array
256/512 x 8
or
128/256 x 16
Data
Register
Mode
Decode
Logic
Clock
Generator
ORG
DI
CS
SK
VCC GND
DO
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4
4. Electrical Characteristics
4.1 Pin Capacitance
Table 4-1. Pin Capacitance(1)
Note: 1. This parameter is characterized and is not 100% tested.
4.2 DC Characteristics
Table 4-2. DC Characteristics
Note: 1. VIL min and VIH max are reference only and are not tested.
Applicable over recommended operating range from TA = 25C, f = 1.0MHz, VCC = +5.0V (unless otherwise noted).
Symbol Test Conditions Max Units Conditions
COUT Output Capacitance (DO) 5 pF VOUT = 0V
CIN Input Capacitance (CS, SK, DI) 5 pF VIN = 0V
Applicable over recommended operating range from: TA = 40C to +125C, VCC = +2.5V to +5.5V (unless otherwise noted).
Symbol Parameter Test Condition Min Typ Max Unit
VCC1 Supply Voltage 2.5 5.5 V
VCC2 Supply Voltage 4.5 5.5 V
ICC Supply Current VCC = 5.0V
Read at 1.0MHz 0.5 2.0 mA
Write at 1.0MHz 0.5 2.0 mA
ISB1 Standby Current VCC = 2.5V CS = 0V 3.0 10.0 μA
ISB2 Standby Current VCC = 5.0V CS = 0V 10.0 15.0 μA
IIL Input Leakage VIN = 0V to VCC 0.1 3.0 μA
IOL Output Leakage VIN = 0V to VCC 0.1 3.0 μA
VIL1(1) Input Low Voltage
2.5V VCC 5.5V
0.6 0.8 V
VIH1(1) Input High Voltage 2.0 VCC + 1
VOL1 Output Low Voltage
2.5V VCC 5.5V
IOL = 2.1m 0.4 V
VOH1 Output High Voltage IOH = 0.4mA 2.4 V
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AT93C56B/66B Automotive [DATASHEET]
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4.3 AC Characteristics
Table 4-3. AC Characteristics
Note: 1. This parameter is characterized and is not 100% tested.
Applicable over recommended operating range from TA = 40°C to + 125°C, VCC = As Specified,
CL = 1 TTL Gate and 100pF (unless otherwise noted).
Symbol Parameter Test Condition Min Typ Max Units
fSK
SK Clock
Frequency
4.5V VCC 5.5V
2.5V VCC 5.5V
0
0
2
1MHz
tSKH SK High Time 4.5V VCC 5.5V
2.5V VCC 5.5V
250
250 ns
tSKL SK Low Time 4.5V VCC 5.5V
2.5V VCC 5.5V
250
250 ns
tCS
Minimum CS
Low Time
4.5V VCC 5.5V
2.5V VCC 5.5V
250
250 ns
tCSS CS Setup Time Relative to SK 4.5V VCC 5.5V
2.5V VCC 5.5V
50
50 ns
tDIS DI Setup Time Relative to SK 4.5V VCC 5.5V
2.5V VCC 5.5V
100
100 ns
tCSH CS Hold Time Relative to SK 0 ns
tDIH DI Hold Time Relative to SK 4.5V VCC 5.5V
2.5V VCC 5.5V
100
100 ns
tPD1 Output Delay to “1” AC Test 4.5V VCC 5.5V
2.5V VCC 5.5V
250
500 ns
tPD0 Output Delay to “0” AC Test 4.5V VCC 5.5V
2.5V VCC 5.5V
250
500 ns
tSV CS to Status Valid AC Test 4.5V VCC 5.5V
2.5V VCC 5.5V
250
250 ns
tDF
CS to DO in High
Impedance
AC Test
CS = VIL
4.5V VCC 5.5V
2.5V VCC 5.5V
100
150 ns
tWP Write Cycle Time 2.5V VCC 5.5V 5 ms
Endurance(1) 5.0V, 25°C 1M Write Cycles
AT93C56B/66B Automotive [DATASHEET]
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6
5. Instruction Set
Table 5-1. Instruction Set for the AT93C56B/66B
Note: The X in the address field represent don’t care values and must be clocked.
Instruction SB Opcode
Address Data
Commentsx 8 x 16 x 8 x 16
Read 1 10 A8 – A0 A7 A0 Reads data stored in memory, at
specified address.
EWEN 1 00 11XXXXXXX 11XXXXXX Write enable must precede all
programming modes.
Erase 1 11 A8 A0 A7 A0 Erase memory location An A0.
Write 1 01 A8 A0 A7 A0 D7 D0 D15 D0 Writes memory location An A0.
ERAL 1 00 10XXXXXXX 10XXXXXX Erases all memory locations. Valid
only at VCC = 4.5V to 5.5V.
WRAL 1 00 01XXXXXXX 01XXXXXX D7 D0 D15 D0
Writes all memory locations. Valid
only at VCC = 5.0V ±10% and
Disable Register cleared.
EWDS 1 00 00XXXXXXX 00XXXXXX Disables all programming
instructions.
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AT93C56B/66B Automotive [DATASHEET]
Atmel-8811C-SEEPROM-AT93C56B-66B-Auto-Datasheet_022016
6. Functional Description
AT93C56B/66B is accessed via a simple and versatile three-wire serial communication interface. Device
operation is controlled by seven instructions issued by the host processor. A valid instruction starts with a rising
edge of CS and consists of a start bit (Logic 1) followed by the appropriate opcode and the desired memory
address location.
Read: The Read instruction contains the address code for the memory location to be read. After the instruction
and address are decoded, data from the selected memory location is available at the serial output pin DO.
Output data changes are synchronized with the rising edges of serial clock SK. It should be noted that a dummy
bit (Logic 0) precedes the 8- or 16-bit data output string. AT93C56B/66B supports sequential read operations.
The device will automatically increment the internal address pointer and clock out the next memory location as
long as Chip Select (CS) is held high. In this case, the dummy bit (Logic 0) will not be clocked out between
memory locations, thus allowing for a continuous stream of data to be read.
Figure 6-1. Read Timing
Erase/Write Enable (EWEN): To assure data integrity, the part automatically goes into the Erase/Write Disable
(EWDS) state when power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first
before any programming instructions can be carried out. Please note that once in the EWEN state,
programming remains enabled until an EWDS instruction is executed or VCC power is removed from the part.
Figure 6-2. EWEN Timing
High Impedance
tCS
CS
SK
DI
DO
AN
DN D0
A0
CS
11 ...
001
SK
DI
tCS
AT93C56B/66B Automotive [DATASHEET]
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Erase: The Erase instruction programs all bits in the specified memory location to the Logical 1 state. The
self-timed erase cycle starts once the Erase instruction and address are decoded. The DO pin outputs the
Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250ns (tCS). A Logic 1
at pin DO indicates that the selected memory location has been erased, and the part is ready for another
instruction.
Figure 6-3. Erase Timing
Write: The Write instruction contains the 8 or 16 bits of data to be written into the specified memory location.
The self-timed programming cycle, tWP, starts after the last bit of data is received at serial data input pin DI. The
DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of
250ns (tCS). A Logic 0 at DO indicates that programming is still in progress. A Logic 1 indicates that the memory
location at the specified address has been written with the data pattern contained in the instruction and the part
is ready for further instructions. A Ready/Busy status cannot be obtained if the CS is brought high after the end
of the self-timed programming cycle, tWP..
Figure 6-4. Write Timing
CS
SK
DI
DO High Impedance High Impedance
1 1 ...1
t
CS
t
SV
t
DF
t
WP
CHECK
STATUS
STANDBY
READY
BUSY
AN AN-1 AN-2 A0
tCS
tWP
110... ...
BUSY READY
CS
SK
DI
DO High Impedance
AN A0 DN D0
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AT93C56B/66B Automotive [DATASHEET]
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Erase All (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array to the Logic 1 state
and is primarily used for testing purposes. The DO pin outputs the ready/busy status of the part if CS is brought
high after being kept low for a minimum of 250ns (tCS). The ERAL instruction is valid only at VCC = 5.0V 10%.
Figure 6-5. ERAL Timing
Note: 1. Valid only at VCC = 4.5V to 5.5V.
Write All (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns
specified in the instruction. The DO pin outputs the Ready/Busy status of the part if CS is brought high after
being kept low for a minimum of 250ns (tCS). The WRAL instruction is valid only at VCC = 5.0V ±10%.
Figure 6-6. WRAL Timing
Note: 1. Valid only at VCC = 4.5V to 5.5V
CS
SK
DI
DO High Impedance
11000
High Impedance
READY
BUSY
CHECK
S TAT U S
STANDBY
tWP
tCS
tSV tDF
CS
SK
DI
DO High Impedance BUSY
READY
1 0 0 1 ...
tCS
tWP
...0 DN D0
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Erase/Write Disable (EWDS): To protect against accidental data disturb, the Erase/Write Disable (EWDS)
instruction disables all programming modes and should be executed after all programming operations. The
operation of the Read instruction is independent of both the EWEN and EWDS instructions and can be
executed at any time.
Figure 6-7. EWDS Timing
tCS
10
000 ...
CS
SK
DI
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AT93C56B/66B Automotive [DATASHEET]
Atmel-8811C-SEEPROM-AT93C56B-66B-Auto-Datasheet_022016
7. Timing Diagrams
Figure 7-1. Synchronous Data Timing
Note: This is the minimum SK period.
Table 7-1. Organization Key for Timing Diagrams
Notes: 1. A8 is a don’t care value, but the extra clock is required.
2. A7 is a don’t care value, but the extra clock is required.
7.1 Power Recommendation
The device internal POR (Power-On Reset) threshold is just below the minimum device operating voltage.
Power shall rise monotonically from 0.0Vdc to full VCC in less than 1ms. Hold at full VCC for at least 100μs before
the first operation. Power shall drop from full VCC to 0.0Vdc in less than 1ms. Power dropping to a non-zero level
and then slowly going to zero is not recommended. Power shall remain off (0.0Vdc) for 0.5s minimum. Please
consult Atmel if your power conditions do not meet the above recommendations.
I/O
AT93C56B (2K) AT93C66B (4K)
x 8 x 16 x 8 x 16
AN A8(1) A7(2) A8 A7
DN D7 D15 D7 D15
Status Valid
VIH
VIL
VIH
VIL
CS
SK
DI
DO (READ)
DO (PROGRAM)
VIH
VIL
VOH
VOL
VOH
VOL
tCSS
tDIS
tSV
tSKH
tDIH
tPD0
tSKL
1µs(1)
tPD1
tCSH
tDF
tDF
AT93C56B/66B Automotive [DATASHEET]
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12
8. Ordering Information
8.1 Ordering Code Detail
8.2 Atmel Ordering Code Information
AT93C56B-SSPD-T
Atmel Designator
Product Family
Device Density
Device Revision Package Type
56 = 2 kilobit
66 = 4 kilobit
Package Device Grade
SS = JEDEC SOIC
X = TSSOP
Shipping Carrier Option
T = Tape and Reel
Operating Voltage
D = 2.5V to 5.5V
93C = 3-wire Automotive
Serial EEPROM
P = Lead-free / Halogen-free
AutomotiveTemperature Range
(-40°C to +125°C)
Ordering Code Lead Finish Package
Delivery Information
Operation RangeForm Quantity
AT93C56B-SSPD-T Lead-free
Halogen-free
8S1
Tape and Reel
4,000 per Reel Automotive
Temperature
(40C to 125C)
AT93C56B-XPD-T 8X 5,000 per Reel
AT93C66B-SSPD-T Lead-free
Halogen-free
8S1
Tape and Reel
4,000 per Reel Automotive
Temperature
(40C to 125C)
AT93C66B-XPD-T 8X 5,000 per Reel
Package Type
8S1 8-lead, 0.150" wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8X 8-lead, 4.4mm body, Plastic Thin Shrink Small Outline (TSSOP)
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Atmel-8811C-SEEPROM-AT93C56B-66B-Auto-Datasheet_022016
9. Product Markings
DRAWING NO. REV.
TITLE
Catalog Number Truncation
AT93C56B Truncation Code ###: 56B
AT93C66B Truncation Code ###: 66B
AAAAAAAA
###D @
ATMLPYWW
8-lead SOIC 8-lead TSSOP
AAAAAAA
###D @
ATPYWW
Note 2: Package drawings are not to scale
Note 1: designates pin 1
93C56-66BAM C
3/15/12
93C56-66BAM, AT93C56B and AT93C66B Automotive
Package Marking Information
Date Codes Voltages
Y = Year M = Month WW = Work Week of Assembly D: 2.5V min
2: 2012 6: 2016 A: January 02: Week 2
3: 2013 7: 2017 B: February 04: Week 4
4: 2014 8: 2018 ... ...
5: 2015 9: 2019 L: December 52: Week 52
Country of Assembly Lot Number Grade/Lead Finish Material
@ = Country of Assembly AAA...A = Atmel Wafer Lot Number P: Automotive/NiPdAu
Trace Code Atmel Truncation
XX = Trace Code (Atmel Lot Numbers Correspond to Code) AT: Atmel
Example: AA, AB.... YZ, ZZ ATM: Atmel
ATML: Atmel
AT93C56B and AT93C66B: Package Marking Information
Package Mark Contact:
DL-CSO-Assy_eng@atmel.com
AT93C56B/66B Automotive [DATASHEET]
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14
10. Packaging Information
10.1 8S1 — 8-lead JEDEC SOIC
DRAWING NO. REV. TITLE GPC
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A1 0.10 – 0.25
A – – 1.75
b 0.31 – 0.51
C 0.17 – 0.25
D 4.90 BSC
E 6.00 BSC
E1 3.90 BSC
e 1.27 BSC
L 0.40 – 1.27
Ø
Ø
0° – 8°
Ø
E
1
N
TOP VIEW
C
E1
END VIEW
A
b
L
A1
e
D
SIDE VIEW
Package Drawing Contact:
packagedrawings@atmel.com
8S1 H
3/6/2015
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC) SWB
15
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10.2 8X — 8-lead TSSOP
DRAWING NO. REV. TITLE GPC
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A - - 1.20
A1 0.05 - 0.15
A2 0.80 1.00 1.05
D 2.90 3.00 3.10 2, 5
E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
b 0.19 0.25 0.30 4
e 0.65 BSC
L 0.45 0.60 0.75
L1 1.00 REF
C 0.09 - 0.20
Side View
End View
Top View
A2
A
L
L1
D
1
E1
N
b
Pin 1 indicator
this corner
E
e
Notes: 1. This drawing is for general information only.
Refer to JEDEC Drawing MO-153, Variation AA, for proper
dimensions, tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate
burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions.
Inter-lead Flash and protrusions shall not exceed 0.25mm
(0.010in) per side.
4. Dimension b does not include Dambar protrusion.
Allowable Dambar protrusion shall be 0.08mm total in excess
of the b dimension at maximum material condition. Dambar
cannot be located on the lower radius of the foot. Minimum
space between protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
Package Drawing Contact:
packagedrawings@atmel.com
8X E
2/27/14
8X, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP) TNR
C
A1
AT93C56B/66B Automotive [DATASHEET]
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16
11. Revision History
Doc. Rev. Date Comments
8811C 02/2016 Updated 8S1 and 8X package drawings and ordering information. Added the ordering
code detail. Removed bulk(tube) options. Document reorganization.
8811B 08/2012 Removed preliminary status.
Updated Atmel logos and disclaimer/copy page.
8811A 06/2012 Initial document release
X
XXX
XX
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© 2016 Atmel Corporation. / Rev.: Atmel-8811C-SEEPROM-AT93C56B-66B-Auto-Datasheet_022016.
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