LP38841
LP38841 0.8A Ultra Low Dropout Linear RegulatorsStable with Ceramic Output
Capacitors
Literature Number: SNVS289B
LP38841
0.8A Ultra Low Dropout Linear Regulators
Stable with Ceramic Output Capacitors
General Description
The LP38841 is a high current, fast response regulator
which can maintain output voltage regulation with minimum
input to output voltage drop. Fabricated on a CMOS process,
the device operates from two input voltages: Vbias provides
voltage to drive the gate of the N-MOS power transistor,
while Vin is the input voltage which supplies power to the
load. The use of an external bias rail allows the part to
operate from ultra low Vin voltages. Unlike bipolar regula-
tors, the CMOS architecture consumes extremely low quies-
cent current at any output load current. The use of an
N-MOS power transistor results in wide bandwidth, yet mini-
mum external capacitance is required to maintain loop sta-
bility.
The fast transient response of these devices makes them
suitable for use in powering DSP, Microcontroller Core volt-
ages and Switch Mode Power Supply post regulators. The
parts are available in TO-220 and TO-263 packages.
Dropout Voltage: 75 mV (typ) @0.8A load current.
Quiescent Current: 30 mA (typ) at full load.
Shutdown Current: 30 nA (typ) when S/D pin is low.
Precision Output Voltage: 1.5% room temperature accu-
racy.
Features
nIdeal for conversion from 1.8V or 1.5V inputs
nDesigned for use with low ESR ceramic capacitors
n0.8V, 1.2V and 1.5V standard voltages available
nUltra low dropout voltage (75mV @0.8A typ)
n1.5% initial output accuracy
nLoad regulation of 0.1%/A (typical)
n30nA quiescent current in shutdown (typical)
nLow ground pin current at all loads
nOver temperature/over current protection
nAvailable in 5 lead TO220 and TO263 packages
n−40˚C to +125˚C junction temperature range
Applications
nASIC Power Supplies In:
- Desktops, Notebooks, and Graphics Cards, Servers
- Gaming Set Top Boxes, Printers and Copiers
nServer Core and I/O Supplies
nDSP and FPGA Power Supplies
nSMPS Post-Regulator
Typical Application Circuit
20102801
* Minimum value required if Tantalum capacitor is used (see Application Hints).
September 2006
LP38841 0.8A Ultra Low Dropout Linear Regulators
Stable with Ceramic Output Capacitors
© 2006 National Semiconductor Corporation DS201028 www.national.com
Connection Diagrams
20102802
TO-220, Top View
20102803
TO-263, Top View
Pin Descriptions
Pin Name Description
BIAS The bias pin is used to provide the low current bias voltage to the chip which operates the internal
circuitry and provides drive voltage for the N-FET.
OUTPUT The regulated output voltage is connected to this pin.
GND This is both the power and analog ground for the IC. Note that both pin three and the tab of the
TO-220 and TO-263 packages are at ground potential. Pin three and the tab should be tied together
using the PC board copper trace material and connected to circuit ground.
INPUT The high current input voltage which is regulated down to the nominal output voltage must be
connected to this pin. Because the bias voltage to operate the chip is provided seperately, the input
voltage can be as low as a few hundered millivolts above the output voltage.
SHUTDOWN This provides a low power shutdown function which turns the regulated output OFF. Tie to V
BIAS
if
this function is not used.
Ordering Information
Order Number Package Type Package Drawing Supplied As
LP38841S-0.8 TO263-5 TS5B Rail
LP38841SX-0.8 TO263-5 TS5B Tape and Reel
LP38841T-0.8 TO220-5 T05A Rail
LP38841T-0.8 LB03 TO220-5 T05D Rail
LP38841S-1.2 TO263-5 TS5B Rail
LP38841SX-1.2 TO263-5 TS5B Tape and Reel
LP38841T-1.2 TO220-5 T05A Rail
LP38841T-1.2 LB03 TO220-5 T05D Rail
LP38841S-1.5 TO263-5 TS5B Rail
LP38841SX-1.5 TO263-5 TS5B Tape and Reel
LP38841T-1.5 TO220-5 T05A Rail
LP38841T-1.5 LB03 TO220-5 T05D Rail
LP38841
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Block Diagram
20102824
LP38841
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature Range −65˚C to +150˚C
Lead Temp. (Soldering, 5 seconds) 260˚C
ESD Rating
Human Body Model (Note 3)
Machine Model (Note 9)
2kV
200V
Power Dissipation (Note 2) Internally Limited
V
IN
Supply Voltage (Survival) −0.3V to +6V
V
BIAS
Supply Voltage (Survival) −0.3V to +7V
Shutdown Input Voltage (Survival) −0.3V to +7V
I
OUT
(Survival) Internally Limited
Output Voltage (Survival) −0.3V to +6V
Junction Temperature −40˚C to +150˚C
Operating Ratings
V
IN
Supply Voltage (V
OUT
+V
DO
) to 5.5V
Shutdown Input Voltage 0 to +5.5V
I
OUT
0.8A
Operating Junction
Temperature Range
−40˚C to +125˚C
V
BIAS
Supply Voltage 4.5V to 5.5V
V
OUT
0.8V to 1.5V
Electrical Characteristics Limits in standard typeface are for T
J
= 25˚C, and limits in boldface type apply
over the full operating temperature range. Unless otherwise specified: V
IN
=V
O
(NOM) + 1V, V
BIAS
= 4.5V, I
L
= 10 mA, C
IN
=
10 µF CER, C
OUT
= 22 µF CER, C
BIAS
= 1 µF CER, V
S/D
=V
BIAS
. Min/Max limits are guaranteed through testing, statistical
correlation, or design.
Symbol Parameter Conditions Min Typ
(Note 4) Max Units
V
O
Output Voltage Tolerance 10 mA <I
L
<0.8A
V
O
(NOM) + 1V V
IN
5.5V
4.5V V
BIAS
5.5V
0.788
0.776 0.8 0.812
0.824
V
1.182
1.164 1.2 1.218
1.236
1.478
1.455 1.5 1.523
1.545
V
O
/V
IN
Output Voltage Line Regulation
(Note 6)
V
O
(NOM) + 1V V
IN
5.5V 0.01 %/V
V
O
/I
L
Output Voltage Load Regulation
(Note 7)
10 mA <I
L
<0.8A 0.1 0.4
1.3 %/A
V
DO
Dropout Voltage (Note 8) I
L
= 0.8A 75 120
205 mV
I
Q
(V
IN
) Quiescent Current Drawn from
V
IN
Supply
10 mA <I
L
<0.8A 30 35
40 mA
V
S/D
0.3V 0.06 1
30 µA
I
Q
(V
BIAS
) Quiescent Current Drawn from
V
BIAS
Supply
10 mA <I
L
<0.8A 24
6mA
V
S/D
0.3V 0.03 1
30 µA
I
SC
Short-Circuit Current V
OUT
= 0V 2.6 A
Shutdown Input
V
SDT
Output Turn-off Threshold Output = ON 0.7 1.3 V
Output = OFF 0.3 0.7
Td (OFF) Turn-OFF Delay R
LOAD
XC
OUT
<< Td (OFF) 20 µs
Td (ON) Turn-ON Delay R
LOAD
XC
OUT
<< Td (ON) 15
I
S/D
S/D Input Current V
S/D
=1.3V 1 µA
V
S/D
0.3V −1
θ
J-A
Junction to Ambient Thermal
Resistance
TO-220, No Heatsink 65 ˚C/W
TO-263, 1 sq.in Copper 35
LP38841
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Electrical Characteristics Limits in standard typeface are for T
J
= 25˚C, and limits in boldface type apply
over the full operating temperature range. Unless otherwise specified: V
IN
=V
O
(NOM) + 1V, V
BIAS
= 4.5V, I
L
= 10 mA, C
IN
=
10 µF CER, C
OUT
= 22 µF CER, C
BIAS
= 1 µF CER, V
S/D
=V
BIAS
. Min/Max limits are guaranteed through testing, statistical
correlation, or design. (Continued)
Symbol Parameter Conditions Min Typ
(Note 4) Max Units
AC Parameters
PSRR (V
IN
) Ripple Rejection for V
IN
Input
Voltage
V
IN
=V
OUT
+1V, f = 120 Hz 80
dB
V
IN
=V
OUT
+1V,f=1kHz 65
PSRR
(V
BIAS
)
Ripple Rejection for V
BIAS
Voltage
V
BIAS
=V
OUT
+ 3V, f = 120 Hz 58
V
BIAS
=V
OUT
+3V,f=1kHz 58
e
n
Output Noise Density f = 120 Hz 1 µV/root−Hz
Output Noise Voltage
V
OUT
= 1.5V
BW = 10 Hz 100 kHz 150 µV (rms)
BW = 300 Hz 300 kHz 90
Note 1: Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device
is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications, see Electrical Characteristics. Specifications do not
apply when operating the device outside of its rated operating conditions.
Note 2: At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink thermal values. θJ-A for TO-220
devices is 65˚C/W if no heatsink is used. If the TO-220 device is attached to a heatsink, a θJ-S value of 4˚C/W can be assumed. θJ-A for TO-263 devices is
approximately 35˚C/W if soldered down to a copper plane which is at least 1 square inch in area. If power dissipation causes the junction temperature to exceed
specified limits, the device will go into thermal shutdown.
Note 3: The human body model is a 100 pF capacitor discharged through a 1.5k resistor into each pin.
Note 4: Typical numbers represent the most likely parametric norm for 25˚C operation.
Note 5: If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to ground.
Note 6: Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.
Note 7: Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from no load to full load.
Note 8: Dropout voltage is defined as the minimum input to output differential required to maintain the output with 2% of nominal value.
Note 9: The machine model is a 220 pF capacitor discharged directly into each pin.
LP38841
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Typical Performance Characteristics Unless otherwise specified: T
J
= 25˚C, C
IN
= 10 µF CER,
C
OUT
= 22 µF CER, C
BIAS
= 1 µF CER,S/D Pin is tied to V
BIAS
,V
OUT
= 1.2V, I
L
= 10mA, V
BIAS
= 5V, V
IN
=V
OUT
+ 1V.
V
BIAS
Transient Response Dropout Voltage Over Temperature
20102836
20102839
V
OUT
vs Temperature V
BIAS
PSRR
20102840
20102841
V
BIAS
PSRR V
IN
PSRR
20102851 20102842
LP38841
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Application Hints
EXTERNAL CAPACITORS
To assure regulator stability, input and output capacitors are
required as shown in the Typical Application Circuit.
OUTPUT CAPACITOR
An output capacitor is required on the LP3884X devices for
loop stability. The minimum value of capacitance necessary
depends on type of capacitor: if a solid Tantalum capacitor is
used, the part is stable with capacitor values as low as 4.7µF.
If a ceramic capacitor is used, a minimum of 22 µF of
capacitance must be used (capacitance may be increased
without limit). The reason a larger ceramic capacitor is re-
quired is that the output capacitor sets a pole which limits the
loop bandwidth. The Tantalum capacitor has a higher ESR
than the ceramic which provides more phase margin to the
loop, thereby allowing the use of a smaller output capacitor
because adequate phase margin can be maintained out to a
higher crossover frequency. The tantalum capacitor will typi-
cally also provide faster settling time on the output after a
fast changing load transient occurs, but the ceramic capaci-
tor is superior for bypassing high frequency noise.
The output capacitor must be located less than one centi-
meter from the output pin and returned to a clean analog
ground. Care must be taken in choosing the output capacitor
to ensure that sufficient capacitance is provided over the full
operating temperature range. If ceramics are selected, only
X7R or X5R types may be used because Z5U and Y5F types
suffer severe loss of capacitance with temperature and ap-
plied voltage and may only provide 20% of their rated ca-
pacitance in operation.
INPUT CAPACITOR
The input capacitor is also critical to loop stability because it
provides a low source impedance for the regulator. The
minimum required input capacitance is 10 µF ceramic (Tan-
talum not recommended). The value of C
IN
may be in-
creased without limit. As stated above, X5R or X7R must be
used to ensure sufficient capacitance is provided. The input
capacitor must be located less than one centimeter from the
input pin and returned to a clean analog ground.
BIAS CAPACITOR
The 0.1µF capacitor on the bias line can be any good quality
capacitor (ceramic is recommended).
BIAS VOLTAGE
The bias voltage is an external voltage rail required to get
gate drive for the N-FET pass transistor. Bias voltage must
be in the range of 4.5 - 5.5V to assure proper operation of
the part.
UNDER VOLTAGE LOCKOUT
The bias voltage is monitored by a circuit which prevents the
regulator output from turning on if the bias voltage is below
approximately 4V.
SHUTDOWN OPERATION
Pulling down the shutdown (S/D) pin will turn-off the regula-
tor. Pin S/D must be actively terminated through a pull-up
resistor (10 kto 100 k) for a proper operation. If this pin
is driven from a source that actively pulls high and low (such
as a CMOS rail to rail comparator), the pull-up resistor is not
required. This pin must be tied to V
BIAS
if not used.
POWER DISSIPATION/HEATSINKING
A heatsink may be required depending on the maximum
power dissipation and maximum ambient temperature of the
application. Under all possible conditions, the junction tem-
perature must be within the range specified under operating
conditions. The total power dissipation of the device is given
by:
P
D
=(V
IN
−V
OUT
)I
OUT
+(V
IN
)I
GND
where I
GND
is the operating ground current of the device.
The maximum allowable temperature rise (T
Rmax
) depends
on the maximum ambient temperature (T
Amax
) of the appli-
cation, and the maximum allowable junction temperature
(T
Jmax
):
T
Rmax
=T
Jmax
−T
Amax
The maximum allowable value for junction to ambient Ther-
mal Resistance, θ
JA
, can be calculated using the formula:
θ
JA
=T
Rmax
/P
D
These parts are available in TO-220 and TO-263 packages.
The thermal resistance depends on amount of copper area
or heat sink, and on air flow. If the maximum allowable value
of θ
JA
calculated above is 60 ˚C/W for TO-220 package
and 60 ˚C/W for TO-263 package no heatsink is needed
since the package can dissipate enough heat to satisfy these
requirements. If the value for allowable θ
JA
falls below these
limits, a heat sink is required.
HEATSINKING TO-220 PACKAGE
The thermal resistance of a TO220 package can be reduced
by attaching it to a heat sink or a copper plane on a PC
board. If a copper plane is to be used, the values of θ
JA
will
be same as shown in next section for TO263 package.
The heatsink to be used in the application should have a
heatsink to ambient thermal resistance,
θ
HA
≤θ
JA
θ
CH
θ
JC
.
In this equation, θ
CH
is the thermal resistance from the case
to the surface of the heat sink and θ
JC
is the thermal resis-
tance from the junction to the surface of the case. θ
JC
is
about 3˚C/W for a TO220 package. The value for θ
CH
de-
pends on method of attachment, insulator, etc. θ
CH
varies
between 1.5˚C/W to 2.5˚C/W. If the exact value is unknown,
2˚C/W can be assumed.
HEATSINKING TO-263 PACKAGE
The TO-263 package uses the copper plane on the PCB as
a heatsink. The tab of this package is soldered to the copper
plane for heat sinking. The graph below shows a curve for
the θ
JA
of TO-263 package for different copper area sizes,
using a typical PCB with 1 ounce copper and no solder mask
over the copper area for heat sinking.
LP38841
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Application Hints (Continued)
As shown in the graph below, increasing the copper area
beyond 1 square inch produces very little improvement. The
minimum value for θ
JA
for the TO-263 package mounted to a
PCB is 32˚C/W.
Figure 2 shows the maximum allowable power dissipation
for TO-263 packages for different ambient temperatures,
assuming θ
JA
is 35˚C/W and the maximum junction tempera-
ture is 125˚C.
20102825
FIGURE 1. θ
JA
vs Copper (1 Ounce) Area for TO-263
package
20102826
FIGURE 2. Maximum power dissipation vs ambient
temperature for TO-263 package
LP38841
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Physical Dimensions inches (millimeters) unless otherwise noted
TO220 5-lead, Molded, Stagger Bend Package (TO220-5)
NS Package Number T05D
TO220 5-lead, Molded, Straight Lead Package (TO220-5)
NS Package Number T05A
LP38841
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
TO263 5-Lead, Molded, Surface Mount Package (TO263-5)
NS Package Number TS5B
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the right at any time without notice to change said circuitry and specifications.
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LP38841 0.8A Ultra Low Dropout Linear Regulators
Stable with Ceramic Output Capacitors
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