16-Channel, 16-Bit/12-Bit
Voltage Output denseDACs
Data Sheet
AD5766/AD5767
Rev. C Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2017–2018 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Complete 16-channel, 12-bit/16-bit DACs
8 software-programmable output ranges: −20 V to 0 V,
−16 V to 0 V, −10 V to 0 V, −10 V to +6 V, −12 V to +14 V,
−16 V to +10 V, ±5 V and ±10 V
Integrated DAC output buffers with ±20 mA output current
capability
4 mm × 4 mm WLCSP package and 40-lead LFCSP package
Integrated reference buffers
2 dither signal input pins
Channel monitoring multiplexer
1.8 V logic compatibility
Temperature range: −40°C to +105°C
APPLICATIONS
Mach Zehnder modulator bias control
Optical networking
Instrumentation
Industrial automation
Data acquisition systems
Analog output modules
GENERAL DESCRIPTION
The AD5766/AD5767 are 16-channel, 16-bit/12-bit, voltage output
denseDAC® digital-to-analog converters (DACs).
The DACs generate output voltage ranges from an external 2.5 V
reference. Depending on the voltage range selected, the midpoint
of the output span can be adjusted, allowing a minimum output
voltage as low as −20 V or a maximum output voltage of up to
+14 V. Each of the 16 channels can be monitored with an
integrated output voltage multiplexer.
The AD5766/AD5767 have integrated output buffers that can
sink or source up to 20 mA. In conjunction with these buffers, a
low frequency signal can be superimposed onto each DAC output
via dedicated dither pins. These dedicated dither pins simplify
the system design by reducing the number of external components
required for a similar external implementation, like operational
amplifiers or resistors. The reduction of external components
makes the AD5766/AD5767 suitable for indium phosphide Mach
Zehnder modulator (InP MZM) biasing applications.
The devices incorporate a power-on reset (POR) circuit that
ensures that the DAC outputs are clamped to ground on power
up and remain at this level until the output range of the DAC is
configured. The outputs of all DACs are updated through register
configuration, with the added functionality of user-selectable
DAC channels to be simultaneously updated.
The AD5766/AD5767 use a versatile 4-wire serial interface that
operates at clock rates of up to 50 MHz for write mode and is
compatible with serial peripheral interface (SPI), QSPI™,
MICROWIRE™, and DSP interface standards. The AD5766/
AD5767 also contain a VLOGIC pin intended for 1.8 V/3.3 V/5 V
logic.
The AD5766/AD5767 are available in a 4 mm × 4 mm WLCSP
package and a 40-lead LFCSP package. The AD5766/AD5767
operate at a temperature range of −40°C to +105°C.
FUNCTIONAL BLOCK DIAGRAM
INPUT
REGISTER 0
INPUT
REGISTER 1
n
n
n
DAC 0
DAC 1
n
DAC 15
RANGE
SET DAC
V
REF
V
OUT
15
V
OUT
1
V
OUT
0
SDI
SCLK
SDO
V
LOGIC
SYNC
AD5766/AD5767
INPUT
SHIFT
REGISTER
AND
CONTROL
LOGIC
AV
DD
INPUT
REGISTER 15
DAC
REGISTER 0
DAC
REGISTER 1
DAC
REGISTER 15
AV
CC
N0 N1
RESET
DGND
16-TO-1
MUX MUX_OUT
V
OUT
0
V
OUT
15
AGND AV
SS
AGND
15145-001
Figure 1.
AD5766/AD5767 Data Sheet
Rev. C | Page 2 of 43
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications ..................................................................................... 4
AC Performance Characteristics ................................................ 8
Timing Characteristics ................................................................ 9
Absolute Maximum Ratings .......................................................... 11
Thermal Resistance .................................................................... 11
ESD Caution ................................................................................ 11
Pin Configurations and Function Descriptions ......................... 12
Typical Performance Characteristics ........................................... 16
Dither Characteristics ................................................................ 25
Terminology .................................................................................... 27
Theory of Operation ...................................................................... 29
Digital-to-Analog Converter .................................................... 29
DAC Architecture ....................................................................... 29
Resistor String ............................................................................. 29
Power-On Reset (POR) .............................................................. 29
Dither ........................................................................................... 31
Dither Power-Down Mode ........................................................ 31
Monitor Mux ............................................................................... 31
Serial Interface ............................................................................ 32
Register Details ............................................................................... 33
Input Shift Register .................................................................... 33
Monitor Mux Control ................................................................ 34
No Operation .............................................................................. 35
Daisy-Chain Mode ..................................................................... 35
Write and Update Commands .................................................. 35
Span Register ............................................................................... 36
Dither Power Control Register ................................................. 36
Write Input Data to All DAC Registers ................................... 36
Software Full Reset ..................................................................... 37
Select Register for Readback ..................................................... 37
Apply N0 or N1 Dither Signal to DACs Register ................... 38
Dither Scale ................................................................................. 38
Invert Dither Register ................................................................ 39
Applications Information .............................................................. 40
Dither Configuration ................................................................. 40
Thermal Considerations ............................................................ 40
Microprocessor Interfacing ....................................................... 40
AD5766/AD5767 to SPI Interface............................................ 40
Layout Guidelines....................................................................... 41
Outline Dimensions ....................................................................... 42
Ordering Guide .......................................................................... 43
Data Sheet AD5766/AD5767
Rev. C | Page 3 of 43
REVISION HISTORY
1/2018—Rev. B to Rev. C
Changes to Output Voltage Settling Time Parameter, Table 3 ......... 8
Changes to Figure 6......................................................................... 14
Changes to Figure 11 ...................................................................... 16
Changes to Figure 13 ...................................................................... 17
Changes to Figure 37 ...................................................................... 21
Change to Terminology Section .................................................... 27
Changes to Figure 72 ...................................................................... 32
Changes to Ordering Guide ........................................................... 43
10/2017—Rev. A to Rev. B
Added AD5766 ................................................................... Universal
Changes to Features Section, Applications Section, and
General Description Section ............................................................ 1
Changes to Table 1 ............................................................................ 4
Added Table 2; Renumbered Sequentially ..................................... 7
Changes to Table 3 ............................................................................ 8
Changes to t14 and t15 Parameters, Table 4 and Figure 2 ............... 9
Changes to Figure 4......................................................................... 10
Change to AVCC Pin Description, Table 7 .................................... 13
Change to AVCC Pin Description, Table 8 .................................... 15
Changes to Figure 7 to Figure 12................................................... 16
Changes to Figure 13 to Figure 18 ................................................ 17
Deleted Figure 30; Renumbered Sequentially ............................. 17
Added Figure 19 to Figure 24; Renumbered Sequentially ......... 18
Added Figure 29 and Figure 30 ..................................................... 19
Added Figure 31 to Figure 36 ........................................................ 20
Added Figure 37 to Figure 42 ........................................................ 21
Added Figure 43 and Figure 46 ..................................................... 22
Changes to Figure 49 ...................................................................... 23
Added Figure 50 to Figure 54 ........................................................ 23
Changes to Figure 56 ...................................................................... 24
Added Figure 67 .............................................................................. 26
Changes to Digital-to-Analog Converter Section, DAC
Architecture Section, and Power-On Reset (POR) Section .......... 29
Added Figure 70 .............................................................................. 30
Changes to Dither Section and Dither Power-Down Mode
Section .............................................................................................. 31
Changes to Table 10 ........................................................................ 33
Added Table 17 and Table 19 ......................................................... 35
Changes to Dither Power Control Register Section, Table 26, Write
Input Data to All DAC Registers Section, and Table 28 ............... 36
Changes to Table 32 and Table 33 ................................................. 37
Changes to Dither Configuration Section ................................... 40
Updated Outline Dimensions........................................................ 42
Changes to Ordering Guide ........................................................... 43
4/2017—Rev. 0 to Rev. A
Added 40-Lead LFCSP Package ....................................... Universal
Changes to Features .......................................................................... 1
Changes to General Description ..................................................... 1
Changes to Functional Block Diagram, Figure 1 .......................... 1
Added Figure 6 and Added Table 7; Renumbered
Sequentially ...................................................................................... 12
Changes to Figure 23 and Figure 24 ............................................. 16
Added Figure 26 .............................................................................. 17
Changes to Figure 28 and Figure 29 ............................................. 17
Changes to Dither DC Shift Section ............................................. 20
Changes to Figure 43, Caption Only ............................................ 23
Changes to Input Shift Register Section and Table 9 ................. 25
Changes to Table 18 ........................................................................ 27
Changes to Thermal Considerations Section .............................. 32
Changes to Layout Guidelines Section and Added Figure 47 ... 33
Updated Outline Dimensions........................................................ 34
Changes to Ordering Guide ........................................................... 35
1/2017—Revision 0: Initial Versi on
AD5766/AD5767 Data Sheet
Rev. C | Page 4 of 43
SPECIFICATIONS
AVCC = 2.97 V to 3.6 V, VLOGIC = 1.7 V to 5.5 V, AVDD = 2.97 V to 16 V, AVSS = −22 V to −7 V, AGND = DGND = 0 V, VREF = 2.5 V, output
range = ± 5 V, VOUTx unloaded, all specifications TMIN to TMAX, typical specifications at TA = 25°C, dither powered on, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
STATIC PERFORMANCE
Resolution 16 Bits AD5766
12 Bits AD5767
Relative Accuracy (INL)
AD5766 −16 +16 LSB
AD5767 −1 +1 LSB
Differential Nonlinearity −1 +1 LSB Guaranteed monotonic by design
Bipolar Zero Error −85 ±12 +85 mV ±5 V range
−110 ±13 +110 mV −10 V to +6 V range
−120 ±15 +120 mV ±10 V range
−145
±16
+145
mV
−12 V to +14 V range
−145 ±16 +145 mV −16 V to +10 V range
Bipolar Zero Error Temperature
Coefficient (TC)
±2 ppm FSR/°C
Zero-Scale Error All 0s loaded to DAC register
−80 ±25 +80 mV −10 V to 0 V range
−80 ±25 +80 mV ±5 V range
−110 ±35 +110 mV −16 V to 0 V range
−110 ±35 +110 mV −10 V to +6 V range
−130 ±35 +130 mV −20 V to 0 V range
−130 ±35 +130 mV ±10 V range
−140
±45
+140
mV
−12 V to +14 V range
−140
±45
+140
mV
−16 V to +10 V range
Zero-Scale Error Temperature
Coefficient (TC)
±2 ppm FSR/°C
Full-Scale Error All 1s loaded to DAC register.
−0.9 ±0.23 +0.9 % FSR −10 V to 0 V range
−0.9 ±0.23 +0.9 % FSR ±5 V range
−0.8
±0.2
+0.8
% FSR
−16 V to 0 V range
−0.8 ±0.2 +0.8 % FSR −10 V to +6 V range
−0.7 ±0.18 +0.7 % FSR −20 V to 0 V range
−0.7 ±0.18 +0.7 % FSR ±10 V range
−0.6 ±0.15 +0.6 % FSR −12 V to +14 V range
−0.6
±0.15
+0.6
% FSR
−16 V to +10 V range
Full-Scale Error Drift ±3 ppm FSR/°C
Gain Error −0.4 ±0.07 +0.4 % FSR
Gain Error Temperature
Coefficient (TC)
±2 ppm FSR/°C
Offset Error −80 ±25 +80 mV −10 V to 0 V range
−80
±25
+80
mV
±5 V range
−110 ±35 +110 mV −16 V to 0 V range
−110 ±35 +110 mV −10 V to +6 V range
−130 ±35 +130 mV −20 V to 0 V range
−130 ±35 +130 mV ±10 V range
−140 ±45 +140 mV −12 V to +14 V range
−140 ±45 +140 mV −16 V to +10 V range
Offset Error Drift ±2 µV/°C
Data Sheet AD5766/AD5767
Rev. C | Page 5 of 43
Parameter Min Typ Max Unit Test Conditions/Comments
Total Unadjusted Error −0.9 ±0.18 +0.9 %FSR −10 V to 0 V range
−0.9 ±0.18 +0.9 %FSR ±5 V range
−0.8 ±0.15 +0.8 %FSR −16 V to 0 V range
−0.8 ±0.15 +0.8 %FSR −10 V to +6 V range
−0.7
±0.13
+0.7
%FSR
−20 V to 0 V range
−0.7 ±0.13 +0.7 %FSR ±10 V range
−0.6 ±0.12 +0.6 %FSR −12 V to +14 V range
−0.6 ±0.12 +0.6 %FSR −16 V to +10 V range
DC Crosstalk 30 µV Due to output voltage change
35 µV/mA Due to load current change (1 LSB)
OUTPUT CHARACTERISTICS
Output Voltage Ranges1 −20 0 V
−16 0 V
−10
0
V
−10 +6 V
−12 +14 V
−16 +10 V
−5 +5 V
−10
+10
V
Output Current −20 +20 mA Refer to the Thermal Considerations section
Capacitive Load Stability 1 nF
DC Output Impedance 0.2 Ω
Short-Circuit Current ±60 mA Single channel only
Output Amplifier Bandwidth 108 kHz
REFERENCE INPUT
Reference Input Voltage 2.5 V ±1% for specified performance
Reference Range 2.375 2.625 V Functional performance only
DC Input Impedance 2.5 MΩ
Input Current 1 µA
DITHER INPUTS
For dither input to DAC output attenuation, see
Figure 62 to Figure 65 for typical performance
Dither Frequency 10 kHz Lower −3 dB point
100 kHz Upper −3 dB point
Amplitude 0.25 V p-p Peak-to-peak ac voltage
0 AVCC V Peak-to-peak ac and dc voltage
DC Shift
See the Terminology section
AD5766 −2 ±1 +2 LSB
AD5767 −1 ±0.063 +1 LSB
Dither Transient Dither enabled/disabled, N0 and N1 floating
Dither Selected Channel 5 nV-sec AVCC = 2.97 V and AVCC = 3.6 V
Dither Nonselected Channels 2 nV-sec AVCC =2.97 V and AVCC = 3.6 V
Dither Crosstalk1 −70 dB 10 kHz dither frequency
−55 dB 100 kHz dither frequency
LOGIC INPUTS
Input High Voltage, VIH 0.7 × VLOGIC V
Input Low Voltage, VIL 0.3 × VLOGIC V
Input Current −2 +2
µA Per pin
−6 +6 µA RESET pin pulled high
−57 +57 µA RESET pin pulled low
Input Capacitance 2 pF Per pin
AD5766/AD5767 Data Sheet
Rev. C | Page 6 of 43
Parameter Min Typ Max Unit Test Conditions/Comments
LOGIC OUTPUT
Output Low Voltage 0.4 V Sinking 200 µA
Output High Voltage VLOGIC − 0.4 V Sourcing 200 µA
High Impedance Leakage
Current
−1 +1 µA
High Impedance Output
Capacitance
5 pF
VOLTAGE MONITOR PIN
(MUX_OUT)
Impedance 1.3 kΩ
Three-State Leakage Current −1 0.006 +1 µA
Continuous Current −1 +1 mA Die temperature below 105°C
Glitch Impulse 0.2 nV-sec VOUTx glitch due to mux enable
Voltage Settling Time
12
µs
¼ to ¾ scale settling to ±0.5 LSB, ±5 V range
and −10 V to 0 V range
POWER SUPPLIES
AVDD 2.97 16 V AVDD − AVSS must be less than or equal to 30 V
AVSS −22 −7 V AVDD − AVSS must be less than or equal to 30 V
AVCC 2.97 3.6 V
VLOGIC 1.7 5.5 V
Headroom/Footroom ±0.7 V Output voltage offset to ±2 LSB for 20 mA
output load; applies to AVDD and AVSS
±2 V Output voltage offset to ±1 LSB for 20 mA
output load; applies to AVDD and AVSS
Normal Mode
AIDD 6 9 mA All output ranges, −40°C to +105°C
AISS −11 −9 mA All output ranges, −40°C to +105°C
AICC 8.3 10 mA All output ranges, −40°C to +105°C
ILOGIC 0.02 1 µA All output ranges, −40°C to +105°C,
VIH = VLOGIC, VIL = DGND
DC Power Supply Rejection
Ratio (PSRR)
50 µV/V AVDD power supply
50
µV/V
AV
SS
power supply
3 mV/V AVCC power supply
AC Power Supply Rejection
Ratio (PSRR)
−80 dB AVDD power supply, at 50 Hz
−80 dB AVSS power supply, at 50 Hz
−50 dB AVCC power supply, at 50 Hz
1 Output amplifier headroom requirement is 2 V minimum.
Data Sheet AD5766/AD5767
Rev. C | Page 7 of 43
AVCC = 2.97 V to 3.6 V, VLOGIC = 1.7 V to 5.5 V, AVDD = 2.97 V to 16 V, AVSS = −22 V to −7 V, AGND = DGND = 0 V, VREF = 2.5 V, output
range = ± 5 V, VOUTx unloaded, all specifications TMIN to TMAX, typical specifications at TA = 25°C, dither powered off, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
BIPOLAR ZERO ERROR −50 ±11 +50 mV ±5 V range
−75 ±12 +75 mV −10 V to +6 V range
−90
±12
+90
mV
±10 V range
−110 ±13 +110 mV −12 V to +14 V range
−110 ±13 +110 mV −16 V to +10 V range
ZERO-SCALE ERROR
All 0s loaded to DAC register
−50 ±15 +50 mV −10 V to 0 V range
−50 ±15 +50 mV ±5 V range
−75 ±20 +75 mV −16 V to 0 V range
−75 ±20 +75 mV −10 V to +6 V range
−90 ±25 +90 mV −20 V to 0 V range
−90 ±25 +90 mV ±10 V range
−110 ±35 +110 mV −12 V to +14 V range
−110 ±35 +110 mV −16 V to +10 V range
FULL-SCALE ERROR −0.5 ±0.15 +0.5 % FSR All 1s loaded to DAC register; all output ranges
GAIN ERROR
−0.3
±0.07
+0.3
% FSR
All output ranges
OFFSET ERROR −50 ±15 +50 mV −10 V to 0 V range
−50 ±15 +50 mV ±5 V range
−75 ±20 +75 mV −16 V to 0 V range
−75 ±20 +75 mV −10 V to +6 V range
−90 ±25 +90 mV −20 V to 0 V range
−90 ±25 +90 mV ±10 V range
−110 ±35 +110 mV −12 V to +14 V range
−110 ±35 +110 mV −16 V to +10 V range
TOTAL UNADJUSTED ERROR −0.5 ±0.12 +0.5 %FSR All output ranges
AD5766/AD5767 Data Sheet
Rev. C | Page 8 of 43
AC PERFORMANCE CHARACTERISTICS
AVCC = 2.97 V to 3.6 V, VLOGIC = 1.7 V to 5.5 V, AVDD = 2.97 V to 15 V, AV SS = −22 V to −7 V, AGND = DGND = 0 V, VREF = 2.5 V, output
range = −10 V to 0 V, VOUTx unloaded, all specifications TMIN to TMAX, typical specifications at TA = 25°C, dither powered on, analog dither
signals not applied, unless otherwise noted.
Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE1
Output Voltage Settling Time
AD5766 16 µs ¼ to ¾ scale settling to ±0.5 LSB, ±5 V range, and −10 V to 0 V range
14 µs 256 LSB step to ±0.5 LSB
AD5767 10 µs ¼ to ¾ scale settling to ±0.5 LSB, ±5 V range, and −10 V to 0 V range
4 µs 32 LSB step to ±0.5 LSB
Slew Rate 1 V/µs
Digital-to-Analog Glitch Energy 10 nV-sec 1 LSB change around major carry for 10 V span
Glitch Impulse Peak Amplitude 8 mV
Digital Feedthrough
1
nV-sec
Digital Crosstalk 2 nV-sec
Analog Crosstalk 15 nV-sec
DAC-to-DAC Crosstalk 15 nV-sec
Total Harmonic Distortion −80 dB VREF = 2.5 V ± 0.1 V p-p, frequency = 10 kHz, AVCC = 2.97 V and 3.6 V
−75 dB VREF = 2.5 V ± 0.1 V p-p, frequency = 10 kHz, AVCC = 3.6 V
Output Noise Spectral Density1 375 nV/√Hz −10 V to 0 V and ±5 V ranges, frequency = 1 kHz
605 nV/√Hz −16 V to 0 V and −10 V to +6 V ranges, frequency = 1 kHz
750 nV/√Hz −20 V to 0 V and ±10 V ranges, frequency = 1 kHz
835 nV/√Hz −12 V to 14 V and −16 V to +10 V ranges, frequency = 1 kHz
280 nV/√Hz −10 V to 0 V and ±5 V ranges, frequency = 10 kHz
440 nV/√Hz −16 V to 0 V and −10 V to +6 V ranges, frequency = 10 kHz
470 nV/√Hz −20 V to 0 V and ±10 V ranges, frequency = 10 kHz
610 nV/√Hz −12 V to 14 V and −16 V to +10 V ranges, frequency = 10 kHz
Output Noise2 Dither disabled
20 μV rms ±5 V range
23 μV rms −10 V to 0 V range
33
μV rms
−10 V to +6 V range
38 μV rms −16 V to 0 V range
36 μV rms ±10 V range
45 μV rms −20 V to 0 V range
45 μV rms −16 V to 10 V range
45 μV rms −12 V to 14 V range
1 DAC code = midscale. AVDD = VOUT_MAX + 2 V. AVSS = VOUT_MIN − 2 V.
2 0.1 Hz to 10 Hz. AVDD = VOUT_MAX + 2 V. AVSS = VOUT_MIN − 2 V.
Data Sheet AD5766/AD5767
Rev. C | Page 9 of 43
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2,
Figure 3, and Figure 4. AVCC = 2.97 V to 3.6 V, VLOGIC = 1.7 V to 5.5 V, VREF = 2.5 V, all specifications −40°C to +105°C, dither powered on,
unless otherwise noted.
Table 4.
Parameter Limit at TMIN, TMAX Unit Description
t11 20 ns min SCLK cycle time
t2 10 ns min SCLK high time
t3 10 ns min SCLK low time
t4 15 ns min SYNC falling edge to SCLK falling edge setup time
t5 15 ns min SCLK falling edge to SYNC rising edge time
t6 20 ns min Minimum SYNC high time (write mode)
t7 5 ns min Data setup time
t8 5 ns min Data hold time
t9 4 µs typ DAC output settling time, 32 code step to ±0.5 LSB at 12-bit resolution (see Table 3)
t
10
100
ns typ
RESET2
pulse width low
t11 100 ns typ RESET2 pulse activation time
t12 10 ns min SYNC rising edge to SCLK falling edge
t13 40 ns max SCLK rising edge to SDO valid (CL_SDO 3 = 15 pF)
t14 80 ns min Minimum SYNC high time (readback/daisy-chain mode)
t15 5 µs typ SYNC rising edge to SYNC rising edge (DAC register updates)
1 Maximum SCLK frequency is 50 MHz for write mode and 10 MHz for readback mode.
2 Minimum time between a reset and the subsequent successful write is typically 25 ns.
3 CL_SDO is the capacitive load on the SDO output.
Timing Diagrams
D23
SCLK
SDI
RESET
V
OUT
V
OUT
2421
D0
SYNC
t
6
t
4
t
3
t
2
t
1
t
5
t
7
t
8
t
15
t
9
t
10
t
11
15145-002
Figure 2. Serial Interface Timing Diagram
AD5766/AD5767 Data Sheet
Rev. C | Page 10 of 43
SDO
SDI
SYNC
SCLK 4824
D0D23D0
D23
D23
INPUT WORD FOR DAC NUNDEFINED
INPUT WORD FOR DAC N – 1INPUT WORD FOR DAC N
D0
t1
t3t2t5
t12
t4
t14
t7
t13
t8
15145-003
Figure 3. Daisy-Chain Timing Diagram
24 24
D23 D0 D23 D0
SELECTED REGISTER DATA
CLOCKED OUT
UNDEFINED
NOP CONDITIONINPUT WORD SPECIFIES
REGISTER TO BE READ
11
D23 D0 D23 D0
t
14
SCLK
SYNC
SDI
SDO
1
1
SDO OUTPUT BUFFER ENABLED
2
SDO OUTPUT BUFFER DISABLED
SELECTED REGISTER DATA
CLOCKED OUT
HIGH-Z
DB23 DB0
SDO
2
15145-004
Figure 4. Readback Timing Diagram
Data Sheet AD5766/AD5767
Rev. C | Page 11 of 43
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause silicon controlled rectifier (SCR) latch-up.
Table 5.
Parameter Rating
AVDD to AGND −0.3 V to +34 V
AVSS to AGND +0.3 V to −34 V
AVDD to AVSS −0.3 V to +34 V
AVCC to AGND −0.3 V to +7 V
AVCC to AGND −0.3 V to AVDD + 0.3 V
VLOGIC to DGND −0.3 V to +7 V
Digital Inputs1 to DGND −0.3 V to VLOGIC + 0.3 V
Digital Output (SDO) to DGND −0.3 V to VLOGIC + 0.3 V
N0, N1 to AGND −0.3 V to AVCC + 0.3 V
VREF to AGND −0.3 V to AVCC + 0.3 V
V
OUT
x to AGND
AV
SS
− 0.3 V to AV
DD
+ 0.3 V
AGND to DGND −0.3 V to +0.3 V
Operating Temperature Range,
TA Industrial
−40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature, TJ MAX 150°C
Power Dissipation (TJ MAX − TA)/θJA
Lead Temperature
Soldering Reflow 260°C, as per JEDEC J-STD-020
1 The digital inputs include RESET, SCLK, SYNC, and SDI.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure.
Table 6. Thermal Resistance
Package Type θJA Unit
CB-49-41 53 °C/W
CP-40-71 31.71 °C/W
1 Thermal impedance simulated values are based on JEDEC 2S2P thermal test
board with 16 thermal vias. See JEDEC JESD51.
ESD CAUTION
AD5766/AD5767 Data Sheet
Rev. C | Page 12 of 43
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
A
D5766/AD5767
1
DNC VOUT1V
OUT2V
OUT4V
OUT5V
OUT6DNC
SDI
AVSS
SCLK
DNC
DGND
VLOGIC
NIC
SDO
AGND
VOUT9
VOUT7
DNC
NIC
NIC
VOUT8
VOUT10
VOUT3
NIC
NIC
NIC
VOUT12
VOUT11
VOUT0
NIC
NIC
NIC
VOUT15
VOUT13
AGND
NIC
NIC
NIC
VREF
VOUT14
A
B
C
D
E
F
G
234567
AVCC
MUX_OUT
AVDD
N1
N0
DNC
RESET
SYNC
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THESE PINS.
2. NIC = NO INTERNAL CONNECTION. THESE PINS SHOULD BE
ROUTED TO THERMAL VIAS ON THE PCB TO AID WITH HEAT
DISSIPATION. CONNECT THESE PINS TO GROUND.
15145-005
Figure 5. WLCSP Package Pin Configuration
Table 7. 49-Ball WLCSP Pin Function Descriptions
Pin No. Mnemonic Description
Dither
F1 N0
Dither Signal Input Pin 0. A signal connected to this pin can be added to the DAC outputs via
register commands. If unused, connect this pin to ground. Refer to the Dither section for more
information.
E1 N1
Dither Signal Input Pin 1. A signal connected to this pin can be added to the DAC outputs via
register commands. If unused, connect this pin to ground. Refer to the Dither section for more
information.
Logic Inputs and Outputs
E7 SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial
clock input. Data can be transferred at rates of up to 50 MHz for write mode and 10 MHz for
readback and daisy-chain mode.
F7 SYNC Active Low Control Input. SYNC is the frame synchronization signal for the input data. When
SYNC goes low, it powers on the SCLK and SDI buffers and enables the input shift register. Data
is transferred in on the falling edges of the next 24 clocks. If SYNC is taken high before the 24th
falling edge, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by
the device.
C7 SDI
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the
falling edge of the serial clock input.
E6 SDO
Serial Data Output. This pin clocks data from the serial register in daisy-chain or readback mode.
Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.
B7 RESET Active Low Reset Input. Asserting this pin logic low returns the AD5766/AD5767 to the default
power-on state. After this pin returns to logic high, the device comes out of the reset mode and
is ready to accept a new SPI command. This pin can be left floating, because there is a weak
internal pull-up resistor.
Analog Outputs
B3 VOUT0 Analog Output Voltage from DAC 0.
A2 VOUT1 Analog Output Voltage from DAC 1.
A3 VOUT2 Analog Output Voltage from DAC 2.
B4 VOUT3 Analog Output Voltage from DAC 3.
A4 VOUT4 Analog Output Voltage from DAC 4.
A5 VOUT5 Analog Output Voltage from DAC 5.
A6 VOUT6 Analog Output Voltage from DAC 6.
Data Sheet AD5766/AD5767
Rev. C | Page 13 of 43
Pin No. Mnemonic Description
B5 VOUT7 Analog Output Voltage from DAC 7.
F5 VOUT8 Analog Output Voltage from DAC 8.
G6 VOUT9 Analog Output Voltage from DAC 9.
G5 VOUT10 Analog Output Voltage from DAC 10.
G4
V
OUT
11
Analog Output Voltage from DAC 11.
F4 VOUT12 Analog Output Voltage from DAC 12.
G3 VOUT13 Analog Output Voltage from DAC 13.
G2 VOUT14 Analog Output Voltage from DAC 14.
F3 VOUT15 Analog Output Voltage from DAC 15.
Power Supplies and
Reference Input
F2 VREF Reference Input Voltage. For specified performance, VREFIN = 2.5 V.
C6 VLOGIC Digital Power Supply.
B1 AVCC Power Supply Input. The AD5766/AD5767 operates from 2.97 V to 3.6 V. Decouple AVCC with a
10 µF capacitor in parallel with a 0.1 µF capacitor to analog ground.
D1 AVDD Output Amplifier Positive Analog Supply.
D7 AVSS Output Amplifier Negative Analog Supply.
B2, F6 AGND Analog Ground.
B6
DGND
Digital Ground Pin.
Channel Monitoring
C1 MUX_OUT Monitor Output. This pin acts as the output of a 16-to-1 channel multiplexer that can be
programmed to multiplex one of 16 channels, Channel 0 to Channel 15, to the MUX_OUT pin.
Do Not Connect
A1, A7, C5, G1, G7 DNC Do Not Connect. Do not connect to these pins.
No Internal Connection
C2 to C4, D2 to D6,
E2 to E5
NIC No Internal Connection. Route these pins to thermal vias on the PCB to aid with heat
dissipation. Connect these pins to ground.
AD5766/AD5767 Data Sheet
Rev. C | Page 14 of 43
1DNC
2DGND
3
4V
LOGIC
5SDI
6AV
SS
7SLCK
8
9SDO
10AGND
23 N0
24 N1
25 NIC
26 AV
DD
27 MUX_OUT
28 AV
CC
29 AGND
30 DNC
22 V
REF
21 DNC
11DNC
12V
OUT
8
13V
OUT
9
15V
OUT
11
17V
OUT
13
16
V
OUT
12
18V
OUT
14
19V
OUT
15
20NIC
14V
OUT
10
33 V
OUT
1
34 V
OUT
2
35 V
OUT
3
36 V
OUT
4
37 V
OUT
5
38 V
OUT
6
39 V
OUT
7
40 DNC
32 V
OUT
0
31 NIC
AD5766/
AD5767
TOP VIEW
(Not to Scale)
RESET
SYNC
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THESE PINS.
2
. NIC = NO INTERNAL CONNECTION. THESE PINS SHOULD BE
ROUTED TO THERMAL VIAS ON THE PCB TO AID WITH HEAT
DISSIPATION. THESE SHOULD BE CONNECTED TO GROUND.
3
. EXPOSED PAD (LFCSP PACKAGE ONLY). CONNECT THIS
EXPOSED PAD TO THE POTENTIAL OF THE AV
SS
PIN, OR,
ALTERNATIVELY, LEAVE IT ELECTRICALLY UNCONNECTED.
IT IS RECOMMENDED THAT THE PAD BE THERMALLY
CONNECTED TO A COPPER PLANE FOR ENHANCED
THERMAL PERFORMANCE.
15145-006
Figure 6. LFCSP Package Pin Configuration
Table 8. 40-Lead LFCSP Pin Function Descriptions
Pin No. Mnemonic Description
Dither
23 N0
Dither Signal Input Pin 0. A signal connected to this pin can be added to the DAC outputs via
register commands. If unused, connect this pin to ground. Refer to the Dither section for more
information.
24 N1
Dither Signal Input Pin 1. A signal connected to this pin can be added to the DAC outputs via
register commands. If unused, connect this pin to ground. Refer to the Dither section for more
information.
Logic Inputs and Outputs
7 SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial
clock input. Data can be transferred at rates of up to 50 MHz for write mode and 10 MHz for
readback and daisy-chain mode.
8 SYNC Active Low Control Input. SYNC is the frame synchronization signal for the input data. When
SYNC goes low, it powers on the SCLK and SDI buffers and enables the input shift register. Data
is transferred in on the falling edges of the next 24 clocks. If SYNC is taken high before the 24th
falling edge, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by
the device.
5 SDI
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the
falling edge of the serial clock input.
9 SDO
Serial Data Output. This pin clocks data from the serial register in daisy-chain or readback mode.
Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.
3 RESET Active Low Reset Input. Asserting this pin logic low returns the AD5766/AD5767 to the default
power-on state. After this pin returns to logic high, the device comes out of the reset mode and
is ready to accept a new SPI command. This pin can be left floating, because there is a weak
internal pull-up resistor.
Analog Outputs
32 VOUT0 Analog Output Voltage from DAC 0.
33 VOUT1 Analog Output Voltage from DAC 1.
34 VOUT2 Analog Output Voltage from DAC 2.
35 VOUT3 Analog Output Voltage from DAC 3.
36 VOUT4 Analog Output Voltage from DAC 4.
37 VOUT5 Analog Output Voltage from DAC 5.
Data Sheet AD5766/AD5767
Rev. C | Page 15 of 43
Pin No. Mnemonic Description
38 VOUT6 Analog Output Voltage from DAC 6.
39 VOUT7 Analog Output Voltage from DAC 7.
12 VOUT8 Analog Output Voltage from DAC 8.
13 VOUT9 Analog Output Voltage from DAC 9.
14
V
OUT
10
Analog Output Voltage from DAC 10.
15 VOUT11 Analog Output Voltage from DAC 11.
16 VOUT12 Analog Output Voltage from DAC 12.
17 VOUT13 Analog Output Voltage from DAC 13.
18 VOUT14 Analog Output Voltage from DAC 14.
19 VOUT15 Analog Output Voltage from DAC 15.
Power Supplies and
Reference Input
22 VREF Reference Input Voltage. For specified performance, VREFIN = 2.5 V.
4 VLOGIC Digital Power Supply.
28 AVCC Power Supply Input. The AD5766/AD5767 operates from 2.97 V to 3.6 V. Decouple AVCC with a
10 µF capacitor in parallel with a 0.1 µF capacitor to analog ground.
26 AVDD Output Amplifier Positive Analog Supply.
6 AVSS Output Amplifier Negative Analog Supply.
10, 29
AGND
Analog Ground.
2 DGND Digital Ground Pin.
Channel Monitoring
27 MUX_OUT Monitor Output. This pin acts as the output of a 16-to-1 channel multiplexer that can be
programmed to multiplex one of 16 channels, Channel 0 to Channel 15, to the MUX_OUT pin.
Do Not Connect
1, 11, 21, 30, 40
DNC
Do Not Connect. Do not connect to these pins.
No Internal Connection
20, 25, 31 NIC No Internal Connection. Route these pins to thermal vias on the PCB to aid with heat
dissipation. Connect these pins to ground.
Not Applicable EPAD Exposed Pad. Connect this exposed pad to the potential of the AVSS pin, or, alternatively, leave it
electrically unconnected. It is recommended that the exposed pad be thermally connected to a
copper plane for enhanced thermal performance.
AD5766/AD5767 Data Sheet
Rev. C | Page 16 of 43
TYPICAL PERFORMANCE CHARACTERISTICS
–6
–4
–2
0
2
4
6
8
10
12
010000 20000 30000 40000 50000 60000
INL ERROR (LSB)
CODE
–10V TO 0VRANGE
–16V TO 0V RANGE
–20V TO0V RANGE
AV
DD
/AV
SS
=RANGE ±2V
AV
CC
=3.3V
T
A
=25°C
15145-207
Figure 7. AD5766 INL Error vs. DAC Code (Unipolar Output)
0.6
–0.2
0.5
0.3
0.4
0.2
0
0.1
–0.1
–0.3
0400025001000 35001500 30002000500
INL ERROR (LSB)
CODE
AVDD/AVSS = RANGE ± 2V
AVCC = 3.3V
TA = 25°C
–20V TO 0V RANGE
–16V TO 0V RANGE
–10V TO 0V RANGE
15145-107
Figure 8. AD5767 INL Error vs. DAC Code (Unipolar Output)
–6
–4
–2
0
2
4
6
8
10
12
010000 20000 30000 40000 50000 60000
INL ERROR (LSB)
CODE
AV
DD
/AV
SS
=RANGE ±2V
AV
CC
=3.3V
T
A
= 25°C
15145-209
±5V RANGE
–16V TO +10V RANGE
–12V TO +14V RANGE
–10V TO +10V RANGE
–10V TO +6V RANGE
Figure 9. AD5766 INL Error vs. DAC Code (Bipolar Outputs)
0400025001000 35001500 30002000500
0.6
–0.2
0.5
0.3
0.4
0.2
0
0.1
–0.1
–0.3
INL ERROR (LSB)
CODE
AVDD/AVSS = RANGE ± 2V
AVCC = 3.3V
TA = 25°C
±5V RANGE
–16V TO +10V RANGE
–12V TO +14V RANGE
–10V TO +10V RANGE
–10V TO +6V RANGE
15145-108
Figure 10. AD5767 INL Error vs. DAC Code (Bipolar Outputs)
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
010000 20000 30000 40000 50000 60000
DNL ERROR (LSB)
CODE
±5V RANGE
±10V RANGE
–16V TO +10V RANGE
–10V TO +6V RANGE
–12V TO +14V RANGE
AV
DD
/AV
SS
=RANGE ±
2V
AVCC =3.3V
TA= 25°C
15145-211
Figure 11. AD5766 DNL Error vs. DAC Code (Bipolar Outputs)
0400025001000 35001500 30002000500
0.05
–0.04
0.03
0.04
0.02
0
0.01
–0.02
–0.03
–0.01
–0.05
DNL ERROR (LSB)
CODE
AVDD/AVSS = RANGE ± 2V
AVCC = 3.3V
TA = 25°C
±5V RANGE
±10V RANGE
–16V TO +10V RANGE
–10V TO +6V RANGE
–12V TO +14V RANGE
15145-109
Figure 12. AD5767 DNL Error vs. DAC Code (Bipolar Outputs)
Data Sheet AD5766/AD5767
Rev. C | Page 17 of 43
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
010000 20000 30000 40000 50000 60000
DNL ERROR ( LSB)
CODE
AV
DD
/AV
SS
=RANGE ±2V
AV
CC
=3.3V
T
A
=25°C
–20V TO 0V RANGE
–16V TO 0V RANGE
–10V TO 0V RANGE
15145-213
Figure 13. AD5766 DNL Error vs. DAC Code (Unipolar Outputs)
040002500
1000 35001500 30002000500
0.05
–0.04
0.03
0.04
0.02
0
0.01
–0.02
–0.03
–0.01
–0.05
DNL ERROR (LSB)
CODE
AVDD/AVSS = RANGE ± 2V
AVCC = 3.3V
TA = 25°C
–20V TO 0V RANGE
–16V TO 0V RANGE
–10V TO 0V RANGE
15145-110
Figure 14. AD5767 DNL Error vs. DAC Code (Unipolar Outputs)
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0
5000
10000
15000
20000
25000
30000
35000
40000
45000
50000
55000
60000
65000
TUE (%FSR)
CODE
AV
DD
/AV
SS
= RANGE ± 2V
AV
CC
= 3.3V
T
A
= 25°C
DITHER ENABLED
–20V TO 0V RANGE
–16V TO 0V RANGE
–10V TO 0V RANGE
15145-215
Figure 15. Total Unadjusted Error (TUE) vs. DAC Code (Unipolar Outputs)
–0.16
–0.14
–0.12
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
TUE (%FSR)
0
5000
10000
15000
20000
25000
30000
35000
40000
45000
50000
55000
60000
65000
CODE
15145-216
AV
DD
/AV
SS
= RANGE ± 2V
AV
CC
= 3.3V
DITHER ENABLED
±5V RANGE
±10V RANGE
–16V TO +10V RANGE
–10V TO +6V RANGE
–12V TO +14V RANGE
Figure 16. Total Unadjusted Error (TUE) vs. DAC Code (Bipolar Outputs)
0.8
–0.4
0.2
0.6
0.4
0
–0.2
–0.6
–40 10060020 8040–20
INL ERROR (LSB)
TEMPERATURE (°C)
MIN INL
MAX INL
AV
DD
/AV
SS
= RANGE ± 2V
AV
CC
= 3.3V
±5V RANGE
15145-111
Figure 17. INL Error vs. Temperature
–40 10060020 8040–20
0.06
–0.04
0.02
0.04
0
–0.02
–0.06
DNL ERROR (LSB)
TEMPERATURE (°C)
MIN INL
MAX INL
AV
DD
/AV
SS
= RANGE ± 2V
AV
CC
= 3.3V
±5V RANGE
15145-112
Figure 18. DNL Error vs. Temperature
AD5766/AD5767 Data Sheet
Rev. C | Page 18 of 43
–40 10060020 8040–20
–19.0
–22.0
–20.5
–19.5
–20.0
–21.0
–21.5
–22.5
ZERO-SCALE ERROR (mV)
TEMPERATURE (°C)
AV
DD
/AV
SS
= RANGE ± 2V
AV
CC
= 3.3V
±5V RANGE
15145-115
Figure 19. Zero-Scale Error vs. Temperature
–40 10060020 8040–20
0.020
0.015
0.005
0.010
0
BIPOLAR ZERO ERROR (V)
TEMPERATURE (°C)
–10V TO +6V RANGE
±5V RANGE
±10V RANGE
–12V TO +14V AND –16V TO +10V RANGE
15145-116
AV
DD
/AV
SS
= RANGE ± 2V
AV
CC
= 3.3V
Figure 20. Bipolar Zero Error vs. Temperature
–40 10060020 8040–20
0.20
0.18
0.06
0.12
0.16
0.04
0.10
0.14
0.02
0.08
0
FULL-SCALE ERROR (% FSR)
TEMPERATURE (°C)
–20V TO 0V RANGE
–10V TO 0V RANGE
±5V RANGE
–12V TO +14V AND –16V TO +10V RANGE
–16V TO 0V RANGE
–10V TO +6V RANGE
±10V RANGE
15145-117
AVDD/AVSS = RANGE ± 2V
AVCC = 3.3V
Figure 21. Full-Scale Error vs. Temperature
–40 10060020 8040–20
0.10
0.09
0.03
0.06
0.08
0.02
0.05
0.07
0.01
0.04
0
GAIN ERROR (% FSR)
TEMPERATURE (°C)
–20V TO 0V RANGE
–10V TO 0V RANGE
±5V RANGE
–12V TO +14V AND –16V TO +10V RANGE
–16V TO 0V RANGE
–10V TO +6V RANGE
±10V RANGE
15145-118
AV
DD
/AV
SS
= RANGE ± 2V
AV
CC
= 3.3V
Figure 22. Gain Error vs. Temperature
–40 10060
020 8040–20
15
10
–20
–5
5
–25
–10
0
–15
–30
OFFSET ERROR (mV)
TEMPERATURE (°C)
–20V TO 0V RANGE
–10V TO 0V RANGE
±5V RANGE
–12V TO +14V AND –16V TO +10V RANGE
–16V TO 0V RANGE
–10V TO +6V RANGE
±10V RANGE
15145-119
AV
DD
/AV
SS
= RANGE ± 2V
AV
CC
= 3.3V
Figure 23. Offset Error vs. Temperature
–40 10060020 8040–20
0.25
0.20
0
0.15
–0.05
0.10
0.05
–0.10
TOTAL UNADJUSTED ERROR (% FSR)
TEMPERATURE (°C)
–20V TO 0V RANGE
–10V TO 0V RANGE
±5V RANGE
–12V TO 14V AND –16V TO +10V RANGE
–16V TO 0V RANGE
–10V TO +6V RANGE
±10V RANGE
15145-120
AV
DD
/AV
SS
= RANGE ± 2V
AV
CC
= 3.3V
Figure 24. Total Unadjusted Error vs. Temperature
Data Sheet AD5766/AD5767
Rev. C | Page 19 of 43
6
–4
2
4
0
–2
–6
–20 50
30010 40
20–10
V
OUT
(V)
TIME (µs)
±5V RANGE
AV
DD
/AV
SS
= RANGE ± 2V
AV
CC
= 3.3V
T
A
= 25°C
15145-124
Figure 25. Full-Scale Settling Time (Rising Voltage Step)
6
–4
2
4
0
–2
–6
–20 5030010 4020–10
V
OUT
(V)
TIME (µs)
±5V RANGE
AV
DD
/AV
SS
= RANGE ± 2V
AV
CC
= 3.3V
T
A
= 25°C
15145-125
Figure 26. Full-Scale Settling Time (Falling Voltage Step)
20
–10
5
15
10
0
–5
–15
–0.06 0.060.04
–0.02 00.02–0.04
V
OUT
(V)
V
OUT
CURRENT OUTPUT (A)
–12V TO +14V
–20V TO 0V
AV
DD
/AV
SS
= RANGE ± 2V
AV
CC
= 3.3V
T
A
= 25°C
15145-126
Figure 27. Source and Sink Capability of Output Amplifier
0.05
–0.10
–0.09
–0.08
–0.07
–0.06
–0.05
–0.04
–0.03
–0.02
–0.01
0
0.01
0.02
0.03
0.04
–20 60
5030
010 4020
–10
VOUT (V)
TIME (µs)
±5V RANGE
AVDD/AVSS = RANGE ± 2V
AVCC = 3.3V
10nF
1nF
15145-130
Figure 28. Output Voltage (VOUT) vs. Settling Time at Various Capacitive Loads
0
0.2
0.4
0.6
0.8
1.0
0 2 4 6 8 10 12 14 16 18 20
HEADROOM (V)
OUTPUT CURRENT (mA)
AV
CC
= 3.3V
CODE: FULL-SCALE
T
A
= 25°C
15145-229
Figure 29. Headroom vs. Output Current
–1.0
–0.8
–0.6
–0.4
–0.2
0
–20 –18 –16 –14 –12 –10 –8 –6 –4 –2 0
FOOTROOM (V)
OUTPUT CURRENT (mA)
AVCC = 3.3V
CODE: ZERO SCALE
TA = 25°C
15145-230
Figure 30. Footroom vs. Output Current
AD5766/AD5767 Data Sheet
Rev. C | Page 20 of 43
–10
–8
–6
–4
–2
0
2
4
–0.10
–0.08
–0.06
–0.04
–0.02
0.00
0.02
0.04
0.06
0.08
0.10
130 132 134 136 138 140 142 144
SYNC AND RESET (V)
OUTPUT VOLTAGE (V)
TIME (µs)
V
OUTx
SYNC
RESET
±5V RANGE
AV
DD
/AV
SS
= RANGE ±2V
AV
CC
= 3.3V
15145-231
Figure 31. Hardware Reset Glitch
–0.30
–0.20
–0.10
0
0.10
0.20
–10
–8
–6
–4
–2
2
4
6
8
10
6 8 10 12 14 16 18 20
OUTPUT VOLTAGE (V)
VOLTAGE SUPPLIES (V)
TIME (ms)
±5V RANGE
AV
DD
/AV
SS
= RANGE ± 2V
AV
SS
AV
DD
AV
CC
, LOGIC
V
OUTx
15145-232
Figure 32. Power-Up Glitch
60 65 70 75 80 85 90 95 100 105 110
–10
–8
–6
–4
–2
0
2
4
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
0.25
0.30
SYNC AND RESET (V)
OUTPUT VOLTAGE (V)
TIME (µs)
V
OUTx
SYNC
RESET
±5V RANGE
AV
DD
/AV
SS
= RANGE ±2V
AV
CC
= 3.3V
15145-233
Figure 33. Output Span Enable Glitch
–0.5
–0.3
–0.1
0.1
0.3
0.5
0.7
0.9
0 1020304050607080
V
OUTx
(mV)
TIME (µs)
AV
DD
/AV
SS
= RANGE ± 2V
0x7FFF TO 0x8000
WLCSP PACKAGE
15145-234
Figure 34. Digital-to-Analog Glitch Impulse for WLCSP Package
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0 1020304050607080
V
OUTx
(mV)
TIME (µs)
AV
DD
/AV
SS
= RANGE ± 2V
0x7FFF TO 0x8000
LFCSP PACKAGE
15145-235
Figure 35. Digital-to-Analog Glitch Impulse for LFCSP Package
–3
–2
–1
0
1
2
3
4
5
0 5 10 15 20 25 30 35 40 45 50
VOUTx (mV)
TIME (µs)
±5V RANGE
AVDD/AVSS =RANGE ±2V
0x0000 TO 0xFFFF
DITHER ON
WLCSP PACKAGE
15145-236
Figure 36. Analog Crosstalk for WLCSP Package (Dither Enabled)
Data Sheet AD5766/AD5767
Rev. C | Page 21 of 43
–3
–2
–1
0
1
2
3
4
0 1020304050607080
V
OUTx
(mV)
TIME (µs)
±5V RANGE
AV
DD
/AV
SS
= RANGE ± 2V
0x0000 TO 0xFFFF
DITHER ON
LFCSP PACKAGE
15145-237
Figure 37. Analog Crosstalk for LFCSP Package (Dither Enabled)
–6
–5
–4
–3
–1
1
3
–2
0
2
0 5 10 15 20 25 30 35 40 45 50
V
OUTx
(mV)
TIME (µs)
±5V RANGE
AV
DD
/AV
SS
= RANGE ± 2V
0x0000 TO 0xFFFF
DITHER OFF
WLCSP PACKAGE
15145-238
Figure 38. Analog Crosstalk for WLCSP Package (Dither Disabled)
–7
–6
–5
–4
–3
–1
1
3
–2
0
2
4
0 5 10 15 20 25 30 35 40 45 50
V
OUTx
(mV)
TIME (µs)
±5V RANGE
AV
DD
/AV
SS
=RANGE ±2V
0x0000 TO 0xFFFF
DITHER OFF
LFCSP PACKAGE
15145-239
Figure 39. Analog Crosstalk for LFCSP Package (Dither Disabled)
–3
–2
–1
0
2
4
6
1
3
5
7
0 5 10 15 20 25 30 35 40 45 50
V
OUTx
(mV)
TIME (µs)
±5V RANGE
AV
DD
/AV
SS
=RANGE ±2V
0x0000 TO 0xFFFF
DITHER ON
WLCSP PACKAGE
15145-240
Figure 40. DAC-to-DAC Crosstalk for WLCSP Package (Dither Enabled)
–3
–2
–1
0
2
4
1
3
5
0 5 10 15 20 25 30 35 40 45 50
V
OUTx
(mV)
TIME (µs)
15145-241
±5V RANGE
AV
DD
/AV
SS
=RANGE ±2V
0x0000 TO 0xFFFF
DITHER ON
LFCSP PACKAGE
Figure 41. DAC-to-DAC Crosstalk for LFCSP Package (Dither Enabled)
–5
–4
–3
–1
1
3
4
–2
0
2
0 5 10 15 20 25 30 35 40 45 50
V
OUTx
(mV)
TIME (µs)
±5V RANGE
AV
DD
/AV
SS
= RANGE ± 2V
0x0000 TO 0xFFFF
DITHER OFF
WLCSP PACKAGE
15145-242
Figure 42. DAC-to-DAC Crosstalk for WLCSP Package (Dither Disabled)
AD5766/AD5767 Data Sheet
Rev. C | Page 22 of 43
–6
–5
–4
–3
–1
1
3
–2
0
2
4
5
0 5 10 15 20 25 30 35 40 45 50
V
OUTx
(mV)
TIME (µs)
±5V RANGE
AV
DD
/AV
SS
=RANGE ±2V
0x0000 TO 0xFFFF
DITHER OFF
LFCSP PACKAGE
15145-243
Figure 43. DAC-to-DAC Crosstalk for LFCSP Package (Dither Disabled)
0.00008
0.00004
0.00006
–0.00004
–0.00002
0
0.00002
–0.00006
01035 9714682
V
OUT
(V)
TIME (µs)
±5V RANGE
MIDSCALE CODE
15145-131
Figure 44. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth) with Dither Disabled
3000
2000
2500
500
1000
1500
0
10 100k10k100 1k
NSD (nV/
√
Hz)
FREQUENCY (Hz)
±5V RANGE
MIDSCALE CODE
15145-132
Figure 45. Noise Spectral Density (NSD) vs. Frequency
100
1k
10k
100k
1 10 100 1k 10k 100k
NSD (nV/
√
Hz)
FREQUENCY (Hz)
TA = –40°C
TA = –20°C
TA = 0°C
TA = +25°C
TA = +85°C
TA = +105°C
15145-246
AVDD/AVSS =RANGE ±2V
AVCC = 3.3V
±5V RANGE
MIDSCALE RANGE
DITHER ON
NOT SELECTED ON CHANNEL
Figure 46. Output Noise (NSD) vs. Frequency over Temperature
–10
–8
–6
–4
–2
0
2
4
–500
–400
–300
–200
–100
0
100
200
300
400
500
600
700
800
0 30 60 90 120 150 180 210 240 270 300
V
OUTx
(µV)
TIME (µs)
SYNC (V)
15145-247
AV
DD
/AV
SS
=RANGE ±2V
AV
CC
=V
LOGIC
= 3.3V
T
A
= 25°C
WLCSP PACKAGE
Figure 47. Digital Feedthrough for WLCSP Package
–10
–8
–6
–4
–2
0
2
4
–400
–300
–200
–100
0
100
200
300
400
500
–50 –30 –10 10 30 50 70 90 110
V
OUTx
(µV)
TIME (µs)
SYNC (V)
15145-248
AV
DD
/AV
SS
=RANGE ±2V
AV
CC
=V
LOGIC
= 3.3V
T
A
= 25°C
LFCSP PACKAGE
Figure 48. Digital Feedthrough for LFCSP Package
Data Sheet AD5766/AD5767
Rev. C | Page 23 of 43
4.1
4.0
3.9
3.8
3.7
3.6
3.5
2.9 3.0 3.1 3.2 3.3 3.4 3.63.5
AI
CC
(mA)
AV
CC
(V)
15145-136
Figure 49. Supply Current (AICC) vs. Supply Voltage (AVCC)
15145-250
5.70
5.75
5.80
5.85
5.90
5.95
6.00
6.05
6.10
6.15
6.20
6.25
6.30
9.5 10.0 10.5 11.0 11.5 12.0 12.5
AI
DD
(mA)
AV
DD
(V)
±10V RANGE
AVDD = RANGE TO RANGE +2V
Figure 50. Supply Current (AIDD) vs. Supply Voltage (AVDD)
–7.20
–7.15
–7.10
–7.05
–7.00
–6.95
–6.90
–6.85
–6.80
–6.75
–6.70
–12.5 –12.0 –11.5 –11.0 –10.5 –10.0 –9.5
AI
SS
(mA)
AV
SS
(V)
15145-251
±10V RANGE
AV
SS
=RANGE –2V TO RANGE
Figure 51. Supply Current (AISS) vs. Supply Voltage (AVSS)
5.60
5.62
5.64
5.66
5.68
5.70
5.72
010000 20000 30000 40000 50000 60000
AI
CC
(mA)
CODE
±10V RANGE
15145-252
Figure 52. Supply Current (AICC) vs. Code
AD5766/AD5767 Data Sheet
Rev. C | Page 24 of 43
5.8
5.9
6.0
6.1
6.2
010000 20000 30000 40000 50000 60000
AI
DD
(mA)
CODE
15145-253
±10V RANGE
Figure 53. Supply Current (AIDD) vs. Code
–7.1
–7.0
–6.9
–6.8
–6.7
–6.6
010000 20000 30000 40000 50000 60000
AISS (mA)
CODE
±10V RANGE
15145-254
Figure 54. Supply Current (AISS) vs. Code
14
12
10
8
6
4
2
0
ILOGIC (nA)
VLOGIC (V)
15145-138
1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
±5V RANGE
–10 V TO 0 V RANGE
–10 V TO +6 V RANGE
–16 V TO 0V RANGE
±10 V RANGE
–20 V TO 0V RANGE
–12V TO +14V RANGE
–16V TO +10V RANGE
Figure 55. Logic Current (ILOGIC) vs. Logic Input Voltage (VLOGIC)
–40 100
60020 8040–20
8
6
–2
4
–6
2
0
–10
–4
–8
CURRENT (mA)
TEMPERATURE (°C)
AIDD
AISS
AICC
15145-139
Figure 56. Supply Current vs. Temperature
Data Sheet AD5766/AD5767
Rev. C | Page 25 of 43
DITHER CHARACTERISTICS
700
400
600
200
0
300
500
100
–100
–200
02510 15 205
V
OUT
(µV)
TIME (µs)
±5V RANGE
15145-151
Figure 57. Transient on Dither Selected Channel (Dither Enabled)
150
100
0
50
–100
–50
–150
02510 15 205
V
OUT
(µV)
TIME (µs)
±5V RANGE
15145-152
Figure 58. Transient on Nondither Selected Channel (Dither Enabled)
200
150
50
100
–50
0
–100
02510 15 205
V
OUT
(µV)
TIME (µs)
±5V RANGE
15145-153
Figure 59. Transient on Dither Selected Channel (Dither Disabled)
150
100
0
50
–150
–100
–50
–200
02510 15 20
5
V
OUT
(µV)
TIME (µs)
±5V RANGE
15145-154
Figure 60. Transient on Nondither Selected Channel (Dither Disabled)
650
550
450
250
350
–50
50
150
–150
–0.3 1.50.3 0.6 1.20.90
VOUT (µV)
TIME (µs)
±5V RANGE
15145-155
Figure 61. Dither DC Shift
0
–2.0
–0.5
–4.0
–3.0
–1.0
–1.5
–4.5
–3.5
–2.5
–5.0
1k 1M100k
10k
ATTENUATION (dB)
FREQUENCY (Hz)
AV
DD
/AV
SS
= RANGE ± 2V
AV
CC
= 5V
DITHER SIGNAL: 0.25V p-p
±5V RANGE
–10V TO 0V RANGE
15145-158
Figure 62. Dither Input to DAC Output Attenuation vs. Frequency
(±5 V Range and −10 V to 0 V Range)
AD5766/AD5767 Data Sheet
Rev. C | Page 26 of 43
0
–2.0
–0.5
–4.0
–3.0
–1.0
–1.5
–4.5
–3.5
–2.5
–5.0
1k 1M100k10k
ATTENUATION (dB)
FREQUENCY (Hz)
AV
DD
/AV
SS
= RANGE ± 2V
AV
CC
= 5V
DITHER SIGNAL: 0.25V p-p
±10V RANGE
–20V TO 0V RANGE
15145-159
Figure 63. Dither Input to DAC Output Attenuation vs. Frequency
(±10 V Range and −20 V to 0 V Range)
0
–2.0
–0.5
–4.0
–3.0
–1.0
–1.5
–4.5
–3.5
–2.5
–5.0
1k 1M100k10k
ATTENUATION (dB)
FREQUENCY (Hz)
AV
DD
/AV
SS
= RANGE ± 2V
AV
CC
= 5V
DITHER SIGNAL: 0.25V p-p
–10V TO +6V RANGE
–16V TO 0V RANGE
15145-160
Figure 64. Dither Input to DAC Output Attenuation vs. Frequency
(−10 V to +6 V Range and −16 V to 0 V Range)
0
–2.0
–0.5
–4.0
–3.0
–1.0
–1.5
–4.5
–3.5
–2.5
–5.0
1k 1M
100k10k
ATTENUATION (dB)
FREQUENCY (Hz)
AV
DD
/AV
SS
= RANGE ± 2V
AV
CC
= 5V
DITHER SIGNAL: 0.25V p-p
–12V TO +14V RANGE
–16V TO +10V RANGE
15145-161
Figure 65. Dither Input to DAC Output Attenuation vs. Frequency
(−12 V to +14 V Range and −16 V to +10 V Range)
0
–190
–180
–170
–160
–150
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
100 1k 10k 100k
THD (dB)
FREQUENCY (Hz)
±5V RANGE
AV
CC
= 5V
15145-166
Figure 66. Total Harmonic Distortion (THD) vs. Frequency
–150
–100
–50
0
50
100
1k 10k 100k 1M
–20V TO 0V RANGE –16V TO 0V RANGE
–10V TO 0V RANGE –12V TO +14V RANGE
–16V TO +10V RANGE –10V TO +6V RANGE
±10V ±5V
PHASE SHIFT (Degrees)
FREQUENCY (Hz)
AV
DD
/AV
SS
=RANGE ± 2V
AV
DD
=3.3V
DITHER SIGNAL: 0.25v p-p
15145-267
Figure 67. Dither Input to DAC Output Phase Shift vs. Frequency
Data Sheet AD5766/AD5767
Rev. C | Page 27 of 43
TERMINOLOGY
Total Unadjusted Error (TUE)
Total unadjusted error is a measure of the output error taking
all the various errors into account, namely INL error, offset
error, gain error, and output drift over supplies, temperature,
and time. TUE is expressed in % FSR.
Relative Accuracy or Integral Nonlinearity (INL)
Relative accuracy or integral nonlinearity is a measurement of
the maximum deviation, in LSBs, from a straight line passing
through the endpoints of the DAC transfer function. Typical
INL error vs. DAC code plots are shown in Figure 7 and Figure 10.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. Typical DNL error vs. DAC code plots are shown in
Figure 12 and Figure 14.
Zero-Scale Error
Zero-scale error is a measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Zero code
error is expressed in mV.
Zero-Scale Error Temperature Coefficient
Zero code error drift is a measure of the change in zero code
error with a change in temperature. It is expressed in µV/°C.
Bipolar Zero Error
Bipolar zero error is the deviation of the analog output from the
ideal half-scale output of 0 V when the DAC register is loaded
with 0x2000.
Bipolar Zero Error Temperature Coefficient
Bipolar zero drift is a measure of the change in the bipolar zero
error with a change in temperature. It is expressed in µV/°C.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal expressed as % FSR.
Gain Error Temperature Coefficient
Gain temperature coefficient is a measurement of the change in
gain error with changes in temperature. It is expressed in ppm
of FSR/°C.
Offset Error
Offset error is a measurement of the difference between VOUTx
(actual) and VOUTx (ideal), expressed in mV, in the linear region
of the transfer function. Offset error can be negative or positive.
Offset Error Drift
Offset error drift is a measurement of the change in offset error
with a change in temperature. It is expressed in µV/°C.
Dither DC Shift
Dither dc shift is a measurement of the dc voltage difference
between VOUTx (actual) and VOUTx (ideal) due to the coupling of
a dither tone to the analog output. It is expressed in LSB.
Dither Transient
Dither transient is the amplitude of the impulse injected into
the analog outputs due to the enabling or disabling of the dither
functionality on an output channel. The transients are measured
the selected output channel and the other nonselected channels.
It is specified in nV-sec.
DC Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by
changes in the supply voltage. PSRR is the ratio of the change in
VOUTx to a change in AVDD for a full-scale output of the DAC. It
is measured in V/V.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output of a DAC to settle to a specified level for a ¼ to ¾
full-scale input change and is measured from the rising edge
of SYNC.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec,
and is measured when the digital input code is changed by 1 LSB at
the major carry transition (0x7FFF to 0x800 for the AD5767
and 0x7FFF to 0x8000 for the AD5766).
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-sec, and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC (or
power-down and power-up) while monitoring another DAC
maintained at midscale. It is expressed in μV.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to
another DAC kept at midscale. It is expressed in μV/mA.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s and vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed in
nV-sec.
AD5766/AD5767 Data Sheet
Rev. C | Page 28 of 43
Analog Crosstalk
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s and vice versa), then executing a
software LDAC command (see Table 21), and monitoring the
output of the DAC whose digital code was not changed. The
area of the glitch is expressed in nV-sec.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
analog output change of another DAC. It is measured by
loading the attack channel with a full-scale code change (all 0s
to all 1s and vice versa), using the write to and update commands
while monitoring the output of the victim channel that is at
midscale. The energy of the glitch is expressed in nV-sec.
Output Noise Spectral Density
Output noise spectral density is a measurement of the internally
generated random noise. Random noise is characterized as a
spectral density (nV/√Hz). It is measured by loading the DAC
to midscale and measuring noise at the output. It is measured
in nV/√Hz.
Data Sheet AD5766/AD5767
Rev. C | Page 29 of 43
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER
The AD5766/AD5767 are 16-channel, 16-bit/12-bit, serial
input, voltage output DACs capable of providing multiple
output ranges with ±20 mA output current capability. The
available output voltage ranges are as follows:
• −20 V to 0 V
• −16 V to 0 V
• −10 V to 0 V
• −10 V to +6 V
• −12 V to +14 V
• −16 V to +10 V
• ±5 V
• ±10 V
The devices operate from four supply voltages: AVCC, AVDD,
AVSS, and VLOGIC. AVCC is the power supply input voltage for the
DACs and other low voltage circuitry, whereas AVDD and AVSS
are the positive and negative analog supplies for the output
amplifiers. The output amplifiers require +2 V of headroom and
−2 V of footroom to drive 20 mA with a minimum output
voltage error of less than 1 LSB. Table 9 shows the power supply
requirements for the selected output range. VLOGIC defines the
logic levels for the digital input and output signals.
Table 9. Power Supply Requirements for the Selected
Output Range
Range (V) AVSS Maximum (V) AVDD Minimum (V)
−20 to 0 −22 2.97
−16 to 0 −18 2.97
−10 to 0 −12 2.97
−10 to +6 −12 8
−12 to +14 −14 16
−16 to +10 −18 12
−5 to +5
−7
7
−10 to +10 −12 12
DAC ARCHITECTURE
The architecture of one DAC channel consists of a resistor
string DAC followed by an output buffer amplifier. The voltage
at the VREF pin provides the reference voltage for the all DAC
channels. Figure 68 shows a block diagram of the DAC
architecture.
INPUT
REGISTER
OUTPUT
BUFFER AMPLIFIER
REFERENCE
BUFFER
V
OUT
X
V
REF
RESISTOR
STRING
DAC
REGISTER
15145-068
Figure 68. DAC Architecture
The input coding to the DAC is straight binary, the ideal output
voltage is given by
MIN
OUT
V
N
D
Span
V+
×=
where:
Span is the full extent of the DAC output voltage range from the
minimum to the maximum limit.
D is the decimal equivalent of the binary code that is loaded to
the DAC register.
N is 4096 for the AD5767 (12-bit version), and 65536 for the
AD5766 (16-bit version).
VMIN is the lowest voltage of the span.
RESISTOR STRING
The resistor string section is shown in Figure 69. It is a
simplified resistor string structure, each of Value R. The digital
code loaded to the DAC register determines at which node on
the string the voltage is connected to be fed into the output
amplifier. The voltage is tapped off by closing one of the
switches connecting the string to the amplifier. Because a string
of resistors is used, the DAC is guaranteed to be monotonic.
R
R
R
R
R
TO OUTPUT
AMPLIFIER
15145-069
Figure 69. Resistor String
POWER-ON RESET (POR)
The AD5766/AD5767 contain a POR circuit that controls the
output voltage during power-up. The AD5766/AD5767 outputs
are clamped to ground at power-up and remain powered up at
this level until a valid write sequence is made to the span register
to configure the output range of the DAC. At power-on, the
dither functionality is also enabled.
A software executable reset function resets the DAC to the
power-up state. Command 0111 is reserved for this reset
function (see Table 30). A minimum time is required between a
reset and a successful write (see the timing characteristics in
Table 4). Figure 70 shows the programming sequence to follow
to configure the AD5766/AD5767 upon power-on.
AD5766/AD5767 Data Sheet
Rev. C | Page 30 of 43
POWER-ON
(OUTPUTS CLAMPED TO GROUND,DITHER ENABLED)
SOFTWARE FULL RESET
DITHER FUNCTIONALITYCONFIGURATION
•DITHER POWER DOWN CONTROL REGISTER WRITE (ONE WRITECOMMAND)
•DITHER SCALE REGISTER WRITE (TWO WRITE COMMAND)
•INVERTDITHERREGISTER WRITE (TWO WRITE COMMAND)
OUPUT VOLTAGERANGE CHA
NGE
• CONFIGURE DAISY-CHAIN MODE (IF REQUIRED)
•SPAN REGISERWRITE(ONE WRITE COMMAND)
• WRITE REQUIRED CODE TO INPUT/DAC REGISTER
DAC OUTPUTCONFIGURATION
15145-264
Figure 70. Programming Sequence to Write/Enable the AD5766/AD5767 Outputs
Data Sheet AD5766/AD5767
Rev. C | Page 31 of 43
DITHER
External dither signals can be coupled onto any DAC output by
writing the appropriate value to the dither registers. The dither
signals are applied to the N0 and N1 input pins (see Figure 71).
If dither is not required, connect these pins to AGND. The
dither signals amplitude have a maximum peak-to-peak voltage
(ac voltage) of 0.25 V p-p, and the absolute input voltage (ac
and dc voltage) must not exceed the range of 0 V to AVCC. The
dither signals can be attenuated and/or inverted internally on a
per channel basis if required. Dither signals in the range of 10
kHz to 100 kHz can be applied to the dither input pins. Due to
the nature of the internal dither circuitry, the dc value of the
output can shift (see Table 1) and the shift can be compensated for.
For the recommended configuration of the dither functionality,
see the Applications Information section.
DITHER POWER-DOWN MODE
The AD5766/AD5767 contain a dither block power-down
mode per channel. Command 0101 is reserved for the power-
down function (see Table 10). The power-down mode is
software-programmable by setting four bits, Bit D19 to Bit D16,
in the power control register. To address the dither block
power-down per channel function, D19 to D16 must be set to
0001 (see Table 26). Table 27 shows how the state of the Bit D16
corresponds to the mode of operation of the device. The dither
functionality of any or all DACs can be powered down to the
selected mode by setting the corresponding 16 bits (D15 to D0)
to 1.
Ensure that all channels are powered up before writing to the
span register.
MONITOR MUX
The AD5766/AD5767 contain a channel monitor function that
consists of an analog multiplexer addressed via the serial
interface, allowing any channel output to be routed to the
common MUX_OUT pin for external monitoring.
Because the MUX_OUT pin is not buffered, the amount of
current drawn from this pin creates a voltage drop across the
switches, which in turn leads to an error in the voltage being
monitored. Therefore, the MUX_OUT pin must be connected
to only high impedance inputs or externally buffered.
15145-071
SELECT N0/N1/NO
DITHER SIGNAL
DAC 0
V
t
VN0p-p
V
t
N0
N1
VDAC0
INVERTED SIGNAL
NOT INVERTED SIGNAL
INVERT DITHER
100%
75%
50%
25%
DITHER SCALE
100%
75%
50%
25%
DITHER SCALE
INVERTED SIGNAL
NOT INVERTED SIGNAL
INVERT DITHER
VN1p-p
V
VDAC0
t
VAC p-p
BAND-PASS
FILTER
BAND-PASS
FILTER
Figure 71. Dither Signal Generation
AD5766/AD5767 Data Sheet
Rev. C | Page 32 of 43
SERIAL INTERFACE
The AD5766/AD5767 4-wire (SYNC, SCLK, SDI, and SDO)
interface is compatible with SPI, QSPI, and MICROWIRE
interface standards as well as most digital signal processors
(DSPs). The write sequence begins after bringing the SYNC line
low, maintaining this line low until the complete data-word is
loaded from the SDI pin. Data is loaded into the AD5766/AD5767
at the SCLK falling edge transition (see Figure 2). When a rising
edge is detected on SYNC, the serial data-word is decoded
according to the instructions in Table 10. The command must
be a multiple of 24; otherwise, the device ignores the command.
The AD5766/AD5767 contain an SDO pin to allow the user to
daisy-chain multiple devices together or to read back the
contents of the status register.
Readback Operation
The contents of the status registers can be read back via the
SDO pin. Figure 4 shows how the registers are decoded. After a
register has been addressed for a read, the next 24 clock cycles
clock the data out on the SDO pin. The clocks must be applied
while SYNC is low. For a read of a single register, the no
operation (NOP) function clocks out the data. Alternatively, if
more than one register is to be read, the data of the first register
to be addressed clocks out at the same time that the second
register to be read is being addressed.
Daisy-Chain Operation
Daisy chaining minimizes the number of port pins required
from the controlling IC. As shown in Figure 72, the SDO pin of
one package must be tied to the SDI pin of the next package. To
enable daisy-chain mode, the DC_EN bit in Table 15 must be
high. When two AD5766/AD5767 devices are daisy-chained,
48 bits of data are required. The first 24 bits are assigned to U2,
and the second 24 bits are assigned to U1, as shown in Figure 72.
Keep the SYNC pin low until all 48 bits are clocked into their
respective serial registers.
The SYNC pin is then pulled high to complete the operation.
To prevent data from mislocking (for example, due to noise) the
device includes an internal counter; if the SCLK falling edges
count is not a multiple of 24, the device ignores the command.
A valid clock count is 24, 48, 72, and so on. The counter resets
when SYNC returns high.
Daisy-chain mode is disabled by default and is enabled using
the daisy-chain control register (see Table 15).
AD5766/
AD5767
SDI
SYNC SCLK
SCLK
SDOU1
AD5766/
AD5767
SDI
SYNC SCLK
SDOU2
MICROCONTROLLER
MOSI
MISO SS
15145-070
Figure 72. Daisy-Chain Block Diagram
Data Sheet AD5766/AD5767
Rev. C | Page 33 of 43
REGISTER DETAILS
INPUT SHIFT REGISTER
The input shift register of the AD5766/AD5767 are 24 bits wide. Data is loaded MSB first (D23). The first four bits are the command bits,
C3 to C0 (see Figure 73), followed by the 4-bit DAC address bits (see Table 11), and finally the data bits. The 24-bit data-word is
transferred to the input register on the 24 falling edges of SCLK and are updated on the rising edge of SYNC.
ADDRESS BITSCOMMAND BITS
A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
C3 C2 C1 C0
D23 (MSB) D0 (LSB)
DATA BITS
15145-072
Figure 73. Input Shift Register Content
Table 10. Command Definitions1
C3 C2 C1 C0 A3 A2 A1 A0 Name Description
0 0 0 0 0 0 0 0 NOP/monitor mux control No operation (all zeros register). Monitor mux control
register (D4 = 1) determines whether a DAC output or no
output is switched out on the MUX_OUT pin.
0 0 0 0 0 0 0 1 Daisy-chain mode Enables/disables the SDO output buffer for daisy-chain
mode.
0
0
0
1
A3
2
A2
2
A1
2
A0
2
Write to DACx input register
Writes data to the input register for the selected DAC
channel.
0 0 1 0 A32 A22 A12 A02 Write to input register and
DAC register
Writes data to the input register and DAC register for the
selected DAC channel.
0 0 1 1 X X X X Software load DAC (LDAC) Updates the selected DAC register with data from the
corresponding input register.
0 1 0 0 X X X X Span Selects the output span of the AD5766/AD5767.
0 1 0 1 X X X 0 Reserved Not applicable.
0 1 0 1 0 0 0 1 Dither power control Powers up/down dither functionality of individual DAC
channels.
0 1 1 0 X X X X Write input data to all DAC
registers
Writes data to input registers and DAC registers for all DAC
channels.
0 1 1 1 0 0 0 0 Software full reset Writing 0x1234 to this register resets the AD5766/AD5767.
1 0 0 0 A32 A22 A12 A02 Select register for readback Selects the register to read back for a selected DAC
channel.
1 0 0 1 X X X X Apply N0 or N1 dither signal
to DACs (DAC 7 to DAC 0)
Selects whether dither on N0, dither on N1, or no dither is
applied to each DAC output.
1 0 1 0 X X X X Apply N0 or N1 dither signal
to DACs (DAC 15 to DAC 8)
Selects whether dither on N0, dither on N1, or no dither is
applied to each DAC output.
1 1 0 0 X X X X Dither scale (DAC 7 to
DAC 0)
Scales the dither signal applied to the selected DAC
outputs.
1 1 0 1 X X X X Dither scale (DAC 15 to
DAC 8)
Scales the dither signal applied to the selected DAC
outputs.
1 0 1 1 X X X X Invert dither Inverts the dither signal applied to the selected DAC
outputs.
1 1 1 0 X X X X Reserved Not applicable.
1 1 1 1 X X X X Reserved Not applicable.
1 X means don’t care.
2 See Table 11 for the address bit setting.
AD5766/AD5767 Data Sheet
Rev. C | Page 34 of 43
Table 11 shows the DAC x address commands. For applications using the WLCSP package that do not require all 16 channels, do not use
Channel 8 because it is more sensitive to crosstalk and digital feedthrough.
Table 11. DAC x Address Commands
Address
A3 A2 A1 A0 Selected DAC
0 0 0 0 DAC 0
0 0 0 1 DAC 1
0 0 1 0 DAC 2
0
0
1
1
DAC 3
0 1 0 0 DAC 4
0 1 0 1 DAC 5
0 1 1 0 DAC 6
0 1 1 1 DAC 7
1 0 0 0 DAC 8
1 0 0 1 DAC 9
1 0 1 0 DAC 10
1 0 1 1 DAC 11
1 1 0 0 DAC 12
1 1 0 1 DAC 13
1
1
1
0
DAC 14
1 1 1 1 DAC 15
MONITOR MUX CONTROL
The monitor mux control command determines whether one of the DAC outputs or none is switched out on the MUX_OUT pin
depending on the desired D[4:0] value. To assert the no operation command, write all zeros to the D15 to D0 bits.
Table 12. Monitor Mux Control Register
D23 D22 D21 D20 D19 D18 D17 D16 D15 to D5 D4 to D0
0 0 0 0 0 0 0 0 Don’t care VOUT_SEL
Table 13. Output Voltage Selection from Mux
VOUT_SEL, Bits[4:0]1 Mux Output
0 X X X X No output is switched out
1 0 0 0 0 VOUT0
1 0 0 0 1 VOUT1
1
0
0
1
0
V
OUT
2
1 0 0 1 1 VOUT3
1 0 1 0 0 VOUT4
1 0 1 0 1 VOUT5
1 0 1 1 0 VOUT6
1 0 1 1 1 VOUT7
1 1 0 0 0 VOUT8
1 1 0 0 1 VOUT9
1 1 0 1 0 VOUT10
1 1 0 1 1 VOUT11
1 1 1 0 0 VOUT12
1 1 1 0 1 VOUT13
1 1 1 1 0 VOUT14
1 1 1 1 1 VOUT15
1 X means don’t care.
Data Sheet AD5766/AD5767
Rev. C | Page 35 of 43
NO OPERATION
Writing all zeros does not vary the state of the device.
Table 14. No Operation Register
D23 D22 D21 D20 D19 D18 D17 D16 D15 to D0
0 0 0 0 0 0 0 0 0000 0000 0000 0000
DAISY-CHAIN MODE
To use the daisy-chain mode, enable the DC_EN bit in the daisy-chain control register. This bit is linked to the internal SDO buffer. If the
functionality is not required, set the DC_EN bit to 0 to save the power consumed by the SDO buffer.
Table 15. Daisy-Chain Control Register
D23 D22 D21 D20 D19 D18 D17 D16 D15 to D1 D0
0 0 0 0 0 0 0 1 Don’t care DC_EN
Table 16. Daisy-Chain Enable/Disable Bit Description
DC_EN
Description
0
Daisy chain disabled (default)
1
Daisy chain enabled
WRITE AND UPDATE COMMANDS
Write to DAC x Input Register
This command allows the user to write to the dedicated input register of each DAC individually. The output of the DAC does not change
its value until a write to the software LDAC register occurs with the appropriate bit set to include the addressed channel in the update.
Table 17. AD5766 Write to DAC x Input Register
D23 D22 D21 D20 D19 to D16 D15 to D0
0 0 0 1 DAC x address (see Table 11) Input register data
Table 18. AD5767 Write to DAC x Input Register
D23 D22 D21 D20 D19 to D16 D15 to D4 D3 to D0
0 0 0 1 DAC x address (see Table 11) Input register data Don’t care
Write to Input Register and DAC Register
This command writes directly to the selected DAC register and updates the output accordingly.
Table 19. AD5766 Write to DACx Input and DAC Register
D23 D22 D21 D20 D19 to D16 D15 to D0
0 0 1 0 DAC x address (see Table 11) Input register data
Table 20. AD5767 Write to DACx Input and DAC Register
D23 D22 D21 D20 D19 to D16 D15 to D4 D3 to D0
0 0 1 0 DAC x address (see Table 11) Input register data Don’t care
Software LDAC Register
This command copies data from the selected input registers to the corresponding DAC registers and the outputs update accordingly.
Table 21. Software LDAC Register
D23 D22 D21 D20 D19 to D16 D15 to D0
0 0 1 1 Don’t care LDAC (bit for each channel)
Table 22. LDAC Bit Description
LDAC Description
0 Do not update channel
1
Update channel
AD5766/AD5767 Data Sheet
Rev. C | Page 36 of 43
SPAN REGISTER
This register selects the output span of the AD5766/AD5767. See Table 24 and Table 25. Always issue a software reset before writing to the
span register.
Table 23. Span Register
D23 D22 D21 D20 D19 to D5 D4 to D3 D2 to D0
0 1 0 0 Don’t care P[1:0] (power-up condition) S[2:0] (span)
Table 24. Span Selection
S2 S1 S0 Output Voltage Range
0 0 0 −20 V to 0 V
0 0 1 −16 V to 0 V
0 1 0 −10 V to 0 V
0 1 1 −12 V to +14 V
1 0 0 −16 V to +10 V
1 0 1 −10 V to +6 V
1 1 0 −5 V to +5 V
1 1 1 −10 V to +10 V
Table 25. Power-Up Condition Selection
P1 P0 Power-Up Condition
0 0 Zero scale
0 1 Midscale
1 Don’t care Full scale
DITHER POWER CONTROL REGISTER
The dither power control register with D[19:16] = 0001 powers up or powers down the dither functionality of the individual DACs. It is
recommended to power down the selected channel dither block during the first write to the AD5766/AD5767 if no dither tone is input on
to the dither inputs N0 or N1.
Table 26. Dither Power Control Register
D23
D22
D21
D20
D19
D18
D17
D16
D15 to D0
0 1 0 1 0 0 0 1 Power-down bit for each channel dither block (for example, D15 = DAC 15,
D8 = DAC 8, and D0 = DAC 0)
Table 27. Dither Power Control
D16 Operating Mode
0 Normal operation (default)
1 Powered down
WRITE INPUT DATA TO ALL DAC REGISTERS
This command writes the data in D[15:0] to the DAC register of all DACs and sets all DAC outputs to the same value. For the
AD5766/AD5767, the data is written in D[15:0] for the 16-bit resolution DAC and in D[15:4] for the 12-bit resolution version.
Table 28. AD5766 Write Input Data to All DAC Registers
D23 D22 D21 D20 D19 to D16 D15 to D0
0 1 1 0 Don’t care DAC register data
Table 29. AD5767 Write Input Data to All DAC Registers
D23 D22 D21 D20 D19 to D16 D15 to D4 D3 to D0
0 1 1 0 Don’t care DAC register data Don’t care
Data Sheet AD5766/AD5767
Rev. C | Page 37 of 43
SOFTWARE FULL RESET
Writing 0x1234 initiates a reset routine, which returns the AD5766/AD5767 to the power-on state.
Table 30. Software Full Reset Register
D23 D22 D21 D20 D19 to D16 D15 to D12 D11 to D8 D7 to D4 D3 to D0
0 1 1 1 0000 0001 0010 0011 0100
SELECT REGISTER FOR READBACK
This command selects which registers to read back (see Table 31). After issuing this command, the contents of the selected registers are
clocked out on the SDO on the next 24-bit frame (see Table 32).
Table 31. Initiate Readback Register
D23 D22 D21 D20 D19 to D16 D15 to D0
1 0 0 0 DAC x address (see Table 11) Don’t care
Table 32. Readback Data Register
D23
D22
D21
D20
D19 to D16
D15 to D10
D9
D8 to D7
D6 to D5
D4
D3
D2 to D0
1 0 0 0 DAC x address
(see Table 11)
000000 Invert
dither
Dither scale Dither
signal
Reserved Reserved Span S[2:0]
Table 33. Readback Register Data Functions
Bit Name Description
Span S[2:0] Span register
D2 D1 D0 Output Voltage Range
0 0 0 −20 V to 0 V
0 0 1 −16 V to 0 V
0 1 0 −10 V to 0 V
0 1 1 −12 V to +14 V
1 0 0 −16 V to +10 V
1 0 1 −10 V to +6 V
1 1 0 −5 V to +5 V
1 1 1 −10 V to +10 V
Reserved This is a reserved bit; ignore its contents
Dither Signal Apply N0 or N1 dither signal to DACs register
D6 D5 Dither Setting
0 0 No dither applied
0 1 N0 dither applied
1 0 N1 dither applied
1 1 No dither applied
Dither Scale Dither scale register
D8 D7 Scaling Factor
0 0 No scaling
0 1 75% scaling
1 0 50% scaling
1
1
25% scaling
Invert Dither Invert dither register
D9 Dither Mode
0 Dither signal is not inverted
1 Dither signal is inverted
AD5766/AD5767 Data Sheet
Rev. C | Page 38 of 43
APPLY N0 OR N1 DITHER SIGNAL TO DACs REGISTER
These commands determine which dither signal, N0 or N1, is applied to the selected DACs. Couple the dither signals to the AD5766/
AD5767 outputs after the dither signals are configured and the clamp to ground is removed by writing to the span register. Refer to the
Applications Information section for a more information.
Table 34. Apply N0 or N1 Dither Signal to DACs Register (DAC 7 to DAC 0)
D23 to D20 D19 to D16 D15 to D14 D13 to D12 D11 to D10 D9 to D8 D7 to D6 D5 to D4 D3 to D2 D1 to D0
1001 Don’t care DAC 7 DAC 6 DAC 5 DAC 4 DAC 3 DAC 2 DAC 1 DAC 0
Table 35. Apply N0 or N1 Dither Signal to DACs Register (DAC 15 to DAC 8)
D23 to D20 D19 to D16 D15 to D14 D13 to D12 D11 to D10 D9 to D8 D7 to D6 D5 to D4 D3 to D2 D1 to D0
1010 Don’t care DAC 15 DAC 14 DAC 13 DAC 12 DAC 11 DAC 10 DAC 9 DAC 8
Table 36 shows the dither scaling setting using Bits[D15:D14] as an example. To apply the N0 dither to DAC 7 (see Table 34), set D15 to 0
and D14 to 1. The same dither selection settings apply to the other bits, Bits[D13:D12], Bits[D11:D10], Bits[D9:D8], Bits[D7:D6],
Bits[D5:D4], Bits[D3:D2], and Bits[D1:D0] in Table 34 and Table 35.
Table 36. Dither Selection for DAC x (DAC 0 to DAC 15)
D15 D14 Dither Setting
0 0 No dither applied
0 1 N0 dither signal applied
1 0 N1 dither signal applied
1 1 No dither applied
DITHER SCALE
This command scales the dither before it is applied to the selected channel.
Table 37. Dither Scaling Register (DAC 7 to DAC 0)
D23 to
D20 D19 to D16 D15 to D14 D13 to D12 D11 to D10 D9 to D8 D7 to D6 D5 to D4 D3 to D2 D1 to D0
1100 Don’t care DAC 7 DAC 6 DAC 5 DAC 4 DAC 3 DAC 2 DAC 1 DAC 0
Table 38. Dither Scaling Register (DAC 15 to DAC 8)
D23 to
D20 D19 to D16 D15 to D14 D13 to D12 D11 to D10 D9 to D8 D7 to D6 D5 to D4 D3 to D2 D1 to D0
1101 Don’t care DAC 15 DAC 14 DAC 13 DAC 12 DAC 11 DAC 10 DAC 9 DAC 8
Table 39 shows the dither scaling setting using Bits[D15:D14] as an example. To apply 25% scaling to DAC 7 (see Table 37), set D15 to 1
and D14 to 1. The same dither scaling settings apply to the other bits, Bits[D13:D12], Bits[D11:D10], Bits[D9:D8], Bits[D7:D6],
Bits[D5:D4], Bits[D3:D2], and Bits[D1:D0] in Table 34 and Table 35.
Table 39. Apply Dither Signal to DAC x (DAC 0 to DAC 15)
D15 D14 Scaling Factor
0 0 No scaling
0 1 75% scaling
1 0 50% scaling
1 1 25% scaling
Data Sheet AD5766/AD5767
Rev. C | Page 39 of 43
INVERT DITHER REGISTER
This command inverts the dither applied to the selected DACs when the appropriate bit is set to 0.
Table 40. Invert Dither Register
D23 D22 D21 D20 D19 to D16 D15 to D0
1 0 1 1 Don’t care Dx (invert dither bit for each channel)
Table 41. Invert Dither
Dx Dither Mode
0 Dither signal is not inverted (default)
1 Dither signal is inverted
AD5766/AD5767 Data Sheet
Rev. C | Page 40 of 43
APPLICATIONS INFORMATION
DITHER CONFIGURATION
The AD5766/AD5767 contain two dither input pins to allow dither
tone signals to be coupled to any of the 16 DAC output channels.
Operate the AD5766/AD5767 using the dither functionality to
minimize the transient amplitude seen on the DAC outputs when
the dither functionality is enabled or disabled. The recommended
configuration of the dither functionality is as follows:
1. After the AD5766/AD5767 power up, the input dither
signals must be configured by writing to the dither scale
register and the invert dither register if required.
2. Configure the AD5766/AD5767 in normal operating mode
before applying dither by programming the span register.
3. Write to the apply N0 or N1 dither signal to DACs register
to couple the N0/N1 input dither signals to any DAC
output, VOUTx.
Enabling the dither feature on a channel can increase its
sensitivity to digital feedthrough.
THERMAL CONSIDERATIONS
Up to ±20 mA can be sourced from each channel on the
AD5766/AD5767; thus, it is important to understand the effects
of power dissipation on the package and its effects on junction
temperature. The internal junction temperature must not
exceed 150°C. The AD5766/AD5767 are packaged in a 49-ball,
4 mm × 4mm WLCSP and a 40-lead 6 mm × 6 mm LFCSP
package. The thermal impedance, θJA, is specified in the
Absolute Maximum Ratings section. It is important that the
device is not operated under conditions that cause the junction
temperature to exceed the maximum temperature specified in
the Absolute Maximum Ratings section.
The Thermal Calculation Example (WLCSP) section details
how to calculate the die temperature and maximum permitted
ambient temperature. The quiescent current of the AVDD, AVSS,
AVCC, and VLOGIC pins must also be included in the calculation
of the junction temperature. These calculations use the typical
supply currents specified in Table 1.
Thermal Calculation Example (WLCSP)
For this thermal calculation example, all 16 channels are
enabled with the ±10 V output voltage range used. Each channel
is drawing 2 mA for a +1V output voltage.
AVDD = Span + 2 V = 12 V
AVSS = Span − 2 V = −12 V
AVCC = VLOGIC = 3.3 V
where Span is the output voltage range, ±10 V.
The current required to supply 16 channels (output power) is
2 mA × 16 = 32 mA
The power required on the AVDD rail for the AD5766/AD5767
to supply the 16 channels and 6 mA typical supply current is
12 V × (32 mA + 6 mA) = 0.456 W
Next, add power dissipated by the AVSS, AVCC, and VLOGIC rails
(input power) as follows:
0.456 W + (−12 V × −9 mA) + (3.3 V × 8.3 mA) + (3.3 V ×
0.02 μA) = 0.59 W
To calculate the power dissipated by the AD5766/AD5767, use
the following equation:
PDISS = Input Power − Output Power
For example,
0.59 W − (32 mA × 1 V) = 0.558 W
Then, calculate the die temperature,
0.558 W × 53°C/W = 29.57°C
Using the following equation to calculate the maximum
permitted ambient temperature:
TA MAX = TJ MAX − Die Temperature
For example,
150°C − 29.57° = 120°C
The θJA specification assumes that proper layout and grounding
techniques are followed to minimize power dissipation, as
outlined in the Layout Guidelines section
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5766/AD5767 is via a
serial bus that uses a standard protocol compatible with DSPs
and microcontrollers. The communications channel requires a
4-wire serial interface consisting of a clock signal, a data input
signal, a data output signal, and a synchronization signal. The
device requires a 24-bit data-word with data valid on the falling
edge of SCLK.
AD5766/AD5767 TO SPI INTERFACE
The SPI interface of the AD5766/AD5767 is designed to be easily
connected to industry-standard DSPs and microcontrollers.
Figure 74 shows the AD5766/AD5767 connected to the Analog
Devices, Inc., ADSP-BF531 Blackfin® DSP. The Blackfin has an
integrated SPI port that can be connected directly to the SPI
pins of the AD5766/AD5767.
ADSP-BF531
AD5766/AD5767
SYNCSPISELx
SCLKSCK
DINMOSI
SDOMISO
RESETPF8
15145-073
Figure 74. ADSP-BF531 SPI Interface
Data Sheet AD5766/AD5767
Rev. C | Page 41 of 43
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The PCB on which the AD5766/AD5767
are mounted must be designed so that the AD5766/AD5767 lay
on the analog plane. Ensure that the board has separate analog
and digital sections. If the AD5766/AD5767 are in a system
where other devices require an AGND to DGND connection,
make the connection at one point only. Keep this ground point
as close as possible to the AD5766/AD5767.
The AD5766/AD5767 must have ample supply bypassing of 10 µF
in parallel with 0.1 µF on each supply, located as close to the
package as possible, ideally right up against the device. The
10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor
must have low effective series resistance (ESR) and low effective
series inductance (ESI). Ceramic capacitors, for example, provide
a low impedance path to ground at high frequencies to handle
transient currents due to internal logic switching.
Ensure that the power supply line has as large a trace as possible
to provide a low impedance path and reduce glitch effects on
the supply line. Shield clocks and other fast switching digital
signals from other parts of the board by using a digital ground.
Avoid crossover of digital and analog signals if possible. When
traces cross on opposite sides of the board, ensure that they run
at right angles to each other to reduce feedthrough effects
through the board. The best board layout technique is the
microstrip technique, where the component side of the board is
dedicated to the ground plane only, and the signal traces are
placed on the solder side. However, this technique is not always
possible with a 2-layer board.
It is often useful to provide some heat sinking capability to
allow the power to dissipate easily.
For the WLCSP package, heat is transferred through the solder
balls to the PCB board. θJA thermal impedance is dependent on
board construction. More copper layers enable heat to be
removed more effectively.
The LFCSP package of the AD5766/AD5767 have an exposed
pad beneath the device. Connect this pad to the AVSS supply of
the device. For optimum performance, use special
consideration when designing the motherboard and mounting
the package. For enhanced thermal, electrical, and board level
performance, solder the exposed pad on the bottom of the
package to the corresponding thermal land pad on the PCB.
Design thermal vias into the PCB land pad area to improve heat
dissipation further.
The AVSS plane on the device can be increased (as shown in
Figure 75) to provide a natural heat sinking effect.
BOARD
AV
SS
PLANE
15145-074
Figure 75. Exposed Pad Connection to Board
AD5766/AD5767 Data Sheet
Rev. C | Page 42 of 43
OUTLINE DIMENSIONS
A
B
C
D
E
F
G
4.000
3.960 SQ
3.920
1
234567
3.00 REF
SQ
0.50
BSC
0
1-20-2017-B
BALL A1
IDENTIFIER
0.650
0.595
0.540
0.380
0.355
0.330
0.270
0.240
0.210
0.340
0.320
0.300
COPLANARITY
0.05
P
KG-005027
SEATING
PLANE
BOTTOM VIEW
(BALL SIDE UP)
TOP VIEW
(BALL SIDE DOWN)
END VIEW
Figure 76. 49-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-49-4)
Dimensions shown in millimeters
10-12-2016-A
0.50
BSC
BOTTOM VIEWTOP VIEW
PIN 1
INDICATOR
SEATING
PLANE
0.05 MAX
0.02 NOM
0.203 REF
COPLANARITY
0.08
0.30
0.25
0.18
6.10
6.00 SQ
5.90
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.45
0.40
0.35
0.20 MIN
4.70
4.60 SQ
4.50
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-5
40
1
11
10
20
21
30
31
END VIEW
EXPOSED
PAD
PKG-005131/005253
PIN 1
INDICATOR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
Figure 77. 40-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm × 6 mm and 0.75 mm Package Height
(CP-40-7)
Dimensions shown in millimeters
Data Sheet AD5766/AD5767
Rev. C | Page 43 of 43
ORDERING GUIDE
Model1, 2
Resolution (Bits)
Temperature Range
Package Description
Package Option
AD5766BCBZ-RL7 16 −40°C to +105°C 49-Ball Wafer Level Chip Scale Package [WLCSP] CB-49-4
AD5766BCPZ-RL7 16 −40°C to +105°C 40-Lead Lead Frame Chip Scale Package [LFCSP] CP-40-7
AD5767BCBZ-RL7 12 −40°C to +105°C 49-Ball Wafer Level Chip Scale Package [WLCSP] CB-49-4
AD5767BCPZ-RL7 12 −40°C to +105°C 40-Lead Lead Frame Chip Scale Package [LFCSP] CP-40-7
EVAL-AD5766SD2Z Evaluation Board
EVAL-AD5767SD2Z Evaluation Board
EVAL-SDP-CB1Z Controller Board
1 Z = RoHS Compliant Part.
2 To interface with the EVAL-AD5767SD2Z an EVAL-SDP-CB1Z is also required.
©2017–2018 Analog Devices, Inc. All rights reserved. Trademarks
and registered tr
ademarks are the property of their respective
owners. D15145-0-1/18(C)
