Low Power HART Modem
Data Sheet
AD5700/AD5700-1
Rev. G Document Feedback
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FEATURES
HART-compliant fully integrated FSK modem
1200 Hz and 2200 Hz sinusoidal shift frequencies
115 µA maximum supply current in receive mode
Suitable for intrinsically safe applications
Integrated receive band-pass filter
Minimal external components required
Clocking optimized for various system configurations
Ultralow power crystal oscillator (60 µA maximum)
External CMOS clock source
Precision internal oscillator (AD5700-1only)
Buffered HART output—extra drive capability
8 kV HBM ESD rating
1.71 V to 5.5 V power supply
1.71 V to 5.5 V interface
−40°C to +125°C operation
4 mm × 4 mm LFCSP package
HART physical layer compliant
UART interface
APPLICATIONS
Field transmitters
HART multiplexers
PLC and DCS analog I/O modules
HART network connectivity
GENERAL DESCRIPTION
The AD5700/AD5700-1 are single-chip solutions, designed
and specified to operate as a HART® FSK half-duplex modem,
complying with the HART physical layer requirements. The
AD5700/AD5700-1 integrate all of the necessary filtering, signal
detection, modulating, demodulating and signal generation
functions, thus requiring few external components. The 0.5%
precision internal oscillator on the AD5700-1 greatly reduces
the board space requirements, making it ideal for line-powered
applications in both master and slave configurations. The maxi-
mum supply current consumption is 115 µA, making the AD5700/
AD5700-1 an optimal choice for low power loop-powered applica-
tions. Transmit waveforms are phase continuous 1200 Hz and
2200 Hz sinusoids. The AD5700/AD5700-1 contain accurate
carrier detect circuitry and use a standard UART interface.
Table 1. Related Products
Part No.
Description
AD5755-1
Quad-channel, 16-bit, serial input, 4 mA t o 20 mA and
voltage output DAC, dynamic power cont rol, HART
connectivity
AD5421 16-bit, serial input , l oop powered, 4 mA to 20 mA DAC
AD5410/
AD5420
Single-channel, 12-bit/16-bit, serial input, 4 mA to 20 mA
current source DACs
AD5412/
AD5422
Single-channel, 12-bi t/16-bit, serial input, c ur re nt
source and voltage output DACs
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
OSC
XTAL1
REF REF_EN AGNDDGND FILTER_SEL
CLKOUT
REG_CAPVCC
RESET
CD
DUPLEX
IOVCC
HART_OUT
ADC_IP
HART_IN
RXD
TXD
RTS
CLK_CFG0
CLK_CFG1
XTAL_EN
AD5700/AD5700-1
XTAL2
CONTROL LOGIC
10435-001
FSK
MODULATOR
VOLTAGE
REFERENCE
DAC
FSK
DEMODULATOR
BAND-PASS
FILTER AND
BIASING
ADC
BUFFER
AD5700/AD5700-1 Data Sheet
Rev. G | Page 2 of 24
TABLE OF CONTENTS
Features .....................................................................................1
Applications...............................................................................1
General Description ..................................................................1
Functional Block Diagram.........................................................1
Revision History ........................................................................2
Specifications .............................................................................3
Timing Characteristics...........................................................5
Absolute Maximum Ratings ......................................................6
Thermal Re sistance ................................................................6
ESD Caution ..........................................................................6
Pin Configuration and Function Descriptions...........................7
Typical Performance Characteristics .........................................9
Terminology ............................................................................12
Theory of Operation................................................................13
FSK Modulator .................................................................... 13
Connecting to HART_OUT ................................................ 14
FSK Demodulator................................................................ 14
Connecting to HART_IN or ADC_IP ................................. 14
Clock Configuration ............................................................ 15
Supply Current Calculations................................................ 16
Power-Down Mode ............................................................. 16
Full Duplex Operation......................................................... 16
Applications Information ........................................................ 17
Supply Decoupling............................................................... 17
Transient Voltage Protection................................................ 17
Typical Connection Diagrams ............................................. 18
Outline Dimensions ................................................................ 21
Ordering Guide ................................................................... 21
REVISION HISTORY
12/2016—Rev. F to Rev. G
Changes to Figure 2 and Table 6 ................................................7
1/2014—Rev. E to Rev. F
Changes to Figure 3 to Figure 7 .................................................9
Changes to Example Section....................................................14
10/2013—Rev. D to Rev. E
Changes to t7 and t8 Descriptions, Table 3..................................5
Changed θJA from 30°C/W to 56°C/W .......................................6
Added Figure 13 and Figure 14................................................10
Changes to External Crystal Section an d Figure 25 .................15
5/2013—Rev. C to Rev. D
2/2013—Rev. B to Rev. C
Changed 2 V to 5.5 V Power Supply to 1.71 V to 5.5 V Power
Supply, Features Section ............................................................1
Changes to Summary Statement, VCC Parameter, and Internal
Reference Voltage Parameter Test Conditions/Comments,
Table 2 .......................................................................................3
Changed VCC = 2 V to 5.5 V to VCC = 1.71 V to 5.5 V in the
Summary Statement, Table 3 .....................................................5
Changes to Pin 18 Description and EPAD Mnemonic and
Description, Table 6 ...................................................................7
Changes to Figure 9 and Figure 13 ..........................................10
Changes to Figure 28 ...............................................................18
Change to Figure 30.................................................................20
7/2012—Rev. A to Rev. B
Removed VCC an d IOVCC Current Consumption Text, Table 2.. 3
Added Internal Oscillator and External Clock Parameters
to Table 2 ................................................................................... 4
Changes to t2 Description and Endnote 2, Table 3..................... 5
Changes to IOVCC
Description, Table 6 ..................................... 7
Added Supply Current Calculations Section ........................... 16
Added Transient Voltage Protection Section, Figure 26, and
Figure 27; Renumbered Sequentially ....................................... 17
Changes to Typical Connection Diagrams Section.................. 18
Changes to Figure 29 ............................................................... 19
Changes to Figure 30 ............................................................... 20
Updated Outline Dimensions.................................................. 21
4/2012—Rev. 0 to Rev. A
Change to Transmit Impedance Parameter, RTS Low, Table 2 .. 4
Changes to Figure 3, Figure 4, Figure 5, an d Fig ure 7................ 9
Changes to Figure 10 and Figure 11 ........................................ 10
Changed AD5755 to AD5755-1 Throughout .......................... 17
Change to Figure 27 ................................................................ 18
2/2012—Revision 0: Initial Version
Data Sheet AD5700/AD5700-1
Rev. G | Page 3 of 24
SPECIFICATIONS
VCC = 1.71 V to 5.5 V, IOVCC = 1.71 V to 5.5 V, AGND = DGND, CLKOUT disabled, HART_OUT with 5 nF load, internal and external
receive filter, internal reference; all specifications are from −40°C to +125°C and relate to both A and B models, unless otherwise noted.
Table 2.
Parameter1 Min Typ Max Unit Test Conditions/Comments
POWER REQUIREMENTS2
VCC 1.71 5.5 V
IOVCC 1.71 5.5 V
VCC and IOVCC Current Consumption
Demodulator 86 115 µA B model, external clock, −40°C to +85°C
179 µA B model, external clock, −40°C to +125°C
69 97 µA
B model, external clock, −40°C to +85°C,
external reference
157 µA B model, external clock, −40°C to +125 °C,
external reference
260 µA A model, external clock, −40°C to +125°C
Modulator 124 140 µA B model, external clock, −40°C to +85°C
193 µA B model, external clock, −40°C to +125°C
73 96 µA
B model, external clock, −40°C to +85°C,
external reference
153 µA
B model, external clock, −40°C to +125°C,
external reference
270 µA
A model, external clock, −
40
°C to +125
°C
Crystal Oscillator3 33 60 µA External crystal, 16 pF at XTAL1 and XTAL2
44 71 µA External crystal, 36 pF at XTAL1 and XTAL2
Internal Oscillator4 218 285 µA AD5700-1 only, external crystal not required
Power-Down Mode RESET = REF_EN = DGND
16 35 µA Internal reference disabled, −40°C to +85°C
75 µA Internal reference disabled, −40°C to +125°C
INTERNAL VOLTAGE REFERENCE
Internal Reference Voltage 1.47 1.5 1.52 V
REF_EN = IOV
CC
to enable use of internal
reference; VCC = 1.71 V minimum
Load Regulation 18 ppm/µA Tested with 50 µA load
OPTIONAL EXTERNAL VOLTAGE
REFERENCE
External Reference Input Voltage 2.47 2.5 2.53 V REF_EN = DGND to enable use of external
reference, VCC = 2.7 V minimum
External Reference Input Current
Demodulator 16 21 µA
Current required by external reference in
receive mode
Modulator 28 33 µA
Current required by external reference in
transmit mode
Internal Oscillator 5.5 7 µA Current required by external reference if
using internal oscillator
Power-Down 4.6 8.6 µA
DIGITAL INPUTS
VIH, Input High Voltage 0.7 × IOVCC V
VIL, Input Low Voltage 0.3 × IOVCC V
Input Current −0.1 +0.1 µA
Input Capacitance 5 5 pF Per pin
AD5700/AD5700-1 Data Sheet
Rev. G | Page 4 of 24
Parameter
1
Min Ty p Max Unit Test Conditions/Comments
DIGITAL OUTPUTS
VOH, Output High Voltage IOVCC − 0.5 V
VOL, Output Low Voltage 0.4 V
CD Assert 6 85 100 110 mV p-p
HART_IN INPUT5
Input Voltage Range 0 REF V External reference source
0 1.5 V Internal reference enabled
HART_OUT OUTPUT
Output Voltage 459 493 505 mV p-p
AC-coupled (2.2 µF), measured at HART_OUT
pin with 160 Ω load (worst-case load), see
Figure 17 and Figure 18 for HART_OUT
voltage vs. load
Mark Frequency7 1200 Hz Internal oscillator
Space Frequency7 2200 Hz Internal oscillator
Frequency Error −0.5 +0.5 % Internal oscillator, −40°C to +85°C
−1 +1 % Internal oscillator, −40°C to +125°C
Phase Continuity Error5 0 Degrees
Maximum Load Current5 160 Ω
Worst-case load is 160 Ω, ac-coupled with
2.2 µF, see Figure 21 for recommended
configuration if driving a resistive load
Transmit Impedance 7 Ω RTS low, at the HART_OUT pin
70 kΩ RTS high, at the HART_OUT pin
INTERNAL OSCILLATOR
Frequency 1.2226 1.2288 1.2349 MHz −40°C to +85°C
1.2165 1.2288 1.2411 MHz −40°C to +125°C
EXTERNAL CLOCK
External Clock Source Frequency 3.6496 3.6864 3.7232 MHz
1 Temperature range: −40°C to +125°C; typical at 25°C.
2 Current consumption specifications are based on mean current values.
3 The demodulator and modulator currents are specified using an external clock. If using an external crystal oscillator, the crystal oscillator current specification must be
added to the corresponding VCC and IOVCC demodulator/modulator current specification to obtain the total supply current required in this mode.
4 The demodulator and modulator currents are specified using an external clock. If using the internal oscillator, the internal oscillator current specification must be
added to the corresponding VCC and IOVCC demodulator/modulator current specification to obtain the total supply current required in this mode.
5 Guaranteed by design and characterization, but not production tested.
6 Specification set assuming a sinusoidal input signal containing preamble characters at the input and an ideal external filter (see Figure 23).
7 If the internal oscillator is not used, frequency accuracy is dependent on the accuracy of the crystal or clock source used.
Data Sheet AD5700/AD5700-1
Rev. G | Page 5 of 24
TIMING CHARACTERISTICS
VCC = 1.71 V to 5.5 V, IOVCC = 1.71 V to 5.5 V, TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
1
Limit at TMIN, TMAX Unit Description
t1 1 Bit time 2 max Carrier start time. Time from RTS falling edge to carrier reaching its first peak. See
Figure 3.
t2 1 Bit time2 max Carrier stop time. Time from RTS rising edge to carrier amplitude dropping below
the minimum receive amplitude.
t3 1 Bit time2 max Carrier decay time. Time from RTS rising edge to carrier amplitude dropping to ac
zero. See Figure 4.
t4 6 Bit times2 max Carrier detect on. Time from carrier on to CD rising edge. See Figure 5.
t5 6 Bit times2 max Carrier detect off. Time from carrier off to CD falling edge. See Figure 6.
t6 10 Bit times2 max
Carrier detect on when switching from transmit mode to receive mode in the
presence of a constant valid carrier. Time from RTS rising edge to CD rising edge.
See Figure 7.
t7 2.1 ms typ Crystal oscillator power-up time. On application of a valid power supply voltage at
VCC or on enabling of the oscillator via the X TA L_ EN pin. Crystal load capacitors =
16 pF.
t8 6 ms typ Crystal oscillator power-up time. Crystal load capacitors = 36 pF.
t9 25 µs typ
Internal oscillator power-up time. On application of a valid power supply voltage
at VCC or on enabling of the oscillator via the CLK_CFG0 and CLK_CFG1 pins.
t10 10 ms typ
Reference
power-up time.
t11 30 µs typ Transition time from power-down mode to normal operating mode (external
clock source, external reference).
1 Specifications apply to AD5700/AD5700-1 configured with internal or external receive filter.
2 Bit time is the length of time to transfer one bit of data (1 bit time = 1/1200 Hz = 833.333 µs).
AD5700/AD5700-1 Data Sheet
Rev. G | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Transient currents of up to 100 mA do not cause SCR latch-up.
Table 4.
Parameter
Rating
VCC to GND −0.3 V to +7 V
IOVCC to GND −0.3 V to +7 V
Digital Inputs to DGND
−0.3 V to IOV
CC
+ 0.3 V or
+7 V (whichever is less)
Digital Output to DGND
−0.3 V to IOV
CC
+ 0.3 V or
+7 V (whichever is less)
HART_OUT to AGND −0.3 V to +2.5 V
HART_IN to AGND
−0.3 V to V
CC
+ 0.3 V or
+7 V (whichever is less)
ADC_IP −0.3 V to VCC + 0.3 V or
+7 V (whichever is less)
AGND to DGND −0.3 V to +0.3 V
Operating Temperature Range (TA)
Industrial −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (T
J M AX) 150°C
Power Dissipation (TJ MAX – TA)/θJA
Lead Temperature, JEDEC industry standard
Soldering J-STD-020
ESD
Human Body Model
(ANSI/ESDA/JEDEC JS-001-
2010)
8 kV
Field Induced Charge Model
(JEDEC JESD22_C101E)
1.5 kV
Machine Model
(ANSI/ESD S5.2-2009)
400 V
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 5. Thermal Resistance
Package Type θJA1 θJC Unit
24-Lead LFCSP 56 3 °C/W
1 Thermal impedance simulated values are based on JEDEC 2S2P thermal test
board with thermal vias. See JEDEC JESD51.
ESD CAUTION
Data Sheet AD5700/AD5700-1
Rev. G | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 XTAL_EN Crystal Oscillator Circuit Enable. A low state enables the crystal oscillator circuit, and an external crystal is
required. A high state disables the crystal oscillator circuit, and an external clock source or the internal oscillator
(AD5700-1only) provides the clock source. This pin is used in conjunction with the CLK_CFG0 and CLK_CFG1 pins
in configuring the required clock generation scheme.
2 CLKOUT
Clock Output. If using the crystal oscillator or the internal RC oscillator, a clock output can be configured at the
CLKOUT pin. Enabling the clock output consumes extra current to drive the load on this pin. See the CLKOUT
section for more details.
3 CLK_CFG0 Clock Configuration Control. See Table 7.
4 CLK_CFG1 Clock Configuration Control. See Table 7.
5 RESET Active Low Digital Input. Holding RESET low places the AD5700/AD5700-1 in power-down mode. A high state on
RESET returns the AD5700/AD5700-1 to their power-on state. If not using this pin, tie this pin to IOVCC.
6 CD Carrier Detect—Digital Output. A high on CD indicates a valid carrier is detected.
7 TXD Transmit Data—Digital Input. Data input to the modulator.
8 RTS Request to Send—Digital Input. A high state enables the demodulator and disables the modulator. A low state
enables the modulator and disables the demodulator.
9 DUPLEX
A high state on this pin enables full duplex operation. See the Theory of Operation section. A low state disables
this feature.
10 RXD Receive Data—UART Interface Digital Data Output. Data output from the demodulator is accessed on this pin.
11 IOVCC Digital Interface Supply. Digital threshold levels are referenced to the voltage applied to this pin. The applied
voltage can be in the range of 1.71 V to 5.5 V. IOVCC should be decoupled to ground with low ESR 10 μF and
0.1 μF capacitors (see the Supply Decoupling section).
12 DGND Digital Circuitry Ground Reference Connection. For typical operation, it is recommended to connect this pin to
AGND.
13 REG_CAP
Capacitor Connection for Internal Voltage Regulator. Connect a 1 μF capacitor from this pin to ground. Connect
REG_CAP to VCC when VCC ≤ 1.98 V.
14 HART_OUT HART FSK Signal Output. See the FSK Modulator section and Figure 30 for typical connections.
15 REF Internal Reference Voltage Output, or External 2.5 V Reference Voltage Input. Connect a 1 μF capacitor from this
pin to ground. When supplying an external reference, the VCC supply requires a minimum voltage of 2.7 V.
16 HART_IN
HART FSK Signal. When using the internal filter, couple the HART input signal into this pin using a 2.2 nF series
capacitor. If using an external band-pass filter as shown in Figure 23, do not connect to this pin.
17 ADC_IP
If using the internal band-pass filter, connect 680 pF to this pin. Alternatively, this pin allows direct connection to
the ADC input, in which case an external band-pass filter network must be used, as shown in Figure 23.
10435-002
2
1
3
4
5
6
18
17
16
15
14
13
CD
RESET
CLK_CFG1
CLK_CFG0
CLKOUT
XTAL_EN
REG_CAP
HART_OUT
REF
HART_IN
ADC_IP
V
CC
8
9
10
11
7
RTS
DUPLEX
RXD
IOV
CC
12
DGND
TXD
20
19
21
XTAL2
AGND
XTAL1
22 DGND
23 REF_EN
24 FILTER_SEL
AD5700/
AD5700-1
TOP VIEW
(Not to Scale)
NOTES
1. THE EXPOSED PADDLE MUST BE CONNECTED
TO AGND OR DGND, OR, ALTERNATIVELY, IT CAN
BE LEFT ELECTRICALLY UNCONNECTED. IT IS
RECOMMENDED THAT THE PADDLE BE THERMALLY
CONNECTED TO A COPPER PLANE FOR ENHANCED
THERMAL PERFORMANCE.
AD5700/AD5700-1 Data Sheet
Rev. G | Page 8 of 24
Pin No. Mnemonic Description
18 VCC Power Supply Input. 1.71 V to 5.5 V can be applied to this pin. VCC should be decoupled to ground with low ESR
10 µF and 0.1 µF capacitors (see the Supply Decoupling section).
19 AGND Analog Circuitry Ground Reference Connection.
20 XTA L 2
Connection for External 3.6864 MHz Crystal. Do not connect to this pin if using the internal RC oscillator
(AD5700-1 only) or an external clock source.
21 XTA L 1 Connection for External 3.6864 MHz Crystal or External Clock Source Input. Tie this pin to ground if using the
internal RC oscillator (AD5700-1 only).
22 DGND
Digital Circuitry Ground Reference Connection. For typical operation, it is recommended to connect this pin to
AGND.
23 REF_EN
Reference Enable. A high state enables the internal 1.5 V reference and buffer. A low state disables the internal
reference and input buffer, and a buffered external 2.5 V reference source must be applied at REF. If REF_EN is
tied low, VCC must be greater than 2.7 V.
24 FILTER_SEL
Band-Pass Filter Select. A high state enables the internal filter and the HART signal should be applied to the
HART_IN pin. A low state disables the internal filter and an external band-pass filter must then be connected at
the ADC_IP input pin. In this case, the HART signal should be applied to the ADC_IP pin.
EPAD EPAD
The exposed paddle must be connected to AGND or DGND, or, alternatively, it can be left electrically
unconnected. It is recommended that the paddle be thermally connected to a copper plane for enhanced
thermal performance.
Data Sheet AD5700/AD5700-1
Rev. G | Page 9 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 3. Carrier Start Time
Figure 4. Carrier Stop/Decay Time
Figure 5. Carrier Detect On Timing
Figure 6. Carrier Detect Off Timing
Figure 7. Carrier Detect on When Switching from Transmit Mode to Receive
Mode in the Presence of a Constant Valid Carrier
Figure 8. Supply Currents vs. Supply Voltage—External Reference
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.3 00.3 0.6 0.9 1.2 1.5 1.8 2.1
TIME (ms)
HART_OUT (V)
10435-003
TXD
RTS
T
A
= 25° C; V
CC
= IOV
CC
= 3.3V ; INT V
REF
RTS AND TXD DC LEV E LS HAVE BE E N ADJUS TED FOR
CLARITY. IN REALITY, BOTH OF THESE SIGNALS RANGE
FROM 0V TO 3.3V.
HART_OUT
t
1
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–2.0 –1.5 –1.0 –0.5 00.5 1.0
TIME (ms)
HART_OUT (V)
10435-004
TXD
RTS
HART_OUT
T
A
= 25° C; V
CC
= IOV
CC
= 3.3V ; INT V
REF
RTS AND TXD DC LEV E LS HAVE BE E N ADJUS TED FOR
CLARITY. IN REALITY, BOTH OF THESE SIGNALS RANGE
FROM 0V TO 3.3V.
t3
t2
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.5 00.5 1.0 1.5 2.0 2.5
TIME (ms)
HART S I GNAL (V )
10435-005
RXD
CD
HART S I GNAL
TA = 25° C; VCC = IOVCC = 3. 3V; INT VREF
CD AND RXD DC L EV E LS HAVE BE E N ADJUS TED FOR
CLARITY. IN REALITY, BOTH OF THESE SIGNALS RANGE
FROM 0V TO 3.3V.
t4
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4–5 –4 –3 –2 –1 0 1
TIME (ms)
HART S I GNAL (V )
10435-006
RXD
CD
HART S I GNAL
TA = 25° C; VCC = IOVCC = 3. 3V; INT VREF
CD AND RXD DC L EV E LS H AVE BEEN ADJUSTED FOR
CLARITY. IN REALITY, BOTH OF THESE SIGNALS RANGE
FROM 0V TO 3.3V.
t5
1.50
1.25
1.00
0.75
0.50
0.25
0
–0.50
–0.25
–0.75
–1.00
–10 –7.5 –5.0 –2.5 02.5
TIME (ms)
HART_OUT (V)
10435-007
CD
HART_OUT
HART S I GNAL
RTS
T
A
= 25° C; V
CC
= IOV
CC
= 3.3V ; INT V
REF
RTS AND CD DC LEVEL S HAV E BE E N ADJUS TED FOR
CLARITY. IN REALITY, BOTH OF THESE SIGNALS RANGE
FROM 0V TO 3.3V.
HART S I GNAL HAS ALSO
BEEN O FFSE T BY –0.6V .
t6
100
90
80
70
60
50
40
30
20
10
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
V
CC
= IOV
CC
(V)
SUPPLY CURRENT ( µA)
10435-008
T
A
= 25° C
V
CC
= IOV
CC
= 2.7V TO 5. 5V
DEV 1 EXT REF
DEMOD I
CC
AND IO I
CC
DEMOD I
REF
MO D I
REF
MO D I
CC
AND IO I
CC
AD5700/AD5700-1 Data Sheet
Rev. G | Page 10 of 24
Figure 9. Supply Currents vs. Supply Voltage—Internal Reference
Figure 10. Current in Tx Mode vs. Resistive Load
Figure 11. Current in Tx Mode vs. Capacitive Load
Figure 12. Input Filter Frequency Response
Figure 13. Carrier Detect—Voltage vs. Current, 2 V
Figure 14. Carrier Detect—Voltage vs. Current, 3.3 V
200
180
160
140
120
100
80
60
40
20
0
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
V
CC
= IOV
CC
(V)
I
CC
AND IOI
CC
(µA)
10435-026
T
A
= 25°C
V
CC
= IOV
CC
= 1.71V TO 5.5V
DEV 1 INT REF
REG_CAP IS CONNECTED
TO V
CC
FOR SUPPLIES OF ≤ 2.0V
DEMOD I
CC
AND IOI
CC
MOD I
CC
AND IOI
CC
700
600
500
400
300
200
100
0
0 200 400 600 800 1000 1200
RLOAD (Ω) WITH 22nF TO GND
ICC CURRENT (µA)
10435-009
HART_OUT
2.2µF
22nF RLOAD
TXD = 1
TXD = 0
TA = 25°C; VCC = IOVCC = 3.3V; INT VREF
CLK CONFIG = XTAL OSCILLATOR
IOICC = 41µA
250
225
200
175
150
125
100
75
50
25
0
0 102030405060
C
LOAD
(nF)
I
CC
CURRENT (µA)
10435-010
T
A
= 25°C; V
CC
= IOV
CC
= 3.3V; INT V
REF
CLK CONFIG = XTAL OSCILLATOR
CAPACITIVE LOAD ONLY
IOI
CC
= 41µA
TXD = 1
TXD = 0
0
–2
–4
–6
–8
–10
–12
–14
–16
–20
–18
100 1k 10k
FREQUENCY (Hz)
GAIN (dB)
10435-011
EXTERNAL FILTER
INTERNAL FILTER
T
A
= 25°C
V
CC
= IOV
CC
= 3.3V
INT V
REF
2.5
0
0.5
1.0
1.5
2.0
02.01.81.61.41.21.00.80.60.40.2
10435-032
CD VOLTAGE (V)
CD CURRENT (mA)
T
A
= 25°C
V
CC
= IOV
CC
= 2V
3.5
3.0
2.5
0
0.5
1.0
1.5
2.0
07654321
10435-033
CD VOLTAGE (V)
CD CURRENT (mA)
T
A
= 25°C
V
CC
= IOV
CC
= 3.3V
Data Sheet AD5700/AD5700-1
Rev. G | Page 11 of 24
Figure 15. Reference Voltage vs. VCC
Figure 16. Reference Voltage vs. Temperature
Figure 17. HART_OUT Voltage vs. RL O AD
Figure 18. HART_OUT Voltage vs. CL O AD
1.5012
1.5010
1.5008
1.5006
1.5004
1.5002
1.5000
1.4998
1.4994
1.4996
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
V
CC
(V)
V
REF
INT E RNAL (V)
10435-012
T
A
= 25° C
V
CC
= IOV
CC
= 1.71V TO 5.5V
1.5006
1.5004
1.5002
1.5000
1.4998
1.4996
1.4994
1.4992
1.4990
–40 –20 020 40 60 80 100 120
TEMPERATURE (°C)
VREF INTE RNAL (V)
10435-013
VCC = IOVCC = 2. 7V
TEMPERATURE = –40°C TO + 125°C
500
495
490
485
480
475
470
4650200 400 600 800 1000 1200
R
LOAD
(Ω) || WITH 22nF TO GND
HART_OUT (mV p-p)
10435-014
HART_OUT 2.2µF
22nF R
LOAD
1200Hz
2200Hz
T
A
= 25° C
V
CC
= IOV
CC
= 3.3V
INT V
REF
505
501
502
503
504
500
499
498
497
496
495010 20 30 40 50 60
C
LOAD
(nF)
HART_OUT (mV p-p)
10435-015
1200Hz
2200Hz
T
A
= 25° C
V
CC
= IOV
CC
= 3.3V
INT V
REF
CAPACITIVE LOAD ONLY
AD5700/AD5700-1 Data Sheet
Rev. G | Page 12 of 24
TERMINOLOGY
VCC and IOVCC Current Consumption
This specification gives a summation of the current consump-
tion of both the VCC and the IOVCC supplies. Figure 11 shows
separate measurements for VCC and IOVCC currents vs. varying
capacitive loads, in transmit mode.
Load Regulation
Load regulation is the change in reference output voltage due to
a specified change in load current. It is expressed in ppm/µA.
CD Assert
The minimum value at which the carrier detect signal asserts is
85 mV p-p and the maximum value it asserts at is 110 mV p-p. CD
is already high (asserted) for HART input signals greater than
110 mV p-p. This specification was set assuming a sinusoidal
input signal containing preamble characters at the input and an
ideal external filter (see Figure 23).
HART_OUT Output Voltage
This is the peak-to-peak HART_OUT output voltage. The
specification in Table 2 was set using a worst-case load of 160 Ω,
ac-coupled with a 2.2 µF capacitor. Figure 17 and Figure 18 show
HART_OUT output voltages for both resistive and purely
capacitive loads.
Mark/Space Frequency
A 1.2 kHz signal represents a digital 1, or mark, whereas a
2.2 kHz signal represents a 0, or space.
Phase Continuity Error
The DDS engine in this design inherently generates continuous
phase signals, thus avoiding any output discontinuity when
switching between frequencies. This attribute is desirable for
signals that are to be transmitted over a band limited channel,
because discontinuities in a signal introduce wideband fre-
quency components. As the name suggests, for a signal to be
continuous, the phase continuity error must be 0o.
Data Sheet AD5700/AD5700-1
Rev. G | Page 13 of 24
THEORY OF OPERATION
Highway Addressable Remote Transducer ( HART) Communica-
tion is the global standard for sending and receiving digital
information across analog wires between smart field devices
and control systems. This is a digital two-way communication
system, in which a 1 mA p-p frequency shift keyed (FSK) signal
is modulated on top of a 4 mA to 20 mA analog current signal.
The AD5700/AD5700-1 are designed and specified to operate
as a single-chip, low power, HART FSK half-duplex modem,
complying with the HART physical layer requirements
(Revision 8.1).
A single-chip solution, the AD5700/AD5700-1 not only inte-
grate the modulation and demodulation functions, but also
contain an internal reference, an integrated receive band-pass
filter (which has the flexibility of being bypassed if required),
and an internally buffered HART output, giving a high output
drive capability and removing the need for external buffering.
The AD5700-1 option also contains a precision internal RC
oscillator. The block diagram in Figure 1 shows a graphical
illustration of how these circuit blocks are connected together.
As a result of such extensive integration options, minimal
external components are required. The AD5700/AD5700-1
are suitable for use in both HART field instrument and master
configurations.
The AD5700/AD5700-1 either transmit or receive 1.2 kHz and
2.2 kHz carrier signals. A 1.2 kHz signal represents a digital 1,
or mark, whereas a 2.2 kHz signal represents a 0, or space.
There are three main clocking configurations supported by
these parts, two of which are available on the AD5700 option,
whereas all three are available on the AD5700-1 device:
• External crystal
• CMOS clock input
• Internal RC oscillator (AD5700-1 only)
The device is controlled via a standard UART interface. The
relevant signals are RTS, CD, TXD, and RXD (see Table 6 for
more detail on individual pin descriptions).
FSK MODULATOR
The modulator converts a bit stream of UART-encoded HART
data at the TXD input to a sequence of 1200 Hz and 2200 Hz
tones (see Figure 19). This sinusoidal signal is internally buff-
ered and output on the HART_OUT pin. The modulator is
enabled by bringing the RTS signal low.
Figure 19. AD5700/AD5700-1 Modulator Waveform
The modulator block contains a DDS engine that produces a
1.2 kHz or 2.2 kHz sine wave in digital form and then performs
a digital-to-analog conversion. This DDS engine inherently
generates continuous phase signals, thus avoiding any output
discontinuity when switching between frequencies. For more
information on DDS fundamentals, see MT-085, Fundamentals
of Direct Digital Synthesizers (DDS). Figure 20 demonstrates a
simple implementation of this FSK encoding.
Figure 20. DDS-Based FSK Encoder
10435-016
STOP
START
8-BIT DATA + PARITY
TXD
HART_OUT
"1" = MARK
1.2kHz "0" = SPACE
2.2kHz
10435-017
1.2kHz
WORD
2.2kHz
WORD
MUX
DDS DAC FSK
0
DATA1
CLOCK
AD5700/AD5700-1 Data Sheet
Rev. G | Page 14 of 24
CONNECTING TO HART_OUT
The HART_OUT pin is dc biased to 0.75 V and should be
capacitively coupled to the load. The current consumption
specifications in Table 2 are based on driving a 5 nF load. If
the application requires a larger load value, more current is
required. This value can be calculated from the following
formula:
RMSLOADAD5700
TOTAL III +=
2
2
2
1
24
mV500
LOAD
LOAD
RMSLOAD
R
Cf
I
+
××
×
=
π
(1)
where:
IAD5700 is the current drawn by the AD5700/AD5700-1 in
transmit mode as per specifications (see Table 2). Note that the
specifications in Table 2 assume a 5 nF CLOAD.
f is the output frequency (1.2 kHz or 2.2 kHz).
CLOAD is the capacitive load to ground on HART_OUT.
RLOAD is the resistive load on the loop.
When driving a purely capacitive load, the load should be in the
range of 5 nF to 52 nF. See Figure 11 for a typical plot of supply
current vs. capacitive load.
Example
Assume use of an internal reference, and CLOAD = 52 n F.
ICC + IOICC = 140 µA maximum (from Table 2
specification)
Note that this is incorporating a 5 nF load.
Therefore, to calculate the load current required to drive the
extra 47 n F, use Equation 1.
Substituting f = 1200 Hz, CLOAD = 47 nF, and RLOAD = 0 Ω into
the formula results in ILOAD of 31.3 µA.
If using the crystal oscillator, this adds 60 µA maximum (see
Table 2 for conditions).
Thus, the total worst-case current in this example is:
140 µA + 31.3 µA + 60 µA = 231.3 µA
If driving a load with a resistive element, it is recommended to
place a 22 nF capacitor to ground at the HART_OUT pin. The
load should be coupled with a 2.2 µF series capacitor. For low
impedance devices, the RLOAD range is typically 230 Ω to 600 Ω.
Figure 21. AD5700/AD5700-1 with Resistive Load at HART_OUT
FSK DEMODULATOR
Figure 22. AD5700/AD5700-1 Demodulator Waveform
(Preamble Message 0xFF)
When RTS is logic high, the modulator is disabled and the
demodulator is enabled, that is, the AD5700/AD5700-1 are in
receive mode. A high on CD indicates a valid carrier is detected.
The demodulator accepts an FSK signal at the HART_IN pin
and restores the original modulated signal at the UART
interface digital data output pin, RXD. The combination of the
ADC, digital filtering and digital demodulation results in a
highly accurate output on the RXD pin. The HART bit stream
follows a standard UART frame with a start bit, 8-bit data, one
parity, and a stop bit (see Figure 22).
CONNECTING TO HART_IN OR ADC_IP
The AD5700/AD5700-1 have two filter configuration options:
an external filter (HART signal is applied to ACP_IP) and an
internal filter (HART signal is applied to HART_IN).
The external filter configuration is shown in Figure 23. In this
case, the HART signal is applied to the ADC_IP pin through an
external filter circuit. In safety critical applications, the AD5700/
AD5700-1 must be isolated from the high voltage of the loop
supply. The recommended external band-pass filter includes a
150 kΩ resistor, which limits current to a sufficiently low level
to adhere to intrinsic safety requirements. In this case, the input
has higher transient voltage protection and should, therefore,
not require additional protection circuitry, even in the most
demanding of industrial environments. Assuming the use of a
1% accurate resistor and 10% accurate capacitor components,
the calculated variation in CD trip voltage levels vs. the ideal is
±3.5 m V.
Figure 23. AD5700/AD5700-1 with External Filter on ADC _IP
10435-018
HART_OUT 2.2µF
22nF R
LOAD
10435-019
STOP
START
8-BIT DATA + PARITY
RXD
HART_IN
10435-020
HART
NETWORK
150kΩ
1.2MΩ
1µF
1.2MΩ 300pF 150pF
HART_OUT
REF
ADC_IP
AD5700/
AD5700-1
Data Sheet AD5700/AD5700-1
Rev. G | Page 15 of 24
The internal filter configuration is shown in Figure 24. This
option is beneficial where cost or board space is a large concern
because it removes the need for multiple external components.
This configuration achieves an 8 kV ESD HBM rating but
requires extra external protection circuitry for EMC and surge
protection purposes if used in harsh industrial environments.
Figure 24. AD5700/AD5700-1 Using Internal Filter on HART_IN
CLOCK CONFIGURATION
The AD5700/AD5700-1 support numerous clocking configura-
tions to allow the optimal trade-off between cost and power:
• External crystal
• CMOS clock input
• Internal RC oscillator (AD5700-1 only)
The CLK_CFG0, CLK_CFG1, and X TAL_ E N pins configure
the clock generation as shown in Table 7. The AD5700/AD5700-1
can also provide a clock output at CLKOUT (for more details,
see the CLKOUT section).
External Crystal
The typical connection for an external crystal (ABLS-3.6864MHZ-
L4Q-T) is shown in Figure 25. To ensure minimum current
consumption and to minimize stray capacitances, connections
between the crystal, capacitors, and ground should be made as
close to the AD5700/AD5700-1 as possible. Consult individual
crystal vendors for recommended load information and crystal
performance specifications.
Figure 25. Crystal Oscillator Connection
The ABLS-3.6864MHZ-L4Q-T crystal oscillator data sheet
recommended two 36 pF capacitors. Because the crystal current
consumption is dominated by the load capacitance, in an effort
to reduce the crystal current consumption, two 16 pF capacitors
were used on the X TAL1 and XTAL2 pins. The AD5700/AD5700-1
still functioned as expected, even with the resulting reduction in
frequency performance from the crystal due to the smaller
capacitance values. Crystals are available that support 16 pF
capacitors. It is recommended to consult the relevant crystal
manufacturers for this information.
CMOS Clock Input
A CMOS clock input can also be used to generate a clock for the
AD5700/AD5700-1. To use this mode, connect an external
clock source to the XTAL 1 pin, and leave XTAL2 open circuit
(see Figure 26).
Figure 26. CMOS Clock Connection
Internal Oscillator (AD5700-1 only)
Consuming typically 218 µA, the low power, internal, 0.5 %
precision RC oscillator, available only on theAD5700-1, has an
oscillation frequency of 1.2288 MHz. To use this mode, tie the
XTAL1 pin to ground and leave the XTAL2 pin open circuit
(see Figure 27).
Figure 27. Internal Oscillator Connection
CLKOUT
The AD5700/AD5700-1 can provide a clock output at CLKOUT
(see Table 7).
• If using the crystal oscillator, this clock output can be
configured as a 3.6864 MHz, 1.8432 MHz, or 1.2288 MHz
buffer clock.
• If using a CMOS clock, no clock output can be configured
at the CLKOUT pin.
• If using the internal RC oscillator, this clock output is only
available as a 1.2288 MHz buffer clock.
The amplitude of the clock output depends on the IOVCC level;
therefore, the clock output can be in the range of 1.71 V p-p to
5.5 V p-p. Enabling the clock output of the AD5700/AD5700-1
increases the current consumption of the device. This increase
is due to the current required to drive any load at the CLKOUT
pin, which should not be more than 30 p F.
This capacitance should be minimized to reduce current
consumption and provide the clock with the cleanest edges.
The additional current drawn from the IOVCC supply can be
calculated using the following equation:
I = C × V × f
10435-021
HART
NETWORK
680pF
2.2nF
HART_OUT
HART_IN
ADC_IP
AD5700/
AD5700-1
10435-022
ABLS-3-6864MHZ-L4Q-T
36pF36pF
XTAL1
XTAL2
AD5700/AD5700-1
10435-027
XTAL1
XTAL2
AD5700/AD5700-1
10435-028
XTAL1
XTAL2
AD5700-1
AD5700/AD5700-1 Data Sheet
Rev. G | Page 16 of 24
Table 7. Clock Configuration Options
X TAL _ E N CLK_CFG1 CLK_CFG0 CLKOUT Description
1 0 0 No output 3.6864 MHz CMOS clock connected at XTA L1 pin
1 0 1 No output 1.2288 MHz CMOS clock connected at XTA L1 pin
1 1 0 No output Internal oscillator enabled (AD5700-1 only)
1 1 1 1.2288 MHz output Internal oscillator enabled, CLKOUT enabled (AD5700-1only)
0 0 0 No output Crystal oscillator enabled
0 0 1 3.6864 MHz output Crystal oscillator enabled, CLKOUT enabled
0 1 0 1.8432 MHz output Crystal oscillator enabled, CLKOUT enabled
0 1 1 1.2288 MHz output Crystal oscillator enabled, CLKOUT enabled
SUPPLY CURRENT CALCULATIONS
The VCC and IOVCC current consumption specifications shown
in Table 2 are derived using the internal reference and an
external clock source. This specification is given for a
maximum temperature of 85oC (115 µA receive current and
140 µA transmit current) and an extended maximum
temperature of 125oC (179 µA receive current and 193 µA
transmit current). Alternatively, if the external reference is
preferred, (assuming a maximum temperature of 85oC), the
receive and transmit supply current values become 118 µA and
129 µA respectively, including the current required by the
external reference. A similar calculation can be done for the
125oC maximum temperature case.
If the crystal oscillator or internal oscillator is used, VCC and
IOVCC current consumption figures return to the 115 µA receive
current and 140 µA transmit current. However, the resultant
current consumption from the crystal oscillator or internal
oscillator must now be accounted for, 60 µA maximum addi-
tional current for the crystal oscillator, or 285 µA maximum
additional current for the internal oscillator option. This gives
a maximum current consumption of 175 µA in receive mode
and 200 µA in transmit mode, when using the internal reference
and the crystal oscillator. Utilizing the internal reference
and the internal oscillator (AD5700-1 only) results in a total
maximum current consumption of 400 µA for receive current
and 425 µA for transmit current.
POWER-DOWN MODE
The AD5700/AD5700-1 can be placed into power-down mode
by holding the RESET pin low. If using the internal reference, it
is recommended to tie the REF_EN pin to the RESET pin so
that it is also powered down. If the reference is not powered
down while RESET is low, the output voltage on the REF pin is
approximately 1.7 V until RESET is brought high again.
In this mode, the receive, transmit, and oscillator circuits are all
switched off, and the device consumes a typical current of 16 µA.
FULL DUPLEX OPERATION
Full duplex operation means that the modulator and demodula-
tor of the AD5700/AD5700-1 are enabled at the same time. This
is a powerful feature, enabling a self-test procedure of not only
the HART device but also the complete signal path between the
HART device and the host controller. This provides verification
that the local communications loop is functional. This increased
level of system diagnostics is useful in production self-test and
is advantageous in improving the application’s safety integrity
level (SIL) rating. The full duplex mode of operation is enabled by
connecting the DUPLEX pin to logic high.
Data Sheet AD5700/AD5700-1
Rev. G | Page 17 of 24
APPLICATIONS INFORMATION
SUPPLY DECOUPLING
It is recommended to decouple the VCC and IOVCC supplies with
10 F in parallel with 0.1 F capacitors to ground. For many
applications, 1 F in parallel with 0.1 F ceramic capacitors to
ground should be sufficient. The REG_CAP voltage of 1.8 V is
used to supply the AD5700/AD5700-1 internal circuitry and is
derived from the VCC supply using a high efficiency clocking
LDO. Decouple this REG_CAP supply with a 1 µF ceramic
capacitor to ground. It is also required to decouple the REF pin
with a 1 µF ceramic capacitor to ground. Place decoupling
capacitors as close to the relevant pins as possible.
For loop-powered applications, it is recommended to connect a
resistance in series with the VCC supply to minimize the effect of
any noise, which may, depending on the system configuration, be
introduced onto the loop as a result of current draw variations
from the AD5700/AD5700-1. For typical applications, 470 Ω of
resistance has proven most effective. However, depending on the
application conditions, alternative values may also be acceptable
(see R1 in Figure 31).
TRANSIENT VOLTAGE PROTECTION
Many industrial control applications have requirements for
HART-enabled current input and output modules. Figure 28
shows an example of a HART-enabled current input module
that contains transient voltage protection circuitry, which is
very important in harsh industrial control environments.
The module is powered from a 24 V field supply, and the 250 Ω
load is within the low impedance module itself. This configuration
is in contrast to Figure 29, which demonstrates a secondary HART
device, in which the load is outside of the module. For transient
voltage protection, a 10 V unidirectional (for protection against
positive high voltage transients) transient voltage suppressor (TVS)
is placed at the connection point of the current input module.
The TVS component that is used in a given application circuit
must have power ratings that are appropriate to the individual
system. When choosing the TVS, low leakage current is also an
important specification for maintaining the accuracy of the analog
current input. In the event of a transient spike, the 22 Ω series
resistor acts as a current limiting resistor for the FSK output pin.
The FSK input pin is inherently protected by the 150 kΩ resistor,
which forms part of the recommended external filter circuitry
at the FSK input. The voltage divider, made up of both a 75 kΩ
resistor and a 22 kΩ resistor, is used to maintain a 0.75 V dc bias
at the field side of the FSK output switch.
Figure 28. Current Input Module, HART Circuit
Figure 29. Secondary HART Device
10435-031
HART_OUT
ADC_IP
AGND
TXD
RXD
RTS
CD
V
CC
AD5700/
AD5700-1
ADC
REF
10nF
3.3V
75kΩ
22kΩ
2.2µF
22Ω
6.8nF
3.3V
1.2MΩ
1.2MΩ
300pF
150kΩ
150pF
10µF
10V
400W
MICRO-
CONTROLLER
V
LOOP
24V
FIELD
INSTRUMENT
20kΩ
250Ω
1µF
10435-030
HART_OUT
ADC_IP
AGND
TXD
RXD
RTS
CD
AD5700/
AD5700-1
REF
10nF
3.3V
75kΩ
22kΩ
2.2µF
50V
4.7Ω
0.5W
6.8nF
50V
3.3V
1.2MΩ
1.2MΩ
300pF
150kΩ
150pF
39V
1500W
20Ω
10V
400W HOST
1µF
V
CC
AD5700/AD5700-1 Data Sheet
Rev. G | Page 18 of 24
As previously mentioned, Figure 29 shows an example secondary
HART device, incorporating two-stage protection circuitry. In
this example, a bidirectional (for protection against both positive
and negative high voltage transients) TVS is included to provide
flexibility in the polarity of the connection points of the module.
Because this module could be connected to any point on the
current loop, the higher TVS rating was chosen. The lower
rated second stage provides added protection for the AD5700/
AD5700-1 device.
TYPICAL CONNECTION DIAGRAMS
Figure 30 shows a typical connection diagram for the AD5700/
AD5700-1 using the external and internal options. See the
Connecting to HART_IN or ADC_IP section for more details.
The AD5700/AD5700-1 are designed to interface easily with
Analog Devices, Inc., innovative portfolio of industrial
converters like the AD5421 loop-powered current-output DAC,
the AD5410/AD5420 and AD5412/AD5422 family of line-
powered current-output DACs, and the AD5755-1, a quad DAC
with innovative dynamic power control technology. The
combination of Analog Devices industrial converters and the
AD5700/AD5700-1 greatly simplifies system design, enhancing
reliability while reducing overall PCB size.
Figure 31 shows how the AD5700/AD5700-1 HART modem
can be interfaced with the AD5421 (4 mA to 20 mA loop-powered
DAC) and the ADuCM360 microcontroller to construct a loop
powered transmitter circuit. The HART signal from
HART_OUT is introduced to the AD5421 via the CIN pin.
The HART enabled smart transmitter reference demo circuit
(the block diagram shown in Figure 32) was developed by
Analog Devices and uses the AD5421, a 16-bit, loop-powered,
4 mA to 20 mA DAC, the ADuCM360 microcontroller and the
AD5700 modem. This circuit has been compliance tested,
verified, and registered as an approved HART solution by the
HART Communication Foundation. Contact your sales
representative for further information about this demo circuit.
In conclusion, the AD5700/AD5700-1 enable quick and easy
deployment of a robust HART-compliant system.
Figure 30. AD5700/AD5700-1 Typical Connection Diagram for External and Internal Filter Options
10435-023
10µF
0.1µF
0.1µF
1µF 10µF
150pF
1µF
1.71V TO 5. 5V1.71V TO 5. 5V
REG_CAP
RESET
IOV
CC
V
CC
AGND
AD5700/AD5700-1
CLKOUT
XTAL1
XTAL2
+
150kΩ
1.2MΩ
1.2MΩ
300pF
REF
HART_OUT
DGND
CONFIGURATION
PINS
REF_EN
FILTER_SEL
DUPLEX
CLK_CFG0
CLK_CFG1
XTAL_EN
HART_IN
ADC_IP
CD
RXD
TXD
RTS
ADuC7060 MICROCO NTROL LER
10µF
0.1µF
1µF
HART NETWO RK
HART NETWO RK
1.71V TO 5. 5V
REG_CAP
RESET
IOV
CC
V
CC
AGND
AD5700/AD5700-1
CLKOUT
XTAL1
XTAL2
+
REF
HART_OUT
DGND
CONFIGURATION
PINS
REF_EN
FILTER_SEL
DUPLEX
CLK_CFG0
CLK_CFG1
XTAL_EN
HART_IN
ADC_IP
CD
RXD
TXD
RTS
ADuC7060 MICROCO NTROL LER
680pF
2.2nF
1µF
+0.1µF10µF
1.71V TO 5. 5V
+
Data Sheet AD5700/AD5700-1
Rev. G | Page 19 of 24
Figure 31. Loop-Powered Transmitter Diagram
10435-025
HART_OUT
ADC_IP
REF
AD5700/AD5700-1
47nF 168nF
300pF
DGNDAGND
V
CC
R
L
200kΩ
LOOP–
R
EXT1
R
EXT2
DRIVE
COMREFOUT1 REFIN
REG_SEL0
REG_SEL1
REG_SEL2
REG
IN
IODV
DD
DV
DD
REG
OUT
V
LOOP
AD5421
19MΩ
1MΩ
V
LOOP
ADuCM360
SYNC
SCLK
SDIN
SDO
R
INT
/R
EXT
ALARM_CURRENT_DIRECTION
RANGE1
RANGE0
FAULT
LDAC
COM
TXD
RXD
RTS
CD
R1
R1
470Ω
1.2MΩ
150kΩ
1.2MΩ150pF
OPTIONAL
RESISTOR
T1
OPTIONAL
MOSFET
DN2540
BSP129
0.1µF
SETS REGULATOR
VOLTAGE
C
IN
10µF
0.1µF
1µF
0.1µF
V
Z
= 4.7V
4.7µF
REFOUT2
OPTIONAL
EMC FILTER
1µF
AD5700/AD5700-1 Data Sheet
Rev. G | Page 20 of 24
Figure 32. Block Diagram—Analog Devices HART-Enabled Smart Transmitter Reference Demo Circuit
10435-029
ADC 0
PRESSURE
SENSOR
SIMULATION
TEMPERATURE
SENSOR
PT100
3.3V
ADC 1
ADC
DAC
ADuCM360
SRAM
FLASH
CLOCK
RESET
WATCHDOG
T1: CD
T2: RTS
T3: COM
T4: TEST
SPI
UART
AD5700
AD5421
V
CC
HART_OUT
REF
ADC_IP
3.3V
3.3V
V
DD
C
IN
C_HART
C_SLEW
HART
INPUT
FILTER
COM
V-REGULATOR
TEMPERATURE
SENSOR
COM
REG
IN
V
LOOP
LOOP–
TEST CONNECTOR
+
–
50Ω
HART MODEM
MICRO-
CONTROLLER
WATCHDOG
TIMER
LEXC
DGNDAGND
4.7nF
Data Sheet AD5700/AD5700-1
Rev. G | Page 21 of 24
OUTLINE DIMENSIONS
Figure 33. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-24-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1 Temperature Range Oscillator Options
Receive Supply
Current Package Description
Package
Option
AD5700BCPZ-R5 −40°C to +125°C External clock, crystal 157 µA 24-Lead LFCSP_WQ CP-24-10
AD5700BCPZ-RL7 −40°C to +125°C External clock, crystal 157 µA 24-Lead LFCSP_WQ CP-24-10
AD5700ACPZ-RL7 −40°C to +125°C External clock, crystal 260 µA 24-Lead LFCSP_WQ CP-24-10
AD5700-1BCPZ-R5 −40°C to +125°C
External clock, crystal
or internal oscillator
442 µA 24-Lead LFCSP_WQ CP-24-10
AD5700-1BCPZ-RL7 −40°C to +125°C External clock, crystal
or internal oscillator
442 µA 24-Lead LFCSP_WQ CP-24-10
AD5700-1ACPZ-RL7 −40°C to +125°C
External clock, crystal
or internal oscillator
540 µA 24-Lead LFCSP_WQ CP-24-10
EVA L -AD5700-1EBZ Evaluation Board for
AD5700 and AD5700-1
1 Z = RoHS Compliant Part.
0.50
BSC
0.50
0.40
0.30
0.30
0.25
0.20
COMPLIANT
TO
JEDEC STANDARDS MO - 220- WGG D- 8.
06-11-2012-A
BOTTOM VIEWTOP VIEW
EXPOSED
PAD
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
SEATING
PLANE
0.80
0.75
0.70
0.20 REF
0.25 M IN
COPLANARITY
0.08
PIN 1
INDICATOR
2.20
2.10 SQ
2.00
1
24
7
12
13
1819
6
FOR PROPE R CONNECTION O F
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURAT ION AND
FUNCTION DE S CRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 M AX
0.02 NO M
AD5700/AD5700-1 Data Sheet
Rev. G | Page 22 of 24
NOTES
Data Sheet AD5700/AD5700-1
Rev. G | Page 23 of 24
NOTES
