Prelimina r y Re v. 0.4 6/12 Copyrigh t © 2012 by Silicon Laboratories Si85xx
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si85xx
Si85XX UNIDIRECTIONAL AC CURRENT SENSORS
Features
Applications
Description
The Si85xx products are unidirectional ac current sensors available in full-scale
ranges of 5, 10, and 20 A. Si85xx products are ideal upgrades for older current-
sensing technol ogies offering size, performance, and c ost advantages over current
transformers, Hall effect devices, DCR circuits, and other approaches. The Si85xx
are extremely low-loss, ad ding less than 1.3 m of se ries resistance and less than
2 nH series inductance in the sensing path at 25 °C. Current-sensing terminals are
isolated from the other package pins, providing up to 5 kVRMS isolation level per
safety approval ratings .
Safety Approval (20-Pin SOIC Only)
Functional Block Diagram
Single-chip ac curren t se nsor
Low loss: <1.3 m primary series
resistance and <2 nH inductance
Leading-edge noise suppression
eliminates ne ed for leading-edge
blanking
"Ping-Pong" ou tpu t ve rs ion allows
one Si85xx to replace two curre nt
transformers in full-bridge designs
5, 10, and 20 A full-scale versions
±5% initial accuracy
50 kHz to 1 MHz input frequency
range
FAULT output to safeguard operation
Large 2 VPP min output at full scale
High-side or low-side current sensing
Compact 4x4x1 mm QFN package
(1 kVRMS isolatio n)
20-pin wide-body S OIC
(5 kVRMS isolatio n)
–40 to 125 °C operating rang e
UL/VDE/CSA approval
Power supplies
Motor controls
Lighting eq uipment
Industrial equipment
UL 1577 recognized
5000 VRMS for 1 minute
CSA component notice 5A ap proval
IEC 60950, 61010, 60 601
approved
VDE certification conformity
IEC 60747- 5-2 (VDE0884 Part 2)
Typical Applicatio n
VDD
VOUT
IIN
IOUT
L
C
Q1
Q2
PH1
PH2
R1
OUT
VDD1
GND2
VIN
Si850x
TRST
R2
Si851x
METAL SLUG
VDD TRST/FAULT
IOUT
IIN
GND
INTEGRATOR SIGNAL CONDITIONING
ADC AUTO CALIBRATION
LOGIC
TEMP
SENSOR
OUT1
OUT2
MODE LOGIC MODE
R1 R2 R3 R4
RESET LOGIC
GND1
Patents pending
Ordering Information:
See page 26.
Pin Assignments:
See page 24
VDD
MODE
R1
R3
R4
OUT1
R2
OUT2
TRST/FAULT
GND
IIN
IIN
IIN
IIN
IIN
IOUT
IOUT
IOUT
IOUT
IOUT
Si851x
20-Pin SO IC
12-Pin QFN
Si851x
R1
R2
R3
R4
OUT1
OUT2
TRST/FAULT
GND
IOUT
IIN
MODE
VDD
Si85xx
2 Preliminary Rev. 0.4
Si85xx
Preliminary Rev. 0.4 3
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.1. Under Voltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.2. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.3. Integrator Reset and Current Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.4. Total Measurement Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.5. Effect of Temperature on Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.6. Leading Edge Noise Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.7. FAULT Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.8. Safe Operating Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3. Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.1. Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.2. Layout Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.3. Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.4. Single-Phase Buck Converter Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.5. Full-Bridge Converter Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.6. Push-Pull Converter Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4. Pin Descriptions—12-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
5. Pin Descriptions—20-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
7. Package Outline—12-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
8. Recommended PCB Land Pattern (12-Pin QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
9. Package Outline: Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
10. Recommended PCB Land Pattern (20-Pin SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
11. Top Marking (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
12. Top Marking (SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Si85xx
4 Preliminary Rev. 0.4
1. Electrical Specifications
Table 1. Electrical Specifications
TA= –40 to +125 ºC (typical specified at 25 ºC), VDD = 3 V (±10%) to 5 V (±10%), f = 400 kHz, unless specified
Parameter Conditions Min Typ Max Unit
Supply Voltage (VDD) 2.7 —5.5 V
Supply Current Fully enabled,
input frequency = 1 MHz — 4 7 mA
Undervoltage Lockout (VUVLO) 2.1 2.3 2.5 V
Undervoltage Lockou t Hysteresis
(VHYST)—100 —mV
Logic Input HIGH Level MODE, R1, R2, R3, R4 inputs
(TTL compatible) 2.0 — — V
Logic Input LOW Level — — 0.8 V
Reset Time (tR)Time for 5% initial accuracy 150 — — ns
Reset Time Resistor Range115 —2500 k
R1, R2, R3, R4 Input Rise Time (tRR) — — 30 ns
R1, R2, R3, R4 Input Fall Time (tFR) — — 30 ns
Measurement Watchdog Timeout (tWD)30 50 80 µs
Series Input Resistance Measured from IIN to IOUT —1.3 — m
Series Inductance Measured from IIN to IOUT — 2 — nH
Input/Output Delay1OUT, OUT1, OUT2 delay relative to
input —150 200 ns
Start-Up Self-Cal Delay (tCAL)1Time from VDD = VUVLO + VHYST to
cal complete —150 200 µs
Input Common Mode Volt age Range
(dc) 14x4 mm QFN 1000 — — VRMS
SOIC-20 5000 — — VRMS
Operating Input Frequency Range (f)150 —1000 kHz
DC Power Supply Rejection Ratio —40 —db
Sensitivity @ VDD = 3 V Si8501/11/17 —404 —mV/A
Si8502/12/18 —202 —mV/A
Si8503/13/19 —101 —mV/A
Sensitivity @ VDD = 5 V Si8501/11/17 —392 —mV/A
Si8502/12/18 —196 —mV/A
Si8503/13/19 —98 —mV/A
Notes:
1. Guaranteed by design and/or chara cteri zation.
2. Maximum output load is not recommended to exceed 200 pF and 5 k.
3. Production tested at 400 kHz (50% duty cycle) at VDD = 3.3 V.
4. See "2.4. Total Measurement Error" on page 11 for more information.
Si85xx
Preliminary Rev. 0.4 5
OUT, OUT1, OUT2 Offset Voltage
(VOUTMIN)Current flow from IIN to IOUT =0 —50 —mV
VOUT Slew Rate1,2 OUT, OUT1, OUT2 load = 5K || 50 pF —50 —V/µs
OUT, OUT1, OUT2 Output Resistance 20 —130
Total Measurement Error (%)
(–40 to 125 ºC Temp Range) 20% of full scale3,4 (all devices) –30 —+30 %
100% of full scale3,4 –10 —+10 %
Table 2. Regulatory Information1 (SOIC-20 Only)
CSA
The Si85xx is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
VDE2
The Si85xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
UL
The Si85xx is certified under UL1577 component recognition program. For more details, see File E257455.
Notes:
1. All 5.0 kVRMS rated devices are production tested to >6.0 kVRMS for 1 sec. For more information, see "6. Ordering
Guide" on page 26.
2. Pending.
Table 1. Electrical Specifications (Continued)
TA= –40 to +125 ºC (typical specified at 25 ºC), VDD = 3 V (±10%) to 5 V (±10%), f = 400 kHz, unless specified
Parameter Conditions Min Typ Max Unit
Notes:
1. Guaranteed by design and/or chara cteri zation.
2. Maximum output load is not recommended to exceed 200 pF and 5 k.
3. Production tested at 400 kHz (50% duty cycle) at VDD = 3.3 V.
4. See "2.4. Total Measurement Error" on page 11 for more information.
Si85xx
6 Preliminary Rev. 0.4
Table 3. Insulation and Safety-Related Specifications
Parameter Symbol Test Condition Value Unit
SOIC-20
Minimum Air Gap (Cle a ranc e) L(1O1) 7.6 min mm
Minimum External Tracking (Creepage) L(1O2) 7.6 min mm
Minimum Internal Gap
(Internal Clearance) 0.2 mm
Tracking Resistance
(Comparative Tracking Index) CTI DIN IEC 60112/VDE 0303 Part 1 > 175 V
Resistance (Input-Output)1RIO 1012
Capacitance (Input-Output)1CIO f=1MHz 1.4 pF
Input Capacitance2CI4.0 pF
Notes:
1. To determine resistance and capacitance, the Si85xx is converted into a 2-terminal device. Pins 1–10 are shorted
together to form the first terminal and pins 11–20 are shorted together to form the second terminal. The parameters are
then measured between these two terminals.
2. Measured from input pin to ground.
Table 4. IEC 60664-1 (VDE 0884 Part 2) Ratings
Parameter Test Conditions Specification
SOIC-20
Basic Isolation Group Material Group IIIa
Installation Classification
Rated Mains Voltages < 150 VRMS I-IV
Rated Mains Voltages < 30 0 VRMS I-IV
Rated Mains Voltages < 40 0 VRMS I-IV
Rated Mains Voltages < 60 0 VRMS I-IV
Rated Mains Voltages < 1000 VRMS I-III
Si85xx
Preliminary Rev. 0.4 7
Table 5. IEC 60747-5-2 Insulation Characteristics*
Parameter Symbol Test Condition Characteristic Unit
SOIC-20
Maximum Working Insulation Voltage VIORM 1414 V peak
Input to Output Test Voltage VPR Method b1
(VIORM x 1.875 = VPR, 100%
Production Test, tm=1 sec,
Partial Discharge < 5 pC)
2652 V peak
Transient Overvoltage VIOTM t = 60 s 8000 V peak
Pollution Degree
(DIN VDE 0110, Table 1) 2
Insulation Resistance at TS, VIO =500V R
S>109W
Note: The Si85xx is suitable for basic and reinforced electrical isolation only within the safety limit data. Maintenance of the
safety data is ensured by protective circuits. The Si85xx provides a climate classification of 40/125/21. Note that the
Si85xx is compliant with the IEC60747-5-2 but neither certified nor inspected to IEC60747-5-2. The Si85xx is
compliant, certified, and factory-inspected to IEC60950.
Table 6. IEC Safety Limiting Values1
Parameter Symbol Test Condition SOIC-20 Unit
Case Temperature TS150 °C
Safety Input Current ISJA = 85, VDD =5.5V,
IIN to IOUT = 20 A,
TJ=150°C, T
A=25°C
30 A
Device Power Dissipation2PD0.9 W
Notes:
1. Maximum value allowed in the event of a failure. Refer to the thermal derating curve in Figure 1.
2. The Si85xx is tested with V DD = 5.5 V, TJ=150ºC, C
L= 15 pF, and with an input current from IIN to IOUT equal to
20 Amps at 500 kHz (duty cycl e = 50%).
Si85xx
8 Preliminary Rev. 0.4
Figure 1. SOIC-20 Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Table 7. Thermal Characteristics
Parameter Symbol Test Condition SOIC-20 4x4 mm
QFN Unit
IC Junction-to-Air Thermal Resistance JA 85 55 °C/W
Table 8. Absolute Maximum Ratings1
Parameter Symbol Min Typ Max Units
Storage temperature TSTG –65 — +150 °C
Ambient temperature under bias TA–40 — +125 °C
Junction Temperature TJ— — 150 °C
Supply voltage VDD — — 5.75 V
Voltage on any pin with respect to ground
(not including IIN, IOUT) VIN –0.5 — VDD + 0.5 V
Output Current Drive LO—— 10mA
Lead solder temperature (10 s) — — 260 ºC
Maximum Input Current Rate of Change — — 1000 A/µs
Maximum Peak AC Input Current Limit — — 200 A
Thermal Limit (DC Current)2— — 30 A
Maximum Isolation Voltage (QFN) — — 1400 VRMS
Maximum Isolation Voltage (SOIC-20) — — 6000 VRMS
ESD (CDM) JEDEC (JESD22-C101C) –1.5 +1.5 kV
ESD (HBM) JEDEC (JESD22-A114E) –2500 +2500 V
ESD (MM) JEDEC (JESD22-A115A) –250 + 250 V
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceed ed. Fun ctional operation should be
restricted to conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2. Refer to “AN329: Extendin g the Full -Scale Range of the Si85xx” for more information.
020015010050
40
20
0
Case Temperature (ºC)
Safety-Limiting Current (A)
10
30 VDD = 5.5 V
IIN to IOUT = 20 Amps
Si85xx
Preliminary Rev. 0.4 9
2. Functional Overview
The Si85xx ac current sensor family of products mimics
the functionality of traditional current transformer (CT)
circuits with burden resistor, diode, and output filter, but
offers enhanced performance and added capabilities.
These devices use inductive current sensing and on-
board signal conditioning electronics to generate a 2 V
full-scale output signal proportional to the ac current
flowing from the IIN to the IOUT terminals. As shown in
Figures 2 and 3, current flowing through the metal
package slug induces a signal in the pickup coil on the
Si85xx die. This signal is applied to the input of an
integrator that reconstructs the ac current flowing from
IIN to IOUT. Onboard circuitry provides cycle-by-cycle
integrator reset and temperature and offset voltage
compensation to achieve initial measurement accuracy
to within ±5%.
Figure 2. Si850x (Single Output) Block Diagram
Figure 3. Si851x (Ping Pong Output) Block
Diagram
The Si85xx is superior to other current sensing
approaches and benefits the system in a number of
ways:
Small size: With its 4x4 mm footprint and 1 mm
height (QFN package option), the Si85xx is among
the smallest current sensors available.
Large output signal: The nominal 2.0 V full-scale
output swing offers superior noise immunity versus
other current sensing technologies.
Low loss: The Si85xx adds only 1.3 m (at 25 °C)
to the sensing path, making it one of the lowest-loss
current sensors available. Low 2 nH primary series
inductance is 2,000 times lower compared to a CT
and results in significantly less ringing.
High precision: All versions are available with an
initial maximum error of ±5% of reading; one of the
most accurate current sensors available.
Ping-Pong output mode (Si851x): Alternately
routes the current measurements from each side of
a full-bridge circuit to separate output pins for
comparison, which is very useful for transformer flux
balancing applications. Eliminates a second CT in a
full-bridge application.
Leading edge noise suppression: Filters out
reflected noise due to long reverse recovery time of
output rectifier. Eliminates the need for e xter nal
leading edge blanking circuit.
High common-mode voltage: The Si85xx of fers a
minimum of 1,000 VRMS (for QFN package) or
5kV
RMS (for SOIC package) of common-mode
voltage range (or isolation), making it useful over a
very wide voltage range.
Si850x
METAL SLUG
VDD1 TRST
IOUT
IIN
GND1
INTEGRATOR SIGNAL CONDITIONING
ADC AUTO CA LIBRATION
LOGIC
TEMP
SENSOR
OUT
VDD2
R1 R2
RESET LOGIC
GND2
NC
GND3
PICKUP
COIL
Si851x
METAL SLUG
VDD TRST/FAULT
IOUT
IIN
GND
INTEGRATOR SIG N A L C ON D IT IO NING
ADC AUTO C A LIBRATION
LOGIC
TEMP
SENSOR
OUT1
OUT2
MODE LOGIC MODE
R1 R2 R3 R4
RESET LOGIC
PICKUP
COIL
Si85xx
10 Preliminary Rev. 0.4
FAULT output (Si8517/8/9): Goes low when
external reset timing is in error.
Ease-of-use: Other than con ve nt ion al po we r an d
grounding techniques, no special board layout
considerations are required. Built-in timing interface
circuits allow already-available system switching
signals to be used for reset with no external circuits
required.
2.1. Under Voltage Lockout (UVLO)
UVLO is provided to prevent er roneous operatio n during
device start-up and shutdown or when VDD is
significantly below the specified operating range. The
Si85xx is in UVLO state when VDD < VUVLO (Figure 4).
During UVLO, the output(s) are held at minimum value
regardless of the amount of current flowing from IIN to
IOUT, and signals on integrator reset inputs R1–R4 are
ignored. The Si85xx exits UVLO when VDD > (VUVLO +
VHYST).
2.2. Device Startup
Upon exit from UVLO, the Si85xx performs a voltage
offset and temperature self-calibration cycle. During this
time, output(s) are held at minimum value and reset
inputs (R1-R4) are ignored. The reset inputs are
enabled at the end of the self-calibration cycle, and an
integrator reset cycle is initiated on the first occurrence
of active signals on R1–R4. A current measurement is
initiated immediately after the completion of the
integrator reset cycle, and the resulting current
waveforms appear on the output pins. This "reset-
measure-reset" pattern repeats throughout steady-state
operation.
2.3. Integrator Reset and
Current Measurement
The Si85xx measures current flowing from the IIN to
IOUT terminals. Current is allowed to flow in the
opposite direction, but will not be measured (OUT1 and
OUT 2 remain at their minimum values during reverse
current flow. Reverse current flow will not damage the
Si85xx).
To achieve the specified accuracy, the integrator
capacitor must be discharged (reset) for time period tR
prior to the start of every measurement cycle. This
cycle-by-cycle reset is implemented by connecting
existing system gate control signals to the R1–R4 input s
in a way that resets the integrator when no current is
flowing from IIN to IOUT. To achieve rated accuracy, the
reset cycle must be completed prior to the start of the
measurement cycle. For maximum flexibility, integrator
reset operation can be configured in one of two ways:
Option 1: The start and duration of reset is
determined by the states of the timing
signals applied to R1–R4.
Option 2: The timing signals applied to R1–R4 trigger
the start of reset, and the duration of the
reset is determined by an onboard
programmable reset timer.
Figure 4. Si85xx Startup and Control Timing
UNDER VOLTAGE
LOCKO U T S TATE MEASURE CURRENT
VDD
SUPPLY
INTEGRATOR
RESET
Si85xx
STATUS
Si85xx
OUTPUT
First Positive Edge
Following End of Self-Cal
START-UP
SELF-CAL CYCLE
tCAL
RESET RESET
DON’T CARE
tR
VOUTMIN OUT1, OUT2
VALID
tRP
tR
VUVLO + VHYST
tRP
Si85xx
Preliminary Rev. 0.4 11
Integrator reset Option 1 is selected by connecting TRST
to VDD. In this mode, the Si85xx is held in reset as long
as the signals on R1–R4 satisfy the logic equations of
Table 11. It is typically used in applications where the
gate drivers are external to the system controller IC (the
gate driver delay ensures reset is completed prior to the
start of measurement).
Reset Option 2 is selected by connecting a timing
resistor (RTRST in Figure 5) from the TRST input to
ground. It is typically used in applications where the
gate drivers are on-board the controller. In this mode,
the on-chip reset timer is triggered when the signals on
R1–R4 satisfy the logic equations in Table 11. Once
triggered, the timer maintains integrator in reset for time
duration tR as programmed by the value of resistor
RTRST. The user must select the value of resisto r RTRST
to terminate the reset cycle prior to the start of
measurement under worst-case timing conditions. Note
that values of tR below the specified value in "1.
Electrical Specifications" on page 4 results in increased
integrator output offset error and increased ou tput noise
on VOUT. Moreover, tR’s time is summarized by the
following equation (see Table 9):
tR= 10 ns/k
where values of RTRST that produce a reset time less
than 150 ns (RTRST < 15 k) should not be used.
Figure 5. Programming Reset Time (tR)
2.4. Total Measurement Error
The Si85xx’s absolute accuracy is affected by the
following factors:
Ambient operating temperature
VDD supply voltage
Time
Table 10 includes a composite of all environmental and
operating conditions that can ultimately affect the
absolute measurement accuracy of the Si85xx. The
total worst-case accuracy at full scale can be estima ted
by the sum of the initial accuracy (u p to ±5%) plus a ging
(up to ±1.5%) and supply variations (up to ±3.5%). For
example, the total measurement error expected for a
device operating at a given VDD supply of 5 V (±10 %) is
10% if the device is operated over a temperature range
of –40 to 125 °C for up to 10 years. If the temperature
range is limited to 0 to 85 °C, the measurement error
can be improved by up to 2%. See Figure 6 for details.
2.5. Effect of Temperature on Accuracy
Offset voltage present at the Si85xx output terminals
(output of fset volt age) is calibrated out each time VDD is
applied to the Si85xx; so, its error contribution is
minimized when the temperature at which calibration
occurred is at or near the steady-state operating
temperature of the Si85xx. For example, applying VDD
at 25 °C (offset cal is performed) and operating at 85 °C
will result in a larger of fset error than operating at 50 °C.
The effect of this error is summarized in Figure 6. The
chart is referenced to 25 °C. If the Si85xx is powered up
at 25 °C and then operated at 125 °C with no auto-
calibration performed (i.e., the power is not cycled at
125 °C, which causes an auto-calibration), a 3%
measurement error can be expected.
Table 9. Typical Reset Time vs. RTRST
Resistance
RTRST Reset Time (tR)
15 k150 ns
100 k1µs
1M9µs
2.2 M20 µs
Si85xx
TRST
RTRST
Table 10. Tot al Mea surement Error Contributors
Error Contributor % Error Added
Initial error
@ given VDD ±10%, 25 °C ±5%
Temperatur e var iation
–40 to 125 °C ±3.5%
Aging (10 years) ±1.5%
Si85xx
12 Preliminary Rev. 0.4
Figure 6. Differential Temperature
Calibration Error
Figure 7 shows the Si85xx thermal characteristics of the
on-chip sense resistance over the temperature range of
–40 to +125 °C. Series inductance is constant at 2 nH
(max) across this same temperature range.
Figure 7. Series Resistance Thermal
Characteristics
2.6. Leading Edge Noise Suppression
High-amplitude spikes on the leading edge of the
primary switching waveforms can cause the PWM latch
to be erroneously reset at the start of the switching cycle
when operating in current mode control. To prevent this
problem, leading edge blanking is commonly used to
disable the current comparator during the early portion
of the primary-side switching cycle. The Si85xx
eliminates leading-edge noise spikes by including them
in the signal integration. As shown in the output
waveform of Figure 8 (Si8502 waveform measured
directly on OUT pin with no external filter), noise present
in the input waveform is eliminated without the use of
blanking.
Figure 8. Leading-Edge Noise Suppression
Waveforms (200 kHz, 9.3 A Load)
2.7. FAULT Output
The FAULT output (Si8517/8/9) guards against Si85xx
output signal errors caused by missing reset cycles.
FAULT is asserted when a measurement cycle exceeds
the internal watchdog timer times limit of tWD. FAULT
can be used to alert a local microcontroller or digital
power controller of a current sense failure or to initiate a
system shutdown. To detect faults, tie a 200 k resistor
from TRST/FAULT to VDD.
2.8. Safe Operating Limits
The Si85xx is a very robust current sensor. Its maximum
input current rate of change is limited to 1000 A/µs. The
maximum peak ac input current limit is 200 A. The
thermal limit or continuous dc current flow limit is 30 A.
Exceeding these limits may cause long-term reliability
issues. Refer to “AN329: Extending the Full-Scale
Range of the Si85xx” for more information.
-3.5%
-3.0%
-2.5%
-2.0%
-1.5%
-1.0%
-0.5%
0.0%
0.5%
1.0%
0 25 50 75 100 125
Temperature (Celcius)
% Typi cal E rro
r
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
-20 0 20 40 60 80 100 120
Temperature (°C)
Typical Series Resistance (mOhm)
Current Sense
Transformer
Si8502
Si85xx
Preliminary Rev. 0.4 13
3. Application Information
3.1. Board Layout
The Si85xx is co nnected in the ser ies path of the cu rrent
to be measured. The Si85xx must be located as far as
possible from transformer and other magnetic field
sources. Like other analog components, the Si85xx
should be powered from a low-noise dc source and,
preferably, to a low-noise analog ground plane.
Recommended bypass capacitors are 1 µF in parallel
with a 0.1 µF, positioned as close to the Si85xx as
possible. When using the Si850x (single output
versions), all three ground pins MUST be connected to
the same ground point, and both VDD1 and VDD2 pins
MUST be tied to the VDD system power supply.
3.2. Layout Requirements
The Si85xx requires special layout techniques to ensure
proper operation (see Figures 9 and 10). Due to the
close proximity of the current-carrying slug and current
sensor silicon, magnetic coupling between the current-
carrying slug and the silicon can form a ground loop
causing the output voltage to be 0 V even though
current is flowing through the slug. To eliminate any
such coupling issues, a red fly-wire VDD trace (see
Figures 9 and 10) should be implemented in the layout.
For the SOIC package, the red fly-wire trace should be
approximately 3.5 mm from the center edge of the
package intersecting approximately in the center of the
package (see Figure 9). For the QFN package, the red
fly-wire should be approximately in the center of the
package (see Figur e 10). Standard wire thic knesses for
10 mA current-carrying capabilities should be used.
Moreover, note that the fly-wire trace should be
completely under the ground plane since this will also
reduce coupling.
Regarding isolation voltage requirements, the trace
does not need to follow the lead frame and bonding
traces exactly, as long as the net magnetic flux is close
to zero. The goal here is to keep the magnetic coupling
small and, at the same time, keep the isolation distance
large. Moreover, to ensure that the layout meets the
design’s required creepage and clearance
requirements, the VDD trace should be placed on one
of the inner layers or even the back side of the board.
For example, one can lay out the return VDD trace on
the other side of the PCB so the PCB itself can help to
provide high isolation voltage.
Figure 9. SOIC Layout Requirements
Figure 10. QFN Layout Requirements
VDD Pin
Gnd Pin
SOIC Package
Current
Carrying Slug
Current
Sensor Die
Top View
VDD Fly Wire
5 V VDD Trace
Mode Pin
(Non-Ping-Pong)
Ground
Plane Edge
3.5 mm
Bonding Wire
Ground
Plane Edge
Bypass Capacitor
5V VD D Trace
VDD Pin
QFN Pa ckage
Current
Carrying Slug
Current
Sensor Die
Top View
VDD
Fly Wire
Mode Pin
(Non-Ping-Pong)
Ground
Plane Edge
2 mm
Bonding
Wires
Ground Plane Edge
Gnd Pin
Bypass Ca pa citor
Si85xx
14 Preliminary Rev. 0.4
3.3. Device Configuration
Configuring the Si85xx involves the following steps:
1. Selecting an output mode
2. Configuring integrator reset timing
3. Setting integrator reset time tR
3.3.1. Device Selection
The Si85xx family offers three output modes: Single
output (Si850x), and 2 and 4-Wire Ping Pong (Si851x).
The Si851x products can be configured to operate in all
three of these ou tp u t mo de s.
The Si850x products operate ONLY in Single output
mode. Most half-wave and single-phase applications
require only Single output mode and will typically use
the Si850x.
In Single output mode, output current always appears
on the OUT pin (Si850x) or the OUT1 pin (Si851x). A
single integrator reset signal is typically sufficient when
operating in this mode.
Ping-Pong mode routes the current waveform to two
different output pins on alternate measurement cycles.
It is useful in full-wave and push-pull topologies where
external circuitry can be used to monitor and/or control
transformer flux balance. (Section "3. Application
Information" on page 13 shows design examples using
both output modes in various power topologies.)
2-wire Ping-Pong mode is useful mainly in non-
overlapping two-phase bu ck conve rters but ma y also b e
used in full-bridge applications. In this output mode,
reset inputs R1 and R2 are used, and input R3 is
grounded. Measured current appears on OUT1 when
R1 is high and on OUT2 when R2 is high as shown in
the full-bridge timing example of Figures 11 and 12.
Figure 11. Two-Phase Buck Timing Example A
Figure 12. Full-Bridge Timing Example B
4-Wire Ping-Pong mode is recommended for full-bridge
applications over 2-wire because it uses all four inputs,
making the reset function tolerant to single-point signal
failures. In 4-Wire Ping-Pong mode, current appears on
OUT2 when R1 is high and R2 is low, and appears on
OUT1 when R3 is high and R4 is low as shown in the
full-bridge timing example of Figure 13. Table 11 shows
the states of the Mode and R4 inputs that select each
output, and the resulting reset logic functions and truth
tables.
Figure 13. Full-Bridge Timing Example C
R1
R2
RESET
Si85xx State MEASURE
OUT1
OUT2
MEASURE RESET
tR tR
TIME
R1
R2
RESET
Si85xx State MEASURE
OUT1
OUT2
MEASURE RESET
tR tR
TIME
R1
R3
R2
R4
MEASURE
OUT1
OUT2
MEASURE
RESET
tR
RESET
tR
Si85xx
Preliminary Rev. 0.4 15
3.3.2. Selecting Reset Timing Signals
Reset timing signals should be chosen to meet the
following conditions:
Satisfy reset time tR
Not overlap integrator reset into the desired
measurement period
Not violate reset watchdog timeout period tWD
3.3.3. Configuring Integrator Reset
Per Section “2. Functional Overview”, the integrator
must be reset (zeroed) prior to the start of each
measurement cycle to achieve specified measurement
accuracy. This reset must be synchronized with the
system switch timing signals to ensure that current is
measured during the appropriate time; so, the Si85xx
integrator reset circuitry uses system timing as its
reference. Timing signals connect to reset inputs R1
through R4 where built-in logic functions allow the user
to choose the conditions that cause an integrator reset
event. Important Note: reset inputs R1–R4 are rated to
a maximum input voltage of VDD. External resistor
dividers must be used when connecting driver output
signals to R1–R4 that swin g be yo nd V DD.
As shown in Table 11, the Si850x integrator reset logic
is a simple XOR gate where reset is maintained (or
triggered, depending on use of the TRST input) when
states of reset inputs R1 and R2 are not equal.
Figure 14 shows the logic for the Si851x products,
where any one of three reset logic functions can cause
integrator reset. The output mode (Si851x) is
determined by the states of the Mode and R4 inputs, as
shown in Table 11.
Si85xx
16 Preliminary Rev. 0.4
Table 11. Si85xx Output and Reset Mode Summary
Output Mode MODE R4 R3 R2 R1 Reset
State1Reset Logic Expression
Single-Ended210
0
00 0
RESET = XOR[R1, (R2|R3)]
01 1
10 1
11 0
1
00 1
01 0
10 1
11 0
2-Wire Ping Pong 1 1 0
00 1
RESET = XNOR[R1,(R2|R3)]
01 0
10 0
11 1
4-Wire Ping Pong 0
0
0
00 0
RESET = (R1&R2)|(R3&R4)
01 0
10 0
11 1
1
00 0
01 0
10 0
11 1
1
0
00 0
01 0
10 0
11 1
1
00 1
01 1
10 1
11 1
Notes:
1. Device is in reset when Reset State = 1.
2. For Si850x devices, RESET = XOR [R1, R2].
Si85xx
Preliminary Rev. 0.4 17
As explained in Section “2.3. Integrator Reset and Current Measurement”, the signals applied to R1–R4 can
control integrator reset in real time (Option 1), or they can trigger a reset event of programmable duration (Option
2). Referring to Figure 14, re set timing is exclusively a function of the signals applied to R1–R4 when TRST is tied
to VDD.
If not connected to VDD, the reset timer is enabled, and TRST must be connected through a resistor to ground to
set the reset duration (tR). Note that the reset timer is retriggerable and generates a timed integrator discharge
pulse whenever the reset logic output transitions from low to high.
Figure 14. Si851x Integrator Reset Logic
R4
R2
R1
R3
INTEGRATOR
MODE = 1
R4 = 0
MODE = 1
R4 = 1
MODE = 0
SYSTEM
CONTROLLER
Logic level gate
control signals
(to Rn inputs)
Logic leve l gate
control signals
(to Rn inputs)
External
Driver
Internal
Driver
Required if driver
output voltage > VDD
Output 1
Output 2
Output 3
RESET
TIMER
OUT
CLK
TRST
PGM
VREF
Reset timing determined
only by inputs R1–R4.
Reset triggered by inputs
R1–R4. Reset time (tR) set
by value of resistor RTRST.
TRST = R1 to GND
TRST = VDD
0+
1
Si85xx
18 Preliminary Rev. 0.4
3.3.4. Settin g Re se t Time tR
The programmable reset timer is triggered when the states of the signals applied to R1–R4 cause the associated
logic expression in Table 11 to go high (transition to the TRUE state).
Because this timer is re-triggerable, R1–R4 must remain TRUE for the duration of the desired tR as shown in
Figure 15. Sho uld R1–R4 tr ansition FAL SE during tR, integrator reset will be immediately halted, resulting in lower
measurement accuracy due to higher integr ator offset error.
Figure 15. Correct tR Programming Using Resistor from TRST Input to Ground
CURRENT
TRUE
FALSE
R1–R4 STATE
RESET MEASURESi85xx STATUS
Programmed
value of tR
Si85xx OU T PU T
R1–R4 T RU E
for programmed
tR (m in im u m )
0 ns (min)
Si85xx
Preliminary Rev. 0.4 19
3.3.5. Measurement Watchdog Timer and FAULT Output
A built-in watchdog timer disables measurement an d holds OUT or OUT 1 and OUT2 at the ir minimum valu es when
the time between integrator resets exceeds the FAULT Detect Time. The output signal from this watchdog is
available on the FAULT output pin (Si8517/8/9 only).
Figure 16 illustrates two means of entering a fault condition. Either fault condition 1 or 2 occurs when the reset
period exceeds the FAULT Detect Time, which ranges from 30 to 80 µs due process variations. The fault condition
ends when the next logic reset cycle begins.
Figure 16. Measurement Watchdog Timer Operation
t Cycle Reset
FAULT Detect Time
30-80 µs
FAULT Condition 1
FAULT Detect Time
30-80 µs
FAULT Condition 2
Output
Reset Logic
Reset Logic
Output
FAULT Output
FAULT Output
Si85xx
20 Preliminary Rev. 0.4
3.3.6. Output Over-Range
The Si85xx can be over-ranged by more than 100% with no adverse effects. For instance, if the Si8512 (a 10 A
nominal full-scale device) has a 15 A peak current applied, then the output voltage (OUT) will be 3 V (assuming
VDD = 5 V). If a 10 A peak current is applied, then the output returns to the nominal 2 V output. The head room of
OUT is VDD–1.4 V. Figure 17 illustrates the head room limitation of the Si85xx versus supply.
Figure 17. Headroom Limitation
0
1
2
3
4
5
50% 100% 150% 200% 250%
OUT (V)
I (Amps ) Pe rce nt Nomi n a l Full-Sc a le In pu t
VDD = 5 V
VDD = 2.7 V
3.6 V
Si85xx
Preliminary Rev. 0.4 21
3.4. Single-Phase Buck Converter Example
In this example, the Si850x is configured to operate in a single-phase synchronous buck converter (Figure 18).
This converter has a PWM frequency of 1 MHz and a maximum duty cycle of 80%.
This is an example of a half-wave application that can be addressed with Single-Ended output mode. The PWM
period is calculated to be 1/10–6 = 1.0 µs, and the worst-case value, tR, is 0.2 x 1.0 x 10–6 = 200 ns at 80%
maximum duty cycle (RTRST =20k).
In this example, the current measurement is made when the buck switch is on; so, PH2 is chosen as the reset
signal by connecting PH2 to R1 and grounding R2. The PH2 signal can be obtained at the input of the driver
external to th e PWM co nt ro ller or the ou tp ut of the controller 's in te r na l dr iver (th rou gh a r es i sto r d ivide r if the drive r
output swings beyond the device VDD range).
Figure 18. Si850x Single-Phase Buck Converter
VDD
VOUT
2 Vpp
IIN
IOUT
L1
C3
Q1
Q2
PH1
PH2
R1 OUT
VDD1 GND1
VIN
Si850x
VDD2
R2
PWM
RESET
PH2
Si850x State
I > 0I = 0
Current
MEASURE
GND2
TRST
RTRST
100 ns
GND3
C1
0.1 µF C2
1 µF
Si85xx
22 Preliminary Rev. 0.4
3.5. Full-Bridge Converter Example
The full-bridge circuit of Figure 19 uses an Si851x configured in 4-Wire Ping-Pong output mode. The switching
frequency of this phase-shifted full-bridge is 150 kHz, and the maximum control phase overlap is 70%.
Figure 19. Full-Bridge Converter
Given the 150 kHz switching frequency (duty cycle fixed at 50%), the equivalent period is 1/150 x 103= 6.6 µs. At
70% maximum overlap, this equates to a worst-case tR value of 0.3 x 6.6 x 10–6 = 1.98 µs. The default value for tR
can, therefore, be used and is selected by connecting TRST to VDD. As shown in the timing diagram of Figure 19,
integrator reset occurs when current circulates between Q1 and Q2 and between Q3 and Q4 (i.e. when current is
not being sourced from VIN). Th e external driver de lay ensures r eset is complete pr ior to the st ar t of measure ment.
IIN
IOUT
TI
Q1
Q3
PH1
PH2
R1
OUT1
GND
VIN
Si851x
MODE
PH4
PH3
Q2
Q4
R2
VDD
VDD
OUT2
OUT1
OUT2
PH1
PH3
PH2
PH4
3–4
1–4 1–2 2–3
RESET RESET
Si85xx State MEASURE
TRST
OUT1
OUT2
MEASURE
R3 R4
Switches Turned ON
VDD
C1
0.1 µF C2
1 µF
Si85xx
Preliminary Rev. 0.4 23
3.6. Push-Pull Converter Example
The Push-Pull converter of Figure 20 uses 2-Wire Ping Pong output mode. As shown in the timing diagram, the
integrator reset occurs when the inputs of both the PH1 and PH2 drivers are low. As shown, TRST is connected to
VDD, selecting the default value of tR (250 ns). Assuming an 80% maximum duty cycle, this value of tR would
deliver specified accuracy over a PWM frequency range of 50 to 400 kHz. Frequencies above 400 kHz would
require the selection of a lower tR value by connecting a resistor from TRST to ground.
Figure 20. Push-Pull Example Using Default tR Value
VDD
IIN
IOUT
Q1
Q2
PH2
R1
OUT1
VDD
GND
VIN
Si851x
MODE
Si85xx Status
T1
PH1
PH2
MEASURE RESET
PH1
R2
R3
R4
OUT2
MEASURE RESET MEASURE
OUT1
OUT2
TRST
C1
0.1 µF C2
1 µF
Si85xx
24 Preliminary Rev. 0.4
4. Pin Descriptions—12-Pin QFN
Figure 21. Example Pin Configurations
Table 12. Si85xx Family Pin Descriptions
Pin# Si850x
Pin Name Description Si851x
Pin Name Description
1 R1 Integrator reset input 1 R1 Integrator reset input 1
2 R2 Integrator reset input 2 R2 Integrator reset input 2
3 GND2 Ground R3 Integrator reset input 3
4 GND3 R4 Integrator reset input 4
5 OUT Output OUT1 Output in single-ended output mode, or
one of two outputs in Ping-Pong mode.
6 NC No connect OUT2 Second of two Ping-Pong mode outputs
7 TRST Reset time control TRST Reset time control
8 GND1 Ground GND Ground
9 IOUT Current output terminal IOUT Current output terminal
10 IIN Current input terminal IIN Current input terminal
11 VDD1 Power supply input VDD Power supply input
12 VDD2 MODE Mode control input
Si850x
R1
R2
GND2
GND3
OUT
NC
TRST
GND1 VDD2
VDD1
IIN
IOUT
Si851x
R1
R2
R3
R4
OUT1
OUT2
TRST/FAULT
GND
MODE
VDD
IIN
IOUT
Si85xx
Preliminary Rev. 0.4 25
5. Pin Descriptions—20-Pin SOIC
Figure 22. Example Pin Configurations
Table 13. Si85xx Family Pin Descriptions
Pin# Si850x
Pin Name Description Si851x
Pin Name Description
1 VDD1 Power supply input VDD Power supply input
2 VDD2 MODE Mode control input
3 R1 Integrator reset input 1 R1 Integrator reset input 1
4 R2 Integrator reset input 2 R2 Integrator reset input 2
5 GND2 Ground R3 Integrator reset input 3
6 GND3 R4 Integrator reset input 4
7 OUT Output OUT1 Output in single-ended output mode, or
one of two outputs in Ping-Pong mode.
8 NC No connect OUT2 Second of two Ping-Pong mode outputs
9 TRST Reset time control TRST Reset time control
10 GND1 Ground GND Ground
11–15 IOUT Current output terminal IOUT Current output terminal
16–20 IIN Current input terminal IIN Current input terminal
VDD
MODE
R1
R3
R4
OUT1
R2
OUT2
TRST/FAULT
GND
IIN
IIN
IIN
IIN
IIN
IOUT
IOUT
IOUT
IOUT
IOUT
Si851x
20-Pin SOIC
VDD1
VDD2
R1
GND2
OUT
R2
NC
TRST
GND1
IIN
IIN
IIN
IIN
IIN
IOUT
IOUT
IOUT
IOUT
IOUT
Si850x
20-Pin SOIC
GND3
Si85xx
26 Preliminary Rev. 0.4
6. Ordering Guide
New
OPNs Full
Scale
Current
(A)
Initial
Accuracy %1Temp
Range Pin 7
Function Isolation
Rating Output
Mode Package2Old Obsolete
OPNs3
(Previously
Specified with
±5% Accuracy
and
–40C to +85 °C)
Old Obsolete
OPNs3
(Previously
Specified with
±20%
Accuracy)
Si8501-C-IM 5
5% –40 to
125 °C
Integrator
Reset Pro-
gramming
Time Input
1kV
RMS
Single
QFN-12
Si8501-C-GM Si8504-C-IM
Si8502-C-IM 10 Si8502-C-GM Si8505-C-IM
Si8503-C-IM 20 Si8503-C-GM Si8506-C-IM
Si8501-C-IS 5
5kV
RMS SOIC-20 New package offeringSi8502-C-IS 10
Si8503-C-IS 20
Si8511-C-IM 5
1kV
RMS
Ping-
Pong
QFN-12
Si8511-C-GM Si8514-C-IM
Si8512-C-IM 10 Si8512-C-GM Si8515-C-IM
Si8513-C-IM 20 Si8513-C-GM Si8516-C-IM
Si8511-C-IS 5
5kV
RMS SOIC-20 New package offeringSi8512-C-IS 10
Si8513-C-IS 20
Si8517-C-IM 5
FAULT
Output
1kV
RMS QFN-12
Si8517-C-GM
—Si8518-C-IM 10 Si8518-C-GM
Si8519-C-IM 20 Si8519-C-GM
Si8517-C-IS 5
5kV
RMS SOIC-20 New Package OfferingSi8518-C-IS 10
Si8519-C-IS 20
Notes:
1. See "2.4. Total Measurement Error" on page 11 for more information.
2. All packages are RoHS-compliant. Moisture Sensitivity level is MSL3 with peak reflow temperature of 260 °C according to the JEDEC
industry classification, and peak solder temperature.
3. Since the initial accuracy for all devices is now specified as ±5%, Si8504/5/6 and Si8514/15/16 OPNs have been replaced with
Si8501/2/3 and Si8511/12/13 OPNs, respectively.
Si85xx
Preliminary Rev. 0.4 27
7. Package Outline—12-Pin QFN
Figure 23 illustrates the package details for the Si85xx. Table 14 lists the values for the dimensions shown in the
illustration.
Figure 23. 12-Pin QFN Package Diagram
Table 14. QFN-12 Package Diagram Dimensions
Dimension Min Nom Max
A 0.80 0.85 0.90
A1 0.00 0.03 0.05
b1 0.20 0.25 0.30
b2 0.95 1.00 1.05
D 4.00 BSC.
e 0.50 BSC.
E 4.00 BSC.
f 0.75 BSC.
g 2.45 BSC.
h 1.30 BSC.
L1 0.35 0.40 0.45
L2 0.85 0.90 0.95
aaa 0.05
bbb 0.05
ccc 0.08
ddd 0.10
eee 0.10
Notes:
1. All dimensions shown are in millimeters (mm).
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
Si85xx
28 Preliminary Rev. 0.4
8. Recommended PCB Land Pattern (12-Pin QFN)
Figure 24 illustrates the PCB land pattern details for the 12-pin QFN package. Table 15 lists the values for the
dimensions shown in the illustration.
Figure 24. 12-Pin QFN PCB Land Pattern
Table 15. 12-Pin QFN PCB Land Pattern Dimensions
Dimension mm
C1 1.95
C2 1.30
D1 3.90
D2 2.45
E0.50
X1 0.80
X2 1.00
Y1 0.30
Y2 1.10
Notes:
1. This Land Pattern Desi gn is based on IPC-7351 design guidelines for
Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a
card fabrication tolerance of 0.05 mm is assumed.
Si85xx
30 Preliminary Rev. 0.4
Table 16. 20-Pin Wide Body SOIC Package Diagram Dimensions
Dimension Min Max
A — 2.65
A1 0.10 0.30
A2 2.05 —
b0.310.51
c0.200.33
D 12.80 BSC
E 10.30 BSC
E1 7.50 BSC
e 1.27 BSC
L0.401.27
h0.250.75
θ0° 8°
aaa — 0.10
bbb — 0.33
ccc — 0.10
ddd — 0.25
eee — 0.10
fff — 0.20
Notes:
1. All dimensions shown are in millime ters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawi n g con forms to JEDEC Ou tl i ne MS-0 13 , Variation AC.
4. Recommended reflow profile per JEDEC J-STD-020C specification for small body,
lead-free components.
Si85xx
Preliminary Rev. 0.4 31
10. Recommended PCB Land Pattern (20-Pin SOIC)
Figure 26 illustrates the PCB land pattern details for the 20-pin SOIC package. Table 17 lists the values for the
dimensions shown in the illustration.
Figure 26. 20-Pin SOIC PCB Land Pattern
Table 17. 20-Pin SOIC PCB Land Pattern Dimensions
Dimension mm
C1 9.40
E1.27
X1 0.60
Y1 1.90
Notes:
1. This Land Pattern Design is based on IPC-7351 design guidelines for
Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a
card fabrication tolerance of 0.05 mm is assumed.
Si85xx
32 Preliminary Rev. 0.4
11. Top Marking (QFN)
Figure 27. QFN Top Marking
Table 18. Top Marking Explanation
Line 1 Marking: Device Part Number Si85XX:
Where XX = 01, 02, 03, 11, 12, 13, 17, 18, 19
Line 2 Marking: RTTTTT = Mfg Code Manufacturing code from assembly house
“R” indicates revision
Line 3 Marking: Circle Bottom-Left Justified Pin 1 Identifier
YY = Year
WW = Work Week Corresponds to the year and work week of the assembly
build date.
Si85XX
RTTTTT
YYWW
Si85xx
Preliminary Rev. 0.4 33
12. Top Marking (SOIC)
Figure 28. SOIC Top Marking
Table 19. Top Marking Explanation
Line 1 Marking: Device Part Number Si85XX-IS
Where XX = 01, 02, 03, 11, 12, 13, 17, 18, 19
Line 2 Marking: YY = Year
WW = Work Week Assigned by the Asse m bly Hous e. Corr es po n ds to the
year and work week of the mold date.
RTTTTT = Mfg Code Manufacturing code from assembly house
“R” indicates revision
Line 3 Marking: Circle = 1.5 mm Diameter
(Center Justified) “e3” Pb-Free Symbol
Country of Origin
ISO Code Abbreviation TW = Taiwan
Si85XX-IS
YYWWRTTTTT
TW
e3
Si85xx
34 Preliminary Rev. 0.4
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Updated Table 1, “Electri cal Specifications,” on
page 4.
Added 20-pin wide-body SOIC package option.
Updated "6. Ordering Guide" on page 26.
All devices are now specified to ±5% initial accuracy.
All devices are now specified for operation over –40 to
+125 °C temperature range. All ordering part numbers
have been updated to reflect this (i.e. previous “-GM”
and “-GS” part number suffixes have been replaced with
“-IM” and “-IS” suffixes).
Added sections “8. Recommended PCB Land
Pattern (12-Pin QFN)” and “ 10. Recommend ed PCB
Land Pattern (20-Pin SOIC)”.
Revision 0.2 to Revision 0.21
Added reference to IEC61010, IEC60601 on page 1.
Updated "6. Ordering Guide" on page 26.
Added Top Marking sect ion s.
Revision 0.21 to Revision 0.3
Updated Table 2 on page 5.
Production test voltage is > 6.0 kVRMS.
Added “2.5. Effect of Switching Frequency on
Accuracy” on page 11.
Added Figure 6, “Full- Scal e Output Accuracy vs.
Frequency,” on page 11.
Updated "3.2. Layout Requirements" on page 13.
Added layout recommendations for QFN.
Added Figure 10, “QFN Layout Requirements,” on
page 13.
Revision 0.3 to Revision 0.4
Updated Table 8 on page 8.
Added junction temperature spec.
Removed Figure 6, “Full-Scale Output Accuracy vs.
Frequency,” on page 11.
Updated Figures 9 and 10 on page 13.
Updated Table 11 on page 16.
Updated notes.
Updated Top Marks.
Added revision description.
Si85xx
Preliminary Rev. 0.4 35
NOTES:
Si85xx
36 Preliminary Rev. 0.4
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