S-93L46A/56A/66A
www.sii-ic.com
LOW VOLTAGE OPERATION
3-WIRE SERIAL E2PROM
© Seiko Instruments Inc., 2004-2011 Rev.7.0_00
Seiko Instruments Inc. 1
The S-93L46A/56A/66A is a low voltage operation, high speed, low current consumption, 3-wire serial E2PROM with a wide
operating voltage range. The S-93L46A/56A/66A has the capacity of 1 K-bit, 2 K-bit and 4 K-bit, and the organization is 64-
word × 16-bit, 128-word × 16-bit, and 256-word × 16-bit. It is capable of sequential read, at which time addresses are
automatically incremented in 16-bit blocks.
The communication method is by the Microwire bus.
Features
• Operating voltage range Read: 1.6 V to 5.5 V
Write: 1.8 V to 5.5 V (WRITE, ERASE)
2.7 V to 5.5 V (WRAL, ERAL)
• Operation frequency: 2.0 MHz (VCC = 4.5 V to 5.5 V)
• Write time: 8.0 ms max.
• Sequential read capable
• Write protect function during the low power supply voltage
• Function to protect against write due to erroneous instruction recognition
• Endurance: 106 cycles / word*1 (Ta = +85°C)
• Data retention: 100 years (Ta = +25°C)
20 years (Ta = +85°C)
• Memory capacity: S-93L46A: 1 K-bit
S-93L56A: 2 K-bit
S-93L66A: 4 K-bit
• Initial shipment data: FFFFh
• Lead-free, Sn 100%, halogen-free*2
*1. For each address (Word: 16-bit)
*2. Refer to “ Product Name Structure” for details.
Packages
• 8-Pin SOP (JEDEC)
• 8-Pin TSSOP
• TMSOP-8
• SNT-8A
• WLP-7D
Caution This product is intended to use in general electronic devices such as consumer electronics, office
equipment, and communications devices. Before using the product in medical equipment or
automobile equipment including car audio, keyless entry and engine control unit, contact to SII is
indispensable.
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A Rev.7.0_00
Seiko Instruments Inc.
2
Pin Configurations
1. 8-Pin SOP (JEDEC)
8-Pin SOP (JEDEC)
Top view Table 1
Pin No. Symbol Description
1 CS Chip select input
2 SK Serial clock input
3 DI Serial data input
4 DO Serial data output
5 GND Ground
6 TEST*1 T est
7 NC No connection
8 VCC Power supply
*1. Connect to GND or VCC.
Even if this pin is not connected, performance is not affected so long as
the absolute maximum rating is not exceeded.
7
6
5
8
2
3
4
1
Figure 1
S-93L46AD0I-J8T1x
S-93L56AD0I-J8T1x
S-93L66AD0I-J8T1x
8-Pin SOP (JEDEC) (Rotated)
Top view Table 2
Pin No. Symbol Description
1 NC No connection
2 VCC Power supply
3 CS Chip select input
4 SK Serial clock input
5 DI Serial data input
6 DO Serial data output
7 GND Ground
8 TEST*1 T est
*1. Connect to GND or VCC.
Even if this pin is not connected, performance is not affected so
long as the absolute maximum rating is not exceeded.
7
6
5
8
2
3
4
1
Figure 2
S-93L46AR0I-J8T1x
S-93L56AR0I-J8T1x
S-93L66AR0I-J8T1x
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
Rev.7.0_00 S-93L46A/56A/66A
Seiko Instruments Inc. 3
2. 8-Pin TSSOP
8-Pin TSSOP
Top view Table 3
Pin No. Symbol Description
1 CS Chip select input
2 SK Serial clock input
3 DI Serial data input
4 DO Serial data output
5 GND Ground
6 TEST*1 T est
7 NC No connection
8 VCC Power supply
*1. Connect to GND or VCC.
Even if this pin is not connected, performance is not affected so
long as the absolute maximum rating is not exceeded.
7
6
5
8
2
3
4
1
Figure 3
S-93L46AD0I-T8T1x
S-93L56AD0I-T8T1x
S-93L66AD0I-T8T1x
3. TMSOP-8
TMSOP-8
Top view Table 4
Pin No. Symbol Description
1 CS Chip select input
2 SK Serial clock input
3 DI Serial data input
4 DO Serial data output
5 GND Ground
6 TEST*1 Test
7 NC No connection
8 VCC Power supply
*1. Connect to GND or VCC.
Even if this pin is not connected, performance is not affected so
long as the absolute maximum rating is not exceeded.
7
6
5
8
2
3
4
1
Figure 4
S-93L46AD0I-K8T3U
S-93L56AD0I-K8T3U
S-93L66AD0I-K8T3U
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A Rev.7.0_00
Seiko Instruments Inc.
4
4. SNT-8A
SNT-8A
Top view Table 5
Pin No. Symbol Description
1 CS Chip select input
2 SK Serial clock input
3 DI Serial data input
4 DO Serial data output
5 GND Ground
6 TEST*1 T est
7 NC No connection
8 VCC Power supply
*1. Connect to GND or VCC.
Even if this pin is not connected, performance is not affected so long as
the absolute maximum rating is not exceeded.
7
6
5
8
2
3
4
1
Figure 5
S-93L46AD0I-I8T1x
S-93L56AD0I-I8T1x
S-93L66AD0I-I8T1x
5. WLP-7D
WLP-7D
Bottom view Table 6
Pin No. Symbol Description
1 CS Chip select input
2 DI Serial data input
3 VCC Power supply
4 TEST*1 Test
5 GND Ground
6 DO Serial data output
7 SK Serial clock input
1 2
3 4 5
6
7
VCC DI
TEST
CS SK
GND
DO
Figure 6
S-93L66AD0I-H7T4S
*1. Connect to GND or VCC.
Even if this pin is not connected, performance is not affected so
long as the absolute maximum rating is not exceeded.
Remark 1. Refer to the “Package drawings” for the details.
2. x: G or U
3. Please select products of environmental code = U for Sn 100%, halogen-free products.
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
Rev.7.0_00 S-93L46A/56A/66A
Seiko Instruments Inc. 5
Block Diagram
Memory array
Data register
Address
decoder
Mode decode logic
Clock pulse
monitoring circuit
Output buffer
VCC
GND
DO
DI
CS
Clock generator
Voltage detector
SK
Figure 7
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A Rev.7.0_00
Seiko Instruments Inc.
6
Instruction Sets
1. S-93L46A Table 7
Start Bit Operation
Code Address Data
Instruction
SK input clock 1 2 3 4 5 6 7 8 9 10 to 25
READ (Read data) 1 1 0 A5 A4 A3 A2 A1 A0 D15 to D0 Output*1
WRITE (Write data) 1 0 1 A5 A4 A3 A2 A1 A0 D15 to D0 Input
ERASE (Erase data) 1 1 1 A5 A4 A3 A2 A1 A0 ⎯
WRAL (Write all) 1 0 0 0 1 x x x x D15 to D0 Input
ERAL (Erase all) 1 0 0 1 0 x x x x ⎯
EWEN (Write enable) 1 0 0 1 1 x x x x ⎯
EWDS (Write disable) 1 0 0 0 0 x x x x ⎯
*1. When the 16-bit data in the specified address has been output, the data in the next address is output.
Remark x: Don’t care
2. S-93L56A Table 8
Start Bit Operation
Code Address Data
Instruction
SK input clock 1 2 3
4 5 6 7 8 9 10 11 12 to 27
READ (Read data) 1 1 0 x A6 A5 A4 A3 A2 A1 A0 D15 to D0 Output*1
WRITE (Write data) 1 0 1 x A6 A5 A4 A3 A2 A1 A0 D15 to D0 Input
ERASE (Erase data) 1 1 1 x A6 A5 A4 A3 A2 A1 A0 ⎯
WRAL (Write all) 1 0 0 0 1 x x x x x x D15 to D0 Input
ERAL (Era s e all) 1 0 0 1 0 x x x x x x ⎯
EWEN (Write enable) 1 0 0 1 1 x x x x x x ⎯
EWDS (Write disable) 1 0 0 0 0 x x x x x x ⎯
*1. When the 16-bit data in the specified address has been output, the data in the next address is output.
Remark x: Don’t care
3. S-93L66A Table 9
Instruction
SK input clock Start Bit Operation
Code Address Data
1 2 3 4 5 6 7 8 9 10 11 12 to 27
READ (Read data) 1 1 0 A7 A6 A5 A4 A3 A2 A1 A0 D15 to D0 Output*1
WRITE (Write data) 1 0 1 A7 A6 A5 A4 A3 A2 A1 A0 D15 to D0 Input
ERASE (Erase data) 1 1 1 A7 A6 A5 A4 A3 A2 A1 A0 ⎯
WRAL (Write all) 1 0 0 0 1 x x x x x x D15 to D0 Input
ERAL (Era s e all) 1 0 0 1 0 x x x x x x ⎯
EWEN (Write enable) 1 0 0 1 1 x x x x x x ⎯
EWDS (Write disable) 1 0 0 0 0 x x x x x x ⎯
*1. When the 16-bit data in the specified address has been output, the data in the next address is output.
Remark x: Don’t care
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
Rev.7.0_00 S-93L46A/56A/66A
Seiko Instruments Inc. 7
Absolute Maximum Ratings
Table 10
Item Symbol Ratings Unit
Power supply voltage VCC −0.3 to +7.0 V
Input voltage VIN −0.3 to VCC + 0.3 V
Output voltage VOUT −0.3 to VCC V
Operating ambient temperature Topr −40 to +85 °C
Storage temperature Tstg −65 to +150 °C
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
Recommended Operating Conditions
Table 11 Ta = −40°C to +85°C
Item Symbol Conditions
Min. Max.
Unit
READ, EWDS 1.6 5.5 V
WRITE, ERASE, EWEN 1.8 5.5 V
Power supply voltage VCC WRAL, ERAL 2.7 5.5 V
VCC = 4.5 V to 5.5 V 2.0 VCC V
VCC = 2.7 V to 4.5 V 0.8 × VCC V
CC V
High level input voltage VIH VCC = 1.6 V to 2.7 V 0.8 × VCC V
CC V
VCC = 4.5 V to 5.5 V 0.0 0.8 V
VCC = 2.7 V to 4.5 V 0.0 0.2 × VCC V
Low level input voltage VIL VCC = 1.6 V to 2.7 V 0.0 0.15 × VCC V
Pin Capacitance
Table 12 Ta = +25°C, f = 1.0 MHz, VCC = 5.0 V)
Item Symbol Conditions Min. Max. Unit
Input Capacitance CIN V
IN = 0 V ⎯ 8 pF
Output Capacitance COUT V
OUT = 0 V ⎯ 10 pF
Endurance
Table 13
Item Symbol Operating Ambient Temperature Min. Max. Unit
Endurance NW Ta = −40°C to +85°C 106 ⎯ Cycles / word*1
*1. For each address (Word: 16-bit)
Data Retention
Table 14
Item Symbol Operating Ambient Temperature Min. Max. Unit
Ta = +25°C 100 ⎯ year
Data Retention ⎯ Ta = −40°C to +85°C 20 ⎯ year
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A Rev.7.0_00
Seiko Instruments Inc.
8
DC Electrical Characteristics
Table 15 Ta = −40°C to +85°C
VCC = 4.5 V to 5.5 V VCC = 2.5 V to 4.5 V VCC = 1.6 V to 2.5 V
Item Symbol Conditions
Min. Max. Min. Max. Min. Max. Unit
Current consumption
(READ) ICC1 DO no load ⎯ 0.8 ⎯ 0.5 ⎯ 0.4
mA
Table 16 Ta = −40°C to +85°C
VCC = 4.5 V to 5.5 V VCC = 1.8 V to 4.5 V
Item Symbol Conditions Min. Max. Min. Max.
Unit
Current consumption
(WRITE) ICC2 DO no load ⎯ 2.0 ⎯ 1.5 mA
Table 17 Ta = −40°C to +85°C
VCC =
4.5 V to 5.5 V VCC =
2.5 V to 4.5 V VCC =
1.6 V to 2.5 V
Item Symbol Conditions
Min. Max. Min. Max. Min. Max.
Unit
Standby current
consumption ISB CS = GND, DO = Open,
Other inputs to VCC or GND ⎯ 1.5 ⎯ 1.5 ⎯ 1.5 μA
Input leakage
current ILI VIN = GND to VCC ⎯ 1.0 ⎯ 1.0 ⎯ 1.0 μA
Output leakage
current ILO V
OUT = GND to VCC ⎯ 1.0 ⎯ 1.0 ⎯ 1.0 μA
IOL = 2.1 mA ⎯ 0.4 ⎯ ⎯ ⎯ ⎯ V Low level output
voltage VOL IOL = 100 μA ⎯ 0.1 ⎯ 0.1 ⎯ 0.1 V
IOH = −400 μA 2.4 ⎯ ⎯ ⎯ ⎯ ⎯ V
IOH = −100 μA VCC − 0.3 ⎯ V
CC − 0.3 ⎯ ⎯ ⎯ V
High level
output voltage VOH IOH = −10 μA VCC − 0.2 ⎯ V
CC − 0.2 ⎯ V
CC − 0.2 ⎯ V
Write enable
latch data hold
voltage VDH Only when write disable
mode 1.5 ⎯ 1.5 ⎯ 1.5 ⎯ V
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
Rev.7.0_00 S-93L46A/56A/66A
Seiko Instruments Inc. 9
AC Electrical Characteristics
Table 18 Measurement Conditions
Input pulse voltage 0.1 × VCC to 0.9 × VCC
Output reference voltage 0.5 × VCC
Output load 100 pF
Table 19 Ta = −40°C to +85°C
VCC = 4.5 V to 5.5 V VCC = 2.5 V to 4.5 V VCC = 1.6 V to 2.5 V
Item Symbol
Min. Max. Min. Max. Min. Max. Unit
CS setup time tCSS 0.2 — 0.4 — 1.0 — μs
CS hold time tCSH 0 — 0 — 0 — μs
CS deselect time tCDS 0.2 — 0.2 — 0.4 — μs
Data setup time tDS 0.1 — 0.2 — 0.4 — μs
Data hold time tDH 0.1 — 0.2 — 0.4 — μs
Output delay time tPD — 0.4 — 0.8 — 2.0 μs
Clock frequency*1 fSK 0 2.0 0 1.0 0 0.25 MHz
SK clock time “L” *1 tSKL 0.1 — 0.25 — 1.0 — μs
SK clock time “H” *1 tSKH 0.1 — 0.25 — 1.0 — μs
Output disable time tHZ1, tHZ2 0 0.15 0 0.5 0 1.0 μs
Output enable time tSV 0 0.15 0 0.5 0 1.0 μs
*1. The clock cycle of the SK clock (frequency: fSK) is 1 / fSK μs. This clock cycle is determined by a combination of
several AC characteristics, so be aware that even if the SK clock cycle time is minimized, the clock cycle (1 / fSK)
cannot be made equal to tSKL (min.) + tSKH (min.).
Table 20
Ta = −40°C to +85°C
VCC = 1.8 to 5.5 V
Item Symbol
Min Typ. Max. Unit
Write time t PR — 4.0 8.0 ms
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A Rev.7.0_00
Seiko Instruments Inc.
10
t SKH
t CDS
t CSS
CS
Valid data
Valid data
DI
tSKL
SK
t SV t HZ2
tCSH
t HZ1
t PD tPD
tDS tDH
t DS t DH
High-Z High-Z
High-Z
DO
DO
(READ)
(VERIFY)
High-Z
*1
1 / fSK
*2
*1. Indicates high impedance.
*2. 1 / fSK is the SK clock cycle. This clock cycle is determined by a combination of several AC
characteristics, so be aware that even if the SK clock cycle time is minimized, the clock cycle (1 / fSK)
cannot be made equal to tSKL (min.) + tSKH (min.).
Figure 8 Timing Chart
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
Rev.7.0_00 S-93L46A/56A/66A
Seiko Instruments Inc. 11
Initial Shipment Data
Initial shipment data of all adresses is “FFFFh”.
Operation
All instructions are executed by inputting DI in synchronization with the rising edge of SK after CS goes high. An
instruction set is input in the order of start bit, instruction, address, and data.
Instruction input finishes when CS goes low. A low level must be input to CS between commands during t CDS. While
a low level is being input to CS, the S-93L46A/56A/66A is in standby mode, so the SK and DI inputs are invalid and no
instructions are allowed.
Start Bit
A start bit is recognized when the DI pin goes high at the rise of SK after CS goes high. After CS goes high, a start bit
is not recognized even if the SK pulse is input as long as the DI pin is low.
1. Dummy clock
SK clocks input while the DI pin is low before a start bit is input are called dummy clocks. Dummy clocks are
effective when aligning the number of instruction sets (clocks) sent by the CPU with those required for serial
memory operation. For example, when a CPU instruction set is 16 bits, the number of instruction set clocks can
be adjusted by inserting a 7-bit dummy clock for the S-93L46A and a 5-bit dummy clock for the S-93L56A/66A.
2. Start bit input failure
• When the output status of the DO pin is high during the verify period after a write operation, if a high level is
input to the DI pin at the rising edge of SK, the S-93L46A/56A/66A recognizes that a start bit has been input.
To prevent this failure, input a low level to the DI pin during the verify operation period (refer to “4. 1 Verify
operation”).
• When a 3-wire interface is configured by connecting the DI input pin and DO output pin, a period in which the
data output from the CPU and the serial memory collide may be generated, preventing successful input of the
start bit. Take the measures described in “ 3-Wire Interface (Direct Connection between DI and DO)”.
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A Rev.7.0_00
Seiko Instruments Inc.
12
3. Reading (READ)
The READ instruction reads data from a specified address.
After CS has gone high, input an instruction in the order of the start bit, read instruction, and address. Since the
last input address (A0) has been latched, the output status of the DO pin changes from high impedance (High-Z) to
low, which is held until the next rise of SK. 16-bit data starts to be output in synchronization with the next rise of
SK.
3. 1 Sequential read
After the 16-bit data at the specified address has been output, inputting SK while CS is high automatically
increments the address, and causes the 16-bit data at the next address to be output sequentially. The above
method makes it possible to read the data in the whole memory space. The last address (An yyy A
1 A0 = 1 yyy 1
1) rolls over to the top address (An yyy A
1 A0 = 0 yyy 0 0).
D
15
D15 D14
D14 D13 D
14
D13
D0
D1
D2
D
15
0 D
0
D
1
D
2 D13
A
1
A
2
A3
A
4
A
5
0 1
<1> A
0
SK
DI
CS
DO
ADRINC
High-Z
282726252423121110
9 8 7 6 5 4 3 2 1 4443 42 41 40 39
ADRINC
High-Z
Figure 9 Read Timin g (S-93L46A)
SK
D13
D
15
0 D14 D14 D13
D0
D1
D2D15 D
14
D
0
D
1
D2D
13
D
15
4140 43 44 42
2827262524
A3
A
4
A
5 A
0
A
1
A
2
DI
13
11 10 9 8 7 6 5 4 3 2 1 12
CS
DO
A
6
45
29
14
High-Z
0 1 <1>
ADRINC ADRINC
x: S-93L56A
A7: S-93L66A
High-Z
Figure 10 Read Timin g (S-93L56A, S-93L 66A)
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
Rev.7.0_00 S-93L46A/56A/66A
Seiko Instruments Inc. 13
4. Writing (WRITE, ERASE, WRAL, ERAL)
A write operation includes four write instructions: data wr ite (WRITE), data erase (ERASE), chip write (WRAL), and
chip erase (ERAL).
A write instruction (WRITE, ERASE, WRAL, ERAL) starts a wr ite operation to the memory cell when a low level is
input to CS after a specified number of clocks have been input. The SK and DI inputs are invalid during the write
period, so do not input an instruction.
Input an instruction while the output status of the DO pin is high or high impedance (High-Z).
A write operation is valid only in program enable mode (refer to “5. Write enable (EWEN) and write disable
(EWDS)”).
4. 1 Verify operation
A write operation executed by any instruction is completed within 8 ms (write time tPR: typically 4 ms), so if the
completion of the write operation is recognized, the write cycle can be minimized. A sequential operation to
confirm the status of a write operation is called a verify operation.
4. 1. 1 Operation
After the write operation has started (CS = low), the status of the write operation can be verified by
confirming the output status of the DO pin by inputting a high level to CS again. This sequence is
called a verify operation, and the period that a high level is input to the CS pin after the write operation
has started is called the verify operation period.
The relationship between the output status of the DO pin and the write operation during the verify
operation period is as follows.
• DO pin = low: Writing in progress (busy)
• DO pin = high: Writing completed (ready)
4. 1. 2 Operation example
There are two methods to perform a verify operation: Waiting for a change in the output status of the
DO pin while keeping CS high, or suspending the verify operation (CS = low) once and then performing it
again to verify the output status of the DO pin. The latter method allows the CPU to perform other
processing during the wait period, allowing an efficient system to be designed.
Caution 1. Input a low level to the DI pin during a verify operation.
2. If a high level is input to the DI pin at the rise of SK when the output status of the DO pin is
high, the S-93L46A/56A/66A latches the instruction assuming that a start bit has been input. In
this case, note that the DO pin immed i ately enters a high-imp ed an ce (High-Z) state.
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A Rev.7.0_00
Seiko Instruments Inc.
14
4. 2 Writing data (WRITE)
To write 16-bit data to a specified address, change CS to high and then input the WRITE instruction, address,
and 16-bit data following the start bit. The write operation starts when CS goes low. There is no need to set
the data to 1 before writing. If the clocks more than the specified number have been input, the clock pulse
monitoring circuit cancels the WRITE instruction. For details of the clock pulse monitoring circuit, refer to
“ Function to Protect Against Write due to Erroneous Instruction Recognition”.
HZ1
A5 A3 A2 A1 A0 D15 A4
1 3 4 5 6 7 8 9 10 2
0 1
<1>
25
t
CDS
Verify
Busy
Standby
t
SV t
Ready
t
PR High-Z
CS
SK
DI
DO High-Z
D0
Figure 11 Data Write Timin g (S-93L46A)
<1>
R eady
Busy
t
PR
t
SV
t
CDS
27 1 2 3 4 5 6 7 8 9 10 11 12
0 1 D0 A6 A5 A4 A3 A2 A1 A0 D15
CS
SK
DI
DO High-Z
Verify Standby
High-Z t
HZ1
x : S-93L56A
A7: S-93L66A
Figure 12 Data Write Timin g (S-93L56A, S-93L66A)
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
Rev.7.0_00 S-93L46A/56A/66A
Seiko Instruments Inc. 15
4. 3 Erasing data (ERASE)
To erase 16-bit data at a specified address, set all 16 bits of the data to 1, change CS to high, and then input
the ERASE instruction and address following the start bit. There is no need to input data. The data erase
operation starts when CS goes low. If the clocks have been input more than the s pecified number, the clock
pulse monitoring circuit cancels the ERASE instruction. For details of the clock pulse monitoring circuit, refer
to “ Function to Protect Against Write due to Erroneous Instruction Recognition”.
Verify
t
SV
SK
DI A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9
CS
DO
t
CDS
t
PR
Busy High-Z
Standby
High-Z t
HZ1
<1> 1 A0
Ready
1
Figure 13 Data Erase Timing (S-93L46A)
Ready
t
CDS
t
SV
High-Z
t
HZ1
t
PR
SK
DI <1> A6 A5 A4 A3 A2 A1 A0
1 2 3 4 5 6 7 8 9 10 11
CS
DO Busy
Verify Standby
High-Z
1 1
x : S-93L56A
A7: S-93L66A
Figure 14 Data Erase Timing (S-93L56A, S-93L66A)
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A Rev.7.0_00
Seiko Instruments Inc.
16
4. 4 Writing to chip (WRAL)
To write the same 16-bit data to the entire memory address space, change CS to high, and then input the
WRAL instruction, an address, and 16-bit data following the start bit. Any address can be input. The write
operation starts when CS goes low. There is no need to set the data to 1 before writing. If the clocks more
than the specified number have been input, the clock pulse monitoring circuit cancels the WRAL instruction.
For details of the clock pulse monitoring circuit, refer to “ Function to Protect Against Write due to
Erroneous Instruction Recognition”.
2 3 4 5 6 7 8 9 10 1
SK
DI
t
CDS
t
SV t
HZ1
High-Z
t
PR
CS
DO B usy
Verify Standby
High-Z
25
<1> 0 D0
R eady
0 0 1 4Xs D15
Figure 15 Chip Write Timing (S-93L46A)
Verify
2 3 4 5 6 7 8 9 10 1
SK
DI
t
CDS
t
SV t
HZ1
High-Z
t
PR
CS
DO B usy
Standby
High-Z
11 12 27
<1> 0 D0
R eady
0 0 1 6Xs D15
Figure 16 Chip Write Timing (S-93L56A, S-93L66A)
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
Rev.7.0_00 S-93L46A/56A/66A
Seiko Instruments Inc. 17
4. 5 Erasing chip (ERAL)
To erase the data of the entire memory address space, set all the data to 1, change CS to high, and then
input the ERAL instruction and an address following the start bit. Any address can be input. There is no
need to input data. The chips erase operation starts when CS goes low. When the clocks more than the
specified number have been input, the clock pulse monitoring circuit cancels the ERAL instruction. For
details of the clock pulse monitoring circuit, refer to “ Function to Protect Against Write due to Erroneous
Instruction Recognition”.
t
CDS
4Xs
0 1 0
8 7 6 5 4 3 2 1
<1> 0
t
PR
High-Z
t
HZ1
R eady
B usy
t
SV
Standby
Verify
9
SK
DI
CS
DO High-Z
Figure 17 Chip Erase Ti ming (S-93L46A)
7 6 5 4 3 2 1 9 8
CS
SK
DI
DO
t
CDS
t
SV
R eady
B us y
t
HZ1
High-Z
t
PR
11
6Xs
0 1 0
<1> 0
Standby
Verify
10
High-Z
Figure 18 Chip Erase Ti ming (S-93L56A, S-93L66A)
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A Rev.7.0_00
Seiko Instruments Inc.
18
5. Write enable (EWEN) and write disable (EWDS)
The EWEN instruction is an instruction that enables a write operation. The status in which a write operation is
enabled is called the program enable mode.
The EWDS instruction is an instruction that disables a write operation. The status in which a write operation is
disabled is called the program disable mode.
After CS goes high, input an instruction in the order of the start bit, EWEN or EWDS instruction, and address
(optional). Each mode becomes valid by inputting a low level to CS after the last address (optional) has been
input.
5 4 3 2 1 9 8 7 6
SK
DI
CS
4Xs
11 = EWEN
00 = EWDS
0
<1> 0
Standby
Figure 19 Write Enable / Disable Timin g (S-93L 46A)
DI
SK 6 5 4 3 2 1 9 8 11 10
7
CS
6Xs
11 = EWEN
00
= EWDS
0
<1> 0
Standby
Figure 20 Write Enable / Disable Timing (S-93L56A, S-93L66A)
5. 1 Recommendation for write operation disable instruction
It is recommended to implement a design that prevents an incorrect write operation when a write instruction is
erroneously recognized by executing the write operation disable instruction when executing instructions other
than write instruction, and immediately after power-on and before power off.
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
Rev.7.0_00 S-93L46A/56A/66A
Seiko Instruments Inc. 19
Write Protect Function during the Low Pow er Supply Voltage
The S-93L46A/56A/66A provides a built-in detector to detect a low power supply voltage and disable writing. When
the power supply voltage is low or at power application, the write instructions (WRITE, ERASE, WRAL, and ERAL) are
cancelled, and the write disable state (EWDS) is automatically set. The detection voltage and the release voltage are
1.4 V typ. (refer to Figure 21).
Therefore, when a write operation is performed after the power supply voltage has dropped and then risen again up to
the level at which writing is possible, a write enable instruction (EWEN) must be sent before a write instruction (WRITE,
ERASE, WRAL, or ERAL) is executed.
When the power supply voltage drops during a write operation, the data being written to an address at that time is not
guaranteed.
Power supply
Detection voltage (−V
DET
)
1.4 V typ.
Write instruction cancelled
Write disable state (EWDS) automatically set
Release voltage ( +V
DET
)
1.4 V typ.
Figure 21 Operation during Low Power Supply Voltage
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A Rev.7.0_00
Seiko Instruments Inc.
20
Function to Protect Against Write due to Erroneous Instruction Recognition
The S-93L46A/56A/66A provides a built-in clock pulse monitoring circuit which is used to prevent an erroneous write
operation by canceling write instructions (WRITE, ERASE, WRAL, and ERAL) recognized erroneously due to an
erroneous clock count caused by the application of noise pulses or double counting of clocks.
Instructions are cancelled if a clock pulse more or less than specified number decided by each write operation (WRITE,
ERASE, WRAL, or ERAL) is detected.
<Example> Erroneous recognition of program disable instruction (EWDS) as erase instruction (ERASE)
1 3 4 5 6 7 2 8 9
CS
SK
DI
Input EWDS instruction
Erroneous recognition as
ERASE instruction due to
noise pulse
1 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 1 0
Noise pulse
Example of S-93L46A
1
In products that do not incl ude a clock pulse monitoring circuit, FF FF is mistakenly written
on address 00h. H owever the S-93L46A detects the overcount and cancels the instruction
without performing a write operation.
Figure 22 Example of Clock Pulse Monitoring Circuit Operation
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
Rev.7.0_00 S-93L46A/56A/66A
Seiko Instruments Inc. 21
3-Wire Interface (Direct Connection between DI and DO)
There are two types of serial interface configurations: a 4-wire interface configured using the CS, SK, DI, and DO pins,
and a 3-wire interface that connects the DI input pin and DO output pin.
When the 3-wire interface is employed, a period in which the data output from the CPU and the data output from the
serial memory collide may occur, causing a malfunction. To prevent such a malfunction, connect the DI and DO pins
of the S-93L46A/56A/66A via a resistor (10 kΩ to 100 kΩ) so that the data output from the CPU takes precedence in
being input to the DI pin (refer to Figure 23).
CPU
DI
SIO
DO
S-93L46A/56A/66A
R: 10 k
Ω
to 100 k
Ω
Figure 23 Connectio n of 3-Wire Interface
Input Pin and Output Pin
1. Connection of input pins
All the input pins of the S-93L46A/56A/66A employ a CMOS structure, so design the equipment so that high
impedance will not be input while the S-93L46A/56A/66A is operating. Especially, deselect the CS input (a low
level) when turning on / off power and during standby. When the CS pin is deselected (a low level), incorrect data
writing will not occur. Connect the CS pin to GND via a resistor (10 k Ω to 100 kΩ pull-down resistor). To prevent
malfunction, it is recommended to use equivalent pull-down resistors for pins other than the CS pin.
2. Equivalent circuit of input pin and output pin
The following shows the equivalent circuits of input pins of the S-93L46A/56A/66A. None of the input pins
incorporate pull-up and pull-down elements, so special care must be taken when designing to prevent a floating
status.
Output pins are high-level / low-level / high-impedance tri-state outputs. The TEST pin is disconnected from the
internal circuit by a switching transistor during normal operation. As long as the absolute maximum rating is
satisfied, the TEST pin and internal circuit will never be connected.
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A Rev.7.0_00
Seiko Instruments Inc.
22
2. 1 Input pin
CS
Figure 24 CS Pin
SK, DI
Figure 25 SK, DI Pin
TEST
Figure 26 TEST Pin
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
Rev.7.0_00 S-93L46A/56A/66A
Seiko Instruments Inc. 23
2. 2 Output pin
DO
VCC
Figure 27 DO Pin
3. Input pin noise elimination time
The S-93L46A/56A/66A include a built-in low-pass filter to eliminate noise at the SK, DI, and CS pins. This means
that if the supply voltage is 5.0 V (at room temperature), noise with a pulse width of 20 ns or less can be eliminated.
Note, therefore, the noise with a pulse width of more than 20 ns will be recognized as a pulse if the voltage exceeds
VIH / VIL.
Precautions
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
• SII claims no responsibility for any disputes arising out of or in connection with any infringement by products
including this IC of patents owned by a third party.
Precautions for WLP package
• The side of device silicon substrate is exposed to the marking side of device package. Since this portion has lower
strength against the mechanical stress than the standard plastic package, chip, crack, etc should be careful of the
handing of a package enough. Moreover, the exposed side of silicon has electrical potential of device substrate, and
needs to be kept out of contact with the external potential.
• In this package, the overcoat of the resin of translucence is carried out on the side of device area. Keep it mind that
it may affect the characteristic of a device when exposed a device in the bottom of a high light source.
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A Rev.7.0_00
Seiko Instruments Inc.
24
Characteristics (Typical Data)
1. DC Characteristics
1. 1 Current consumption (READ) ICC1
vs. ambient temperature Ta 1. 2 Current consumption (READ) ICC1
vs. ambient temperature Ta
Ta (°C)
0.4
0.2
VCC = 5.5 V
fSK = 2 MHz
DATA = 0101
0 −40 0 85
ICC1
(mA)
Ta
(
°C
)
0.4
0.2
VCC = 3.3 V
fSK = 500 kHz
DATA = 0101
0−40 085
ICC1
(mA)
1. 3 Current consumption (READ) ICC1
vs. ambient temperature Ta 1. 4 Current consumption (READ) ICC1
vs. power supply voltage VCC
ICC1
(mA)
Ta (°C)
0.4
0.2
VCC = 1.8 V
fSK = 10 kHz
DATA = 0101
0 −40 0 85
1 MHz
∼
500 kHz
ICC1
(mA)
0.4
0.2
0 2 3 4 5 6 7
Ta
=
25°C
fSK = 1 MHz, 500 kHz
DATA
=
0101
VCC (V)
1. 5 Current consumption (READ) ICC1
vs. power supply voltage VCC 1. 6 Current consumption (READ) ICC1
vs. Clock frequency fSK
100 kHz
10 kHz
ICC1
(mA)
0.4
0.2
0 2 3 4 5 6 7
VCC (V)
Ta = 25°C
fSK = 100 kHz, 10 kHz
DATA = 0101
ICC1
(
mA
)
0.4
0.2
0
VCC = 5.0 V
Ta = 25°C
1 M 2M 10M 10 k 100 k
f
SK
(
Hz
)
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
Rev.7.0_00 S-93L46A/56A/66A
Seiko Instruments Inc. 25
1. 7 Current consumption (WRITE) ICC2
vs. ambient temperature Ta 1. 8 Current consumption (WRITE) ICC2
vs. ambient temperature Ta
Ta (°C)
1.0
0.5
VCC = 5.5 V
0 −40 0 85
ICC2
(mA)
ICC2
(mA)
Ta
(
°C
)
1.0
0.5
VCC = 3.3 V
0−40 085
1. 9 Current consumption (WRITE) ICC2
vs. ambient temperature Ta 1. 10 Current consumption (WRITE) ICC2
vs. power supply voltage VCC
Ta (°C)
1.0
0.5
VCC = 2.7 V
0 −40 0 85
ICC2
(mA)
1.0
0.5
0 2 3 4 5 6 7
Ta
=
25°C
VCC (V)
ICC2
(mA)
1. 11 Current consumption in standby mode ISB
vs. ambient temperature Ta 1. 12 Current consumption in standby mode ISB
vs. power supply voltage VCC
Ta (°C)
1.0
0.5
VCC = 5.5 V
CS = GND
0 −40 0 85
ISB
(μA)
ISB
(μA)
1.0
0.5
02 3 4 5 6 7
Ta = 25°C
CS = GND
VCC
(
V
)
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A Rev.7.0_00
Seiko Instruments Inc.
26
1. 13 Input leakage current ILI
vs. ambient temperature Ta 1. 14 Input leakage current ILI
vs. ambient temperature Ta
1.0
0.5
VCC = 5.5 V
CS, SK, DI,
TEST = 0 V
0 −40 0 85
ILI
(μA)
Ta (°C)
Ta (°C)
1.0
0.5
0
−
40 0 85
VCC
=
5.5 V
CS, SK, DI,
TEST
=
5.5 V
ILI
(μA)
1. 15 Output leakage current ILO
vs. ambient temperature Ta 1. 16 Output leakage current ILO
vs. ambient temperature Ta
Ta (°C)
1.0
0.5
VCC = 5.5 V
DO = 0 V
0 −40 0 85
ILO
(μA)
Ta
(
°C
)
1.0
0.5
VCC = 5.5 V
DO = 5.5 V
0
−
40 085
ILO
(μA)
1. 17 High-level output voltage VOH
vs. ambient temperature Ta 1. 18 High-level output voltage VOH
vs. ambient temperature Ta
Ta
(
°C
)
4.6
4.4
VCC = 4.5 V
IOH = −400 μA
−40 0 85
VOH
(V)
4.2
Ta (°C)
2.7
2.6
VCC
=
2.7 V
IOH
=
−
100
μ
A
−
40 085
VOH
(V)
2.5
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
Rev.7.0_00 S-93L46A/56A/66A
Seiko Instruments Inc. 27
1. 19 High-level output voltage VOH
vs. ambient temperature Ta 1. 20 High-level output voltage VOH
vs. ambient temperature Ta
Ta (°C)
2.5
2.4
VCC = 2.5 V
IOH = −100 μA
−40 0 85
VOH
(V)
2.3
Ta (°C)
1.9
1.8
VCC = 1.8 V
IOH = −10 μA
−
40 0 85
VOH
(V)
1.7
1. 21 Low-level output voltage VOL
vs. ambient temperature Ta 1. 22 L o w-level output voltage VOL
vs. ambient temperature Ta
Ta (°C)
0.3
0.2
VCC = 4.5 V
IOL = 2.1 mA
−40 0 85
V
OL
(V)
0.1
Ta (°C)
0.03
0.02
VCC
=
1.8 V
IOL
=
100
μ
A
−
40 085
VOL
(V)
0.01
1. 23 High-level output current IOH
vs. ambient temperature Ta 1. 24 High-level output current IOH
vs. ambient temperature Ta
Ta (°C)
−20.0
−10.0
VCC = 4.5 V
VOH = 2.4 V
0 −40 0 85
IOH
(mA)
Ta
(
°C
)
−
2
−
1
VCC = 2.7 V
VOH = 2.4 V
0
−
40 085
IOH
(mA)
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A Rev.7.0_00
Seiko Instruments Inc.
28
1. 25 High-level output current IOH
vs. ambient temperature Ta 1. 26 High-level output current IOH
vs. ambient temperature Ta
Ta (°C)
−2
−1
VCC = 2.5 V
VOH = 2.2 V
0 −40 0 85
IOH
(mA)
Ta (°C)
−
1.0
−
0.5
VCC
=
1.8 V
VOH
=
1.6 V
0
−
40 085
IOH
(mA)
1. 27 Low-level output current IOL
vs. ambient temperature Ta 1. 28 Low-level output current IOL
vs. ambient temperature Ta
Ta
(
°C
)
20
10
VCC = 4.5 V
VOL = 0.4 V
0
−40 0 85
IOL
(mA)
Ta (°C)
1.0
0.5
VCC = 1.8 V
VOL = 0.1 V
0−40 085
IOL
(mA)
1. 29 Input inverted voltage VINV
vs. power supply voltage VCC 1. 30 Input inverted voltage VINV
vs. ambient temperature Ta
3.0
1.5
0 1 2 3 4 5 6
Ta = 25°C
CS, SK, DI
VCC (V)
VINV
(V)
7
Ta (°C)
3.0
2.0
VCC
=
5.0 V
CS, SK, DI
0
−
40 085
VINV
(
V
)
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
Rev.7.0_00 S-93L46A/56A/66A
Seiko Instruments Inc. 29
1. 31 Low supply voltage detection voltage −VDET
vs. ambient temperature Ta 1. 32 Low supply voltage release voltage +VDET
vs. ambient temperature Ta
Ta (°C)
2.0
1.0
0 -40 0 85
-VDET
(V)
Ta (°C)
2.0
1.0
0-40 085
+VDET
(V)
2. AC Characteristics
2. 1 Maximum operating frequency fMAX.
vs. power supply voltage VCC 2. 2 Write time tPR
vs. power supply voltage VCC
10k
2 3 4 5
Ta = 25°C
VCC (V)
f
MAX.
(Hz)
1
100k
1M
2M
4
2
234 56 7
Ta
=
25°C
VCC (V)
tPR
(ms)
1
2. 3 Write time tPR
vs. ambient temperature Ta 2. 4 Write time tPR
vs. ambient temperature Ta
Ta (°C)
6
4
VCC = 5.0 V
−40 0 85
2
t
PR
(ms)
Ta
(
°C
)
6
4
VCC = 3.0 V
−
40 085
2
t
PR
(ms)
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A Rev.7.0_00
Seiko Instruments Inc.
30
2. 5 Write time tPR
vs. ambient temperature Ta 2. 6 Data output delay time tPD
vs. ambient temperature Ta
Ta (°C)
6
4
VCC = 2.7 V
−40 0 85
2
t
PR
(ms)
Ta (°C)
0.3
0.2
VCC
=
4.5 V
−
40 0 85
0.1
tPD
(μs)
2. 7 Data output delay time tPD
vs. ambient temperature Ta 2. 8 Data output delay time tPD
vs. ambient temperature Ta
Ta (°C)
0.6
0.4
VCC = 2.7 V
−40 0 85
0.2
tPD
(μs)
Ta (°C)
1.5
1.0
VCC
=
1.8 V
−
40 0 85
0.5
tPD
(μs)
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
Rev.7.0_00 S-93L46A/56A/66A
Seiko Instruments Inc. 31
Product Name Structure
1. Product name
1. 1 8-Pin SOP (JEDEC), 8-Pin TSSOP, SNT-8A
Package name (abbreviation) and IC packing specifications
J8T1: 8-Pin SO P (JEDEC), Tape
T8T1: 8-Pin TSSOP, Tape
I8T1: SNT-8A, Tape
Fixed
Pin configurations
D: 8-Pin SOP (JEDEC)
8-Pin TSSOP
SNT-8A
R: 8-Pin SO P (JEDEC) (Rotated)
Product name
S-93L46A: 1 K-bit
S-93L56A: 2 K-bit
S-93L66A: 4 K-bit
S-93LxxA x 0I - xxxx x
Environmental code
U: Lead-free (Sn 100%), halogen-free
G: Lead-free (for details, please contact our sales office)
1. 2 TMSOP-8
Package name (abbreviation) and IC packing specifications
K8T3: TMSOP-8, Tape
Fixed
Product name
S-93L46A: 1 K-bit
S-93L56A: 2 K-bit
S-93L66A: 4 K-bit
S-93LxxA D0I - K8T3 U
Environmental code
U: Lead-free
(
Sn 100%
)
, halo
g
en-free
1. 3 WLP-7D
S-93L66A D0I - H7T4 S
Environmental code
S: Lead-free, halogen-free
Package name (abbreviation) and IC packing specifications
H7T4: WLP-7D, Tape
Fixed
Product name
S-93L66A: 4 K-bit
LOW VOLTAGE OPERATION 3-WIRE SERIAL E2PROM
S-93L46A/56A/66A Rev.7.0_00
Seiko Instruments Inc.
32
2. Packages
Drawing code
Package name Package Tape Reel Land
Environmental code = G FJ008-A-P-SD FJ008-D-C-SD FJ008-D-R-SD
8-Pin SOP
(JEDEC) Environmental code = U FJ008-A-P-SD FJ008-D-C-SD FJ008-D-R-S1 ⎯
Environmental code = G FT008-A-P-SD FT008-E-C-SD FT008-E-R-SD
8-Pin
TSSOP Environmental code = U FT 008-A-P-SD FT008-E-C-SD FT008-E-R-S1 ⎯
TMSOP-8 FM008-A-P-SD FM008-A-C-SD FM008-A-R-SD ⎯
SNT-8A PH008-A-P-SD PH008-A-C-SD PH008-A-R-SD PH008-A-L-SD
WLP-7D HD007-C-P-SD HD007-C-C-SD
HD007-A-R-SD
⎯
No. FJ008-A-P-SD-2.1
No.
TITLE
SCALE
UNIT mm
SOP8J-D-PKG Dimensions
Seiko Instruments Inc.
FJ008-A-P-SD-2.1
0.4±0.05
1.27
0.20±0.05
5.02±0.2
14
85
No.
TITLE
SCALE
UNIT mm
5
8
1
4
ø2.0±0.05
ø1.55±0.05 0.3±0.05
2.1±0.1
8.0±0.1
5°max.
6.7±0.1
2.0±0.05
Seiko Instruments Inc.
Feed direction
4.0±0.1(10 pitches:40.0±0.2)
SOP8J-D-Carrier Tape
No. FJ008-D-C-SD-1.1
FJ008-D-C-SD-1.1
No.
TITLE
SCALE
UNIT mm
QTY. 2,000
2±0.5
13.5±0.5
60°
2±0.5
ø13±0.2
ø21±0.8
Seiko Instruments Inc.
Enlarged drawing in the central part
SOP8J-D-Reel
No. FJ008-D-R-SD-1.1
FJ008-D-R-SD-1.1
No.
TITLE
SCALE
UNIT mm
QTY. 4,000
2±0.5
13.5±0.5
60°
2±0.5
ø13±0.2
ø21±0.8
Seiko Instruments Inc.
Enlarged drawing in the central part
SOP8J-D-Reel
No. FJ008-D-R-S1-1.0
FJ008-D-R-S1-1.0
No.
TITLE
SCALE
UNIT
Seiko Instruments Inc.
TSSOP8-E-PKG Dimensions
No. FT008-A-P-SD-1.1
FT008-A-P-SD-1.1
0.17±0.05
3.00 +0.3
-0.2
0.65
0.2±0.1
14
5
8
mm
No.
TITLE
SCALE
UNIT
Seiko Instruments Inc.
ø1.55±0.05
2.0±0.05
8.0±0.1 ø1.55 +0.1
-0.05
(4.4)
0.3±0.05
1
45
8
4.0±0.1
Feed direction
TSSOP8-E-Carrier Tape
No. FT008-E-C-SD-1.0
FT008-E-C-SD-1.0
+0.4
-0.2
6.6
mm
No.
TITLE
SCALE
UNIT
Seiko Instruments Inc.
Enlarged drawing in the central part
No. FT008-E-R-SD-1.0
2±0.5
ø13±0.5
ø21±0.8
13.4±1.0
17.5±1.0
3,000
QTY.
TSSOP8-E-Reel
FT008-E-R-SD-1.0
mm
No.
TITLE
SCALE
UNIT
Seiko Instruments Inc.
Enlarged drawing in the central part
2±0.5
ø13±0.5
ø21±0.8
13.4±1.0
17.5±1.0
4,000
QTY.
TSSOP8-E-Reel
FT008-E-R-S1-1.0
mm
No. FT008-E-R-S1-1.0
No.
TITLE
SCALE
UNIT mm
Seiko Instruments Inc.
2.90±0.2
85
0.2±0.1
0.65±0.1
0.13±0.1
14
TMSOP8-A-PKG Dimensions
No. FM008-A-P-SD-1.0
FM008-A-P-SD-1.0
No.
TITLE
SCALE
UNIT mm
Seiko Instruments Inc.
0.30±0.05
1.00±0.1
1.05±0.05
1.55
2.00±0.05
4.00±0.1
3.25±0.05
4.00±0.1
1
4
58
TMSOP8-A-Carrier Tape
Feed direction
No. FM008-A-C-SD-1.0
FM008-A-C-SD-1.0
+0.1
-0
No.
TITLE
SCALE
UNIT mm
Seiko Instruments Inc.
16.5max.
13.0±0.3
QTY. 4,000
(60°)
(60°)
13±0.2
Enlarged drawing in the central part
TMSOP8-A-Reel
No. FM008-A-R-SD-1.0
FM008-A-R-SD-1.0
1.97±0.03
0.2±0.05
0.48±0.02
0.08
No.
TITLE
SCALE
UNIT mm
Seiko Instruments Inc.
SNT-8A-A-PKG Dimensions
PH008-A-P-SD-2.0
No. PH008-A-P-SD-2.0
0.5
+0.05
-0.02
123 4
56
78
No.
TITLE
SCALE
UNIT mm
Seiko Instruments Inc.
PH008-A-C-SD-1.0
SNT-8A-A-Carrier Tape
No. PH008-A-C-SD-1.0
Feed direction
4.0±0.1
2.0±0.05
4.0±0.1
ø1.5 +0.1
-0
ø0.5±0.1
2.25±0.05
0.65±0.05
0.25±0.05
2134
7865
5°
12.5max.
9.0±0.3
ø13±0.2
(60°) (60°)
Enlarged drawing in the central part
QTY.
PH008-A-R-SD-1.0
No.
TITLE
SCALE
UNIT mm
Seiko Instruments Inc.
SNT-8A-A-Reel
No. PH008-A-R-SD-1.0
5,000
No.
TITLE
SCALE
UNIT mm
SNT-8A-A-Land Recommendation
Seiko Instruments Inc.
PH008-A-L-SD-3.0
0.3
0.20.3
0.20.3
0.52
2.01
0.52
No. PH008-A-L-SD-3.0
0.3 0.2
Caution Making the wire pattern under the package is possible. However, note that the package
may be upraised due to the thickness made by the silk screen printing and of a solder
resist on the pattern because this package does not have the standoff.
1.50±0.03
0.04 S
S
ø0.25±0.02 0.08±0.02
0.33max.
1.28±0.03
No.
TITLE
SCALE
UNIT
No. HD007-C-P-SD-2.0
WLP-7D-C-PKG Dimensions
HD007-C-P-SD-2.0
Seiko Instruments Inc.
Pin No.
1
2
3
4
5
6
CS
SK
DI
DO
GND
TEST
Pin name
7
VCC
4
2
1
7
6
5
7-(ø0.25)
ø0.05 MSAB
0.50.5
B
A
0.5
3
0.43
0.43
(S-93L66AD)
No.
TITLE
SCALE
UNIT mm
Seiko Instruments Inc.
2.0±0.05
4.0±0.1
ø1.5 +0.1
-0
ø0.5±0.05
2.0±0.1
4.0±0.1
No. HD007-C-C-SD-1.0
WLP-7D-C-Carrier Tape
HD007-C-C-SD-1.0
0.55±0.05
0.18±0.05
0.7
1.66
0.5
1.36±0.05
Feed direction
3
5
47
6
1
(S-93L66AD)
No.
TITLE
SCALE
UNIT mm
Seiko Instruments Inc.
HD007-A-R-SD-1.1
WLP-7D-C-Reel
QTY. 3,000
12.5max.
9.0±0.3
ø13±0.2
Enlarged drawing in the central part
(S-93L66AD)
No. HD007-A-R-SD-1.1
www.sii-ic.com
• The information described herein is subject to change without notice.
• Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein
whose related industrial properties, patents, or other rights belong to third parties. The application circuit
examples explain typical applications of the products, and do not guarantee the success of any specific
mass-production design.
• When the products described herein are regulated products subject to the Wassenaar Arrangement or other
agreements, they may not be exported without authorization from the approp riate government al authority.
• Use of the information described herein for other purposes and/or reproduction or copying without the
express permissi on of Seiko Instruments Inc. is strictly prohibited.
• The products described herein cannot be used as part of any device or equipment affecting the human
body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus
installed in airplanes and other vehicle s, without prior written permission of Seiko Instruments Inc.
• The products described herein are not designed to be radiation -p roof.
• Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the
failure or malfunction of semiconductor products may occur. The user of these products should therefore
give thorough consideration to safety design, including redundancy, fire-prevention measures, and
malfunction prevention, to prevent any accidents, fires, or comm unity damage that may ensue.
