LTC4307
1
4307f
Low Offset Hot Swappable
2-Wire Bus Buffer with Stuck
Bus Recovery
The LTC®4307 hot swappable, 2-wire bus buffer allows
I/O card insertion into a live backplane without corrup-
tion of the data and clock busses. The LTC4307 provides
bidirectional buffering, keeping the backplane and card
capacitances isolated. Low offset and high VOL tolerance
allows multiple devices to be cascaded on the clock and
data busses. If SDAOUT or SCLOUT are low for 30ms, the
LTC4307 will automatically break the bus connection. At
this time the LTC4307 automatically generates up to 16
clock pulses on SCLOUT in an attempt to free the bus. A
connection will resume if the stuck bus is cleared.
During insertion, the SDA and SCL lines are pre-charged
to 1V to minimize bus disturbances. When driven high,
the ENABLE input allows the LTC4307 to connect after a
stop bit or bus idle. Driving ENABLE low breaks the con-
nection between SDAIN and SDAOUT, SCLIN and SCLOUT.
READY is an open-drain output which indicates that the
backplane and card sides are connected.
■ Live Board Insertion
■ Servers
■ Capacitance Buffer/Bus Extender
■ RAID Systems
■ ATCA
■ Bidirectional Buffer with Stuck Bus Recovery
■ 60mV Buffer Offset Independent of Load
■ 30ms Stuck Bus Timeout
■ Compatible with Non-Compliant VOL I2C Devices
■ Prevents SDA and SCL Corruption During Live
Board Insertion and Removal from Backplane
■ ±5kV Human Body Model ESD Protection
■ Isolates Input SDA and SCL Line from Output
■ Compatible with I2CTM, I2C Fast Mode and SMBus
■ READY Open-Drain Output
■ 1V Precharge on All SDA and SCL Lines
■ High Impedance SDA, SCL Pins for VCC = 0V
■ Small 8-Lead (3mm × 3mm) DFN and 8-Lead MSOP
Packages
APPLICATIO S
U
FEATURES DESCRIPTIO
U
TYPICAL APPLICATIO
U
VCC
3.3V
ENABLE
10k
LTC4307
SCLIN
SDAIN
SCLOUT
SDAOUT
READY
GND
BACKPLANE
CONNECTOR
10k 2.7k 10k 10k 0.01μF
CARD_SCL
CARD_SDA
10k
100k
3.3V
VCC
ENABLE
LTC4307
SCLIN
SDAIN
SCLOUT
SDAOUT
READY
GND
CARD
10k
4307 TA01a
3.3V
2.7k
MICRO-
CONTROLLER
CARD
CONNECTOR
0.01μF
100ns/DIV
00 100 200 300 400 600500
200mV/DIV
200
400
600
800
1000
4307 TA01b
SDAOUT
SDAIN
LOW
OFFSET
Rising Edge from Asserted Low
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 7032051, 6356140, 6650174
LTC4307
2
4307f
VCC to GND ................................................. – 0.3V to 6V
SDAIN, SCLIN, SDAOUT, SCLOUT,
READY, ENABLE .......................................... –0.3V to 6V
Maximum Sink Current (SDAIN, SCLIN, SDAOUT,
SCLOUT, READY) .............................................. 50mA
Operating Temperature Range
LTC4307C ................................................ 0°C to 70°C
LTC4307I .............................................– 40°C to 85°C
ORDER PART
NUMBER
DD PART*
MARKING
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 9) CONNECTION TO GND IS OPTIONAL
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
LBTW
LBTW
LTC4307CDD
LTC4307IDD
(Notes 1, 7)
The
● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VCC = 3.3V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Supply
VCC Positive Supply Voltage ●2.3 5.5 V
ICC Supply Current VCC = 5.5V, VSCLOUT = VSDAOUT = 0V (Note 6) ●811 mA
ISD Shutdown Supply Current VCC = 5.5V, ENABLE = GND, SDA, SCL = 5.5V ●900 1200 μA
VPRE Precharge Voltage SDA, SCL Floating ●0.8 1 1.2 V
tIDLE Bus Idle Time ●55 95 175 μs
VTHR_ENABLE ENABLE Threshold 0.8 1.4 2 V
IENABLE ENABLE Input Current ENABLE from 0V to VCC ●0.1 ±5 μA
tPLH_EN ENABLE Delay Off-On VCC = 3.3V (Figure 1) 95 μs
tPHL_EN ENABLE Delay On-Off VCC = 3.3V (Note 3) (Figure 1) 10 ns
tPLH_READY READY Delay Off-On VCC = 3.3V (Note 3) (Figure 1) 10 ns
tPHL_READY READY Delay On-Off VCC = 3.3V (Note 3) (Figure 1) 10 ns
VOL_READY READY Output Low Voltage IPULLUP = 3mA, VCC = 2.3V ●0.4 V
IOFF_READY READY Off Leakage Current VCC = READY = 5.5V ●0.1 ±5 μA
ELECTRICAL CHARACTERISTICS
ABSOLUTE AXI U RATI GS
W
WW
U
PACKAGE/ORDER I FOR ATIO
UUW
Storage Temperature Range
DFN ....................................................– 65°C to 125°C
MSOP ................................................– 65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MSOP ............................................................... 300°C
TOP VIEW
9
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
5
6
7
8
4
3
2
1ENABLE
SCLOUT
SCLIN
GND
VCC
SDAOUT
SDAIN
READY
ORDER PART
NUMBER
MS8 PART*
MARKING
LTC4307CMS8
LTC4307IMS8
LTBTV
LTBTV
1
2
3
4
ENABLE
SCLOUT
SCLIN
GND
8
7
6
5
VCC
SDAOUT
SDAIN
READY
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 200°C/W
LTC4307
3
4307f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Propagation Delay and Rise-Time Accelerators
tPHL SDA/SCL Propagation Delay High to Low CLOAD = 50pF, 2.7k to VCC on SDA, SCL,
VCC = 3.3V (Notes 2, 3) (Figure 1)
70 ns
tPLH SDA/SCL Propagation Delay Low to High CLOAD = 50pF, 2.7k to VCC on SDA, SCL,
VCC = 3.3V (Notes 2, 3) (Figure 1)
10 ns
tRISE SDA/SCL Transition Time Low to High CLOAD = 100pF, 10k to VCC on SDA, SCL, VCC
= 3.3V (See Notes 3, 4) (Figure 1)
30 300 ns
tFALL SDA/SCL Transition Time High to Low CLOAD = 100pF, 10k to VCC on SDA, SCL, VCC
= 3.3V (See Notes 3, 4) (Figure 1)
30 300 ns
IPULLUPAC Transient Boosted Pull-Up Current Positive Transition on SDA, SCL, VCC = 3.3V
(Note 5)
58 mA
Input-Output Connection
VOS Input-Output Offset Voltage 2.7k to VCC on SDA, SCL, VCC = 3.3V,
Driven SDA/SCL = 0.2V
●20 60 100 mV
VTHR SDA, SCL Logic Input Threshold Voltage Rising Edge 0.45VCC 0.55VCC 0.65VCC V
VHYS SDA, SCL Logic Input Threshold Voltage
Hysteresis
(Note 3) 50 mV
CIN Digital Input Capacitance SDAIN, SDAOUT,
SCLIN, SCLOUT
(Note 3) 10 pF
ILEAK Input Leakage Current SDA, SCL, Pins ●±5 μA
VOL Output Low Voltage SDA, SCL Pins, ISINK = 4mA,
Driven SDA/SCL = 0.2V, VCC = 2.7V
●0 0.4 V
2.7k to VCC on SDA, SCL, VCC = 3.3V,
Driven SDA/SCL = 0.1V
●120 160 205 mV
VILMAX Buffer Input Logic Low Voltage VCC = 3.3V ●1.2 V
Bus Stuck Low Timeout
tTIMEOUT Bus Stuck Low Timer VCC = 3.3V, SDAOUT, SCLOUT = 0V ●25 30 35 ms
Timing Characteristics
fI2C,MAX I2C Maximum Operating Frequency (Note 3) 400 600 kHz
tBUF Bus Free Time Between Stop and Start
Condition
(Note 3) 1.3 μs
tHD,STA Hold Time After (Repeated) Start Condition (Note 3) 100 ns
tSU,STA Repeated Start Condition Set-Up Time (Note 3) 0 ns
tSU,STO Stop Condition Set-Up Time (Note 3) 0 ns
tHD,DATI Data Hold Time Input (Note 3) 0 ns
tSU,DAT Data Set-Up Time (Note 3) 100 ns
The ● denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. VCC = 3.3V, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: See “Propagation Delays” in the Operations section for a
discussion of tPHL and tPLH as a function of pull-up resistance and bus
capacitance.
Note 3: Determined by design, not tested in production.
Note 4: Measure points are 0.3 • VCC and 0.7 • VCC.
Note 5: IPULLUP varies with temperature and VCC voltage as shown in the
Typical Performance Characteristics section.
Note 6: ICC test performed with connection circuitry active.
Note 7: All currents into pins are positive; all voltages are referenced to
GND unless otherwise specifi ed.
LTC4307
4
4307f
ENABLE, CONNECT, READY Timing
tPLH_EN
ENABLE
CONNECT
READY
tPLH_READY tPHL_READY
tPHL_EN
4307 TD01
Rising and Falling Propagation Delay and Rise and Fall Times for SDAIN, SDAOUT and SCLIN, SCLOUT
tPLH
SDAIN/SCLIN
SDAOUT/SCLOUT
tPHL tRISE tFALL
tRISE tFALL
4307 TD02
Figure 1. Timing Diagrams
TIMING DIAGRAMS
LTC4307
5
4307f
ICC vs Temperature IPULLUPAC vs Temperature ISD vs Temperature
Input-Output High to Low
Propagation Delay vs COUT
C
onnec
ti
on
Ci
rcu
it
ry
V
OUT –
V
IN
(
V
OS)
TYPICAL PERFOR A CE CHARACTERISTICS
UW
TA = 25°C, VCC = 3.3V, unless otherwise indicated.
Bus Stuck Low Timeout vs VCC
TEMPERATURE (°C)
–50
ICC (mA)
6.8
7.1
7.4
25 75
4307 G01
6.5
6.2
5.9 –25 0 50
7.7
8.0
8.3
100
VCC = 5.5V
VCC = 3.3V
VCC = 2.3V
TEMPERATURE (°C)
–50
0
IPULLUPAC (mA)
4
8
12
–25 025 50
4307 G02
75
16
20
100
VCC = 5.5V
VCC = 3.3V
TEMPERATURE (°C)
–50
700
ISD (μA)
750
800
850
–25 025 50
4307 G02
75
900
950
100
VCC = 5.5V
VCC = 3.3V
VCC = 2.3V
TEMPERATURE (°C)
–50
0
tPHL (ns)
20
40
60
80
100
–25 02550
4307 G04
75 100
CIN = COUT = 50pF
RPULLUPIN = RPULLUPOUT = 10k
VCC = 5.5V
VCC = 3.3V
VCC = 2.3V
VCC (V)
2
tTIMEOUT (ms)
26
28
30
32
344.5
4307 G06
34
2.5 3.5 55.5
Input-Output High to Low
Propagation Delay vs Temperature
COUT (pF)
0
tPHL (ns)
130
120
110
100
90
80
70
60
800
4307 G07
200 400 600 1000
CIN = 50pF
RPULLUPIN = RPULLUPOUT = 10k
VCC = 5.5V
VCC = 3.3V
RPULLUP (kΩ)
1
45
55
VOUT – VIN (mV)
65
75
85
2345
4307 G05
678910
LTC4307
6
4307f
PI FU CTIO S
UUU
ENABLE (Pin 1): Connection Enable Input. This is a 1.4V
digital threshold input pin. For normal operation pull or tie
ENABLE high. Driving ENABLE below 0.8V isolates SDAIN
from SDAOUT, SCLIN from SCLOUT and asserts READY
low. A rising edge on ENABLE after a fault has occurred
forces a connection between SDAIN, SDAOUT and SCLIN,
SCLOUT. Connect to VCC if unused.
SCLOUT (Pin 2): Serial Clock Output. Connect this pin to
an SCL bus segment where stuck bus recovery is needed.
A pull-up resistor should be connected between this pin
and VCC.
SCLIN (Pin 3): Serial Clock Input. Connect this pin to an
SCL bus segment that needs to be isolated from stuck
bus problems. A pull-up resistor should be connected
between this pin and VCC.
GND (Pin 4): Device Ground. Connect this pin to a ground
plane for best results.
READY (Pin 5): Connection READY Status Output. The
READY pin is an open-drain N-channel MOSFET output that
pulls low when ENABLE is low, or when the start-up and
connection sequence described in the Operation section
has not been completed. READY also goes low when the
LTC4307 disconnects the inputs from the outputs due to
the bus being stuck low for at least 30ms. READY goes high
when ENABLE is high and a connection is made. Connect
a pull-up resistor, typically 10k, from this pin to VCC to
provide the pull-up. This pin can be fl oated if unused.
SDAIN (Pin 6): Serial Data Input. Connect this pin to an
SDA bus segment that needs to be isolated from stuck
bus problems. A pull-up resistor should be connected
between this pin and VCC.
SDAOUT (Pin 7): Serial Data Output. Connect this pin
to the SDA bus segment where stuck bus recovery is
needed. A pull-up resistor should be connected between
this pin and VCC.
VCC (Pin 8): Supply Voltage Input. Place a bypass capacitor
of at least 0.01μF close to VCC for best results.
Exposed Pad (Pin 9, DFN Package Only): Exposed Pad
may be left open or connected to device ground.
LTC4307
7
4307f
BLOCK DIAGRA
W
100k
PRECHARGE
PC_CONNECT
100k
0.55VCC
0.55VCC
1.4V
UVLO
100k
0.55VCC
0.55VCC
CONNECT
CONNECT
100k
8mA
IBOOSTSDA IBOOSTSDA
SDAIN
6
SLEW RATE
DETECTOR
8mA
CONNECT
CONNECT
SLEW RATE
DETECTOR
8mA
IBOOSTSCL IBOOSTSCL
SLEW RATE
DETECTOR
8mA
SLEW RATE
DETECTOR
CONNECT
SDAOUT 7
VCC 8
SCLIN
3
CONNECT
SCLOUT 2
READY 5
PC_CONNECT
30ms
TIMER
LOGIC
ENABLE
PC_CONNECT
IBOOSTSCL
IBOOSTSDA
1
GND
4307 BD
4
95μs
DELAY
+
+
–
–
+
–
+
–
+
–
Low Offset 2-Wire Bus Buffer with Stuck Low Timeout
OPERATION
Start-Up
When the LTC4307 fi rst receives power on its VCC pin,
either during power-up or live insertion, it starts in an
undervoltage lockout (UVLO) state, ignoring any activity
on the SDA or SCL pins until VCC rises above 2V (typ).
This is to ensure that the LTC4307 does not try to function
until it has enough voltage to do so.
During this time, the 1V precharge circuitry is active and
forces 1V through 100k nominal resistors to the SDA
and SCL pins. Because the I/O card is being plugged
into a live backplane, the voltage on the backplane SDA
and SCL busses may be anywhere between 0V and VCC.
Precharging the SCL and SDA pins to 1V minimizes the
worst-case voltage differential these pins will see at the
LTC4307
8
4307f
moment of connection, therefore minimizing the amount
of disturbance caused by the I/O card.
Once the LTC4307 comes out of UVLO, it monitors both
the backplane and card sides for either a stop bit or bus idle
condition to indicate the completion of data transactions.
When both sides are idle or one side has a stop bit condi-
tion while the other is idle, the input-to-output connection
circuitry is activated, joining the SDA and SCL busses on
the I/O card with those on the backplane. In addition, the
precharge circuitry is deactivated and will not be reactivated
unless the VCC voltage falls below the UVLO threshold.
Connection Circuitry
Once the connection circuitry is activated, the functionality
of the SDAIN and SDAOUT pins is identical. A low forced
on either pin at any time results in both pin voltages be-
ing low. The LTC4307 is tolerant of I2C bus DC logic low
voltages up to the 0.3VCC VIL I2C specifi cation.
When the LTC4307 senses a rising edge on the bus, it
deactivates its pull-down devices for bus voltages as low
as 0.48V and activates its accelerators. This methodology
maximizes the effectiveness of the rise time accelerator
circuitry and maintains compatibility with the other devices
in the LTC4300 bus buffer family. Care must be taken to
ensure that devices participating in clock stretching or
arbitration force logic low voltages below 0.48V at the
LTC4307 inputs.
SDAIN and SDAOUT enter a logic high state only when
all devices on both SDAIN and SDAOUT release high.
The same is true for SCLIN and SCLOUT. This important
feature ensures that clock stretching, clock synchroniza-
tion, arbitration and the acknowledge protocol always
work, regardless of how the devices in the system are
tied to the LTC4307.
Another key feature of the connection circuitry is that it
provides bidirectional buffering, keeping the backplane
and card capacitances isolated. Because of this isolation,
the waveforms on the backplane busses look slightly
different than the corresponding card bus waveforms as
described here.
OPERATION
Input to Output Offset Voltage
When a logic low voltage, VLOW1, is driven on any of the
LTC4307’s data or clock pins, the LTC4307 regulates the
voltage on the opposite data or clock pins to a slightly
higher voltage, typically 60mV above VLOW1. This offset is
practically independent of pull-up current (see the Typical
Performance curves).
Propagation Delays
During a rising edge, the rise time on each side is de-
termined by the bus pull-up resistor and the equivalent
capacitance on the line. If the pull-up resistors are the
same, a difference in rise time occurs which is directly
proportional to the difference in capacitance between
the two sides. This effect is displayed in Figure 2 for
VCC = 5.5V and a 10k pull-up resistor on each side (50pF
on one side and 150pF on the other). Since the output
side has less capacitance than the input, it rises faster
and the effective propagation delay is negative.
There is a fi nite propagation delay through the connec-
tion circuitry for falling waveforms. Figure 3 shows the
falling edge waveforms for the same pull-up resistors and
equivalent capacitance conditions as used in Figure 2.
An external N-channel MOSFET device pulls down the
voltage on the side with 150pF capacitance; the LTC4307
pulls down the voltage on the opposite side with a delay
of 80ns. This delay is always positive and is a function
of supply voltage, temperature and the pull-up resistors
and equivalent bus capacitances on both sides of the bus.
The Typical Performance Characteristics section shows
propagation delay as a function of temperature and voltage
for 10k pull-up resistors and 50pF equivalent capacitance
on both sides of the part. Also, the tPHL vs COUT curve for
VCC = 5.5V shows that increasing the capacitance from
50pF to 150pF results in a tPHL increase from 81ns to 91ns.
Larger output capacitances translate to longer delays (up
to 125ns). Users must quantify the difference in propaga-
tion times for a rising edge versus a falling edge in their
systems and adjust setup and hold times accordingly.
LTC4307
9
4307f
OPERATION
Bus Stuck Low Timeout
When SDAOUT or SCLOUT is low, an internal timer is
started. The timer is only reset by that respective input
going high. If it does not go high within 30ms (typical)
the connection between SDAIN and SDAOUT, and between
SCLIN and SCLOUT is broken. After at least 40μs, the
LTC4307 automatically generates up to 16 clock pulses
at 8.5kHz (typical) on SCLOUT in an attempt to unstick
the bus. When the clock pulses are completed, a stop bit
will be generated on SCLOUT and SDAOUT to reset any
circuity on that bus. When the low SDAOUT or SCLOUT
pin goes high, a connection is enabled waiting for a stop
bit or a bus idle to make a connection.
When powering up into a bus stuck low condition, the
connection circuitry joining the SDA and SCL busses on
the I/O card with those on the backplane is not activated
and is only reset when SDAOUT and SCLOUT are high.
30ms after UVLO, automatic clocking takes place as
described above.
READY Digital Output
This pin provides a digital fl ag which is low when either
ENABLE is low, the start-up sequence described earlier in
this section has not been completed, or the LTC4307 has
disconnected due to a stuck bus condition. READY goes
high when ENABLE is high and the backplane and card
sides are connected. The pin is driven by an open-drain
pull-down capable of sinking 3mA while holding 0.4V on
the pin. Connect a resistor to VCC to provide the pull-up.
ENABLE
When the ENABLE pin is driven below 0.8V with respect to
the LTC4307’s ground, the backplane side is disconnected
from the card side and the READY pin is internally pulled
low. When the pin is driven above 2V, the part waits for
data transactions on both the backplane and card sides to
be complete (as described in the Start-Up section) before
connecting the two sides. At this time the internal pull-
down on READY releases. When ENABLE is low, automatic
clocking is disabled.
A rising edge on ENABLE after a bus stuck low condition
has occurred forces a connection between SDAIN, SDAOUT,
and SCLIN, SCLOUT even if the bus stuck low condition
has not been cleared. At this time the 30ms timer is reset
but not disabled.
Rise Time Accelerators
Once connection has been established, rise time accelerator
circuits on all four SDA and SCL pins are enabled. During
positive bus transitions, the rise time accelerators provide
strong, slew-limited pull-up currents that make the bus
voltage rise at a rate of 100V/μs. The rise time accelerators
signifi cantly improve system reliability in two ways. First,
they provide smooth, controlled transitions during rising
edges for both small and large systems. Because the ac-
celerator pull-up impedance is signifi cantly lower than the
bus pull-up resistance, the system is much less susceptible
to noise on rising edges. Second, the accelerators allow
users to choose large bus pull-up resistors, reducing power
consumption and improving logic low noise margin.
For these reasons, it is strongly recommended that users
choose bus pull-up resistors so that the bus will rise on its
own at a rate of at least 0.8V/μs to guarantee activation of
the accelerators. The rise time accelerators are disabled
until the sequence of events described in the start-up sec-
tion has been completed. They are also disabled during
automatic clocking.
Figure 2. Input-Output Rising Edge Waveforms Figure 3. Input-Output Falling Edge Waveforms
OUTPUT SIDE
50pF
1V/DIV
INPUT SIDE
150pF
1V/DIV
200ns/DIV 4307 F02
INPUT SIDE
150pF
1V/DIV
OUTPUT SIDE
50pF
1V/DIV
200ns/DIV 4307 F03
LTC4307
10
4307f
Live Insertion and Capacitance Buffering Application
Figures 4 and 5 illustrate applications of the LTC4307 that
take advantage of the LTC4307’s Hot SwapTM , capacitance
buffering and precharge features. If the I/O cards were
plugged directly into the backplane without the LTC4307
buffer, all of the backplane and card capacitances would
add directly together, making rise-time and fall-time re-
quirements diffi cult to meet. Placing an LTC4307 on the
edge of each card, however, isolates the card capacitance
from the backplane. For a given I/O card, the LTC4307
drives the capacitance of everything on the card and the
backplane must drive only the capacitance of the LTC4307,
which is less than 10pF.
In most applications the LTC4307 will be used with a
staggered connector where VCC and GND will be long
pins. SDA and SCL are medium length pins to ensure that
the VCC and GND pins make contact fi rst. This will allow
the precharge circuitry to be activated on SDA and SCL
before they make contact. ENABLE is a short pin that is
pulled down when not connected. This is to ensure that
the connection between the backplane and the card’s data
and clock busses is not is not enabled until the transients
associated with live insertion have settled.
Figure 4 shows the LTC4307 in an application with a stag-
gered connector. The LTC4307 receives its VCC voltage
from one of the long “early power” pins. Establishing
early power VCC ensures that the 1V precharge voltage is
present at SDAIN and SCLIN before they make contact.
Figure 4. The LTC4307 in an Application with a Staggered Connector
Hot Swap is a trademark of Linear Technology Corporation.
C1
0.01μF
I/O PERIPHERAL CARD 1
CARD
CONNECTORS
BACKPLANE
CONNECTOR
BACKPLANE
R5
10k
R4
10k
SDAIN
SCLIN
ENABLE
READY
SDAOUT
SCLOUT
VCC
GND
LTC4307
R3
10k
R2
10k
R1
10k
VCC
ENAn
SDA
SCL
ENA1
READY
R6
10k
CARD1_SDA
CARD1_SCL
C2
0.01μF
I/O PERIPHERAL CARD N
R8
10k
R7
10k
4307 F04
SDAIN
SCLIN
ENABLE
READY
SDAOUT
SCLOUT
VCC
GND
LTC4307
R9
10k
CARDn_SDA
CARDn_SCL
•
•
•
APPLICATIONS INFORMATION
LTC4307
11
4307f
The ENABLE pin is driven using a short pin. This is to
ensure that a connection is not enabled until the transients
associated with live insertion have settled.
Figure 5 shows the LTC4307 in an application where all
of the pins have the same length. In this application a
resistor is used to hold the ENABLE pin low during live
insertion, until the backplane control circuitry can enable
the device.
Repeater/Bus Extender Applications
Users who wish to connect two 2-wire systems separated
by a distance can do so by connecting two LTC4307s back-
to-back, as shown in Figure 6. The I2C specifi cation allows
for 400pF maximum bus capacitance, severely limiting
the length of the bus. The SMBus specifi cation places no
restriction on bus capacitance, but the limited impedances
of devices connected to the bus require systems to remain
small if rise time and fall time specifi cations are to be met.
In this situation, the differential ground voltage between
the two systems may limit the allowed distance, because
a valid logic-low voltage with respect to the ground at one
end of the system may violate the allowed VOL specifi cation
with respect to the ground at the other end. In addition, the
connection circuitry offset voltages of the back-to-back
LTC4307s add together, directly contributing to the same
problem.
Figure 7 further illustrates a repeater application. This circuit
could be used in an AdvancedTCA system. In AdvancedTCA
applications, the bus pull-up resistance on the backplane
is quite small. Since there is no effect on the offset due
to the pull-up impedance, multiple LTC4307 buffers can
be used in a single system. This allows the user to divide
the line and device capacitances into more sections with
buffering and meet rise and fall times.
The LTC4307 disconnects when both bus I/Os are above
0.48V and rising. In systems with large ground bounce,
if many devices are cascaded, the 0.48V threshold can be
exceeded and the transients associated with the ground
bounce can appear to be a rising edge. Under this condition,
the LTC4307 with inputs above 0.48V may disconnect.
Figure 5. The LTC4307 in an Application Where All the Pins Have the Same Length
C1
0.01μF
I/O PERIPHERAL CARD 1
CARD
CONNECTORS
BACKPLANE
CONNECTOR
BACKPLANE
R5
10k
R4
10k
SDAIN
SCLIN
ENABLE
READY
SDAOUT
SCLOUT
VCC
GND
LTC4307
R3
10k
R2
10k
R1
10k
VCC
ENAn
SDA
SCL
ENA1
READY
R6
10k
CARD1_SDA
CARD1_SCL
C2
0.01μF
I/O PERIPHERAL CARD N
R8
10k
R7
10k
4307 F05
SDAIN
SCLIN
ENABLE
READY
SDAOUT
SCLOUT
VCC
GND
LTC4307
R9
10k
CARDn_SDA
CARDn_SCL
•
•
•
APPLICATIONS INFORMATION
LTC4307
12
4307f
Systems with Supply Voltage Droop
In large 2-wire systems, the VCC voltages seen by devices
at various points in the system can differ by a few hundred
millivolts or more. This situation is modeled by a series
resistor in the VCC line, as shown in Figure 8. For proper
operation, make sure that the VCC(LTC4307) is ≥ 2.3V.
Figure 6. The LTC4307 in a Repeater/Bus Extender Application Where Two 2-Wire Systems are Separated by a Distance
Figure 7. The LTC4307 in a Repeater Application. The LTC4307’s Low Offset Allows Cascading of Multiple Devices
Figure 8. System with Voltage Droop
C2
0.01μF
R7
10k
R6
10k
4307 F06
SDAIN
SCLIN
SDAOUT
SCLOUT
VCC
GND
LTC4307
R5
10k
R1
10k
R4
10k
R2
10k
C1
0.01μF
R3
10k
3.3V
SDA1
SCL1
SDAIN
SCLIN
SDAOUT
SCLOUT
VCC
GND
R8
10k
SDA2
SCL2
LTC4307
ENABLE
READY
ENABLE
READY
C3
0.01
m
F
R10
2.7k
R9
10k
4307 F07
SDAIN
SCLIN
SDAOUT
SCLOUT
VCC
GND
LTC4307
R5
2.7k
R1
2.7k
R4
2.7k
R2
2.7k
C1
0.01
m
F
R3
10k
VCC
SDA1
SCL1
SDAIN
SCLIN
SDAOUT
SCLOUT
VCC
GND
R11
2.7k
SDA2
SCL2
LTC4307
R8
2.7k
R7
2.7k
C2
0.01
m
F
R6
10k
SDAIN
SCLIN
SDAOUT
SCLOUT
VCC
GND
LTC4307
ENABLE
READY
ENABLE
READY
ENABLE
READY
4307 F08
R5
10k
R1
10k
R4
10k
R2
10k
RDROOP
C1
0.01μF
R3
10k
VCC(BUS)
SDA1
SCL1
READY
SDAIN
SCLIN
SDAOUT
SCLOUT
VCC
GND
SDA2
SCL2
VCC(LTC4307)
LTC4307
ENABLE
READY
APPLICATIONS INFORMATION
LTC4307
13
4307f
Simplifi ed ATCA IPMB Application
High VIL Application
R5
10k
R6
10k
R7
10k
C1
0.01μF
SCL
SDA
READY
R2
1.8k
R1
1.8k
5V
R3
200Ω
R4
200Ω
VCC
LTC4307
TEMPERATURE
SENSOR
SCLIN
SDAIN
ENABLE
SCLOUT
SDAOUT
READY
GND 4307 TA02
5V
SDAOUT
SCLOUT
SDAIN
SCLIN
ENABLE VCC
R1
10k
R2
10k
R3
2.7k
C1
0.01μF
DC/DC DC/DC
R4
2.7k
R5
10k
R6
10k
LTC4307
SDAOUT
SCLOUT
SDAIN
SCLIN
ENABLE
VCC
LTC4307
4307 TA03
VCC
3.3V 3.3V
–48V–48V
–48V
ShMC
VCC
IPMC
IPM
BUS
(1 OF 2)
SHELF MANAGER ATCA BOARD
C2
0.01μF
TYPICAL APPLICATIONS
LTC4307
14
4307f
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
0.38 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
2.38 ±0.10
(2 SIDES)
14
85
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.00 – 0.05
(DD8) DFN 1203
0.25 ± 0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.50
BSC
0.675 ±0.05
3.5 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
PACKAGE DESCRIPTION
LTC4307
15
4307f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev F)
PACKAGE DESCRIPTION
MSOP (MS8) 0307 REV F
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.1016 ± 0.0508
(.004 ± .002)
0.86
(.034)
REF
0.65
(.0256)
BSC
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
12
34
4.90 ± 0.152
(.193 ± .006)
8765
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
0.52
(.0205)
REF
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 ± 0.038
(.0165 ± .0015)
TYP
0.65
(.0256)
BSC
LTC4307
16
4307f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2007
LT 0507 • PRINTED IN USA
PART NUMBER DESCRIPTION COMMENTS
LTC1380/LTC1393 Single-Ended 8-Channel/Differential 4-Channel Analog
MUX with SMBus Interface
Low RON: 35Ω Single Ended/70Ω Differential, Expandable to 32 Single
or 16 Differential Channels
LTC1427-50 Micropower, 10-Bit Current Output DAC with SMBus
Interface
Precision 50μA ±2.5% Tolerance Over Temperature, Four Selectable
SMBus Addresses, DAC Powers Up at Zero or Midscale
LTC1623 Dual High Side Switch Controller with SMBus Interface Eight Selectable Addresses/16-Channel Capability
LTC1663 SMBus Interface 10-Bit Rail-to-Rail Micropower DAC DNL < 0.75LSB Max, 5-Lead SOT-23 Package
LTC1694/LTC1694-1 SMBus Accelerator Improved SMBus/I2C Rise Time, Ensures Data Integrity with Multiple
SMBus/I2C Devices
LTC1695 SMBus/I2C Fan Speed Controller in ThinSOTTM Package 0.75Ω PMOS 180mA Regulator, 6-Bit DAC
LT1786F SMBus Controlled CCFL Switching Regulator 1.25A, 200kHz Floating or Grounded Lamp Confi gurations
LTC1840 Dual I2C Fan Speed Controller Two 100μA 8-Bit DACs, Two Tach Inputs, Four GPIO
LTC4300A-1/
LTC4300A-2/
LTC4300A-3
Hot Swappable 2-Wire Bus Buffers LTC4300A-1: Bus Buffer with READY, ACC and ENABLE
LTC4300A-2: Dual Supply Bus Buffer with READY and ACC
LTC4300A-3: Dual Supply Bus Buffer with READY and ENABLE
LTC4301 Supply Independent Hot Swappable 2-Wire Bus Buffer Supply Independent
LTC4301L Hot Swappable 2-Wire Bus Buffer with Low Voltage
Level Translation
Allows Bus Pull-Up Voltages as Low as 1V on SDAIN and SCLIN
LTC4302-1/LTC4302-2 Addressable 2-Wire Bus Buffer Address Expansion, GPIO, Software Controlled
LTC4303/LTC4304 Hot Swappable 2-Wire Bus Buffers with Stuck Bus
Recovery
Provides Automatic Clocking to Free Stuck I2C Busses
LTC4305/LTC4306 2-/4-Channel, 2-Wire Bus Multiplexers with
Capacitance Buffering
2/4 Selectable Downstream Busses, Stuck Bus Disconnect, Rise Time
Accelerators, Fault Reporting, ±10kV HBM ESD Tolerance
ThinSOT is a trademark of Linear Technology Corporation
RELATED PARTS
The LTC4307 in a Repeater Application. The LTC4307’s Low Offset Allows Cascading of Multiple Devices
C3
0.01
m
F
R10
2.7k
R9
10k
4307 F07
SDAIN
SCLIN
SDAOUT
SCLOUT
VCC
GND
LTC4307
R5
2.7k
R1
2.7k
R4
2.7k
R2
2.7k
C1
0.01
m
F
R3
10k
VCC
SDA1
SCL1
SDAIN
SCLIN
SDAOUT
SCLOUT
VCC
GND
R11
2.7k
SDA2
SCL2
LTC4307
R8
2.7k
R7
2.7k
C2
0.01
m
F
R6
10k
SDAIN
SCLIN
SDAOUT
SCLOUT
VCC
GND
LTC4307
ENABLE
READY
ENABLE
READY
ENABLE
READY
TYPICAL APPLICATION
