SYSTEM LEVEL
INTEGRATED
CIRCUIT
FIELD
PROGRAMMABLE
The FPSLIC™ (Field Programmable System Level Integrated Circuit) family of
devices inc or por at es up t o 40, 000 gates of AT40K FPGA, 36K bytes of SRAM ,
the 30 MIPS 8-bi t AV R® RISC micro con troller co re and fixe d per i pherals on a
monolithic device. For the first time all the components of a typical system are
available in a high-performance field-programmable device.
• A monol i thi c device featuri ng:
- 10K, 20K, or 40K gate FPGA
- 30 MIPS microcontroller
performance
- Ultra-l ow power co nsumption
- In-system reconfigurable
• Completely integrated design t ools
including:
- FPG A In tegrated Development
System
- AVR Studio
- Sy nt hes i s
- Simulation
- Co- ver ification
• FPSLIC su pport s:
- 10K to 40K system-level
logic gates
- Eight global clocks
- Up to 304 programmable
PCI-complia nt I/O pins
• Atmel’s SRAM-based AT40K FPGA
eight- si ded logic cell archit ect ure
performs complex DSP functions
without impacting bus resources
• Discrete FreeRAM™ 10 ns dual-port
SRAM blocks are located at the
cor ners of each 4 x 4 ce ll FPGA
sector. Locating these SRAM blocks
throu ghout the array puts memory
where it’s needed, and suppor t s
high-performanc e FIFO desi gns
•Atmel’s AVR 8- bi t RISC
microcontroller arch ite ct ur e enables
throughput in excess of 30 million
instr uctions per second
•8-bit hardware multiplication
accel erator enables AVR
microcontroller to perform complex
DSP ope ratio ns quickly and
efficiently
•32K byte dynamic allocation program
memory – a 16K x 16 (32K x 8) block
of 15 ns SRAM for program
instr uction storage. If not all 32 K is
required, program memory may be
partitioned during design
development into 4K x 8 bl ocks to
provide addi t io nal dat a memory
storage
•4K byte (4K x 8) data memory (may
be increased by adding partitions
from program memory)
Corporate Headquarters
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Europe
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Asia
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Japan
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Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-758 1
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
© Atmel Corporation 1999.
Atmel Corporation makes no
warranty for the use of its products,
other than those expressly
contained in the Company’s
standard warranty which is detailed
in Atmel’s Terms and Conditions
located on the Company’s web site.
The Company assumes no
responsibility f or any errors which
may appear in this document,
reserves the right to change devices
or specifications detailed herein at
any time without notice, and does
not make any commitment to update
the information contained herein. No
licenses to patents or other
int e llectual property of Atmel are
granted by the Company in
connection with th e sale of Atm el
products, expressly or by
implication. Atmel ’s products are not
authorized for use as critical
components in life support devices
or systems.
Marks bearing ® and/or ™ ar e
registe r ed tr a dem arks an d
trad em arks of Atmel Corporation.
Terms and product names in this
document may be trademarks
of others.
1482A–10/99/7.5M
FIELD PROGRAMMABLE SYSTEM LEVEL INTEGRATED CIRCUIT
FPSLIC
Atmel ha s sol ved the software pro bl em s of system integr ati on, debug and testing ,
by provi di ng a complete sys te m development pro ductivity environm ent. Co-verifi ca-
tion(1) tools al lo w for concurrent softw are and hardwar e development and debug.
Design problems are i dentified earlier in the desi gn process allowi ng them to be
fixed quickly, minimizing their impact on project schedules.
By comb in in g i ndu st ry -s ta ndard development tools and tried and tested design
methodology the System Designer™ softw ar e i s a sy st em architects dream . We
have taken mature tools and combined them with standard third-party design entry
and verif ic at ion tools to prov id e t he ideal environme nt for ra pi d, bug free develop-
ment and “what if” ana lysi s. M ake trade-offs bet w een software and har dw are
implementations of an al gor i th m . Sa ve po w er by running compl ex D SP functions in
FPGA in st ead of software. Reconfigure FPGA o n-the-fly from the micr oc ontroller
to updat e your latest encry pt io n al gorithm. Create you r pr oduct with the interf aces
and peripheral on it neede d t o m ake your designs fly.
Note: 1. Co-verification prov ided by Mentor Graphics.
CONVENTIONAL TIMELINE:
HW/SW DEVELOPMENT
WITHOUT CO-VERIFICATION
FPSLIC TIMELINE:
HW/SW DEVELOPMENT
USING CO-VERIFICATION
HARDWARE DESIGN
PROTOTYPE BUILD
HARDWARE DEBUG
SOFTWARE DESIGN
SOFTWARE CODING
SOFTWARE DEBUG
TIME-TO-MARKET
HARDWARE DESIGN
PROTOTYPE BUILD
HARDWARE DEBUG
SOFTWARE DESIGN
SOFTWARE CODING
SOFTWARE DEBUG
TIME-TO-MARKET
PRODUCT
FINISHED
PRODUCT
FINISHED
System Designer
™
CO-VERIFICATION
Code Entry
Functional
Co-Verification
Back-Annotated
Co-Verification
Debugger
AVR
Programming
Code
FPSLIC
PROGRAMMING
UTILITIES
Waveform
Viewer
Waveform
Viewer
HDL Entry
HDLPlanner
HDL Synthesis
Technology
Mapping
Place & Route
Bitstream
AVR Studio™
FPGA IDS
