NXP Semiconductors
User Guide
Document Number: MPC5748GLCEVBUG
Rev. 1, 08/2016
MPC5748G Low Cost EVB User Guide
(MPC5748G-LCEVB)
© 2016 NXP B.V.
Table of Contents
1. Introduction ........................................................................................................................................................................ 3
2. LCEVB Features ................................................................................................................................................................... 3
2.1. Differences to the Customer EVB ............................................................................................................................... 4
3. Configuration Overview ...................................................................................................................................................... 6
4. Initial Setup ......................................................................................................................................................................... 7
4.1. Power Supply Configuration ....................................................................................................................................... 7
4.1.1. Power Input Connector ..................................................................................................................................... 7
4.1.2. Power Switch ..................................................................................................................................................... 7
4.1.3. Power Status LED ............................................................................................................................................... 8
4.1.4. MCU and Peripheral Voltage Configuration ...................................................................................................... 8
4.2. Reset Control (SW3) ................................................................................................................................................... 8
4.2.1. Reset LEDs ......................................................................................................................................................... 9
4.3. MCU Clock Configuration ......................................................................................................................................... 10
4.4. Debug Connector (P1) .............................................................................................................................................. 10
4.4.1. Debug Connector Pinout ................................................................................................................................. 10
5. Communications & Memory Interfaces: ........................................................................................................................... 11
5.1. CAN Interfaces (P2, P3) ............................................................................................................................................ 11
5.2. LIN Interfaces (P6, P7) .............................................................................................................................................. 12
5.3. USB RS232 Serial Interface (P11) .............................................................................................................................. 12
5.4. USB HOST Interface (P4)........................................................................................................................................... 12
5.5. Ethernet Interface (P5) ............................................................................................................................................. 13
5.6. FlexRay (P8, P9, P10) ................................................................................................................................................ 13
6. User Interface (I/O) ........................................................................................................................................................... 14
6.1. GPIO Matrix .............................................................................................................................................................. 14
6.2. User Switches (SW4, SW5) ....................................................................................................................................... 15
6.3. Hex Encoded Switch (SW1) ...................................................................................................................................... 15
6.4. User LED’s (DS1, DS2, DS3, DS4) ............................................................................................................................... 16
6.5. ADC Input Potentiometer (RVAR, RV1) .................................................................................................................... 16
7. MCU Port Pin LCEVB Functions ......................................................................................................................................... 17
8. Appendix ........................................................................................................................................................................... 18
9. Revision History ................................................................................................................................................................. 34
MPC5748G Low Cost EVB User Guide, Rev. 1, 08/2016
2 NXP Semiconductors
1. Introduction
This user guide details the setup and configuration of the NXP MPC5748G Low Cost Evaluation
Board (hereafter referred to as the LCEVB). The LCEVB is intended to provide a mechanism for easy
evaluation of the MPC5748G family of microcontrollers, and to facilitate basic hardware and software
development.
Note that the LCEVB has a limited feature set compared to the main MPC574xG customer EVB and is
intended for evaluation purposes. Customers moving to serious development activities are recommended to
purchase the fully functional customer EVB which also has device specific daughter cards.
The LCEVB is intended for bench / laboratory use and has been designed using normal
temperature specified components (+70° C).
This product contains components that may be damaged by electrostatic discharge. Observe
precautions for handling electrostatic sensitive devices when using the LCEVB.
The user guide is intended to be read alongside the respective MCU documentation available at
www.nxp.com and includes:
Reference Manuals
Product Data Sheets
Application notes
Device Errata
2. LCEVB Features
The LCEVB provides the following key features:
Single 5 V DC external power supply input with on-board 3.3 V regulator. Power is supplied via
a 2.1 mm barrel style power jack.
Simple jumper less configuration (enhanced configuration is possible via 0 Ohm Resistors
and optional jumpers if required).
Master power switch and regulator status LED.
USB Serial interface.
2 x High Speed CAN transceiver routed to 3-way headers.
2 x LIN interfaces routed to 3-way headers.
Main clock supplied from on board crystal.
User reset switch with reset status LED’s.
Ethernet PHY and RJ45 socket (configured for MII mode).
USB Type A Host interface.
2 x FlexRay interfaces with standard 2-pin connectors.
14-pin JTAG connector.
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3 NXP Semiconductors
4 user LED’s wired to MCU ports.
2 user pushbutton switches wired to MCU ports.
Hexadecimal encoded switch wired to 4 MCU ports.
Simple potentiometer connected to analogue input channel.
2.1. Differences to the Customer EVB
Note that the GPIO pins used for peripherals on the LCEVB are the same as those used on the
customer EVB. This ensures maximum code compatibility between the 2 boards, making it easy to
migrate from one board to the other
Table 1. Customer EVB vs LCEVB features
Feature
Customer EVB
MCU Support
Custom MCU Daughter cards for
Soldered 176QFP MPC5748G
multiple devices (socketed)
Power Supply
External 12 V
External 5 V (Caution)
On Board Regulators (and LED’s)
5
V, 3.3 V, 1.25 V (combination of
3.3 V Switching Regulator
Linear and /or Switching regulators)
Master Power Switch
Yes
Yes
Reset Control
Reset button with MCU and External
Reset button with MCU and External
Reset LED’s
Reset LED’s
USB FTDI Serial Interface
Yes
Yes
CAN Physical Interfaces
2
(routed to 0.1” headers)
2
LIN Physical Interfaces
2
(routed to Molex headers)
2
FlexRay Physical Interfaces
2
(routed to 0.1” headers)
2
Ethernet Physical Interface
1
(MII and RMII Support)
1
USB Physical Interface
2
(USB Host and OTG)
1
MLB Daughter card Connector
Yes
No
SAI Audio / TWRPI Connectors
Yes
No
SDHC Connector
Full Size SDHC Socket
No
Fast External Osc (FXOSC)
Daughter card Crystal * and
40 MHz Crystal
SMA input connector
Slow External Osc (SXOSC)
Daughter card Crystal *
32.768 KHz Crystal
CLKOUT signals available
Yes (GPIO Matrix)
Yes (Standalone pads)
User LEDS
4
4
User Pushbutton Switches
4
2
Hex Encoded Switch
Yes
Yes
Test Potentiometer for ADC
Yes
Yes
GPIO Matrix
All Available Pins not otherwise used
Selection of Pins available from 5
for peripherals
GPIO Ports
Debug
14 Pin JTAG and 50 pin Nexus
14 Pin JTAG
Configuration
Highly configurable via jumper shunts
Fixed (limited configuration via 0 ohm
resistors)
* Daughter card crystals are typically 40 MHz for FXOSC and 32.768 KHz for SXOSC but may
vary between daughter cards.
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LCEVB Features
The figure below shows the customer EVB (left) next to the LCEVB (right).
Figure 1. Customer and LCEVB side by side
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NXP Semiconductors
3. Configuration Overview
Out of the box, there is no configuration required for the LCEVB to function. Unlike the customer EVB,
the LCEVB is primarily designed for a single mode of operation with no requirement for user
configuration. If you wish to have a more flexible configuration the recommendation is that the fully
configurable customer EVB is purchased.
There are however some jumper footprints and zero ohm resistors populated in positions that would
normally have jumper headers fitted (for example on the MCU power supply lines and tracking to the
peripheral interfaces). If required these can be de-soldered to modify functionality. Any such
modification is done at the full risk of the user and no support or warranty repairs will be provided for a
board that has been modified. Modifications should only be attempted by appropriately trained
personnel using the correct equipment and Personal Protective Apparel
The diagram below gives an overview of the functional blocks of the LCEVB
Figure 2. EVB Functional Blocks
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Initial Setup
4. Initial Setup
This section details the power, reset, clocks, and debug configuration which is the minimum
configuration needed in order to power ON the LCEVB.
4.1. Power Supply Configuration
The Power supply
section is located in
the bottom left corner
of the LCEVB
The LCEVB requires an external power supply voltage of 5 V DC, minimum 1 A. There is a single 3.3
V switching regulator on the LCEVB providing MCU and peripheral power.
CAUTION
Connecting a power supply with a voltage greater than 5 V will
result in irrecoverable board damage. Check the power supply
voltage before connecting the plug to the LCEVB.
4.1.1. Power Input Connector
Power is supplied to the LCEVB via a 2.1 mm connector from the wall-plug mains adapter as shown
below. Note – if a replacement or alternative adapter is used, care must be taken to ensure the 2.1 mm
plug uses the correct polarization as shown below:
Figure 3. 2.1 mm Power Connector
4.1.2. Power Switch
Slide switch SW2 can be used to isolate the power supply input from the EVB voltage regulators
if required.
Moving the slide switch to the right (away from the power connector) will turn the EVB ON.
Moving the slide switch to the left (towards the power connector) will turn the EVB OFF.
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4.1.3. Power Status LED
When power is applied to the LCEVB, two green LED’s adjacent to the regulator and power connector
show the presence of the supply voltages as follows:
LED DS5 – Indicates that the 5.0 V supply voltage is present
LED DS6 – Indicates that the 3.3 V switching regulator is functioning
If no LED’s are illuminated when power is supplied to the LCEVB and the power switch is in the
“ON” position, the power adapter may be faulty or there may be a fault with the LCEVB. If only one
LED is illuminated there may be a short in that power supply rail – check there is nothing shorting on
the EVB. If you continue to have problems, contact NXP for support.
CAUTION
In the event of a short on the regulator output (in which case one of the
LED’s would be off or dimly illuminated), the regulator and/or the shorted
component will likely be hot.
4.1.4. MCU and Peripheral Voltage Configuration
The following MCU supply rails are connected to the 3.3 V switching regulator:
VDD_HV_ADC0
VDD_HV_ADC1
VDD_HV_ADC1_REF
VDD_HV_A
VDD_HV_B
VDD_HV_FLA
External Ballast Transistor Supply
Similarly all of the peripheral interfaces (or the I/O power in the peripheral interface) are supplied
from 3.3 V as is the reset circuitry and the voltage sense wire on the JTAG connector.
4.2. Reset Control (SW3)
The reset circuitry is
located in the bottom left
quarter of the LCEVB
next to the power switch
The MCU has a single bi-directional open drain Reset pin. Rather than connect multiple devices to the
reset pin directly, a reset-in and reset-out buffering scheme has been implemented on the LCEVB as
shown in Figure 4. The reset “in” from the reset switch (SW3) and the debug connectors are logically
OR’d together using an AND gate and then connected to the buffer to provide an open-drain output.
The “reset-out” circuitry provides a buffered reset signal that can be used to drive any circuitry
requiring a reset control from the MCU.
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Initial Setup
This scheme is not required if it is guaranteed that anything driving the reset pin has an open drain
drive and that there is no significant output load on the MCU reset pin.
Figure 4. EVB Reset Control
4.2.1. Reset LEDs
As can be seen above, there are two reset LED’s that can be used to identify the source / cause of a reset:
RED LED DS8 (titled “MCU”) will illuminate if:
The MCU issues a reset (in this condition ONLY this LED will be illuminated and LED
DS1 will be off)
There is a target reset (i.e. from the reset switch or from the debugger in which case LED
DS1 will be ON)
YELLOW LED DS7 (titled “EXT”) will illuminate when an external hardware device issues a reset
to the MCU:
The reset switch is pressed
There is a reset being driven from one of the debug connectors
Table 2. Reset LED Decoding
LED DS7 (Yellow)
LED DS8 (Red)
Description
OFF
OFF
No Reset being issued from MCU or external logic
OFF
ON
MCU has issued a reset
ON
OFF
External reset issued from switch or debug BUT not being issued to MCU
(check R137 has not been removed)
ON
ON
External reset issued from reset switch or debug and has been issued to MCU.
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NXP Semiconductors 9
4.3. MCU Clock Configuration
There is an external 40MHz crystal connected to the MCU Fast External Oscillator (FXOSC)
pins EXTAL and XTAL.
There is also a 32.768 crystal connected to the MCU Slow External Oscillator (SXOSC) pins
OSC32K_EXTAL and OSC32K_XTAL. This can be used for accurate time keeping.
There are 2 pads PG6 and PG7 (located just below the MCU) on the LCEVB to facilitate
measurement of the CLKOUT1 and CLKOUT0 signals.
Note – there is no external clock input on the LCEVB
4.4. Debug Connector (P1)
The JTAG debug
connectors is
located in the top left
corner of the LCEVB
The LCEVB has a single 14-pin keyed JTAG connector for connection to an external debugger.
Before attaching or removing the debug cable from the LCEVB remove power from the EVB to
prevent damage to the LCEVB or debug hardware.
4.4.1. Debug Connector Pinout
The following tables list the pinout for the JTAG connector used on the LCEVB
Table 3. 14-Pin JTAG Debug Connector Pinout
Pin No
Function
Connection
Pin No
Function
Connection
1
TDI
PC0
2
GND
GND
3
TDO
PC1
4
GND
GND
5
TCLK
PH9
6
GND
GND
7
EVTI
PL8
8
N/C
---
9
RESET
JTAG – RSTx
10
TMS
PH10
11
VREF
PER_HVA
12
GND
GND
13
RDY
---
14
JCOMP
10k Pulldown
TDI, TDO and TMS have 10K pullup resistors on the LCEVB. TCLK has a 10K pulldown (R147) to
facilitate STANDBY exit without any additional code (at the sacrifice of slightly higher STANDBY
current), however this can be changed to a pullup if required by removing R147 and fitting the resistor
on R56.
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Communications & Memory Interfaces:
Table 4. JTAG Pins Pull State (from MPC5748G Reference Manual)
TERMINAL TYPE
POWERUP pad state
RESET pad status
DEFAULY pad status
RESET
Strong pull-down
Strong pull-down
Weak pull-up
PORST
Weak pull-down
Weak pull-up
Weak pull-up
GPIO
High impedance
High impedance
High impedance
ANALOG
High impedance
High impedance
High impedance
EOUT0, EOUT1
High impedance
High impedance
High impedance
TCK
High impedance
Weak pull-up
Weak pull-up
TMS
High impedance
Weak pull-up
Weak pull-up
TDI
High impedance
Weak pull-up
Weak pull-up
TDO
High impedance
High impedance
High impedance
5. Communications & Memory Interfaces:
This section details the communication interface and storage peripherals that are implemented on
the LCEVB.
5.1. CAN Interfaces (P2, P3)
The CAN circuitry is
located on the top
right edge of the
LCEVB
The LCEVB incorporates two identical CAN interface circuits connected to MCU CAN0 and CAN1
using MC33901 transceivers. Both transceivers are configured for high speed operation by pulling pin
8 to GND via a 4.7 kOhm resistor. There are test points to allow the Select pin to be driven high if
desired. The MC33901 is pin compatible with other CAN transceivers supporting full CAN FD data
rates.
For flexibility, the CAN transceiver I/O is connected to a 0.1” header (P2 for CAN0 / P3 for CAN1)
rather than using non-standard DB9 connectors. The pinout of these headers is shown below.
1
H L GND
Figure 5. CAN Physical Interface Connectors
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5.2. LIN Interfaces (P6, P7)
The LIN Physical
interface circuits are
located on the right
edge of the LCEVB
The LCEVB incorporates two LIN transceiver circuits connected to MCU LIN0 and LIN1, using an
NXP MC33662 transceiver. The MPC5748G LIN0 supports both master and slave modes whereas
LIN1 only supports master mode.
On the LCEVB, the LIN0 transceiver is configured as slave mode by default. Master mode operation is
possible by either populating a zero ohm resistor (R143) or buy fitting a jumper header (J2) – see the
schematics for details. The LIN0 transceiver is hard wired for master mode. To save on board space
and cost, both LIN transceivers are connected to 0.1” pitch 3x1 headers as shown below rather than the
usual LIN Molex header.
Figure 6. LIN Physical Interface Connector
Note that in order for the LIN transceiver to function, external 12v must be supplied via pin 2 of the
connector
5.3. USB RS232 Serial Interface (P11)
The USB RS232
interface is on the
left hand edge of the
board (USB Type B
The LCEVB incorporates a USB RS232 serial interface providing RS232 connectivity via a direct USB
connection between the PC and the EVB. The circuit contains an FTDI FT2232D USB to Serial
interface which should automatically install the drivers for two additional COM ports on your PC. Note
that only one of these ports is used so you will need to try both (usually the higher numbered COM port
is the active one). For more information on the USB drivers and general fault finding, consult the FTDI
website at http://www.ftdichip.com/
The MCU LIN2 signals are routed to the FTDI transceiver (UART TX and RX). No handshaking
signals are implemented and no board configuration is required.
5.4. USB HOST Interface (P4)
The USB Host
interface is on the
top left corner of the
LCEVB on the left
The LCEVB includes a Type A (Host) USB interface, routed to a USB type A female connector.
The USB circuit contains a USB83340 transceiver with a MIC2026-1YM USB power switch. There
is no hardware user configuration required to use the USB circuit.
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GND Vsup LIN
1
5.5. Ethernet Interface (P5)
Communications & Memory Interfaces:
The Ethernet
interface is mid-way
along the top edge
of the LCEVB
The EVB incorporates a single DP83848c Ethernet transceiver with the circuitry configured for MII
mode. The transceiver is connected to a pulse J1011F21PNL RJ45 connector which includes a built-in
isolation transformer. There is no hardware configuration needed.
If you require RMII mode or access to both Ethernet ports on the MPC5748G, please purchase
the MPC5748G customer EVB and appropriate daughter cards.
Note that the MCU Ethernet signals are all in the VDD_HV_B domain. The Ethernet PHY will only
function with 3.3 V I/O so if you have made any modifications to the EVB power domain configuration
(via the zero ohm resistors), you need to ensure the VDD_HV_B domain is at 3.3 V before attempting
to use the Ethernet module. If VDD_HV_B is set to 5 V, the signals routed to the Ethernet PHY (see the
EVB schematics) must be left as tristate to prevent damage to the transceiver.
5.6. FlexRay (P8, P9, P10)
The FlexRay
interfaces are midway
down the left hand
edge of the LCEVB
The LCEVB incorporates two FlexRay TJA1080TS/N interfaces connected to MCU FlexRay
channels A and B and routed to two Molex 1.25 mm pitch Pico Blade shrouded headers (standard on
many NXP EVB’s). There is no hardware configuration required to use FlexRay.
Note that the LCEVB is supplied with a 40 MHz crystal by default. If FlexRay is configured to use
the external clock source, then the crystal should be left at 40 MHz
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NXP Semiconductors 13
6. User Interface (I/O)
This section details the user I/O available on the LCEVB and includes the GPIO matrix, switches,
LED’s and the ADC variable resistor.
6.1. GPIO Matrix
The GPIO matrix is
on the right hand
edge of the LCEVB
A sub-set of available GPIO pins (available pins being those not already routed to LCEVB peripherals)
are available at the GPIO matrix as detailed below. The matrix provides an easy to follow, intuitive,
space saving grid of 0.1” header through-hole pads. Users can solder wires, fit headers or simply insert a
scope probe into the respective pad.
To use the matrix, simply read the port letter from the top or bottom row of text then the pad number
from the columns on the left or right of the matrix. For example, the 1st pad available on Port B is
PB5 as outlined below.
Figure 7. GPIO Matrix
If a pad is populated in the matrix, it means this is available for exclusive use as GPIO. The exception
to this are the port pins detailed below which are also shared with switches or user LED’s (shaded red in
the matrix diagram above).
PD0, PD1, PD2, PD3 – HEX Encoder Switch
PA1, PA2 – User pushbutton Switches
If you require access to all of the available GPIO pads, the customer EVB and daughter card
provides this additional functionality.
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6.2. User Switches (SW4, SW5)
User Interface (I/O)
The user pushbutton
switches are in the
bottom right corner of
the LCEVB
There are two active high (pulled low, driven to 3.3 V) pushbutton switches on the LCEVB connected
directly to MCU GPIO ports. No configuration is required to use the switches.
SW4 is connected to port PA1 (which is also the NMI pin) and SW5 is connected to port PA2
NOTE
The MCU ports used on the user pushbutton switches are also routed
to the GPIO matrix.
6.3. Hex Encoded Switch (SW1)
The hex encoder
switch is located to
the left of the
GPIO Matrix
There is a single hex encoded 16 position rotary switch on the LCEVB. This outputs a binary
encoded hex value (active high) on four MCU ports (Port D[0..3]).
Table 5. Hex Encoder Switch (SW2)
Position
HEX_SW4
HEX_SW3
HEX_SW2
HEX_SW1
(PD3)
(PD2)
(PD1)
(PD0)
0
0
0
0
0
1
0
0
0
1
2
0
0
1
0
3
0
0
1
1
4
0
1
0
0
5
0
1
0
1
6
0
1
1
0
7
0
1
1
1
8
1
0
0
0
9
1
0
0
1
A
1
0
1
0
B
1
0
1
1
C
1
1
0
0
D
1
1
0
1
E
1
1
1
0
F
1
1
1
1
Note that POSN 0 will ensure that no voltage is applied to the pads. This allows the pads to be used as
normal GPIO (with 10K pulldown) and accessed at the respective pads on the GPIO matrix area.
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NXP Semiconductors 15
6.4. User LED’s (DS1, DS2, DS3, DS4)
The user LED’s are
above the user
switches in the lower
right corner
There are four active low user LED’s, DS1 to DS4, connected directly to 4 MCU ports (PG[2..5]) as
shown below. No configuration is required to use the LED’s.
Table 6. Use LED’s (DS1, DS2, DS3 and DS4)
User LED
MCU Pin
DS1
PG2
DS2
PG3
DS3
PG4
DS4
PG5
6.5. ADC Input Potentiometer (RVAR, RV1)
The ADC Pot is
above the hex
switch to the left of
the GPIO matrix
There is a small variable resistor RV1 on the LCEVB which routes a voltage between 0v and 3.3 V to
MCU pin PB4. This is useful for quick ADC testing. Test point RVAR can be used to probe the
voltage with a voltmeter.
Note that this circuit provides a very rough way to evaluate the ADC. There is a small current limiting
series resistor network to limit the injection current to around 4.4 mA.
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MCU Port Pin LCEVB Functions
7. MCU Port Pin LCEVB Functions
The table below shows what each MCU pin is used for on the LCEVB.
Table 7. LCEVB 176QFP Port Pin Functions
No
Port A
Port B
Port C
Port D
Port E
Port F
Port G
Port H
0
GPIO
CAN0
JTAG
GPIO
3
---
GPIO
Ethernet
Ethernet
1
GPIO
2
CAN0
JTAG
GPIO
3
---
GPIO
Ethernet
Ethernet
2
GPIO
2
LIN0
USB1
GPIO
3
FlexRay A
GPIO
GPIO
4,
Ethernet
3
Ethernet
LIN0
USB1
GPIO
3
FlexRay A
GPIO
GPIO
4
---
4
GPIO
ADC Pot
FlexRay B
GPIO
FlexRay B
GPIO
GPIO
4
---
5
GPIO
GPIO
FlexRay A
GPIO
FlexRay B
GPIO
GPIO
4
---
6
GPIO
GPIO
LIN1
GPIO
---
GPIO
GPIO
---
7
Ethernet
GPIO
LIN1
GPIO
---
GPIO
GPIO
---
8
Ethernet
EXTAL32
RS232
GPIO
---
GPIO
---
---
9
Ethernet
XTAL32
RS232
GPIO
---
GPIO
---
JTAG
10
Ethernet
SAI Audio
CAN1
GPIO
---
GPIO
USB1
JTAG
11
Ethernet
GPIO
CAN1
---
GPIO
USB1
USB1
12
GPIO
GPIO
FlexRay
GPIO
Ethernet
GPIO
Ethernet
USB1
13
GPIO
GPIO
FlexRay
GPIO
Ethernet
GPIO
Ethernet
---
14
GPIO
GPIO
FlexRay
GPIO
USB1
Ethernet
USB1
---
15
GPIO
GPIO
FlexRay
GPIO
USB1
Ethernet
USB1
---
No
Port I
Port J
0
GPIO
---
1
GPIO
---
2
GPIO
---
Key:
3
GPIO
---
Pin not bonded out on 176QFP package
4
USB1
---
---
Pin not accessible on LCEVB
5
USB1
6
GPIO
7
USB1
8
GPIO
9
10
11
Ethernet
12
GPIO
13
GPIO
14
GPIO
15
GPIO
2 Shared with user switches
3 Shared with Hex Encoder Switch
4 Shared with user LED’s
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NXP Semiconductors 17
8. Appendix
The MPC5748G LCEVB schematics, Rev B are shown below.
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18 NXP Semiconductors
D
C
B
A
5
4
3
2
1
MPC5748G Low Cost Evaluation Board (MPC5748G-LCEVB)
Revision Information
Table Of Contents:
Rev
Date
Designer
Comments
x1
14 Apr 2015
Alasdair Robertson
Start of capture, Working version (256BGA)
D
Power - Main input and 3.3V regulator
Sheet 2
x2
08 May 2015
Alasdair Robertson
Changed to 176 QFP Package and changed periperhal Matrix
Power - MCU Power
Sheet 3
x3
18 May 2015
Alasdair Robertson
Changes required for initial placement
Power - MCU Decoupling
Sheet 4
x4
19 May 2015
Alasdair Robertson
Tidy Up, Replaced some "hard to source" components
Reset and JTAG
Sheet 5
x5
26 May 2015
Alasdair Robertson
Renumber and Back Annoted from Layout
Clocks
Sheet 6
x6
27 May 2015
Alasdair Robertson
Correction to GND on 3v3 Regulator circuit
MCU GPIO 1
Sheet 7
x7
29 May 2015
Alasdair Robertson
Correction to CAN Test points
MCU GPIO 2
Sheet 8
x8
31 May 2015
Alasdair Robertson
Few refdes changes after layout tweaks
Comms1 - CAN and LIN
Sheet 9
x9
01 Jun 2015
Alasdair Robertson
Correction to user LED Refdes after re-number
Comms 2 - FTDI RS232 Interface
Sheet 10
x10
01 Jun 2015
Alasdair Robertson
DNP Jumpers. 0 Ohm resistors added accross LIN jumpers
Comms 3 - USB Host Interface (device footprints only)
Sheet 11
A
11 Jun 2015
Andrew MacDonald
Prototype Manufacture Release
Comms 4 - Ethernet (MII Mode)
Sheet 12
AX1
29 Sep 2015
Alasdair Robertson
Prodn Build changes (LIN0 default to Slave, LIN1 Master only)
Comms 5 - FlexRay
Sheet 13
PN Changed to MPC5748G-LCEVB
C
User - Switches, LED's and Potentiometer
Sheet 14
AX2
26 Oct 2015
Alasdair Robertson
Change to JTAG Pulls to meet latest RM Spec
User - GPIO Pin Matrix
Sheet 15
AX3
29 Oct 2015
Alasdair Robertson
Changed RV1 current limit resistor. SW4 / SW5 refdes swap
AX4
09 Dec 2015
Alasdair Robertson
Pull DOWN on TCLK to mitigate against STANDBY exit issue.
AX5
20 Jan 2016
Alasdair Robertson
Updated NXP Logos
B
12 Feb 2016
Alasdair Robertson
Updated NXP Logos
Caution:
These schematics are provided for reference purposes only.
As such,NXP does not make any warranty, implied or otherwise, as to the
suitability of circuit design or component selection (type or value) used in
these schematics for hardware design using the NXP Calypso family of
B
Microprocessors. Customers using any part of these schematics as a
3 Different test points used in design:
basis for hardware design, do so at their own risk and NXP does not
TPVx - Through Hole Pad small
assume any liability for such a hardware design.
TPHx - Through Hile Pad Large (for standard 0.1" header).
Also
used on IO Matrix (IOMx)
TPX
- Surface Mount Wire Loop
Notes:
- All components and board processes are to be ROHS compliant
- All small capacitors are 0402 unless otherwise stated
- All resistors are 0603 5% 0.1w unless otherwise stated. All zero ohm links are 0603
- All connectors and headers are denoted Px and are 2.54mm pitch unless otherwise stated
Automotive Microcontroller Applications
- All jumpers are denoted Jx. Jumpers are 2mm pitch
East Kilbride, Scotland
- Jumper default positions are shown in the schematics. For 3 way jumpers, default is always posn 1-2.
2 Pin jumpers generally have the "source" on pin 1.
NXP General Business Use
- All switches are denoted SWx
This document contains information proprietary to NXP and shall not be used for engineering design,
A
- All test points (SMT wire loop style) are denoted TPx
without the express written permission of NXP Semiconductors.
- Test point Vias (just through hole pads) are denoted TPVx
procurement or manufacture in whole or in part Freescale AISG Applications, East Kilbride
Signals (ports) have not been routed via busses as this makes it harder to determine where each signal goes.
Designer:
Drawing Title:
A. Robertson
MPC5748G-LCEVB
User notes are given throughtout the schematics.
Drawn by:
Page Title:
A. Robertson
Index and Title Page
Specific PCB LAYOUT notes are detailed in ITALICS
Approved:
Size
Document Number
PDF: SPF-27897
Rev
A. Robertson
B
SCH-27897
B
Date:
Friday, February 12, 2016
Sheet 1of
15
5 4 3 2 1
5
4
3
2
1
Power Input and Linear Voltage Regulators
Power Supply Input
Power Control
SW2
(Power Switch)
Jumpers can be fitted to
1
3
facilitate power measurements
4
2
2.1mm Barrel
5V0_SR
D
P12 Connector
5V-IN
5
3V3_SR
J3
DNP
1
Main Power In
MCU_3V3
2
C
1
(SR = Swithing Reg)
1
2
MCU_3V3
3
3
C26
D4
C21
HDR 1X2
GND
0.1UF
B340A
10UF
5v0
R142
R48
0
10V
5V0_SR
A
560
J4
DNP
MCU_5V0
C
DS5
A
1
2
MCU_5V0
3
HDR 1X2
GND
LED GREEN
R49
0
5V0_SR
3V3_SR
PER_HVA
3.3v Switching Regulator
R47
0
R45
0
5V0_SR
DNP
U10
PER_HVB
C
8
6
R138
178K
3V3_SR
VIN
PG
R46
0
1
7
1
2
EN
SW
R44
0
3
5
L3
1.0uH
1
DNP
C22
MODE
VOS
R43
2
4
C23
10UF
GND
FB
3v3
270
10V
22UF
9
EP
10V
TPS62082
C
DS6
A
GND
LED GREEN
Inoput Voltage 5V, Output 3.3V at 700mA. Ripple 1.4mV, Approx 90% efficient
B
Test and reference points
GND1 GND2 GND3 GND4
GND15
GND16
1
1
1
1
1
1
GND Test Points,
GND Test Points,
Top Side
underside of board
GND
Automotive Microcontroller
Applications
A
East Kilbride, Scotland
NXP General Business Use
Drawing Title:
MPC5748G-LCEVB
Page Title:
Power Input and Linear Voltage Regulators
Size
Document Number
Rev
B
SCH-27897
PDF: SPF-27897
B
Date:
Friday, February 12, 2016
Sheet 2of
15
D
C
B
A
5 4 3 2 1
5
4
3
2
1
Calypso MCU Power Connections
Power Supply Contraints:
Default Configuration:
- If VDD_HV_A is driven from 3.3V, VDD_HV_FLA must
- ALL MCU supply voltages are set to 3.3V
also be supplied from 3.3V
(ADC0, ADC1, VDD_HV_A, VDD_HV_B, VDD_HV_C,
- If VDD_HV_A is driven from 5V, the VDD_HV_FLA pin
VBallast)
must be disconnected from 3.3V
- VDD_HV_FLA = External 3.3V supplied (jumper
- Don't attempt to over drive an analogue pad to 5V
fitted)
The analogue pins can only be driven to the
D
when the digital VDD_HV_x supply is set to 3.3V.
This will trigger the ESD protectrion on that pad.
same voltage as the VDD_HV_x domain they are
For example if VDD_HV_A is set to 3.3V and the
situated in (i.e. max 3.3V) so makes sense for
analogue supplies are set to 5V, you cannot drive 5V
the analogue supply and reference to be 3.3V
into a pad in the VDD_HV_A domain
2
MCU_3V3
MCU_3V3
2
MCU_5V0
MCU_5V0
3v3
R100
0
R101 0
R98
0
R112 0
R122 0
R124 0
Individual MCU
R97
0
R103
0
R99
0
R111
0
R114
0
supply control
5v0
C
DNP
DNP
DNP
DNP
DNP
R102
0
Q50
4
C_CAP
MJD31CT4
B_CAP
1
ADC1REF CAP
HVA CAP
HVB CAP
H
V
F
L
A
C
A
P
3
E_CAP
L
V
D
E
C
C
A
P
A
D
C
0
C
A
P
AD
C1
CA
P
1
R139
LV
CAP
0
TPH2
9
0
99
98
6
59
85
151
124
27
32
31
54
110
152
30
U20B
VDD HV
ADC0
VDD HV ADC1
HV ADC1
REF
VDD
HV A
6VDDH
VA59V
DDHVA
85VDD
HVA15
1
VDD HV B 124
VDD HV
FLA
VRC
CTRL
VDD LV
31VDDLV54VDDLV
110VDDLV152
VDD LP DEC
B
Analogue
V
D
D
Calypso 6M 176QFP
Flash
1.25v Core & External Ballast
Package 2of3
Power Pins
VSS HV
ADC0
VSS HV ADC1
Central Pad for heat
VSS
HV
7VSSH
V28VS
SHV55
VSSHV
57VSS
HV86V
SSHV1
23
VSS HV 150
VSS HV VPP
VSS
LV
109
dissipation & GND
EP
8
9
97
7
28
55
57
86
123
150
26
109
177
PPC5748GSK0MKU6
1
R123
0
Automotive Microcontroller
GND
GND
GND
TPH3
GND
GND
Applications
A
East Kilbride, Scotland
Notes on signal Grounds:
NXP General Business Use
Drawing Title: MPC5748G-LCEVB
- The scheme shown has the analogue and digital grounds connected to the same plane
- This results in better ADC performance than using an analogue grond plane with single entry
Page Title:
point (or ferrite) to digital ground plane.
Calypso MCU Power
Size
Document Number
Rev
B
SCH-27899
PDF: SPF-27899
B
Date:
Friday, February 12, 2016
Sheet 3
of
15
D
C
B
A
5 4 3 2 1
D
5
4
3
2
1
Calypso MCU Decoupling and bulk storage
ADC
Flash
Capacitor Types:
ADC0_CAP
ADC1_CAP
ADC1REF_CAP
HVFLA_CAP
4700pF
- Ceramic X7R, 50V 10% 0402
0.1uF
- Ceramic X7R, 16V 10%
0402 (Kemet C0402C104K4RAC)
C94
C93
C97
C96
C95
C118
0.68uF
- Ceramic X7R, 16V
10%
0805
(Murata GCM219R71C684KA37)
1uF
0.1UF
1uF
0.1UF
1uF
2.2UF
1uF
- Ceramic X7R, 10V
10%
0603
Low ESR (Taiyo Yuden LMK107B7105KA-T)
2.2uF - Ceramic X7R, 10V
10%
0603
Low ESR (Taiyo Yuden LMK107B7225KA-TR)
GND
GND
GND
GND
D
C
B
A
Place small Caps as close as possible to MCU pins
VDD_HVA
VDD_HVB
HVA_CAP
HVB_CAP
C112
C109
C120
C92
C100
C99
2.2UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
GND
GND
One 0.1uF cap per VDD_HV_x pin. Place as close as possible to pin
VDD_LV
LV_CAP
C110
C111
C27
C108
C116
C98
C113
0.68uF
0.68uF
0.68uF
0.1UF
0.1UF
0.1UF
0.1UF
(low
(low
(low
ESR)
ESR)
ESR)
VDD_LV (1.25V) Decoupling. Place one of the 0.1uF caps close to each VDD_LV GND
pin. Place the 0.68uF caps on each side of the package such that there is
no cap on the side with the ballast transistor
(For regulator stability the total capacitance should be around 2.2uF).
Ballast Transistor
LP Internal Reg Cap
B_CAP
E_CAP
C_CAP
LVDEC_CAP
C119
C122
C117
4700pF
2.2UF
1uF
GND GND
Place close to transistor
Automotive Microcontroller
Applications
East Kilbride, Scotland
NXP General Business Use
Drawing Title: MPC5748G-LCEVB
Page Title:
Calypso MCU Decoupling
Size
Document Number
Rev
B
SCH-27899
PDF: SPF-27899
B
Date:
Friday, February 12, 2016
Sheet 4
of
15
C
B
A
5 4 3 2 1
5
4
3
2
1
Reset and External Clock In
Reset is in the
Reset Input / Output
PORST
PER_HVA
VDD_HVA domain.
D
C
PER_HVA
Connect an external LVI to pad
when supplying external 1.25V so
R37
that PORST is asserted until
3V3_SR
exterbal 1.25V supply is at
10.0K
threshold and stable
TPH1
R140
C24
(0603
1
PORSTx
(0603
270
C25
0.1UF
50V)
0.1UF
50V)
A
TARGET
R135
R134
GND
DS7
RESET
GND
R136
10.0K
10.0K
YELLOW LED
Reset from
8
U12A
LED
U11
4
RST
10.0K Bi Directional reset
Debugger
1
line to/from MCU
5
JTAG-RSTx
VCC
JTAG-RSTx
C
VCC
R137 0
1
7
SYSTEM-RSTx
3
2 RST-INx
MCU-RSTx
RST-SWITCHx
2
MR
RESET
GND
Tri-State Buffered
Reset Switch
GND
4
SN74LVC2G08DCT
RESET signal to
(1.65 to 5.5v operation)
1
reset the MCU
Buffered RESET-out
1
2
SW3
B3WN-6002
GND
ADM6315-26D2ARTZR7
Active reset drive (high / low)
GND
(2.5 to 5v operation)
for any periperhals that need to
TPV5
be reset when MCU is in reset
C121
(0603
3V3_SR
0.1UF
50V)
Note:
R141
270
DS8
A
C
GND
The Reset pad on Calypso is in the VDD_HV_A domain which can be run from either 3.3V or 5V
LED RED
(selected by the VDD_HV_A and PER_HVA jumpers)
U12B
(MCU RESET)
To maintian brightness on the LED's irrespective of the voltage setting, the LED's are
powered from constant 3.3V, grounded via the reset line.
5
3
RST-OUTx
6
PORSTx
7
MCU-RSTx 5,7
RST-OUTx 12
D
C
B
A
SN74LVC2G08DCT
JTAG Standard 14-pin Connector
PER_HVA
R58
R57
R56
R52
ONCE Connector
10.0K
10.0K
10.0K
10.0K
DNP
P1
7
PC0
PC0
TDI
(TDI)
1
2
(GND)
7
PC1
PC1
TDO
(TDO)
3
4
(GND)
7
PH9
PH9
TCLK
(TCLK)
5
6
(GND)
EVTI
(EVTI)
7
8
(N/C)
DBUG-RSTx
(RESET)
9
10
(TMS)
PH10
(VREF)
11
12
(GND)
5
JTAG-RSTx
JTAG-RSTx
R55
0
(RDY)
13
14
JCOMP
(buffered
reset TO MCU)
R147
CON_2X7
R53
Note TCLK needs to be pulled down to allow exit from STANDBY in some corner cases
R54
0
10.0K
5,7
MCU-RSTx
MCU-RSTx
10.0K
(bidirectional
DNP
MCU reset)
Optional
Automotive Microcontroller
Config
GND
Applications
GND
East Kilbride, Scotland
PH10
TMS
NXP General Business Use
7
PH10
Drawing Title:
MPC5748G-LCEVB
Page Title:
Reset Circuitry & External Clock In
Size
Document Number
Rev
B
SCH-27897
PDF: SPF-27897
B
Date:
Friday, February 12, 2016
Sheet 5
of
15
B
A
5 4 3 2 1
5
4
Clocks
D
Oscillators
7
PB9
PB9
(EXTAL32)
R42
1.0M
DNP
7
PB8
PB8
(XTAL32)
C
7
MCU-EXTAL
MCU-EXTAL
R41
1.0M
DNP
7
MCU-XTAL
MCU-XTAL
B
A
1
2
2
1
3
2
1
C18 12PF
Y3
32.768KHZ FC-255 32.7680K-A3 (Load
Capacitance 7pF)
C20 12PF
GND
C19
12PF
Y2
NX8045GB-40.000M-STD-CSJ-1 XTAL
40.0MHZ
(Optimised for Automotive, 8pF Load capacitance)
C17 12PF
GND
Automotive Microcontroller
Applications
East Kilbride, Scotland
NXP General Business Use
Drawing Title: MPC5748G-LCEVB
Page Title:
Clocks
Size
Document Number
Rev
B
SCH-27899
PDF: SPF-27899
B
Date:
Friday, February 12, 2016
Sheet 6
of
15
D
C
B
A
5 4 3 2 1
5
4
3
2
1
Calypso GPIO 1 of 2
U20A
(GPIO)
PA0
24
18
(WKPU2 / NMI0)
15
PA0
PA0
Calypso 176QFP
PE0
(SW1 & GPIO**)
PA1
19
20
14,15
PA1
PA1
PE1
(WKPU3)
14,15
PA2
(SW2 & GPIO)
PA2
17
PA2
PE2
156
PE2
(FR_A_TX_EN)
PE2
13
12
PA3
(MII_RXCLK)
PA3
114
PA3
Package 1of3 GPIO Pins1
PE3
157
PE3
(FR_A_RX)
PE3
13
(GPIO)
PA4
51
160
PE4
(FR_B_TX)
D
Key to text colours:
15
PA4
(GPIO)
PA5
146
PA4
PE4
161
PE5
(FR_B_RX)
PE4
13
15
PA5
PA5
PE5
PE5
13
Purple
- Comms Physical Interfaces
15
PA6
(GPIO)
PA6
147
PA6
PE6
167
Orange
- Other Peripherals and I/O
12
PA7
(MII_RXD2)
PA7
128
PA7
PE7
168
Blue
- Debug (JTAG & Nexus)
12
PA8
(RMII_RXD1)
PA8
129
PA8
PE8
21
Black
- Clock, Reset and Control
12
PA9
(RMII_RXD0)
PA9
130
PA9
PE9
22
RED
- I/O Matrix and other functions (eg LED)
12
PA10
(MII_COL)
PA10
131
PA10
PE10
23
(RMII_RXER)
PA11
132
25
Green
- I/O Matrix (dedicated)
12
PA11
PA11
PE11
(MII_CRS)
15
PA12
(GPIO)
PA12
53
PA12
PE12
133
PE12
PE12
12
(GPIO)
PA13
52
127
PE13
(MII_RXD3)
15
PA13
(GPIO)
PA14
50
PA13
PE13
136
PE14
(USB1_D2)
PE13
12
PA 12..15 has SPI
15
PA14
(GPIO)
PA15
48
PA14
PE14
137
PE15
(USB1_D3)
PE14
11
15
PA15
PA15
PE15
PE15
11
(CAN0_TX)
PB0
39
63
PF0
(GPIO)
9
PB0
PB0
PF0
PF0
15
(CAN0_RX)
PB1
40
64
PF1
(GPIO)
9
PB1
PB1
PF1
PF1
15
(LIN0_TX)
PB2
176
65
PF2
(GPIO)
9
PB2
PB2
PF2
PF2
15
9
PB3
(LIN0_RX)
PB3
1
PB3
PF3
66
PF3
(GPIO)
PF3
15
14
PB4
(ADC_POT)
PB4
88
PB4
PF4
67
PF4
(GPIO)
PF4
15
(GPIO)
PB5
91
68
PF5
(GPIO)
15
PB5
(GPIO)
PB6
92
PB5
PF5
69
PF6
(GPIO)
PF5
15
15
PB6
(GPIO)
PB7
93
PB6
PF6
70
PF7
(GPIO)
PF6
15
15
PB7
PB7
PF7
PF7
15
(XTAL32)
PB8
61
42
PF8
(GPIO)
6
PB8
(EXTAL32)
PB9
60
PB8
PF8
41
PF9
(GPIO)
PF8
15
6
PB9
PB9
PF9
PF9
15
C
15
PB10
(GPIO)
PB10
62
PB10
PF10
46
PF10
(GPIO)
PF10
15
(GPIO)
PB11
96
47
PF11
(GPIO)
15
PB11
(GPIO)
PB12
101
PB11
PF11
43
PF12
(GPIO)
PF11
15
15
PB12
PB12
PF12
PF12
15
(GPIO)
PB13
103
49
PF13
(GPIO)
15
PB13
(GPIO)
PB14
105
PB13
PF13
126
PF14
(RMII_MDIO)
PF13
15
15
PB14
(GPIO)
PB15
107
PB14
PF14
125
PF15
(RMII_RXDV)
PF14
12
15
PB15
(TDI)
PC0
154
PB15
PF15
122
PG0
(RMII_MDC)
PF15
12
5
PC0
PC0
PG0
PG0
12
(TDO)
PC1
149
121
PG1
(RMII_TXCLK)
5
PC1
(USB1_CLK)
PC2
145
PC1
PG1
16
PG2
(LED1 & GPIO)
PG1
12
(eMIOS E1UC_11_H)
11
PC2
(USB1_DIR)
PC3
144
PC2
PG2
15
PG3
(LED2 & GPIO)
PG2
14
11
PC3
PC3
PG3
PG3
14
(eMIOS E1UC_12_H)
13
PC4
(FR_B_TX_EN)
PC4
159
PC4
PG4
14
PG4
(LED3 & GPIO)
PG4
14
(eMIOS E1UC_13_H)
(FR_A_TX)
PC5
158
13
PG5
(LED4 & GPIO)
13
PC5
PC5
PG5
PG5
14
(eMIOS E1UC_14_H)
9
PC6
(LIN1_TX)
PC6
44
PC6
PG6
38
PG6
(CLKOUT1 GPIO)
1
PG6
9
PC7
(LIN1_RX)
PC7
45
PC7
PG7
37
PG7
(CLKOUT0 GPIO)
10
PC8
(RS232_TX)
PC8
175
PC8
PG8
34
10
PC9
(RS232_RX)
PC9
2
PC9
PG9
33
1
PG7
(CAN1_TX)
PC10
36
138
PG10
(USB1_D4)
11
9
PC10
(CAN1_RX)
PC11
35
PC10
PG10
139
PG11
(USB1_D5)
PG10
9
PC11
(FR_DBG0)
PC12
173
PC11
PG11
116
PG12
(MII_TXD2)
PG11
11
13
PC12
(FR_DBG1)
PC13
174
PC12
PG12
115
PG13
(MII_TXD3)
PG12
12
13
PC13
(FR_DBG2)
PC14
3
PC13
PG13
134
PG14
(USB1_D0)
PG13
12
13
PC14
PC14
PG14
PG14
11
(FR_DBG3)
PC15
4
135
PG15
(USB1_D1)
B
13
PC15
PC15
PG15
PG15
11
14,15
PD0
(HEX1 & GPIO)
PD0
77
PD0
PH0
117
PH0
(RMII_TXD1)
PH0
12
(HEX2 & GPIO)
PD1
78
118
PH1
(RMII_TXD0)
14,15
PD1
PD1
PH1
PH1
12
(HEX3 & GPIO)
PD2
79
119
PH2
(RMII_TXEN)
14,15
PD2
(HEX4 & GPIO)
PD3
80
PD2
PH2
120
PH2
12
14,15
PD3
PD3
PH3
15
PD4
(GPIO)
PD4
81
PD4
PH4
162
(GPIO)
PD5
82
163
15
PD5
PD5
PH5
(GPIO)
PD6
83
164
15
PD6
PD6
PH6
(GPIO)
PD7
84
165
PD has ADC0 and ADC1
15
PD7
(GPIO)
PD8
87
PD7
PH7
166
15
PD8
PD8
PH8
PH9
(TCK)
15
PD9
(GPIO)
PD9
94
PD9
PH9
155
PH9
5
(GPIO)
PD10
95
148
PH10
(TMS)
15
PD10
PD10
PH10
140
PH11
(USB1_D6)
PH10
5
(GPIO)
PH11
PH11
11
PD12
100
141
PH12
(USB1_D7)
15
PD12
(GPIO)
PD13
102
PD12
PH12
9
PH12
11
15
PD13
(GPIO)
PD14
104
PD13
PH13
10
15
PD14
(GPIO)
PD15
106
PD14
PH14
8
15
PD15
29
PD15
PH15
5
MCU-RSTx
MCU-RSTx
RESET
PORSTx
153
5
PORSTx
PORST
MCU-XTAL
56
Automotive Micro controller
6
MCU-XTAL
XTAL
Applications
MCU-EXTAL
58
East Kilbride, Scotland
A
6
MCU-EXTAL
EXTAL
NXP General Business Use
PPC5748GSK0MKU6
Drawing Title:
MPC5748G-LCEVB
Page Title:
Calypso GPIO 1of2
Size
Document Number
Rev
B
SCH-27899
PDF: SPF-27899
B
Date:
Friday, February 12, 2016
Sheet 7
of
15
D
C
B
A
5 4 3 2 1
5
4
3
2
1
Calypso GPIO 2 of 2
U20C
(GPIO)
PI0
172
Key to text colours:
15
PI0
PI0
Calypso 176QFP
Purple
- Comms Physical Interfaces
15
PI1
(GPIO)
PI1
171
PI1
Orange
- Other Peripherals and I/O
15
PI2
(GPIO)
PI2
170
PI2
Blue
- Debug (JTAG & Nexus)
15
PI3
(GPIO)
PI3
169
PI3
Package 3of3 GPIO Pins2
Black
- Clock, Reset and Control
11
PI4
(USB1_STP)
PI4
143
PI4
D
RED
- I/O Matrix and other functions (eg LED)
11
PI5
(USB1_NXT)
PI5
142
PI5
Green
- I/O Matrix (dedicated)
15
PI6
(GPIO)
PI6
11
PI6
11
PI7
(USB1_RST)
PI7
12
PI7
PI8
108
15
PI8
PI8
(ENET_RST)
PI11
111
12
PI11
PI11
(GPIO)
PI12
112
15
PI12
PI12
15
PI13
(GPIO)
PI13
113
PI13
(GPIO)
PI14
76
15
PI14
PI14
(GPIO)
PI15
75
15
PI15
PI15
74
PJ0
73
PJ1
72
PJ2
71
PJ3
5
PJ4
C
B
Automotive Microcontroller
Applications
A
East Kilbride, Scotland
NXP General Business Use
Drawing Title: MPC5748G-LCEVB
PPC5748GSK0MKU6
Page Title:
Calypso GPIO 2of2
Size
Document Number
Rev
B
SCH-27899
PDF: SPF-27899
B
Date:
Friday, February 12, 2016
Sheet 8
of
15
D
C
B
A
5 4 3 2 1
5
CAN & LIN Physical
D
7
PB0
PB0
PB1
7
PB1
All CAN and LIN signals are
in power domain VDD_HV_A.
All interfaces will work at
3.3V or 5.0V (PER_HVA)
C
7
PC10
PC10
PC11
7
PC11
B
7
PB3
PB3
PB2
7
PB2
7
PC7
PC7
PC6
A
7
PC6
5
4
3
2
1
CAN0 Physical Interface
5V0_SR
PER_HVA
VDD - 5.0V input supply for CAN transceiver (4.5 to 5.5V)
VI/O - determines the signal level on MCU TX and RX pins
C59
C60
C52
C53
0.1UF
0.1UF
and can range from 2.8 to 5.5V
2.2UF
(0603
2.2UF
(0603
STB - High for Standby mode, pulled low for normal mode.
10V
10V
50V)
50V)
CAN termination resistor
footprint. Place on
D
GND
U1
3
5
GND
underside of PCB
(CAN0_TX)
R64
0
CAN0_TX
1
TXD
VD
D
VIO
R1
120
P2
(CAN0_RX)
R63
0
CAN0_RX
4
RXD
CANH
7
CAN0-CANH
DNP
1
HDR_1X3
R51
4.70K CAN0-S
8
STB
CANL
6
CAN0-CANL
2
GN
D
3
TPV16
GND
2
MC33901WEF
GND
GND
CAN1 Physical Interface
5V0_SR
PER_HVA
VDD - 5.0V input supply for CAN transceiver (4.5 to 5.5V)
C57
C58
C50
C51
CAN termination resistor
VI/O - determines the signal level on MCU TX and RX pins
footprint. Place on
2.2UF
0.1UF
2.2UF0.1UF
and can range from 2.8 to 5.5V
10V
(0603
10V
(0603
underside of PCB
C
STB - High for Standby mode, pulled low for normal mode.
50V)
50V)
GND
U2
3
5
GND
(CAN1_TX)
R62
0
CAN1_TX
1
TXD
VD
D
VIO
R2
120
P3
(CAN1_RX)
R59
0
CAN1_RX
4
RXD
CANH
7
CAN1-CANH
DNP
1
HDR_1X3
R50
4.70K CAN1-S
8
STB
CANL
6
CAN1-CANL
2
GN
D
3
TPV15
GND
2
MC33901WEF
GND
GND
LIN0 Physical Interface
Master Mode Pullup Enable
R143
0
Configired as SLAVE by default
DNP
(Lin0 Supports Master and Slave)
J2
DNP
D50
GF1A
R18
2.0K
VSUP2
HDR_1X3
PER_HVA
U6
1
2
A
C
R17
2.0K
P7
B
(LIN0_RX)
R74
0
LIN0-RX
1
8
HDR 1X2
C
A
1
RXD
INH
1
(LIN0_TX)
R75
0
(Enable)
2
7
D51
GF1A
LIN0-VSUP
2
EN
VSUP
(Wake)
3
6
LIN0-LIN
3
WAKE
LIN
LIN0-TX
4
5
TXD
GND
Total current
C70
Battery
3 pin
GND
MC33662BLEF
GND
0.1UF
C69
through resistors
GND
MC33662LEF LIN transceiver is newer version of 33661 offering:
(LEF = 20K Baud)
(0603
2.2UF
Reverse
(LIN Bus at GND)
header
10V
polarity &
= 12mA (0.144W)
(NOT
- Full LIN compliance (33661 no longer compliant)
EN = PER_HVA enables Transceiver and sets I/O for VDD_HV_A
50V)
Pulse
Each resistor spec
Protection
Molex)
- Improved ESD protection on LIN pin up to 15KV
WAKE = GND ensures no spurious wakeups
= 0.1W (0.2W total)
- Improved ESD on Wake and VSUP Pins
GND
- Other EMC and performance improvements
LIN1 Physical Interface
See freescale.com for more details
Master Mode Pullup Enable
Configired as MASTER by default
(Lin1 only supports Master mode)
D52
GF1A
R6
2.0K
VSUP1
HDR_1X3
PER_HVA
U3
R144
0
A
C
R7
2.0K
P6
Automotive Microcontroller
(LIN1_RX)
R60
0
LIN1-RX
1
8
C
A
1
RXD
INH
1
Applications
(LIN1_TX)
R61
0
(Enable)
2
7
D53
GF1A
LIN1-VSUP
2
East Kilbride, Scotland
EN
VSUP
(Wake)
3
6
LIN1-LIN
3
A
(TXD_0)
WAKE
LIN
NXP General Business Use
LIN1-TX
4
5
TXD
GND
C56
Total current
Drawing Title:
MPC5748G-LCEVB
GND
MC33662BLEF
GND
0.1UF
C55
Battery
through resistors
GND
3 pin
(LEF = 20K Baud)
(0603
2.2UF
Reverse
(LIN Bus at GND)
10V
polarity &
= 12mA (0.144W)
header
Page Title:
50V)
Pulse
Each resistor spec
(NOT
CAN and LIN
EN = PER_HVA enables Transceiver and sets I/O for VDD_HV_A
Protection
= 0.1W (0.2W total)
Molex)
WAKE = GND ensures no spurious wakeups
Size
Document Number
Rev
GND
B
SCH-27897
PDF: SPF-27897
B
Date:
Friday, February 12, 2016
Sheet
9
of
15
4
3
2
1
5
4
3
2
1
USB RS232 (serial) Interface
D
All Signals are in
power domain
VDD_HV_A.
FTDI interface will
work at 3.3V or 5.0V
FTDI USB <-> Serial Interface
- Self Powered mode. No power is taken from USB
- Device efaults to Dual serial (RS232) mode i.e. RS232 on both A and
B
- Configurable I/O voltage on CHA / CHB via VDDIOA/B 5V0_SR
D
C
B
(PER_HVA)
P11
S2
-D
2
2
3
3
+D
4
1
4
G
1
V
S1
USB_TYPE_B
5V0_SR
PER_HVA
D3
1
BGX50A
C105
(0603
C101
C115
R119
2
D1
D2
4
0.1UF
50V)
470
0.1UF
0.1UF
(0603
(0603
D4
D3
C114
50V)
50V)
3
0.033UF
U9
46
3
42
14
3
1
GND
GND
24
AVCC
VCC1
VCC2
VCCIOA
VCCIOB
ADBUS0
23
ADBUS1
GND
6
22
3V3OUT
ADBUS2
21
R38 27
ADBUS3
20
USB_N
USB_RN
ADBUS4
8
19
USBDM
ADBUS5
USB_P
USB_RP
17
ADBUS6
R35 27
7
16
USBDP
ADBUS7
C107
C106
R34
ACBUS0
15
13
1.5K
ACBUS1
R39
5
12
RSTOUT#
ACBUS2
47PF
47PF
4.70K
11
ACBUS3
DNP
DNP
4
10
RESET#
SI/WUA
1
1.0
M
CLK_XTIN_6M
BDBUS0
40
GND
X1
43
39
XTIN
BDBUS1
GND
6 MHZ
38
R127
2
CLK_XTOUT_6M 44
BDBUS2
37
XTOUT
BDBUS3
10.0K
36
BDBUS4
35
5V0_SR
R
3
6
BDBUS5
GND
3
33
BDBUS6
48
BDBUS7
32
EECS
GND
1
30
EESK
BCBUS0
2
29
EEDATA
BCBUS1
R118 10.0K
28
BCBUS2
27
BCBUS3
26
47
SI/WUB
TEST
AGND
GND1GND2GND3 GND4
41
PWREN#
45
9
182534
FT2232D
C102
C103
C104
0.1UF
0.1UF
2.2UF
(0603
(0603
10V
50V)
50V)
GND
Send Immediate / Wakeup
Disabled for CHA PER_HVA
R126 10.0K
FTDI_TXD
R116
0
FTDI_RXD
R115
0
Send Immediate / Wakeup
Disabled for CHB
PER_HVA
5V0_SR
R125 10.0K
R117 10.0K
Disable Receiver when
DNP
in USB suspend mode
FTDI Pin 40 (TXD)
is Output from
FTDI Device,
connect to MCU RXD
FTDI Pin 39 (RXD)
is Input to FTDI
device, connect to
MCU TXD
(MCU_LIN2RX)
PC9
PC9
7
(MCU_LIN2TX)
PC8
PC8
7
C
B
A
GND
Automotive Microcontroller
Applications
East Kilbride, Scotland
NXP General Business Use
Drawing Title: MPC5748G-LCEVB
Page Title:
USB RS232 Interface
Size
Document Number
Rev
B
SCH-27897
PDF: SPF-27897
B
Date:
Friday, February 12, 2016
Sheet 10
of
15
A
5 4 3 2 1
D
C
B
A
5
4
3
2
1
USB (Type A Host and Type AB OTG)
USB Signals
3V3_SR
5V0_SR
General Layout Note. Recommendation is to keep all
are in
tracks between MCU and USB PHI less than 3" See
power
Adobe Acrobat
domain
C6
C5
C3
C2
additional SMSC Layout guidelines PDF to the right
Document
10UF
0.1UF
VDD_HV_A
0.1UF
10UF
(Layout Note: Place Series
(0603
(0603
USB Host, Type A
The USB
Termination resistor close
50V)
32
21
50V)
to USB IC)
U50
3V3_SR
(Available on all packages)
interface
only supports
GND
VDDIO
VB
AT
5V
GND
3.3V
7
PG14
PG14
(USB1_DO)
3
DATA0
REFSEL0
8
(Select 60MHz CLKOUT
(Layout Note: Route DP and DM with
USB_TYPE_A_FEMALE
operation.
7
PG15
PG15
(USB1_D1)
4
DATA1
REFSEL1
11
90 Ohm Differential Pair. Keep
P4
7
PE14
(USB1_D2)
5
14
with 24MHz XTAL)
tracks as short as possible)
All I/O
PE14
DATA2
REFSEL2
7
PE15
PE15
(USB1_D3)
6
DATA3
V
D- D+
G
signals must
7
PG10
PG10
(USB1_D4)
7
DATA4
be 3.3V. If
7
PG11
PG11
(USB1_D5)
9
DATA5
CPEN
17
USB_A_EN
S1
S2
VDD_HVA is
7
PH11
PH11
(USB1_D6)
10
DATA6
R73
20K
(20K for HOST)
C54
C67
L50
26OHM
C1
7
PH12
PH12
(USB1_D7)
13
VBUS
22
USB_A_VBUS
2
USB_A_5V A1
set to 5V,
DATA7
(1/10W 0603)
100UF
1.0UF
1
1000pF
USB
MCU pads
7
PC3
PC3
(USB1_DIR)
31
DIR
DM
19
USB_A_DM
(16V
(16V
(0402
USB_A_DM A2
C78
R81
must be left
8
PI4
PI4
(USB1_STP)
29
STP
DP
18
USB_A_DP
TANT)
TANT) 50v)
C66
USB_A_DP A3
8
PI5
PI5
(USB1_NXT)
2
23
(ID=GND for HOST mode)
+
+
+
A4
1000pf
100
as tri-state
USB1_CLK
1
NXT
ID
(1210
7
PC2
PC2
R65
30
CLKOUT
C68
10UF
with no
PI7
(USB1_RST Active Low)
27
VDD3V3_20
20
USB_A_VDD3.3
1000pF
(35V
GND
2KV)
pullups.
8
PI7
RESET
28
GND
TANT)
(50V
33PF Y50
R71
VDD1V8_28
USB_A_VDD1.8
30
A_XO
25
VDD1V8_30
GND
0402)
GND
24MHZ
10
XO
GND
R3
A_XI
26
24
C64
2
REFCLK/XI
RBIAS
10.0K
GND
16
SPK_R
R72
C4
C65
Layout Note:
15
12
SPK_L
PAD
NC
3V3_SR
8.06K
1uF
1uF
Place caps &
Crystals are
33PF
USB83340
1%
(10V
(10V
resistor as
1
FOXSDLF/240F-20
33
0603
0603
close to
(20pF Load
low
low
R70
Capacitance)
ESR)
ESR)
device as
GND
C63
1.0M
GND
GND
GND
GND
possible
5V0_SR
USB_A_EN
1
U5
2
FLG_A
TPV12
C76
ENA
FLGA
C77
0.1UF
4
3
FLG_B
TPV13
10UF
ENB
FLGB
(0603
50V)
7
IN
OUTA
8USB_A_PWR
6
GND
OUTB
5
GND
MIC2026-1YM
USB Power Switch
GND
Automotive Microcontroller
Applications
East Kilbride, Scotland
NXP General Business Use
Drawing Title: MPC5748G-LCEVB
Page Title:
USB Type A / Type AB
Size
Document Number
Rev
B
SCH-27897
PDF: SPF-27897
B
Date:
Friday, February 12, 2016
Sheet 11of
15
D
C
B
A
5 4 3 2 1
D
C
B
5
4
3
2
1
Ethernet (Configured for MII Mode)
All Ethernet Signals are in power
domain VDD_HV_B
The Ethernet
interface only supports
3V3_SR
L51
3V3_SR
120OHM
3.3V operation. All I/O signals must
1
2
be 3.3V. If VDD_HVA is set to 5V,
Layout Note - Place Caps
Ethernet MCU pads must be left as
and Resistors close to PHI
tri-state
with no pullups.
C71
C73
R12
R11
C81
C79
0.1UF
0.1UF
0.1UF
(MII Clock)
10UF
(0603
2.2K
2.2K
(0603
(0603
C15
(Bulk
5%
5%
R13
3V3_SR
Storage)
50V)
50V)
50V)
49.9
33PF
2
2
2
3248
2021
1%
Y1
GND
10/100 single phy
33PF
25MHZ
U8
AVDD33
IOVDD33 1IOVDD332
RSVDPU1RSVDPU2
GND
GND
1
R23
0
C10
3V3_SR
Pulse J1011F21PNL
(RMII)
CLKIN_X1
34
X1
R14
0.1UF
(0603
(Includes built in
C14
(+MII)
X2
33
X2
49.9
transformer)
7
PG13
PG13
R104
50
(+MII)
TXD3
6
25MHZ_OUT
25
TPV17
1%
50V)
1
P5
RJ45-8
TXD3_SNIMODE
TD+
7
PG12
PG12
R105
50
(+MII)
TXD2
5
TXD2
TDP
17
TDP
GND
2
TD-
GND1
CG1
7
PH0
PH0
R106
50
(RMII)
TXD1
4
TXD1
TDN
16
TDN
3
CT_3
7
PH1
PH1
R107
50
(RMII)
TXD0
3
TXD0
4
GND_4
7
PH2
PH2
R108
50
R32
50
(RMII)
TXEN
2
TXEN
14
RDP
5
GND_5
7
PG1
PG1
(RMII)
TXCLK
1
TXCLK
RDP
6
CT_6
dp83848c
13
RDN
3V3_SR
7
GND2
CG2
7
PE13
PE13
R31
50
(+MII)
RXD3
46
RDN
R15
8
RD+
RXD3_PHYAD3
RD-
7
PA7
PA7
R30
50
(+MII)
RXD2
45
RXD2_PHYAD2
49.9
Y
A
Y
C
G
C
G
A
7
PA8
PA8
R29
50
(RMII)
RXD1
44
RXD1_PHYAD1 LEDACTCOL_ANEN
28
LED_Y
1%
7
PA9
PA9
R28
50
(RMII)
RXD0
43
RXD0_PHYAD1
LEDLINK_AN0
26
LED_G
9
1
0
1112
7
PF15
PF15
R24
50
(RMII)
RXDV
39
RXDV_MIIMODE LEDSPEED_AN1
27
GND
GND
7
PA11
PA11
R26
50
(RMII)
RXER
41
RXER_MDIXEN
C11
C8
C7
7
PA10
PA10
R27
50
(+MII)
COL
42
COL_PHYAD0
PFBOUT
23
PFBOUT
0.1UF
0.1UF
0.1UF
7
PE12
PE12
R25
50
(RMII)
CRS
40
CRS/CRS_DV/LED_CFG
18
R16
(0603
(0603
(0603
R4
R5
7
PA3
PA3
R22
50
(+MII)
RXCLK
38
RXCLK
PFBIN1
49.9
37
1%
50V)
50V)
50V)
270
270
7
PG0
PG0
R109
50
(RMII)
MDC
31
MDC
PFBIN2
7
PF14
PF14
MCU Output
PHI Output
(RMII)
(MDIO)
30
MDIO
GND
3V3_SR
3V3_SR
GND
Resistors Next
Place Next to
29
RESET
Place Caps close
to MCU on
PHI
7
PWRDN_INT
RBIAS
24
RBIAS
to connector
daughtercard
AGN
D 1
AGND 2
DGNDIOGND 1IOGND2
RSVD1RSVD2RS VD3RSVD4RSVD5
Series Termination Resistors:
R10
50 Ohms as per TI spec. Place
4.87K
resistors as close to driving
Layout Note:
source as possible. Termination
1915363547
89101
112
recommended for ALL MII signals
Place 0.1uF cap close to each pin.
GND
C72
C74
C75
C80
10uF TANT as close to pin 23 as
RST-OUTx
R82
50
0.1UF
0.1UF
+
0.1UF
possible as shown in diagram below
5
RST-OUTx
GND
(0603
(0603
10UF
(0603
taken from TI device specificaiton
8
PI11
PI11
R83
0
50V)
50V)
(TANT)
50V)
DNP
PFBIN1
PFBIN2
PFBOUT
3V3_SR
Reset Control:
R84
- Reset from MCU Reset Out (will reset with MCU)
GND
10.0K
- Reset from GPIO. Allows MCU to reset PHY as well as hold PHY in reset
while reset config data can be driven onto pins to change mode etc.
D
C
B
A
Boot Configuration (using PHY internal Pulls)
- Auto Negotiation Enable (All speeds / duplex
supported) (AN_EN, AN0 and AN1 all Internal PullUP)
- Operating Mode (MII)
(SNI_Mode Internal PullDown, MII_Mode control via PF15)
- LED Configuraiton (Mode1)
(LED_CFG Internal PullUp)
- MDIX Enable (Auto MDIX Enabled)
(MDIX_EN Internal PullUP)
- Physical Address (set to 0b00001)
(PHYAD[0] Internal PullUp, PHYAD[1..4] Internal PullDown)
Layout Note:
R110
PF15
2.2K
5%
(MII_MODE)
GND Configured for MII Mode
3V3_SR MDIO Pullup
R113 1.5K PF14
Automotive Microcontroller
Applications
East Kilbride, Scotland
NXP General Business Use
Drawing Title: MPC5748G-LCEVB
A
MII Mode resistor and the MDIP ullup resistor should be placed as close as possible to
the PF15 / PF14 tracks to reduce the effect of a stub on the transmission line.
Page Title:
Ethernet
Size
Document Number
Rev
B
SCH-27897
PDF: SPF-27897
B
Date:
Friday, February 12, 2016
Sheet 12
of
15
5 4 3 2 1
D
C
5
4
3
2
1
FlexRAY Physical Interface
All Signals are in
Note on VBAT:
Decoupling Caps for BOTH IC's. Place next to power pins.
power domain VDD_HV_A.
- Operational range is 6.5v to 60V
FlexRAY interface will
FlexRAY
- Undervoltage detection is max 4.5v
FRBATA
FRBATB
5V0_SR
PER_HVA
On EVB this is supplied from 5v, In theory this
debug
work at 3.3V or 5.0V
connector
should be to battery with 60uS delay between
applying Vbat and I/O voltages. If necessary,
(PER_HVA)
(FR_DBG0)
P9
(FR_DBG1)
12V can be externally supplied by removing the
7
PC12
PC12
1
2
resistor and connecting pad to 12v
C85
C84
C83
C82
7
PC14
PC14
(FR_DBG2)
3
4
(FR_DBG3)
C89
C88
C87
C86
0.1UF
0.1UF
0.1UF
0.1UF
PER_HVA
10UF
10UF
10UF
10UF
(0603
(0603
(0603
(0603
PC15
DNP
5V0_SR
FRBATA
7
PC15
50V)
50V)
50V)
50V)
PC13
R21
0
FRB2
7
PC13
VBAT
VBUF
VCC
VIO
GND
7
PC5
(FR_A_TX)
R120
0
FRA-JTXD
U7
4192014
PC5
7
PE2
PE2
(FR_A_TX_EN)
R90
0
FRA-JTXEN
VIOVCCVBUF
VBAT
7
PE3
PE3
(FR_A_RX)
R89
0
FRA-JRXD
GND
1
FRA-INH2
R33
C16
11
TRXD0
INH2
TPV9
10
2
FRA-INH1
47.0
10PF
TRXD1
INH1
TPV7
C91
1%
P10
PER_HVA
5
18
FRA-BP
1
L2
2
(0603)
BGE: Bus Guardian Enable. Pull
TXD
BP
FRA-DATA-A
4700PF
1
6
17
(50V 0805)
2
TXEN
BM
high to enable transmitter
R88
10.0K
FRA-BGE
8
FRA-BM
4
3
FRA-DATA-B
STBN: Standby Input. Pull High
R87
10.0K
FRA-STBN
9
BGE
7
DLW43SH
STBN
RXD
FRA-ERRN
R19
C12 GND
Crimped lead - 279-9522
R121
10.0K
FRA-EN
3
13
for non standby mode
R91
10.0K
EN
ERRN
12
FRA-RXEN
TPV1
47.0
10PF
Receptacle housing - 279-9156
EN: Enable Input. PUll high to
FRA-WAKE 15
WAKE
GND
RXEN
TPV4
1%
(0603)
enable
GND
TJA1080TS/N
16
Bus voltage +/- 12V (VBAT = 12v)
FlexRAY A
GND
Components spec'd for 12V operation
D
C
B
A
FlexRAY B
7
PE4
PE4
(FR_B_TX)
R85
0
FRB-JTXD
7
PC4
PC4
(FR_B_TX_EN)
R79
0
FRB-JTXEN
7
PE5
PE5
(FR_B_RX)
R78
0
FRB-JRXD
PER_HVA
R77
10.0K
R76
10.0K
R86
10.0K
R80
10.0K
GND
PER_HVA 5V0_SR
R9
0
U4
4
19
20
14
VIOVCCVBUF
VBAT
GND
11
TRXD0
INH2
1
10
2
5
TRXD1
INH1
18
TXD
BP
6
17
TXEN
BM
FRB-BGE
8
BGE
FRB-STBN
9
STBN
RXD
7
FRB-EN
3
13
EN
ERRN
12
FRB-WAKE 15
RXEN
WAKE
GND
16
TJA1080TS/N
GND
MODE
EN
STBN
Normal
1
1
Rec Only
0
1
Go to Sleep
1
0
Sleep
0
0
FRBATB
FRB1
FRB-INH2
TPV8
FRB-INH1
TPV6
L1
FRB-BP
1
2
FRB-DATA-A
FRB-BM
4
FRB-DATA-B
3
DLW43SH
FRB-ERRN TPV2
FRB-RXEN TPV3
R20
C13
47.0 10PF
1%
C90
(0603)
P8
4700PF
1
(50V
0805)
2
R8
C9
GND
Crimped lead - 279-9522
47.0
10PF
Receptacle housing - 279-9156
1%
(0603)
Bus voltage +/- 12V (VBAT = 12v)
Components spec'd for 12V operation
Automotive Microcontroller
Applications
East Kilbride, Scotland
NXP General Business Use
Drawing Title: MPC5748G-LCEVB
Page Title:
FlexRAY Physical Interface
Size
Document Number
Rev
B
SCH-27897
PDF: SPF-27897
B
Date:
Friday, February 12, 2016
Sheet 13
of
15
B
A
5 4 3 2 1
5
4
3
2
1
User Peripheralls (Led's, Switches and ADC Pot)
Switches are hard wired to 3.3V rather than 5V so it's not possible to drive 5V into a 3.3V pad (which would cause damage)
Similarly, the LED's are active low with 3.3v supply so can be safely coupled to pads on either 3.3V or 5V domains
The ADC input is limited to 3.3V, again to prevent driving 5V into a 3.3V pad which would cause damage
D
User LED's (Active Low)
ADC Input Pot and Test Point
PG[2..5] share eMIOS1
3V3_SR
3V3_SR
C DS1
UC[11..14] with PWM
A
R129
270
functionality
DS2
R133
270
3
RV1 2K
1
Current limit resistors to ensure
7
PG2
PG2
(USR_LED1)
C
A
injection spec of 5mA is not
7
PG3
PG3
(USR_LED2)
2
RVAR
exceeded
7
PG4
PG4
(USR_LED3)
DS3
R131
270
GND
7
PG5
PG5
(USR_LED4)
C
A
1
R40
1.5K
DS4
R130
270
(ADC1_P[0])
PB4
PB4
7
C
A
LED's are SMD (1206) Yellow
R146
1.5K
Note that LED2 and LED4 (PG3 and PG5) can be
controlled in LPU_RUN mode (and also have pad
keepers in LPU_STANDBY)
Hex Encoded Switch (Active High)
C
3V3_SR
R92
SW1
1
(HEX_SW1)
PD0
PD0
7,15
C
B C D
E
A
2
(HEX_SW2)
PD1
PD1
7,15
100
9
F
8
0
4
(HEX_SW3)
PD2
PD2
7,15
1
7
6
5 4 3
2
8
(HEX_SW4)
PD3
PD3
7,15
DRS4016
R93
10.0K
R94
10.0K
R95
10.0K
R96
10.0K
GND
B
User Pushbutton Switches (Active High)
Note - PA1 is
3V3_SR
SW4
also the NMI pin!
1
2
(PB_SW1)
(eMIOS H / X)
PA1
PA1
7,15
1
2
(PB_SW2)
(eMIOS G / X)
PA2
PA2
7,15
R132
10.0K
SW5
R128
10.0K
OMRON B3WN-6002 Pushbutton Switch
GND
Automotive Microcontroller
Applications
A
East Kilbride, Scotland
NXP General Business Use
Drawing Title: MPC5748G-LCEVB
Page Title:
User Peripherals
Size
Document Number
Rev
B
SCH-27897
PDF: SPF-27897
B
Date:
Friday, February 12, 2016
Sheet 14
of
15
D
C
B
A
5 4 3 2 1
5
4
3
2
1
GPIO Pin Matrix
All pads are DNP (Do Not Populate) 0.1" pitch headers placed on a 0.1" grid
7
PA0
PA0
PA1
PA[1,2] shared with
7,14
PA1
PORTA
PORTB
PORTD
PortF
PortI
PA2
7,14
PA2
user switches
7
PA4
PA4
D
7
PA5
PA5
1
1
1
1
PA6
PA0
PD0
PF0
PI0
7
PA6
PA12
IOM1
IOM5
IOM10
IOM15
7
PA12
1
1
1
1
PA13
PA1
PD1
PF1
PI1
7
PA13
PA14
IOM2
IOM6
IOM11
IOM16
7
PA14
1
1
1
1
PA15
PA2
PD2
PF2
PI2
7
PA15
IOM3
IOM7
IOM12
IOM17
1
1
1
7
PB5
PB5
PD3
PF3
PI3
PB6
IOM8
IOM13
IOM18
7
PB6
1
1
1
PB7
PA4
PD4
PF4
7
PB7
PB10
IOM4
IOM9
IOM14
7
PB10
1
1
1
1
PB11
PA5
PB5
PD5
PF5
7
PB11
PB12
IOM19
IOM21
IOM24
IOM29
7
PB12
1
1
1
1
1
PB13
PA6
PB6
PD6
PF6
PI6
7
PB13
PB14
IOM20
IOM22
IOM25
IOM30
IOM34
7
PB14
1
1
1
PB15
PB7
PD7
PF7
7
PB15
IOM23
IOM26
IOM31
1
1
1
7,14
PD0
PD0
PD8
PF8
PI8
PD1
IOM27
IOM32
IOM35
7,14
PD1
1
1
PD2
PD9
PF9
7,14
PD2
PD3
IOM28
IOM33
PD[0..3] shared with
7,14
PD3
1
1
1
PD4
PB10
PD10
PF10
7
PD4
Hex Switch
7
PD5
PD5
IOM39
1
IOM44
IOM48
1
PD6
PB11
PF11
7
PD6
PD7
IOM40
IOM49
C
7
PD7
1
1
1
1
1
PD8
PA12
PB12
PD12
PF12
PI12
7
PD8
PD9
IOM36
IOM41
IOM45
IOM50
IOM52
7
PD9
1
1
1
1
1
PD10
PA13
PB13
PD13
PF13
PI13
7
PD10
PD12
IOM37
IOM42
IOM46
IOM51
IOM53
7
PD12
1
1
1
1
PD13
PA14
PB14
PD14
PI14
7
PD13
PD14
IOM38
IOM43
IOM47
IOM54
7
PD14
1
1
1
1
PD15
PA15
PB15
PD15
PI15
7
PD15
IOM55
IOM56
IOM57
IOM58
PF0
7
PF0
PF1
7
PF1
PF2
7
PF2
PF3
7
PF3
TPH4
TPH5
TPH6
TPH7
TPH8
PF4
7
PF4
PF5
7
PF5
PF6
7
PF6
PF7
7
PF7
1
1
1
1
1
PF8
7
PF8
PF9
7
PF9
PF10
7
PF10
PF11
7
PF11
5 GND Pads (one at bottom of each colum)
PF12
GND
7
PF12
PF13
7
PF13
B
8
PI0
PI0
Layout Notes:
PI1
8
PI1
8
PI2
PI2
Pads must be placed in a 5 (W) x 16(H) matrix pattern, 2.54 mm pitch
PI3
8
PI3
PI6
- one column for each port
8
PI6
PI8
- 16 tall (1 row for each port number from 0 to 15).
8
PI8
8
PI12
PI12
- GND pad at bottom of each colum
PI13
8
PI13
- After production, pads should be through hole (not solder filled)
PI14
8
PI14
PI15
8
PI15
Automotive Microcontroller
Applications
A
East Kilbride, Scotland
NXP General Business Use
Drawing Title: MPC5748G-LCEVB
Page Title:
GPIO Pin Matrix
Size
Document Number
Rev
B
SCH-27897
PDF: SPF-27897
B
Date:
Friday, February 12, 2016
Sheet 15
of
15
D
C
B
A
5 4 3 2 1
9. Revision History
Date
Substantial changes
March 2016
Initial release
August 2016
Rev. 1: Updated Schematics and Board Pictures
MPC5748G Low Cost EVB User Guide, Rev. 1, 08/2016
34 NXP Semiconductors
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Document Number: MPC5748GLCEVBUG
Rev. 1 08/2016