DAC7545GLP - Texas Instruments

CMOS 12-Bit Multiplying

DIGITAL-TO-ANALOG CONVERTER

Microprocessor Compatible

FEATURES

●FOUR-QUADRANT MULTIPLICATION

●LOW-GAIN TC: 2ppm/°C typ

●MONOTONICITY ENSURED OVER TEMPERATURE

●SINGLE 5V TO 15V SUPPLY

●TTL/CMOS LOGIC COMPATIBLE

●LOW OUTPUT LEAKAGE: 10nA max

●LOW OUTPUT CAPACITANCE: 70pF max

●DIRECT REPLACEMENT FOR THE AD7545,

PM-7545

DESCRIPTION

The DAC7545 is a low-cost, CMOS, 12-bit, four-quadrant

multiplying, digital-to-analog converter (DAC) with input data

latches. The input data is loaded into the DAC as a 12-bit

data word. The data flows through to the DAC when both the

chip select (

) and the write (

) pins are at a logic low.

Laser-trimmed thin-film resistors and excellent CMOS volt-

age switches provide true 12-bit integral and differential

linearity. The device operates on a single +5V to +15V supply

and is available in an SO-20 package; devices are specified

over the commercial temperature range.

The DAC7545 is well suited for battery-powered or other low-

power applications because the power dissipation is less than

0.5mW when used with CMOS logic inputs and VDD = +5V.

12-Bit

Multiplying DAC AGND

OUT 1

-DB

(Pins 4-15)

17 Input

Data Latches

REF

DGND

SBAS150A – AUGUST 1987 – REVISED FEBRUARY 2003

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DAC7545

2SBAS150A

www.ti.com

ABSOLUTE MAXIMUM RATINGS(1)

TA = +25°C, unless otherwise noted.

VDD to DGND ...........................................................................–0.3V, +17

Digital Input to DGND ............................................................... –0.3V, VDD

VRFB, VREF, to DGND ........................................................................ ±25V

VPIN 1 to DGND ........................................................................ –0.3V, VDD

AGND to DGND ........................................................................ –0.3V, VDD

Power Dissipation: Any Package to +75°C .................................... 450mW

Derates above +75°C by................................ 6mW/°C

Operating Temperature:

Commercial J, K, L, and GL........................................... –40°C to +85°C

Storage Temperature...................................................... –65°C to +150°C

Lead Temperature (soldering, 10s) ............................................... +300°C

NOTE: (1) Stresses above those listed above may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at

these or any other condition above those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect device reliability.

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-

ments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet its

published specifications.

SPECIFIED

RELATIVE GAIN ERROR (LSB) PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT ACCURACY (LSB) VDD = +5V PACKAGE-LEAD DESIGNATOR(1) RANGE MARKING NUMBER MEDIA, QUANTITY

DAC7545 ±2±20 SO-20 DW –40°C to +85°C DAC7545JU DAC7545JU Rails, 38

"±1±10 " " " DAC7545KU DAC7545KU Rails, 38

DAC7545 ±1/2 ±5 SO-20 DW –40°C to +85°C DAC7545LU DAC7545LU Rails, 38

"±1/2 ±2 " " " DAC7545GLU DAC7545GLU Rails, 38

NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.

PACKAGE/ORDERING INFORMATION

PIN CONNECTIONS

DAC7545

OUT 1

AGND

DGND

(MSB) DB11

DB10

DB9

DB8

DB7

DB6

DB5

RFB

VREF

VDD

DB0 (LSB)

DB1

DB2

DB3

DB4

Top View SO

WRITE CYCLE TIMING DIAGRAM

Mode Selection

Write Mode Hold Mode

and

low, DAC responds Either

high, data bus to

Data Bus (DB0-DB11) inputs. (DB0-DB11) is locked out; DAC

holds last data present when

assumed high state.

NOTES: VDD = +5V, tR = tF = 20ns. VDD = +15V, tR = tF = 40ns. All inputs signal

rise and fall times measured from 10% to 90% of VDD. Timing measurement

reference level is (VIH + VIL)/2.

VIH

VIL

Data

Valid

Data In

(DB

-DB

)

DAC7545 3

SBAS150A www.ti.com

ELECTRICAL CHARACTERISTICS

VREF = +10V, VOUT 1 = 0V, and ACOM = DCOM, unless otherwise specified.

NOTES: (1) Temperature ranges—J, K, L, and GL: –40°C to +85°C. (2) This includes the effect of 5ppm max, gain TC. (3) Ensured but not tested. (4) DB0-DB11 = 0V

to VDD or VDD to 0V. (5) Typical. (6) Minimum. (7) Logic inputs are MOS gates. Typical input current (+25°C) is less than 1nA. (8) Sample tested at +25°C to ensure

compliance.

DAC7545

VDD = +5V VDD = +15V

PARAMETER GRADE TA = +25°CT

MAX-TMIN(1) TA = +25°CT

MAX-TMIN(1) UNITS TEST CONDITIONS/COMMENTS

STATIC PERFORMANCE

Resolution All 12 12 12 12 Bits

Accuracy J ±2±2±2±2LSB

K ±1±1±1±1LSB

L±1/2 ±1/2 ±1/2 ±1/2 LSB

GL ±1/2 ±1/2 ±1/2 ±1/2 LSB

Differential Nonlinearity J ±4±4±4±4 LSB 10-Bit Monotonic, TMIN to TMAX

K±1±1±1±1 LSB 10-Bit Monotonic, TMIN to TMAX

L±1±1±1±1 LSB 12-Bit Monotonic, TMIN to TMAX

GL ±1±1±1±1 LSB 12-Bit Monotonic, TMIN to TMAX

Gain Error (with internal RFB)(2) J±20 ±20 ±25 ±25 LSB DAC register loaded with FFFH.

K±10 ±10 ±15 ±15 LSB Gain error is adjustable using

L±5±6±10 ±10 LSB the circuits in Figures 2 and 3.

GL ±2±3±6±7LSB

Gain Temperature Coefficient(3)

(∆Gain/∆Temperature) All ±5±5±10 ±10 ppm/°C Typical Value is 2ppm/°C

for VDD = +5

DC Supply Rejection(3)

(∆Gain/∆VDD) All 0.015 0.03 0.01 0.02 %/% ∆VDD ± 5%

Output Leakage Current at Out 1 J, K, L, GL 10 50 10 50 nA DB0-DB11 = 0V; WR, CS = 0V

DYNAMIC PERFORMANCE

Current Settling Time(3) All 2 2 2 2 µs To 1/2 LSB. Out 1 Load = 100Ω

DAC output measured from

falling edge of WR. CS = 0V.

Propagation Delay(3) (from digital input All

change to 90% of final analog output) 300 250 ns Out 1 Load = 100Ω. CEXT = 13pF(4)

Glitch Energy All 400 250 nV-s(5) VREF = ACOM

AC Feedback at IOUT 1 All 5 5 5 5 mVp-p(5) VREF = ±10V, 10kHz Sine Wave

REFERENCE INPUT

Input Resistance (pin 19 to AGND) All 7 7 7 7 kΩ(6)

Input Resistance TC = 300ppm/°C

(5)

25 25 25 25 kΩ

AC OUTPUTS

Output Capacitance(3): COUT 1 All 70 70 70 70 pF DB0-DB11 = 0V; WR, CS = 0V

COUT 2 All 200 200 200 200 pF DB0-DB11 = VDD; WR, CS = 0V

DIGITAL INPUTS

VIH (Input HIGH Voltage) All 2.4 2.4 13.5 13.5 V(6)

VIL (Input LOW Voltage) All 0.8 0.8 1.5 1.5 V

IIN (Input Current)(7) All ±1±10 ±1±10 µAV

IN = 0V or VDD

Input Capacitance(3): DB0-DB11 All 5 5 5 5 pF VIN = 0V

WR, CS All 20 20 20 20 pF VIN = 0V

SWITCHING CHARACTERISTICS(8)

Chip Select to Write Setup Time, tCS All 280 380 180 200 ns(6) See Timing Diagram

200 270 120 150 ns(5)

Chip Select to Write Hold Time, tCH All 0 0 0 0 ns(6)

Write Pulse Width, tWR All 250 400 160 240 ns(6) tCS ≥ tWR, tCH ≥ 0

175 280 100 170 ns(5)

Data Setup Time, tDS All 140 210 90 120 ns(6)

100 150 60 80 ns(5)

Data Hold Time, tDH All 10 10 10 10 ns(6)

POWER SUPPLY, IDD All 2 2 2 2 mA All Digital Inputs VIL or VIH

All 100 500 100 500 µA All Digital Inputs 0V or VDD

All 10 10 10 10 µA(5) All Digital Inputs 0V or VDD

DAC7545

4SBAS150A

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FIGURE 1. Simplified DAC Circuit of the DAC7545.

2R 2R

2R RFB

OUT 1

AGND

DB0

(LSB)

DB9DB10DB11

(MSB)

VREF

MONOTONICITY

Monotonicity assures that the analog output will increase

or stay the same for increasing digital input codes. The

DAC7545 is ensured monotonic to 12 bits, except the

J grade is specified to be 10-bit monotonic.

POWER-SUPPLY REJECTION

Power-supply rejection is the measure of the sensitivity of the

output (full-scale) to a change in the power-supply voltage.

CIRCUIT DESCRIPTION

Figure 1 shows a simplified schematic of the DAC portion of

the DAC7545. The current from the VREF pin is switched from

OUT 1 to AGND by the FET switch. This circuit architecture

keeps the resistance at the reference pin constant and equal

to RLDR, so the reference can be provided by either a voltage

or current, AC or DC, positive or negative polarity, and have

a voltage range up to ±20V even with VDD = 5V. The RLDR is

equal to R and is typically 11kW.

The output capacitance of the DAC7545 is code dependent

and varies from a minimum value (70pF) at code 000h to a

maximum (200pF) at code FFFh.

The input buffers are CMOS inverters, designed so that

when the DAC7545 is operated from a 5V supply (VDD), the

logic threshold is TTL-compatible. Being simple CMOS in-

verters, there is a range of operation where the inverters

operate in the linear region and thus draw more supply

current than normal. Minimizing this transition time through

the linear region and insuring that the digital inputs are

operated as close to the rails as possible will minimize the

supply drain current.

DISCUSSION OF

SPECIFICATIONS

RELATIVE ACCURACY

This term (also known as end point linearity) describes the

transfer function of analog output to digital input code.

Relative accuracy describes the deviation from a straight line

after zero and full-scale have been adjusted.

DIFFERENTIAL NONLINEARITY

Differential nonlinearity is the deviation from an ideal 1LSB

change in the output, for adjacent input code changes. A

differential nonlinearity specification of 1LSB ensures mono-

tonicity.

GAIN ERROR

Gain error is the difference in measure of full-scale output

versus the ideal DAC output; the ideal output for the DAC7545

is –(4095/4096)(VREF). Gain error can be adjusted to zero

using external trims, see the Applications section.

OUTPUT LEAKAGE CURRENT

The current that appears at OUT 1 with the DAC loaded with

all zeros.

MULTIPLYING FEEDTHROUGH ERROR

The AC output error due to capacitive feedthrough from VREF

to OUT 1 with the DAC loaded with all zeros; this test is

performed using a 10kHz sine wave.

OUTPUT CURRENT SETTLING TIME

The time required for the output to settle within ±0.5 LSB

of final value from a change in code of all zeros to all ones,

or all ones to all zeros.

PROPAGATION DELAY

The delay of the internal circuitry is measured as the time

from a digital code change to the point at which the

output reaches 90% of final value.

DIGITAL-TO-ANALOG GLITCH IMPULSE

The area of the glitch energy measured in nanovolt-seconds.

Key contributions to glitch energy are internal circuitry timing

differences and charge injected from digital

logic. The measurement is performed with VREF = GND,

an OPA600 as the output op amp, and G1 (phase

compensation) = 0pF.

DAC7545 5

SBAS150A www.ti.com

APPLICATIONS

UNIPOLAR OPERATION

Figure 2 shows the DAC7545 connected for unipolar opera-

tion. The high-grade DAC7545 is specified for a 1LSB gain

error, so gain adjust is typically not needed; however, the

resistors shown are for adjusting full-scale errors. The value

of R1 should be minimized to reduce the effects of mismatch-

ing temperature coefficients between the internal and exter-

nal resistors. A range of adjustment of 1.5 times the desired

range will be adequate. For example, for a DAC7545JP, the

gain error is specified to be ±25LSB, therefore, a range of

adjustment of ±37LSB will be adequate. Equation 1 results in

a value of 458W for the potentiometer (use 500Ω).

RRGainError

LADDER

4096 3=

(

)

•

(1)

FIGURE 2. Unipolar Binary Operation.

BINARY CODE ANALOG OUTPUT

MSB LSB

1111 1111 1111 –VIN (4095/4096)

1000 0000 0000 –VIN (2048/4096) = –1/2VIN

0000 0000 0001 –VIN (1/4096)

0000 0000 0000 0V

TABLE I. Unipolar Codes.

OPA604

VIN

VDD RFB

DAC7545 AGND

DGND

OUT 1

DB0-DB11

33pF

+5V

VOUT

VREF

R3, R4, and R5 must match within 0.01% and must be the

same type of resistors (preferably wire-wound or metal foil),

so that the temperature coefficients match; mismatch of R3

value to R4 causes both offset and full-scale error. Mismatch

of R5 to R4 and R3 causes full-scale error.

FIGURE 3. Bipolar Operation (binary two’s complement code).

OPA604

1/2 OPA2604

VIN

VDD RFB

DAC7545 AGND

DB10-DB0

OUT 1

Data Input

33pF

+5V

DB11

VREF VOUT

10kΩ

20kΩ

5kΩ 10%

(see text) 12

Analog Common

18 20

4OPA604

1/2 OPA2604

DATA INPUT ANALOG OUTPUT

MSB LSB

0111 1111 1111 +VIN (2047/2048)

0000 0000 0001 +VIN (1/2048)

0000 0000 0000 0V

1111 1111 1111 –VIN (1/2048)

1000 0000 0000 –VIN (2048/2048)

TABLE II. Binary Two’s Complement Code Table for Circuit

of Figure 3.

tance. Eliminating this capacitor will result in excessive ringing

and an increase in glitch energy, therefore, this capacitor must

be as small as possible to minimize settling time.

The circuit of Figure 2 can be used with input voltages up to

±20V as long as the output amplifier is biased to handle the

excursions. Table I represents the analog output for four

codes into the DAC for Figure 2.

BIPOLAR OPERATION

Figure 3 and Table II illustrate the recommended circuit and

code relationship for bipolar operation. The DAC function uses

offset binary code. The inverter, U

, on the MSB line converts

binary two’s complement input code to offset binary code. If the

inversion is done in software, U

can be omitted.

The addition of R1 will cause a negative gain error. To

compensate for this error, R2 must be added. The value of R2

should be one-third the value of R1.

The capacitor across the feedback resistor is used to compen-

sate for the phase shift due to stray capacitances of the circuit

board, the DAC output capacitance, and op amp input capaci-

DAC7545

6SBAS150A

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FIGURE 5. 8-Bit Processor Interface.

DAC7545

DB0

DB7

DB8

DB11

Latch

Q1(2)

8-Bit Data Bus

Q0(1)

Address Bus

Address

Decode

CPU

DB7

DB0

A15

NOTES: (1) Q0 = decoded address for DAC.

(2) Q1 = decoded address for latch.

FIGURE 4. Digitally Controlled Gain Block.

DAC7545 AGND

DGND

OUT

-DB

OUT

+5V

NOTE: There must be

at least 1LSB loaded in

the DAC or the amp will

saturate due to the lack

of feedback.

OPA111

OUT

=–V

2DB

4DB

+ ••• +

8DB

4096

DIGITALLY-CONTROLLED GAIN BLOCK

Figure 4 shows a circuit for a digitally-controlled gain block.

The feedback for the op amp is made up of the FET switch

and the R-2R ladder. The input resistor to the gain block is

the RFB of the DAC7545. As the FET switch is in the

feedback loop, a zero code into the DAC will result in the op

amp having no feedback, and a saturated op amp output.

APPLICATION HINTS

CMOS DACs, such as the DAC7545, exhibit a code-depen-

dent out resistance. The effect of this is a code-dependent

differential nonlinearity at the amplifier output t h at depends on

the offset voltage, V

, of the amplifier. Thus linearity depends

upon the potential of OUT 1 and AGND being exactly equal to

each other. Usually the DAC is connected to an external op

amp with the noninverting input connected to AGND. The op

amp selected should have a low input bias current and low V

and V

drift over temperature. The op amp offset voltage

should be less than (25 • 10

–6

)(V

REF

) over operating conditions.

Suitable op amps are the OPA37 and the OPA627 for fixed

reference applications and low-bandwidth requirement; the

OPA37 has low V

and does not require an offset trim. For

wide bandwidth, high slew rate, or fast-settling applications, the

OPA604 or 1/2 OPA2604 are recommended.

Unused digital inputs must be connected to VDD or to DGND,

this prevents noise from triggering the high impedance digital

input. It is suggested that the unused digital inputs also be

given a path to ground or VDD through a 1mW resistor to

prevent the accumulation of static charge if the PC card is

unplugged from the system. In addition, in systems where

the AGND to DGND connection is on a backplane, it is

recommended that two diodes be connected in inverse

parallel between AGND and DGND.

INTERFACING

TO MICROPROCESSORS

The DAC7545 can be directly interfaced to either an 8- or 16-

bit microprocessor through its 12-bit wide data latch using

the

and

controls.

An 8-bit processor interface is shown in Figure 5. It uses two

memory addresses: one for the lower 8 bits and one for the

upper 4 bits of data into the DAC via the latch.

DAC7545 7

SBAS150A www.ti.com

PACKAGE DRAWING

DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

16 PINS SHOWN

4040000/E 08/01

Seating Plane

0.400 (10,15)

0.419 (10,65)

0.104 (2,65) MAX

0.012 (0,30)

0.004 (0,10)

0.020 (0,51)

0.014 (0,35)

0.291 (7,39)

0.299 (7,59)

0.010 (0,25)

0.050 (1,27)

0.016 (0,40)

(15,24)

(15,49)

PINS **

0.010 (0,25) NOM

A MAX

DIM

A MIN

Gage Plane

0.500

(12,70)

(12,95)

0.510

(10,16)

(10,41)

0.400

0.410

0.600

0.610

(17,78)

0.700

(18,03)

0.710

0.004 (0,10)

0.010 (0,25)

0.050 (1,27)

0° – 8°

(11,51)

(11,73)

0.453

0.462

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).

D. Falls within JEDEC MS-013

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

DAC7545GLP OBSOLETE ZZ (BB) ZZ222 20 TBD Call TI Call TI

DAC7545GLU NRND SOIC DW 20 25 Green (RoHS &