NT512T64UH4D0FY / NT1GT64U88D0BY / NT2GT64U8HD0BY 512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64 Unbuffered DDR2 SDRAM DIMM 240pin Unbuffered DDR2 SDRAM MODULE Based on 64Mx16 DDR2 SDRAM D-die (512MB) Based on 128Mx8 DDR2 SDRAM D-die (1GB/2GB) Features Performance: PC2-5300 PC2-6400 PC2-6400 Speed Sort -3C -AD -AC DIMM Latency 5 6 5 333 400 400 3 2.5 2.5 ns 667 800 800 Mbps fCK Clock Frequency tCK Clock Cycle fDQ DQ Burst Frequency * JEDEC Standard 240-pin Dual In-Line Memory Module * 64Mx64 DDR2 Unbuffered DIMM based on Nanya 64Mx16 DDR2 SDRAM D-die component - (512MB) * 128Mx64 and 256Mx64 DDR2 Unbuffered DIMM based on Nanya 128Mx8 DDR2 SDRAM D-die component - (1GB/2GB) * Double Data Rate architecture; two data transfer per clock cycle * Differential bi-directional data strobe (DQS & ) * DQS is edge-aligned with data for reads and is center-aligned with data for writes * Differential clock inputs (CK & ) * Intended for 333MHz/400MHz applications * Inputs and outputs are SSTL-18 compatible * VDD = VDDQ = 1.8V 0.1V * 7.8 s Max. Average Periodic Refresh Interval Unit MHz * Programmable Operation: - Device Latency: 3, 4, 5 (-3C/-AC); 4, 5, 6 (-AD) - Burst Length: 4, 8 * Auto Refresh (CBR) and Self Refresh Modes * Automatic and controlled precharge commands * 13/10/1 Addressing (row/column/rank) - 512MB * 14/10/1 Addressing (row/column/rank) - 1GB * 14/10/2 Addressing (row/column/rank) - 2GB * Serial Presence Detect * On Die Termination (ODT) * OCD impedance adjustment * Gold contacts * SDRAMs in 84-ball BGA Package - 512MB * SDRAMs in 60-ball BGA Package - 1GB/2GB * RoHs Compliance Description NT512T64UH4D0FY, NT1GT64U88D0BY and NT2GT64U8HD0BY are 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Unbuffered Dual In-Line Memory Module (UDIMM), organized as one rank 64Mx64 (512MB), one rank 128Mx64 (1GB) and two ranks 256Mx64 (2GB) high-speed memory array. NT512T64UH4D0FY use four 64Mx16 DDR2 SDRAMs, NT1GT64U88D0BY use eight 128Mx8 DDR2 SDRAMs and NT2GT64U8HD0BY use sixteen 128Mx8 DDR2 SDRAMs in BGA packages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint. The DIMM is intended for use in applications operating up to 333MHz (or 400MHz) clock speeds and achieves high-speed data transfer rates of up to 667Mbps (or 800Mbps). Prior to any access operation, the device latency and burst / length /operation type must be programmed into the DIMM by address inputs A0-A12 (512MB) / A0-A13 (1GB/2GB) and I/O inputs BA0, BA1 and BA2 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. REV 1.0 03/2008 1 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64UH4D0FY / NT1GT64U88D0BY / NT2GT64U8HD0BY 512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64 Unbuffered DDR2 SDRAM DIMM Ordering Information Part Number Speed Organization NT512T64UH4D0FY-3C 333MHz (3.00ns @ CL = 5) DDR2-667 PC2-5300 NT512T64UH4D0FY-AD 400MHz (2.50ns @ CL = 6) DDR2-800 PC2-6400 NT512T64UH4D0FY-AC 400MHz (2.50ns @ CL = 5) DDR2-800 PC2-6400 NT1GT64U88D0BY-3C 333MHz (3.00ns @ CL = 5) DDR2-667 PC2-5300 NT1GT64U88D0BY-AD 400MHz (2.50ns @ CL = 6) DDR2-800 PC2-6400 NT1GT64U88D0BY-AC 400MHz (2.50ns @ CL = 5) DDR2-800 PC2-6400 NT2GT64U8HD0BY-3C 333MHz (3.00ns @ CL = 5) DDR2-667 PC2-5300 NT2GT64U8HD0BY-AD 400MHz (2.50ns @ CL = 6) DDR2-800 PC2-6400 NT2GT64U8HD0BY-AC 400MHz (2.50ns @ CL = 5) DDR2-800 PC2-6400 Leads Power GOLD 1.8V Note 64Mx64 128Mx64 256Mx64 Pin Description CK0~CK2 Differential Clock Inputs CKE0, CKE1 DQ0-DQ63 Clock Enable DQS0-DQS8 Data input/output Bidirectional data strobes Row Address Strobe Column Address Strobe Write Enable VDD Power (1.8V) , Chip Selects VREF Ref. Voltage for SSTL_18 inputs DM0-DM8 - A0-A9, A0-A12/A13 Address Inputs A10/AP BA0 ~ BA2 RESET ODT0, ODT1 NC VDDSPD Input Data Mask Differential data strobes Serial EEPROM positive power supply Column Address Input/Auto-precharge VSS Ground SDRAM Bank Address Inputs SCL Serial Presence Detect Clock Input SDA Serial Presence Detect Data input/output Reset pin On-die termination control lines SA0 ~ SA2 Serial Presence Detect Address Inputs No Connect Note: 1. Address Inputs: 512MB (A0-A9, A0-A12), 1GB/2GB (A0-A9, A0-A13). 2. ODT1, CKE1 and are only support in 2GB module type. REV 1.0 03/2008 2 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64UH4D0FY / NT1GT64U88D0BY / NT2GT64U8HD0BY 512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64 Unbuffered DDR2 SDRAM DIMM Pinout Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back 1 VREF 42 NC 82 VSS 121 VSS 162 NC 202 DM4 2 VSS 43 NC 83 122 DQ4 163 VSS 203 NC 3 DQ0 44 VSS 84 DQS4 123 DQ5 164 NC 204 VSS 4 DQ1 45 NC 85 VSS 124 VSS 165 NC 205 DQ38 5 VSS 46 NC 86 DQ34 125 DM0 166 VSS 206 DQ39 6 47 VSS 87 DQ35 126 NC 167 NC 207 VSS 7 DQS0 48 NC 88 VSS 127 VSS 168 NC 208 DQ44 8 VSS 49 NC 89 DQ40 128 DQ6 169 VSS 209 DQ45 9 DQ2 50 VSS 90 DQ41 129 DQ7 170 VDDQ 210 VSS 10 DQ3 51 VDDQ 91 VSS 130 VSS 171 NC,CKE1 211 DM5 11 VSS 52 CKE0 92 131 DQ12 172 VDD 212 NC 12 DQ8 53 VDD 93 DQS5 132 DQ13 173 NC 213 VSS 13 DQ9 54 BA2 94 VSS 133 VSS 174 NC 214 DQ46 14 VSS 55 NC 95 DQ42 134 DM1 175 VDDQ 215 DQ47 15 56 VDDQ 96 DQ43 135 NC 176 A12 216 VSS 16 DQS1 57 A11 97 VSS 136 VSS 177 A9 217 DQ52 17 VSS 58 A7 98 DQ48 137 CK1 178 VDD 218 DQ53 18 NC 59 VDD 99 DQ49 138 179 A8 219 VSS 19 NC 60 A5 100 VSS 139 VSS 180 A6 220 CK2 20 VSS 61 A4 101 SA2 140 DQ14 181 VDDQ 221 21 DQ10 62 VDDQ 102 NC 141 DQ15 182 A3 222 VSS 22 DQ11 63 A2 103 VSS 142 VSS 183 A1 223 DM6 23 VSS 64 VDD 104 143 DQ20 184 VDD 224 NC 24 DQ16 105 DQS6 144 DQ21 225 VSS 25 DQ17 65 VSS 106 VSS 145 VSS 185 CK0 226 DQ54 26 VSS 66 VSS 107 DQ50 146 DM2 186 227 DQ55 27 67 VDD 108 DQ51 147 NC 187 VDD 228 VSS 28 DQS2 68 NC 109 VSS 148 VSS 188 A0 229 DQ60 29 VSS 69 VDD 110 DQ56 149 DQ22 189 VDD 230 DQ61 30 DQ18 70 A10/AP 111 DQ57 150 DQ23 190 BA1 231 VSS 31 DQ19 71 BA0 112 VSS 151 VSS 191 VDDQ 232 DM7 32 VSS 72 VDDQ 113 152 DQ28 192 233 NC 33 DQ24 73 114 DQS7 153 DQ29 193 234 VSS 34 DQ25 74 115 VSS 154 VSS 194 VDDQ 235 DQ62 35 VSS 75 VDDQ 116 DQ58 155 DM3 195 ODT0 236 DQ63 36 76 NC, 117 DQ59 156 NC 196 NC,A13 237 VSS 37 DQS3 77 NC,ODT1 118 VSS 157 VSS 197 VDD 238 VDDSPD 38 VSS 78 VDDQ 119 SDA 158 DQ30 198 VSS 239 SA0 39 DQ26 79 VSS 120 SCL 159 DQ31 199 DQ36 240 SA1 40 DQ27 80 DQ32 160 VSS 200 DQ37 41 VSS 81 DQ33 161 NC 201 VSS KEY KEY Note: 1. NC = No Connect. 2. , ODT1, CKE1 and A13 (Pins 76, 77, 171 and 196) are only support in 2GB module type. REV 1.0 03/2008 3 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64UH4D0FY / NT1GT64U88D0BY / NT2GT64U8HD0BY 512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64 Unbuffered DDR2 SDRAM DIMM Input/Output Functional Description Symbol Type Polarity CK0, CK1, CK2 (SSTL) The positive line of the differential pair of system clock inputs which drives the input to Positive the on-DIMM PLL. All the DDR2 SDRAM address and control inputs are sampled on the Edge rising edge of their associated clocks. , , (SSTL) Negative The negative line of the differential pair of system clock inputs which drives the input to Edge the on-DIMM PLL. CKE0, CKE1 (SSTL) Active High Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. CKE1 apply on 2GB UDIMM only. , (SSTL) Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. apply on 2GB UDIMM only. , , (SSTL) Active Low When sampled at the positive rising edge of the clock, , , define the operation to be executed by the SDRAM. VREF Supply Reference voltage for SSTL-18 inputs VDDQ Supply Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity ODT0, ODT1 Input Active High BA0 - BA2 (SSTL) - Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A12/A13 defines the row address (RA0-RA12/RA13) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke "Autoprecharge" operation at the end of the Burst Read or Write cycle. If AP is high, Autoprecharge's selected and BA0/BA1 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1/BA2 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1/BA2. If AP is low, then BA0/BA1/BA2 are used to define which bank to pre-charge. A0 - A9 A10/AP A11 - A12/A13 (SSTL) - DQ0 - DQ63 (SSTL) Active High VDD, VSS Supply DQS0 - DQS8 - DM0 - DM8 (SSTL) Input Function On-Die Termination control signals. ODT1 apply on 2GB UDIMM only. Data and Check Bit Input / Output pins. Power and ground for the DDR2 SDRAM input buffers and core logic Negative and Data strobe for input and output data Positive Edge Active High The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not used on x64 modules. SA0 - SA2 - Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. SDA - This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pull-up. SCL - This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pull-up. V DDSPD REV 1.0 03/2008 Supply Serial EEPROM positive power supply. 4 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64UH4D0FY / NT1GT64U88D0BY / NT2GT64U8HD0BY 512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64 Unbuffered DDR2 SDRAM DIMM Functional Block Diagram (512MB, 1 Rank, 64Mx16 DDR2 SDRAMs) CS 0 LDQS LDQS LDM DQS0 DQS0 DM 0 DQ 0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS1 DQS1 DM1 CS DQS 5 DQS5 DM5 UDQS UDQS UDM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O 8 I/O 9 I/O 10 I/O11 I/ O12 I/O 13 I/O 14 I/O15 LDQS LDQS LDM DQS2 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQ 24 DQ25 DQ26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31 I/O 8 I/O 9 I/O 10 I/O11 I/ O12 I/O 13 I/O 14 I/O15 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D3 UDQS UDQS UDM DQS7 DQS 7 DM 7 DQ 56 DQ 57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 8 I/O 9 I/O 10 I/O11 I/ O12 I/O 13 I/O 14 I/O15 CS LDQS LDQS LDM DQS6 DQS6 DM6 D1 D2 UDQS UDQS UDM DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 UDQS UDQS UDM DQS3 DQS3 DM3 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D0 CS LDQS LDQS LDM DQS 4 DQS4 DM 4 I/O 8 I/O 9 I/O 10 I/O11 I/ O12 I/O 13 I/O 14 I/O15 Serial PD SCL BA0-BA2 A0- A12 RAS CAS WE CKE0 ODT0 REV 1.0 03/2008 BA0- BA2 : SDRAMs D0-D3 A0 - A12 : SDRAMs D0-D3 RAS : SDRAMs D0-D3 CAS : SDRAMs D0-D3 WE : SDRAMs D0-D3 CKE : SDRAMs D0-D3 ODT : SDRAMs D0-D3 WP A 0 A1 A2 SA0 SA1 SA2 V DDSPD SDA SPD VDD / VDDQ D0 - D3 VREF VSS D0 - D3 D0 - D3 5 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64UH4D0FY / NT1GT64U88D0BY / NT2GT64U8HD0BY 512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64 Unbuffered DDR2 SDRAM DIMM Functional Block Diagram (1GB, 1 Rank, 128Mx8 DDR2 SDRAMs) CS 0 DQS 0 DQS4 DQS0 DM 0 DQS4 DM 4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D0 DQS 1 DQS5 DQS 1 DM1 DQS 5 DM5 DQ8 DQ 9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DQ 40 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 DQ 47 D1 DQS2 DQS6 DQS 2 DM 2 DQS6 DM 6 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D2 DQS 3 DQS 7 DQS 3 DM 3 DQS 7 DM 7 DQ 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D3 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D4 DQS DQS D5 DQS DQS D6 DQS DQS D7 Serial PD SCL WP A0 SA0 BA0- BA2 A0 - A13 RAS CAS WE CKE0 ODT0 REV 1.0 03/2008 BA0- BA2: SDRAMs D 0-D7 A0 - A13: SDRAMs D 0-D7 RAS : SDRAMs D 0-D7 CAS : SDRAMs D 0-D7 WE : SDRAMs D 0-D7 CKE : SDRAMs D 0-D7 ODT : SDRAMs D 0-D7 VDDSPD A1 A2 SA1 SA2 SDA SPD VDD /VDDQ D0 - D7 V REF D0 - D 7 VSS D0 - D 7 6 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64UH4D0FY / NT1GT64U88D0BY / NT2GT64U8HD0BY 512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64 Unbuffered DDR2 SDRAM DIMM Functional Block Diagram (2GB, 2 Ranks, 128Mx8 DDR2 SDRAMs) CS 1 CS 0 DQS0 DQS 4 DQS 0 DM 0 DQS 4 DM 4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D0 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D8 DQS1 DQS5 DQS 1 DM1 DQS 5 DM 5 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS DQS DQS D1 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D9 DQS2 DQS 6 DQS 2 DM 2 DQS 6 DM 6 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CS DQS DQS D2 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D 10 DQS3 DQS7 DQS3 DM 3 DQS 7 DM 7 DM CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 BA0 -BA2 A0-A13 RAS CAS WE CKE0 CKE1 ODT0 ODT1 REV 1.0 03/2008 DQS DQS D3 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 BA0 - BA2 : SDRAMs D 0 -D15 A0 - A13 : SDRAMs D 0-D15 RAS : SDRAMs D 0-D15 CAS : SDRAMs D0-D15 WE : SDRAMs D0-D15 CKE : SDRAMs D 0-D7 CKE : SDRAMs D 8-D15 ODT : SDRAMs D 0-D7 ODT : SDRAMs D 8-D15 CS DQS DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D 11 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS SA0 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D4 DQS DQS D5 DM CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS CS Serial PD D6 D7 V DDSPD SCL WP A0 DQS DQS A1 A2 SA1 SA2 SDA CS DQS DQS D12 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D13 DQS DQS D 14 DQS DQS D 15 SPD VDD /VDDQ D0- D 15 V REF VSS D0- D 15 D0- D 15 7 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64UH4D0FY / NT1GT64U88D0BY / NT2GT64U8HD0BY 512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect -- Part 1 of 2 (512MB) 64Mx64 1 RANK UNBUFFERED DDR2 SDRAM DIMM based on 64Mx16, 8Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD SPD Entry Value Byte Description 667 -3C 800 -AD 800 -AC Serial PD Data Entry (Hexadecimal) 667 -3C 800 -AD 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type DDR2 08 3 Number of Row Addresses on Assembly 13 0D 4 Number of Column Addresses on Assembly 10 0A 5 Number of DIMM Ranks 1 rank, Height=30mm 60 6 Data Width of Assembly X64 40 7 Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL_1.8V 9 DDR2 SDRAM Device Cycle Time at CL=5 10 DDR2 SDRAM Device Access Time from Clock at CL=5 11 DIMM Configuration Type 12 Refresh Rate/Type 13 Primary DDR2 SDRAM Width 14 15 16 17 18 DDR2 SDRAM Device Attributes: CAS Latencies Supported 19 DIMM Mechanical Characteristics 20 DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes: 800 -AC 05 3ns 2.5ns 30 0.45ns 0.4ns 45 25 40 Non parity/ECC 00 7.8s 82 X16 10 Error Checking DDR2 SDRAM Device Width Undefined 00 Reserved Undefined 00 DDR2 SDRAM Device Attributes: Burst Length Supported 4,8 0C DDR2 SDRAM Device Attributes: Number of Device Banks 8 3,4,5 08 4,5,6 3,4,5 38 70 x 4.10 (mm) 01 UDIMM (133.5mm) 02 Normal DIMM 00 Support weak driver, 50 ODT, and PASR 07 38 22 DDR2 SDRAM Device Attributes: General 23 Minimum Clock Cycle at CL=4 3.75ns 3.0ns 3.75ns 3D 30 3D 24 Maximum Data Access Time from Clock at CL=4 0.5ns 0.45ns 0.5ns 50 45 50 25 Minimum Clock Cycle Time at CL=3 5.0ns 3.75ns 5.0ns 50 3D 50 26 Maximum Data Access Time from Clock at CL=3 0.6ns 0.5ns 0.6ns 60 50 60 27 Minimum Row Precharge Time (tRP) 28 Minimum Row Active to Row Active delay (tRRD) 29 Minimum RAS to CAS delay (tRCD) 30 Minimum RAS Pulse Width (tRAS) 31 Module Bank Density 32 Address and Command Setup Time Before Clock (tIS) 0.20ns 0.17ns 20 17 33 Address and Command Hold Time After Clock (tIH) 0.27ns 0.25ns 27 25 34 Data Input Setup Time Before Clock (tDS) 0.10ns 0.05ns 10 05 35 Data Input Hold Time After Clock (tDH) 0.175ns 0.12ns 17 12 36 Write Recovery Time (tWR) 15.0ns 3C 37 Internal Write to Read Command delay (tWTR) 7.5ns 1E 38 Internal Read to Precharge delay (tRTP) 7.5ns 1E 39 Reserved Undefined 00 REV 1.0 03/2008 Note 15ns 12.5ns 3C 10ns 15ns 32 28 12.5ns 3C 32 45ns 2D 512MB 80 8 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64UH4D0FY / NT1GT64U88D0BY / NT2GT64U8HD0BY 512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect -- Part 1 of 2 (512MB) 64Mx64 1 RANK UNBUFFERED DDR2 SDRAM DIMM based on 64Mx16, 8Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD SPD Entry Value Byte Description 667 -3C Extension of Byte 41 tRC and Byte 42 tRFC 41 Minimum Core Cycle Time (tRC) 42 Min. Auto Refresh Command Cycle Time (tRFC) 43 Maximum Clock Cycle Time (tCK) 44 Max. DQS-DQ Skew Factor (tQHS) 0.24ns 45 Read Data Hold Skew Factor (tQHS) 0.34ns 46 PLL Relock Time 60.0ns SPD Revision Checksum for bytes 0-62 57.5ns 92-255 Reserved Note 36 39 7F 80 18 0.30ns 22 14 1E Undefined 00 Undefined 00 1.3 73-91 Module Part number 800 -AC 3C 0.20ns Checksum Data Module Manufacturing Location 800 -AD 06 8.0ns 64-71 Manufacture's JEDEC ID Code 72 667 -3C 127.5ns 46-61 Reserved 63 800 -AC The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns. 40 62 800 -AD Serial PD Data Entry (Hexadecimal) 13 A7 71 8D NANYA 7F7F7F0B00000000 Manufacturing Code -- Module Part Number in ASCII -- Undefined -- 1 Note 1: NT512T64UH4D0FY-3C 4E54353132543634554834443046592D334320 NT512T64UH4D0FY-AD 4E54353132543634554834443046592D414420 NT512T64UH4D0FY-AC 4E54353132543634554834443046592D414320 REV 1.0 03/2008 9 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64UH4D0FY / NT1GT64U88D0BY / NT2GT64U8HD0BY 512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect -- Part 1 of 2 (1GB) 128Mx64 1 RANK UNBUFFERED DDR2 SDRAM DIMM based on 128Mx8, 8Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD SPD Entry Value Byte Description 667 -3C 800 -AD 800 -AC Serial PD Data Entry (Hexadecimal) 667 -3C 800 -AD 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type DDR2 08 3 Number of Row Addresses on Assembly 14 0E 4 Number of Column Addresses on Assembly 10 0A 5 Number of DIMM Ranks 1 rank, Height=30mm 60 6 Data Width of Assembly X64 40 7 Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL_1.8V 9 DDR2 SDRAM Device Cycle Time at CL=5 10 DDR2 SDRAM Device Access Time from Clock at CL=5 11 DIMM Configuration Type 12 Refresh Rate/Type 13 Primary DDR2 SDRAM Width 14 15 16 17 18 DDR2 SDRAM Device Attributes: CAS Latencies Supported 19 DIMM Mechanical Characteristics 20 DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes: 800 -AC 05 3ns 2.5ns 30 0.45ns 0.4ns 45 25 40 Non parity/ECC 00 7.8s 82 X8 08 Error Checking DDR2 SDRAM Device Width Undefined 00 Reserved Undefined 00 DDR2 SDRAM Device Attributes: Burst Length Supported 4,8 0C DDR2 SDRAM Device Attributes: Number of Device Banks 8 3,4,5 08 4,5,6 3,4,5 38 70 x 4.10 (mm) 01 UDIMM (133.5mm) 02 Normal DIMM 00 Support weak driver, 50 ODT, and PASR 07 38 22 DDR2 SDRAM Device Attributes: General 23 Minimum Clock Cycle at CL=4 3.75ns 3.0ns 3.75ns 3D 30 3D 24 Maximum Data Access Time from Clock at CL=4 0.5ns 0.45ns 0.5ns 50 45 50 25 Minimum Clock Cycle Time at CL=3 5.0ns 3.75ns 5.0ns 50 3D 50 26 Maximum Data Access Time from Clock at CL=3 0.6ns 0.5ns 0.6ns 60 50 60 27 Minimum Row Precharge Time (tRP) 28 Minimum Row Active to Row Active delay (tRRD) 29 Minimum RAS to CAS delay (tRCD) 30 Minimum RAS Pulse Width (tRAS) 45ns 2D 31 Module Bank Density 1GB 01 32 Address and Command Setup Time Before Clock (tIS) 0.20ns 0.17ns 20 17 33 Address and Command Hold Time After Clock (tIH) 0.27ns 0.25ns 27 25 34 Data Input Setup Time Before Clock (tDS) 0.10ns 0.05ns 10 05 35 Data Input Hold Time After Clock (tDH) 0.175ns 0.12ns 17 12 36 Write Recovery Time (tWR) 15.0ns 3C 37 Internal Write to Read Command delay (tWTR) 7.5ns 1E 38 Internal Read to Precharge delay (tRTP) 7.5ns 1E 39 Reserved Undefined 00 REV 1.0 03/2008 Note 15ns 12.5ns 3C 7.5ns 15ns 32 1E 12.5ns 3C 32 10 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64UH4D0FY / NT1GT64U88D0BY / NT2GT64U8HD0BY 512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect -- Part 2 of 2 (1GB) 128Mx64 1 RANK UNBUFFERED DDR2 SDRAM DIMM based on 128Mx8, 8Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD SPD Entry Value Byte Description 667 -3C 800 -AD 800 -AC Serial PD Data Entry (Hexadecimal) 667 -3C The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns. 800 -AD 800 -AC 40 Extension of Byte 41 tRC and Byte 42 tRFC 41 Minimum Core Cycle Time (tRC) 42 Min. Auto Refresh Command Cycle Time (tRFC) 43 Maximum Clock Cycle Time (tCK) 44 Max. DQS-DQ Skew Factor (tQHS) 0.24ns 0.20ns 18 14 45 Read Data Hold Skew Factor (tQHS) 0.34ns 0.30ns 22 1E 46 PLL Relock Time 60.0ns 46-61 Reserved 62 SPD Revision 63 Checksum for bytes 0-62 73-91 Module Part number 92-255 Reserved 3C 39 7F 8.0ns 80 Undefined 00 Undefined 00 1.3 13 Checksum Data Module Manufacturing Location 36 127.5ns 64-71 Manufacture's JEDEC ID Code 72 57.5ns 06 17 E1 FD NANYA 7F7F7F0B00000000 Manufacturing Code -- Module Part Number in ASCII -- Undefined -- Note 1 Note 1: NT1GT64U88D0BY-3C 4D325931473634545538384434422D33432020 NT1GT64U88D0BY-AD 4D325931473634545538384434422D41442020 NT1GT64U88D0BY-AC 4D325931473634545538384434422D41432020 REV 1.0 03/2008 11 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64UH4D0FY / NT1GT64U88D0BY / NT2GT64U8HD0BY 512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect -- Part 1 of 2 (2GB) 256Mx64 2 RANKs UNBUFFERED DDR2 SDRAM DIMM based on 128Mx8, 8Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD SPD Entry Value Byte Description 667 -3C 800 -AD 800 -AC Serial PD Data Entry (Hexadecimal) 667 -3C 800 -AD 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type DDR2 08 3 Number of Row Addresses on Assembly 14 0E 4 Number of Column Addresses on Assembly 10 0A 5 Number of DIMM Ranks 2 ranks, Height=30mm 61 6 Data Width of Assembly X64 40 7 Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL_1.8V 9 DDR2 SDRAM Device Cycle Time at CL=5 3.0ns 2.5ns 30 10 DDR2 SDRAM Device Access Time from Clock at CL=5 0.45ns 0.4ns 45 11 DIMM Configuration Type 12 Refresh Rate/Type 13 Primary DDR2 SDRAM Width 14 Error Checking DDR2 SDRAM Device Width 15 Reserved 16 17 18 DDR2 SDRAM Device Attributes: CAS Latencies Supported 19 DIMM Mechanical Characteristics 20 DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes: 800 -AC 05 25 40 Non parity/ECC 00 7.8s/self 82 X8 08 N/A 00 Undefined 00 DDR2 SDRAM Device Attributes: Burst Length Supported 4,8 0C DDR2 SDRAM Device Attributes: Number of Device Banks 8 3,4,5 08 4,5,6 3,4,5 38 70 x 4.10 (mm) 01 UDIMM (133.5mm) 02 Normal DIMM 00 Support weak driver, 50 ODT, and PASR 07 38 22 DDR2 SDRAM Device Attributes: General 23 Minimum Clock Cycle at CL=4 3.75ns 3ns 3.75ns 3D 30 3D 24 Maximum Data Access Time from Clock at CL=4 0.5ns 0.45ns 0.5ns 50 45 50 25 Minimum Clock Cycle Time at CL=3 5.0ns 3.75ns 5.0ns 50 3D 50 26 Maximum Data Access Time from Clock at CL=3 0.6ns 0.5ns 0.6ns 60 50 60 27 Minimum Row Precharge Time (tRP) 28 Minimum Row Active to Row Active delay (tRRD) 29 Minimum RAS to CAS delay (tRCD) 30 Minimum RAS Pulse Width (tRAS) 45.0 2D 31 Module Bank Density 1GB 01 32 Address and Command Setup Time Before Clock (tIS) 0.20ns 0.17ns 20 17 33 Address and Command Hold Time After Clock (tIH) 0.27ns 0.25ns 27 25 34 Data Input Setup Time Before Clock (tDS) 0.10ns 0.05ns 10 05 35 Data Input Hold Time After Clock (tDH) 0.17ns 0.12ns 17 12 36 Write Recovery Time (tWR) 15.0ns 3C 37 Internal Write to Read Command delay (tWTR) 7.5ns 1E 38 Internal Read to Precharge delay (tRTP) 7.5ns 1E 39 Reserved Undefined 00 REV 1.0 03/2008 Note 15ns 12.5ns 3C 7.5ns 15ns 32 1E 12.5ns 3C 32 12 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64UH4D0FY / NT1GT64U88D0BY / NT2GT64U8HD0BY 512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect -- Part 2 of 2 (2GB) 256Mx64 2 RANKs UNBUFFERED DDR2 SDRAM DIMM based on 128Mx8, 8Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD SPD Entry Value Byte Description 667 -3C Extension of Byte 41 tRC and Byte 42 tRFC 41 Minimum Core Cycle Time (tRC) 42 Min. Auto Refresh Command Cycle Time (tRFC) 43 Maximum Clock Cycle Time (tCK) 44 Max. DQS-DQ Skew Factor (tQHS) 0.24ns 45 Read Data Hold Skew Factor (tQHS) 0.34ns 46 PLL Relock Time 60.0ns SPD Revision Checksum for bytes 0-62 57.5ns 92-255 Reserved Note 36 39 7F 80 18 0.30ns 22 14 1E Undefined 00 Undefined 00 1.3 73-91 Module Part number 800 -AC 3C 0.20ns Checksum Data Module Manufacturing Location 800 -AD 06 8.0ns 64-71 Manufacture's JEDEC ID Code 72 667 -3C 127.5ns 46-61 Reserved 63 800 -AC The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns. 40 62 800 -AD Serial PD Data Entry (Hexadecimal) 13 18 E2 FE NANYA 7F7F7F0B00000000 Manufacturing Code -- Module Part Number in ASCII -- Undefined -- 1 Note 1: NT2GT64U8HD0BY-3C 4D325932473634545538484434422D33432020 NT2GT64U8HD0BY-AD 4D325932473634545538484434422D41442020 NT2GT64U8HD0BY-AC 4D325932473634545538484434422D41432020 REV 1.0 03/2008 13 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64UH4D0FY / NT1GT64U88D0BY / NT2GT64U8HD0BY 512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64 Unbuffered DDR2 SDRAM DIMM Absolute Maximum Ratings Symbol Rating Units Voltage on any pin relative to Vss -0.5 to 2.3 V VDDQ Voltage on VDDQ supply relative to Vss -0.5 to 2.3 V VDDQL Voltage on VDDQL supply relative to Vss -0.5 to 2.3 V Voltage on VDD supply relative to Vss -1.0 to +2.3 V VIN, VOUT VDD Parameter Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC Operating Conditions Symbol Parameter TCASE Operating Temperature (Ambient) TSTG Storage Temperature (Plastic) Short Circuit Output Current IL Note: 1. 2. 3. Units Note 0 to 95 C 1,2,3 -55 to 100 C -5 to 5 A Case temperature is measured at top and center side of any DRAMs. tCASE > 85C tREFI = 3.9 s All DRAM specification only support 0C < tCASE < 85C REV 1.0 03/2008 Rating 14 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64UH4D0FY / NT1GT64U88D0BY / NT2GT64U8HD0BY 512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64 Unbuffered DDR2 SDRAM DIMM DC Electrical Characteristics and Operating Conditions (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) Symbol Parameter VDD Min Max Units Notes Supply Voltage 1.7 1.9 V 1 VDDQ Supply Voltage for Output 1.7 1.9 V 1, 3 VDDL Supply Voltage for VDDQL 1.7 1.9 V 3 VREF Input Reference Voltage 0.49VDDQ 0.51VDDQ mV 2 4 Termination Voltage VREF - 0.04 VREF + 0.04 V VIH (DC) Input High (Logic1) Voltage VREF + 0.125 VDDQ + 0.3 V VIL (DC) Input Low (Logic0) Voltage -0.3 VREF - 0.125 V VTT Note: 1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VDDQ tracks with VDD, VDDL tracks with VDD. 4. VTT of transmitting device track VREF of receiving device. Environmental Parameters Symbol Parameter Rating Units Note 3 TOPR Module Operating Temperature Range (ambient) 0 to 55 C HOPR Operating Humidity (relative) 10 to 90 % TSTG Storage Temperature (Plastic) -55 to 100 C 1 HSTG Storage Humidity (without condensation) 5 to 95 % 1 PBAR Barometric Pressure (operating & storage) 105 to 69 K Pascal 1,2 Note: 1. 2. 3. Stresses greater than those listed may cause permanent damage to the device. This is a tress rating only, and device functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Up to 9850 ft. The component maximum case temperature shall not exceed the value specified in the component spec. REV 1.0 03/2008 15 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64UH4D0FY / NT1GT64U88D0BY / NT2GT64U8HD0BY 512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64 Unbuffered DDR2 SDRAM DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.8V 0.1V (512MB, 1 Rank, 64Mx16 DDR2 SDRAMs) PC2-5300 PC2-6400 PC2-6400 (-3C) (-AD) (-AC) Symbol Parameter/Condition I DD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 436 502 502 mA I DD1 Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 541 620 620 mA I DD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 35 35 35 mA I DD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 273 308 308 mA I DD2Q Precharge Quiet Standby Current: All banks idle; is HIGH; CKE is HIGH; tCK = tCK (MIN); Other control and address inputs are stable, Data bus inputs are floating. 189 207 207 mA I DD3PF Active Power-Down Current: All banks open; tCK = tCK (MIN), CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are floating. MRS A12 bit is set to low (Fast Power-down Exit). 123 132 132 mA I DD3PS Active Power-Down Current: All banks open; tCK = tCK (MIN), CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are floating. MRS A12 bit is set to high (Slow Power-down Exit). 53 53 53 mA I DD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 255 282 282 mA I DD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) 550 607 607 mA I DD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA 673 752 752 mA I DD5 Auto-Refresh Current: tRC = tRFC (MIN) 968 990 990 mA I DD6 Self-Refresh Current: CKE 0.2V 40 40 40 mA I DD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1496 1672 1672 mA Unit Note: Module IDD was calculated from component IDD. It may differ from the actual measurement. REV 1.0 03/2008 16 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64UH4D0FY / NT1GT64U88D0BY / NT2GT64U8HD0BY 512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64 Unbuffered DDR2 SDRAM DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.8V 0.1V (1GB, 1 Rank, 128Mx8 DDR2 SDRAMs) PC2-5300 PC2-6400 PC2-6400 (-3C) (-AD) (-AC) Symbol Parameter/Condition I DD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 880 1012 1012 mA I DD1 Operating Current: one bank; active/read/precharge; Burst = 2; t RC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 801 906 906 mA I DD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 70 70 70 mA I DD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 554 625 625 mA I DD2Q Precharge Quiet Standby Current: All banks idle; is HIGH; CKE is HIGH; tCK = tCK (MIN); Other control and address inputs are stable, Data bus inputs are floating. 387 422 422 mA I DD3PF Active Power-Down Current: All banks open; tCK = tCK (MIN), CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are floating. MRS A12 bit is set to low (Fast Power-down Exit). 264 273 273 mA I DD3PS Active Power-Down Current: All banks open; tCK = tCK (MIN), CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are floating. MRS A12 bit is set to high (Slow Power-down Exit). 114 114 114 mA I DD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 493 537 537 mA I DD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) 924 1012 1012 mA I DD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA 1074 1197 1197 mA I DD5 Auto-Refresh Current: tRC = tRFC (MIN) 1936 1980 1980 mA I DD6 Self-Refresh Current: CKE 0.2V 79 79 79 mA I DD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 2094 2446 2446 mA Unit Note: Module IDD was calculated from component IDD. It may differ from the actual measurement. REV 1.0 03/2008 17 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64UH4D0FY / NT1GT64U88D0BY / NT2GT64U8HD0BY 512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64 Unbuffered DDR2 SDRAM DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.8V 0.1V (2GB, 2 Ranks, 128Mx8 DDR2 SDRAMs) PC2-5300 PC2-6400 PC2-6400 (-3C) (-AD) (-AC) Symbol Parameter/Condition I DD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 1373 1549 1549 mA I DD1 Operating Current: one bank; active/read/precharge; Burst = 2; t RC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 1294 1443 1443 mA I DD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 141 141 141 mA I DD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 1109 1250 1250 mA I DD2Q Precharge Quiet Standby Current: All banks idle; is HIGH; CKE is HIGH; tCK = tCK (MIN); Other control and address inputs are stable, Data bus inputs are floating. 774 845 845 mA I DD3PF Active Power-Down Current: All banks open; tCK = tCK (MIN), CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are floating. MRS A12 bit is set to low (Fast Power-down Exit). 528 546 546 mA I DD3PS Active Power-Down Current: All banks open; tCK = tCK (MIN), CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are floating. MRS A12 bit is set to high (Slow Power-down Exit). 229 229 229 mA I DD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 986 1074 1074 mA I DD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) 1417 1549 1549 mA I DD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA 1566 1734 1734 mA I DD5 Auto-Refresh Current: tRC = tRFC (MIN) 2429 2517 2517 mA I DD6 Self-Refresh Current: CKE 0.2V 158 158 158 mA I DD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 2587 2983 2983 mA Unit Note: Module IDD was calculated from component IDD. It may differ from the actual measurement. REV 1.0 03/2008 18 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64UH4D0FY / NT1GT64U88D0BY / NT2GT64U8HD0BY 512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64 Unbuffered DDR2 SDRAM DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 1 of 2) Symbol PC2-5300 Parameter PC2-6400 Unit Min. Max. Min. Max. tCK Clock Cycle Time (Average) 3000 8000 2500 8000 ps tCH CK high-level width (Average) 0.48 0.52 0.48 0.52 tCK 0.48 0.52 0.48 tCL CK low-level width (Average) WL Write command to DQS associated clock edge tDQSS Write command to 1st DQS latching transition RL-1 0.52 RL-1 tCK nCK -0.25 0.25 -0.25 0.25 tCK tDSS DQS falling edge to CK setup time (write cycle) 0.2 - 0.2 - tCK tDSH DQS falling edge hold time from CK (write cycle) 0.2 - 0.2 - tCK DQS input low (high) pulse width (write cycle) 0.35 - 0.35 - tCK tWPRE Write preamble 0.35 - 0.35 - tCK tWPST Write postamble 0.4 0.6 0.4 0.6 tCK Address and control input setup time 200 - 175 - ps 275 - 250 - ps tDQSL,(H) tIS tIH Address and control input hold time tIPW Input pulse width 0.6 - 0.6 - tCK tDS DQ and DM input setup time(differential data strobe) 100 - 50 - ps tDH DQ and DM input hold time(differential data strobe) 175 - 125 - ps tDIPW tAC tDQSCK tHZ DQ and DM input pulse width (each input) 0.35 - 0.35 - tCK DQ output access time from CK/ -450 450 -400 400 ps DQS output access time from CK/ -400 400 -350 350 ps - tAC max - tACmax ps tACmax ps Data-out high-impedance time from CK/ tLZ(DQS) DQS low-impedance time from CK/ tAC min tAC max tACmin tLZ(DQ) DQ low-impedance time from CK/ 2tAC min tAC max 2tAC min tAC max ps tDQSQ DQS-DQ skew (DQS & associated DQ signals) - 240 - 200 ps Min(tCH(abs),tC L(abs)) - Min(tCH(abs), tCL(abs)) - ps - 340 - 300 ps tHP - tQHS - tHP - tQHS - ps Read preamble 0.9 1.1 0.9 1.1 tCK tRPST Read postamble 0.4 0.6 0.4 0.6 tCK tRRD Active bank A to Active bank B command 7.5 - 7.5 - ns tFAW Four Activate Window for 1KB page size products 37.5 - 35 - tCCD to tHP Minimum half clk period for any given cycle; defined by clk high (tCH) or clk low (tCL) time tQHS Data hold Skew Factor tQH Data output hold time from DQS tRPRE tWR Write recovery time without Auto-Precharge tDAL Auto precharge write recovery + precharge time tWTR tRTP - 15 - ns - WR+tnRP - nCK Internal write to read command delay 7.5 - 7.5 - ns Internal read to precharge command delay 7.5 CKE minimum pulse width Exit self refresh to a Non-read command tXSRD Exit self refresh to a Read command 03/2008 ns nCK 15 tCKE REV 1.0 2 WR+tnRP tXSNR tXP 2 3 7.5 ns 3 nCK tRFC+10 - tRFC+10 ns 200 - 200 nCK 2 - 2 Exit precharge power down to any Non- read command - nCK 19 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64UH4D0FY / NT1GT64U88D0BY / NT2GT64U8HD0BY 512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64 Unbuffered DDR2 SDRAM DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 2 of 2) Symbol PC2-5300 Parameter Max. Min. Max. - 2 - tXARD Exit active power down to read command 2 tXARDS Exit active power down to read command 7-AL tAOND ODT turn-on delay tAON ODT turn-on tAONPD ODT turn-on (Power down mode) tAOFD ODT turn-off delay tAOF ODT turn-off PC2-6400 Min. 8-AL Unit nCK nCK 2 2 2 2 nCK tAC (min) tAC (max)+0.7 tAC (min) tAC (max)+0.7 ns tAC (min) +2 2tCK + tAC(max) +1 tAC (min) +2 2tCK + tAC(max) +1 ns 2.5 2.5 2.5 2.5 nCK tAC(min) tAC(max) +0.6 tAC(min) tAC(max) +0.6 ns tAOFPD ODT turn-off (Power down mode) tAC (min)+2 2.5tCK + tAC(max) +1 tAC (min)+2 2.5tCK + tAC(max) +1 ns tANPD ODT to power down entry latency 3 - 3 - nCK tAXPD ODT power down exit latency 8 tMRD Mode register set command cycle time 2 - 2 - nCK tMOD MRS command to ODT update delay 0 12 0 12 ns tOIT OCD drive mode output delay 0 12 0 12 ns tIS + tCK + tIH - tIS + tCK + tIH - ns tDelay Minimum time clocks remains ON after CKE asynchronously drops Low tRFC Refresh to active/Refresh command time tREFI 8 nCK 127.5 127.5 ns Average Periodic Refresh Interval (85C < TCASE 95C) 3.9 3.9 s Average Periodic Refresh Interval (0C TCASE 85C) 7.8 7.8 s Speed Grade Definition -3C Symbol Parameter -AC -AD Min Max Min Max Min Max Unit tRAS Row Active Time 45 70,000 45 70,000 45 70,000 ns tRC Row Cycle Time 60 - 60 - 57.5 - ns tRCD RAS to CAS delay 15 - 15 - 12.5 - ns Row Precharge Time 15 - 15 - 12.5 - ns tRP REV 1.0 03/2008 20 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64UH4D0FY / NT1GT64U88D0BY / NT2GT64U8HD0BY 512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64 Unbuffered DDR2 SDRAM DIMM Package Dimensions (Raw Card Version: C, 512MB, 1 Rank, 64Mx16 DDR2 SDRAMs) FRONT 131. 35 5. 171 128. 95 5. 077 Detail A 2.5 0. 098 Detail B 2.30 0.091 10.0 0.394 17.80 0.700 30.00 1.180 (2X) 4.00 0.157 133. 35 5. 250 BACK 63. 00 2. 480 55. 00 2. 165 SIDE 3.80 0.15 Detail A 2. 50 0. 10 4.00 0.157 3.18 Max 0.125 5. 00 0. 20 1. 50 +/- 0.1 0. 059 +/- 0.004 1. 27+/- 0. 10 0. 050 +/- 0. 004 Detail B 0. 8 +/- 0.5 0. 031 +/- 0. 02 1. 00 Pitch 0. 039 Note: All dimensions are typical with tolerances of +/- 0. 15 (0. 006 ) unless otherwise stated . Units:Millimeters ( Inches) REV 1.0 03/2008 21 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64UH4D0FY / NT1GT64U88D0BY / NT2GT64U8HD0BY 512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64 Unbuffered DDR2 SDRAM DIMM Package Dimensions (Raw Card Version: D, 1GB, 1 Rank, 128Mx8 DDR2 SDRAMs) FRONT 131. 35 5. 171 128. 95 5. 077 Detail A 2.5 0. 098 Detail B 2.30 0.091 10.0 0.394 17.80 0.700 30.00 1.180 (2X) 4.00 0.157 133. 35 5. 250 BACK 63. 00 2. 480 55. 00 2. 165 SIDE 3.80 0.15 Detail A 2. 50 0. 10 4.00 0.157 3.18 Max 0. 125 5. 00 0. 20 1. 50 +/- 0.1 0. 059 +/- 0. 004 1. 27 +/- 0. 10 0. 050 +/- 0. 004 Detail B 0. 8 +/- 0.5 0. 031 +/- 0. 02 1. 00 Pitch 0.039 Note: All dimensions are typical with tolerances of +/- 0. 15 (0. 006 ) unless otherwise stated . Units:Millimeters ( Inches) REV 1.0 03/2008 22 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64UH4D0FY / NT1GT64U88D0BY / NT2GT64U8HD0BY 512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64 Unbuffered DDR2 SDRAM DIMM Package Dimensions (Raw Card Version: E, 2GB, 2 Ranks, 128Mx8 DDR2 SDRAMs) FRONT 131. 35 5. 171 128. 95 5. 077 Detail A 2.5 0. 098 Detail B 2.30 0.091 10.0 0.394 17.80 0.700 30.00 1.180 (2X) 4.00 0.157 133. 35 5. 250 BACK 63. 00 2. 480 55. 00 2. 165 SIDE 3.80 0.15 Detail A 2. 50 0. 10 4.00 0.157 4.00 Max 0. 157 5. 00 0. 20 1. 50 +/- 0.1 0.059 +/- 0. 004 1. 27 +/- 0. 10 0. 050 +/- 0. 004 Detail B 0. 8 +/- 0.5 0. 031 +/- 0. 02 1. 00 Pitch 0.039 Note: All dimensions are typical with tolerances of +/- 0. 15 (0. 006 ) unless otherwise stated . Units:Millimeters ( Inches) REV 1.0 03/2008 23 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64UH4D0FY / NT1GT64U88D0BY / NT2GT64U8HD0BY 512MB: 64M x 64 / 1GB: 128M x 64 / 2GB: 256M x 64 Unbuffered DDR2 SDRAM DIMM Revision Log Rev Date 0.1 02/2008 Preliminary Edition 1.0 03/2008 Official Release REV 1.0 03/2008 Modification 24 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.