LTC2911 Precision Triple Supply Monitor with Power-Fail Comparator DESCRIPTION FEATURES n n n n n n n n n n Ultralow Voltage Reset: VCC = 0.5V Guaranteed Monitors Three Inputs Simultaneously: 3.3V, 5V, ADJ (LTC2911-1) 3.3V, 2.5V, ADJ (LTC2911-2) 3.3V, 1.8V, ADJ (LTC2911-3) 3.3V, 1.2V, ADJ (LTC2911-4) 3.3V, ADJ, ADJ (LTC2911-5) 1.5% Threshold Accuracy Power-Fail Monitor RST State Can Be Held for Margining Low Supply Current: 30A Typical Input Glitch Immunity Adjustable Reset Timeout Period Selectable Internal Timeout Saves Components Space Saving 8-Lead TSOT-23 and 3mm x 2mm DFN Packages APPLICATIONS n n n Network Servers Desktop and Notebook Computers Automotive and Industrial Electronics The LTC(R)2911 is a low power, high accuracy triple supply monitor with a power-fail comparator. Reset timeout may be selected with an external capacitor or set to an internally generated 200ms. The V1 pin monitors a 3.3V supply. The V2 pin monitors a 5V, 2.5V, 1.8V, 1.2V or adjustable supply. A third adjustable input has a nominal 0.5V threshold allowing a resistive divider to configure its threshold. All three comparators feature a tight 1.5% threshold accuracy over the entire operating temperature range while a glitch filter ensures reliable reset operation. A spare comparator can be configured to provide early warning of a low voltage condition. It causes the PFO output to pull low when the voltage of the PFI input falls below 0.5V, allowing the power-fail threshold to be configured with a resistive divider. A latch feature on the TMR pin allows the RST output to be latched to prevent system resets, simplifying margin testing. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6949965, 7292076. TYPICAL APPLICATION RST Output Voltage With 10k Pull-Up to V1 3.3V 6 2.5V DC/DC CONVERTER 1.0V SYSTEM LOGIC 76.8k + Li-Ion BATTERY STACK 576k RST V2 PFO LTC2911-2 ADJ RESET LOBAT 100k PFI 100k 5 10k 4 VRST (V) TMR V1 V1 = V2 3 2 1 GND tRST = 200ms 2911 TA01a 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 V1 (V) 2911 TA01b 2911f 1 LTC2911 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2, 3) Supply Voltages V1, V2.................................................... -0.3V to 6.5V Input Voltages ADJ........................................................ -0.3V to 6.5V PFI............................................................ -0.3V to 2V TMR.............................................-0.3V to (V1 + 0.3V) Output Voltages RST, PFO............................................... -0.3V to 6.5V Operating Temperature Range LTC2911C................................................. 0C to 70C LTC2911I.............................................. -40C to 85C LTC2911H........................................... -40C to 125C Storage Temperature Range.................... -65C to 150C Lead Temperature (Soldering, 10 sec) TSOT-23............................................................. 300C PIN CONFIGURATION TOP VIEW TOP VIEW PFI 1 ADJ 2 TMR 3 GND 4 V2 1 8 V2 7 V1 6 PFO 5 RST V1 2 PFO 3 8 PFI 9 GND RST 4 TS8 PACKAGE 8-LEAD PLASTIC TSOT-23 7 ADJ 6 TMR 5 GND DDB PACKAGE 8-LEAD (3mm x 2mm) PLASTIC DFN TJMAX = 150C, JA = 195C/W TJMAX = 150C, JA = 76C/W EXPOSED PAD (PIN 9) IS GND, PCB CONNECTION OPTIONAL ORDER INFORMATION LTC2911 C DDB -1 #TRM PBF LEAD FREE DESIGNATOR PBF = Lead Free Finish Parts None = Lead Based Finish Parts TAPE AND REEL #TR = Tape and Reel #TRM = 500-Piece Tape and Reel PRODUCT SELECTION -1, -2, -3, -4, -5 See Product Selection Guide for Details PACKAGE TYPE DDB = 8-Lead (3mm x 2mm) Plastic DFN TS8 = 8-Lead Plastic TSOT-23 TEMPERATURE GRADE C = Commercial Temperature Range (0C to 70C) I = Industrial Temperature Range (-40C to 85C) H = Automotive Temperature Range (-40C to 125C) PRODUCT PART NUMBER Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2911f 2 LTC2911 PRODUCT SELECTION GUIDE PART NUMBER PART MARKING PACKAGE DESCRIPTION V1 V2 LTC2911-1 LFHZ 8-Lead (3mm x 2mm) Plastic DFN 3.3V 5V LTC2911-2 LFPG 8-Lead (3mm x 2mm) Plastic DFN 3.3V 2.5V LTC2911-3 LFPJ 8-Lead (3mm x 2mm) Plastic DFN 3.3V 1.8V LTC2911-4 LFPM 8-Lead (3mm x 2mm) Plastic DFN 3.3V 1.2V LTC2911-5 LFPP 8-Lead (3mm x 2mm) Plastic DFN 3.3V ADJ LTC2911-1 LTFJB 8-Lead Plastic TSOT-23 3.3V 5V LTC2911-2 LTFPH 8-Lead Plastic TSOT-23 3.3V 2.5V LTC2911-3 LTFPK 8-Lead Plastic TSOT-23 3.3V 1.8V LTC2911-4 LTFPN 8-Lead Plastic TSOT-23 3.3V 1.2V LTC2911-5 LTFPQ 8-Lead Plastic TSOT-23 3.3V ADJ ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VADJ = 0.55V, VPFI = 0.55V, V1 = 3.3V unless otherwise noted. (Notes 2, 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VRT33 3.3V, 5% Reset Threshold V1 Input l 3.036 3.086 3.135 V VRT50 5V, 5% Reset Threshold V2 Input (LTC2911-1) l 4.600 4.675 4.750 V VRT25 VRT18 2.5V, 5% Reset Threshold V2 Input (LTC2911-2) l 2.300 2.338 2.375 V 1.8V, 5% Reset Threshold V2 Input (LTC2911-3) l 1.656 1.683 1.710 V VRT12 1.2V, 5% Reset Threshold V2 Input (LTC2911-4) l 1.104 1.122 1.140 V VRTA ADJ Pin Threshold ADJ Input and V2 Input of LTC2911-5 l 492.5 500 507.5 mV VPFT PFI Pin Threshold PFI Input Threshold (Falling) l 492.5 500 507.5 mV VPFT PFI Hysteresis l 10 15 19 mV VCC,OP Minimum Operating Voltage to Guarantee PFO High (Note 3) VPFI = 0.55V l 2.3 V IV1 V1 input Current (Note 4) V1 = 3.3V, V1 > V2 l 10 30 80 A V1 = 3.3V, V1 < V2 l 3 10 30 A V2 = 5V (LTC2911-1) V2 = 2.5V (LTC2911-2) V2 = 1.8V (LTC2911-3) V2 = 1.2V (LTC2911-4) V2 = 0.55V (LTC2911-5) C-Grade/I-Grade H-Grade l l l l 10 3 2 2 35 10 10 10 80 30 30 30 A A A A l l 15 40 nA nA IV2 V2 Input Current (Note 4) IADJ ADJ Input Current VADJ = 0.55V (C-Grade) (I-Grade) VADJ = 0.55V (H-Grade) l l 15 40 nA nA IPFI PFI Input Current VPFI = 0.55V (C-Grade) (I-Grade) VPFI = 0.55V (H-Grade) l l 15 40 nA nA ITMR(UP) TMR Pull-Up Current VTMR = 1V l -1.5 -2.2 -2.9 A ITMR(DOWN) TMR Pull-Down Current VTMR = 1V l 1.5 2.2 2.9 A IPU RST, PFO Pull-Up Current VPIN = 0V l -20 -29 -40 A 2911f 3 LTC2911 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VADJ = 0.55V, VPFI = 0.55V, V1 = 3.3V unless otherwise noted. (Notes 2, 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX tP,PF PFI Comparator Propagation Delay to PFO VPFI Driven Beyond Threshold VPFT by More Than 10% tUV V1, V2, ADJ Undervoltage Detect to RST Low VOH UNITS l 8 30 80 s VX Less Than Threshold VRTX by More Than 10% l 8 30 80 s RST, PFO Output Voltage High (Note 5) IRST = -1A l V1 - 1 V1 V VOL RST, PFO Output Voltage Low (Note 6) VCC = 0.5V, I = 5A VCC = 1V, I = 100A VCC = 3V, I = 2.5mA l l l 0.01 0.01 0.10 0.15 0.15 0.30 V V V tRST(EXT) Reset Timeout Period, External CTMR = 2.2nF l 15 20 27 ms tRST(INT) Reset Timeout Period, Internal VTMR = V1 l 140 200 280 ms VTMR(INT) Timer Internal Mode Threshold VTMR Rising l V1 - 0.40 V1 - 0.020 V1 - 0.10 VTMR(INT) Timer Internal Mode Hysteresis VTMR Falling l 40 100 160 mV VTMR(LATCH) Timer Latch Mode Threshold VTMR Falling l 0.10 0.20 0.40 V VTMR(LATCH) Timer Latch Mode Hysteresis VTMR Rising l 40 75 160 mV 0.5 3 s V tP,LR Latch Release Propagation Delay to RST Low VTMR Rising, Step 0V to 0.6V l tSU,MON Monitor Input Setup Time to Latch Enable (Note 7) VTMR Falling, Step 0.6V to 0V Monitor Input Setup Time to Latch Release VTMR Rising, Step 0V to 0.6V Monitor Input Hold Time to Latch Enable VTMR Falling, Step 0.6V to 0V Monitor Input Hold Time to Latch Release VTMR Rising, Step 0V to 0.6V l 2 ms l 0 s tHD, MON Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive; all voltages are referenced to GND unless otherwise noted. Note 3: The internal supply voltage (VCC) is generated from the greater of the voltages on the V1 and V2 inputs. VCC = V1 for the LTC2911-5. Note 4: Under typical operating conditions, quiescent current is drawn from the greater of the voltages on the V1 and V2 inputs. For the LTC29115 only V1 supplies the quiescent current. Note 5: The RST and PFO output pins on the LTC2911 have internal pullups to V1. However, for faster rise times or for VOH voltages greater than V1, use an external pull-up resistor. Note 6: The RST and PFO pull-down currents are derived from V1 and V2 except for the LTC2911-5 where the pull-down strength is derived only from V1. Note 7: tSU,MON is required to latch a low RST state and tSU,MON + tRST is required to latch a high RST state. 2911f 4 LTC2911 TYPICAL PERFORMANCE CHARACTERISTICS Quiescent Supply Current vs Temperature 60 1.010 1.005 1.000 0.995 0.990 0.985 -50 -25 75 0 50 25 TEMPERATURE (C) 100 500 IV2 FOR LTC2911-1 50 400 40 30 20 -25 75 0 50 25 TEMPERATURE (C) 2911 G01 16.0 15.5 15.0 1.0 220 INTERNAL 200 EXTERNAL CTMR = 22nF 180 75 100 140 -50 125 -25 75 0 50 25 TEMPERATURE (C) RST, PFO Voltage Output High vs Source Current 6 V1 = 3.135V, V2 = 5V FOR RST 5 VOLTAGE OUTPUT HIGH (V) 2.5 1.5 1.0 0.5 V1 = V2 = ADJ = PFI 10k PULL-UP TO VCC RST FOR LTC2911-1 4 3 2 1 PFO RST FOR LTC2911-2 LTC2911-3 LTC2911-4 LTC2911-5 0 0 5 20 15 25 10 SOURCE CURRENT (A) 30 35 2911 G07 0.6 0.4 -40C 25C 85C 125C 150C 0.2 0 5 10 15 20 SINK CURRENT (mA) 25 -1 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 2911 G08 30 2911 G06 RST, PFO Voltage Output High vs VCC 2.0 0.8 0 125 VCC = 3V 2911 G05 2911 G04 3.0 100 RST, PFO Pin Source Current vs V1 100 OUTPUT SOURCE CURRENT (A) 50 25 TAMB (C) 100 RST, PFO Voltage Output Low vs Sink Current 160 14.5 0 10 2911 G03 VOLTAGE OUTPUT LOW (V) TIMEOUT PERIOD (ms) HYSTERESIS (mV) 16.5 1 0.1 OVERDRIVE (%) 240 17.0 VOLTAGE OUTPUT HIGH (V) 0 125 260 17.5 0 100 Reset Timeout Period vs Temperature 18.0 -25 200 2911 G02 PFI Hysteresis vs Temperature 14.0 -50 300 100 10 0 -50 125 Allowable Glitch Duration vs Overdrive GLITCH DURATION (s) 1.015 QUIESCENT SUPPLY CURRENT (A) NORMALIZED THRESHOLD VOLTAGE (V/V) Normalized Reset and Power-Fail Threshold Voltages vs Temperature 80 60 40 20 0 PFO 0 1 2 RST 3 V1 (V) 4 5 6 2911 G09 2911f 5 LTC2911 PIN FUNCTIONS ADJ: Adjustable Voltage Monitor Input. Input to a voltage monitor comparator with a 0.5V nominal threshold. Tie to V1 if unused. Exposed Pad (DFN Only): Exposed pad may be left open or connected to device ground. GND: Device Ground. PFI: Power-Fail Voltage Monitor Input. Input to the powerfail comparator with a 500mV threshold at the falling edge and a 515mV threshold at the rising edge, giving a 3% hysteresis for noise rejection. Tie to V1 or GND if unused. PFO: Power-Fail Logic Output. This pin asserts low when the PFI input voltage is below its threshold and goes high when the PFI input voltage is above its threshold. This pin provides a weak pull-up current to V1. This current is typically 29A at V1 = 3.3V. The pin can be pulled to voltages higher than V1 by external pull-up resistors. PFO provides an early warning signal of a system power failure. RST: Reset Logic Output. This pin asserts low when any of the V1, V2, or ADJ inputs are below their reset thresholds. Pulls high when all the monitored inputs are above their thresholds for longer than a timeout period. This pin provides a weak pull-up current to V1. This current is typically 29A at V1 = 3.3V. The pin can be pulled to voltages higher than V1 by external pull-up resistors. The status of RST can be latched by holding the TMR pin at GND. TMR: Reset Timeout Control. Attach an external capacitor, CTMR, to GND to set a reset timeout period of 9.4ms/nF. A low leakage ceramic capacitor is recommended for timer accuracy. A 2.2nF capacitor generates a 20ms timeout. Leaving the TMR pin open without a capacitor generates a minimum timeout of approximately 400s which will vary depending on the parasitic capacitance on the pin. Tying this pin to V1 enables the internal 200ms timeout. Pulling this pin to GND latches the reset state. V1: 3.3V Monitor and Power Supply Input. V1 is an accurate 3.3V, -5% undervoltage supply monitor. The internal VCC is generated from the greater of the voltages at the V1 and V2 inputs for the LTC2911-1/LTC29112/LTC29113/LTC2911-4 options. The LTC2911-5 option always derives its power supply from the V1 pin. Bypass this pin to GND with a 0.1F (or greater) capacitor for the LTC2911-2 through LTC2911-5. V2: Voltage Monitor and Power Supply Input. V2 is a -5% undervoltage supply monitor for a 5V, 2.5V, 1.8V or 1.2V supply for the LTC2911-1/LTC29112/LTC29113/LTC29114 options, respectively. Because the internal VCC is generated from the greater of the V1 and V2 inputs for these options, the V2 pin should be bypassed to GND with a 0.1F (or greater) capacitor for the LTC2911-1. The V2 pin of the LTC2911-5 is a high impedance input with a 0.5V threshold, allowing the trip threshold of the monitored supply to be configured with a resistive divider. 2911f 6 LTC2911 BLOCK DIAGRAM V1 V1 V2* POWER DETECT 114k VCC - PFI PFO +PFI COMP VCC LOW VOLTAGE PULL-DOWN TMR 1.36M V1 - 263k THREE-STATE DECODE V1 COMP + V1 114k RX** V2 ADJUSTABLE PULSE GENERATOR - 231k** V2 COMP LATCH + 200ms PULSE GENERATOR - ADJ RST VCC LOW VOLTAGE PULL-DOWN ADJ COMP + 0.5V + - MONITORED VOLTAGES GND LTC2911 LTC2911-1 LTC2911-2 LTC2911-3 LTC2911-4 LTC2911-5 V2 5V 2.5V 1.8V 1.2V ADJ RX 1.93M 850k 547k 288k ** *FOR OPTIONS LTC2911-1 THROUGH LTC2911-4 ONLY. **OMIT THE RESISTIVE DIVIDER FOR THE LTC2911-5. 2911 BD 2911f 7 LTC2911 TIMING DIAGRAMS Power-Fail Timing Undervoltage and Reset Timing VX PFI VRTX tUV tP,PF tRST RST VPFT tP,PF PFO 1.0V 2911 TD03 1.0V 2911 TD01 Latch Release to RST Low Timing TMR 0.4V tP,LR 1.0V RST 2911 TD02 NOTE: ADJ FORCED LOW BEFORE TMR RELEASE Latching RST High Input Valid to Latch Enable Setup and Hold Timing TMR VTMR(LATCH) + VTMR(LATCH) VTMR(LATCH) tRST ADJ, V1, V2 Input Valid to Latch Release Setup Timing tSU,MON tHD,MON VRTX 3% OVERDRIVE t > tSU,MON MARGINING -3% OVERDRIVE RST POWER UP 2911 TD04 1V LATCH IN NOTE: FOR THE LTC2911-5, V1 LOW RESETS RST TO A LOW STATE INPUT RETURNING TO ABOVE VRTX FOR t > tSU,MON, RST PIN STAYS HIGH Latching RST Low Input Invalid to Latch Enable Setup and Hold Timing TMR RST VTMR(LATCH) + VTMR(LATCH) VTMR(LATCH) tHD,MON tSU,MON tUV ADJ, V1, V2 Input Invalid to Latch Release Setup Timing t > tSU,MON 3% OVERDRIVE MARGINING VRTX -3% OVERDRIVE 1V -3% OVERDRIVE VRTX LATCH IN NOTE: FOR THE LTC2911-5, V1 LOW RESETS RST TO A LOW STATE 2911 TD05 INPUT RETURNING TO BELOW VRTX FOR t > tSU,MON, RST PIN STAYS LOW 2911f 8 LTC2911 APPLICATIONS INFORMATION The LTC2911 is a low power, high accuracy triple supply monitor with power-fail comparator. For the LTC2911-1, LTC2911-2, LTC2911-3 and LTC29114 options, the V1 and V2 pins monitor two supplies. Their thresholds are preset internally based on the option chosen. A resistive divider connected to the ADJ pin configures the third threshold. For the LTC2911-5, the V2 pin is a high impedance adjustable input similar to the ADJ pin. Reset timeout of the device may be selected with an external capacitor or set to an internally generated 200ms. The ADJ, V1 and V2 inputs must be valid (above their thresholds) for longer than the reset timeout period before the RST pin transitions high. The LTC2911 uses proprietary low voltage drive circuitry for the RST and PFO pins which holds them low with VCC (the higher of V1 and V2) as low as 0.5V. This helps prevent indeterminate voltages from appearing on the outputs during power-up. For additional details refer to the Output Pin Characteristics section. When V1 and V2 are ramped simultaneously (for LTC29111/LTC2911-2/LTC2911-3/LTC2911-4), the pulldown current from the RST and PFO pins is about twice the current available when V1 or V2 is grounded. Power Down The power-fail comparator causes the PFO pin to pull low when the PFI pin falls below 0.5V. A resistive divider connected to the PFI pin configures the threshold of the monitored voltage. The PFO output typically provides an early warning of imminent power failure so that the system may begin shutdown procedures such as supply sequencing and/or storage of system state in nonvolatile memory. On power-down, when the voltage monitored by the powerfail comparator falls below the threshold configured by its resistive divider, the PFO pin pulls low to provide an early warning of imminent power failure. In a typically configured system, this occurs before the supplies monitored by V1, V2 or ADJ fall below their thresholds and cause the RST pin to pull low. The RST and PFO pins maintain a logic low output for VCC as low as 0.5V. See the Output PIn Characteristics section for additional details. Power-Up Power-Fail Monitoring and PFO Signaling The LTC2911-1, LTC2911-2, LTC2911-3 and LTC2911-4 supervisors are powered from the V1 and V2 pins, automatically selecting the pin with the higher potential. The exception in the device family, the LTC2911-5, derives its internal supply voltage (VCC) only from V1. When all monitor inputs are above their thresholds, the quiescent supply current drawn from VCC is typically 30A (35A for the LTC2911-1). When the three monitor inputs (V1, V2 and ADJ) rise above their thresholds, the appropriate timeout delay begins, after which RST pulls to V1. Once the PFI input rises above 515mV, the PFO output signals high indicating that the supply or voltage monitored by PFI is above threshold. The LTC2911's PFI input monitors a voltage through a resistive divider and compares it to the internal power-fail threshold. When PFI drops below 0.50V (the power-fail threshold) the PFO output pulls low to provide an early warning of a low voltage condition. When the PFI pin rises above 0.515V again, the PFO output signals high indicating a valid supply condition. The PFI input typically monitors the primary power supply of a system. For example, the PFI pin may monitor the input supply of a DC/DC converter or a Li-Ion battery stack voltage. The PFO output typically provides a warning to the system that the power supply is on the verge of failing so that it can prepare for a controlled shutdown. For 2911f 9 LTC2911 APPLICATIONS INFORMATION example, the PFO pin may connect to a processor nonmaskable interrupt. When the battery pack voltage drops below the shutdown threshold, as sensed at PFI, the PFO pin pulls low to issue an interrupt. Next, the processor begins shutdown procedures which may include supply sequencing and/or storage/erasure of system state in nonvolatile memory. Threshold Accuracy Specifying the minimum supply voltage for a system requires the designer to consider three factors: minimum supply voltage for proper operation, power supply tolerance, and supervisor reset threshold accuracy. Highly accurate supervisors ease the design challenge by decreasing the overall voltage margin required for reliable system operation. The reset threshold band and the power supply tolerance bands should not overlap. This prevents false or nuisance resets when the power supply is actually within its specified tolerance band. The actual reset threshold of supervisors varies over a specified band. The LTC2911 supervisor varies 1.5% around its nominal threshold voltage over temperature. 3.3V The system must operate reliably a little below 3.036V (or 3.3V, -8%), or risk malfunction before a reset signal is properly issued. A less accurate supervisor increases the supply voltage tolerance requirements and the risk of system malfunction. The LTC2911's 1.5% threshold voltage specification minimizes these requirements. V1 and V2 Supply Monitors All the LTC2911 options have a V1 threshold equal to 3.086V (3.3V - 6.5%). The V2 thresholds are 4.675V (5V - 6.5%), 2.338V (2.5V - 6.5%), 1.683V (1.8V - 6.5%) and 1.122V (1.2V - 6.5%) for options LTC2911-1, NOMINAL SUPPLY VOLTAGE SUPPLY TOLERANCE MINIMUM RELIABLE SYSTEM VOLTAGE 1.5% THRESHOLD BAND Figure 1 illustrates a typical 3.3V monitor. The LTC2911 has 1.5% reset threshold accuracy. The nearest practical supervisor trip point is the sum of power supply tolerance and the LTC2911 tolerance. So a "5%" threshold is typically set to -6.5%, excluding resistor errors. Thus for a 3.3V "5%" threshold, the practical supervisor trip point is at 3.086V. The threshold is guaranteed to lie in the band between 3.036V and 3.135V over the operating temperature range. This 3.135V maximum threshold is at the lower limit of supply tolerance (3.3V - 5%) to prevent false tripping. IDEAL SUPERVISOR THRESHOLD 3.135V -5% 3.086V -6.5% 3.036V -8% REGION OF POTENTIAL MALFUNCTION 2911 F01 Figure 1. 1.5% Threshold Accuracy Improves System Reliability 2911f 10 LTC2911 APPLICATIONS INFORMATION LTC29112, LTC2911-3 and LTC2911-4 respectively. V2 of the LTC29115 option is a high impedance input with a nominal 0.5V threshold. To minimize errors arising from the ADJ input bias current, a value of less than 100k is recommended for R1. R2 is then chosen by: Input Noise Filtering for RST The V1, V2 and ADJ comparators have a response time that is inversely proportional to overdrive. This characteristic is illustrated in the Typical Performance Characteristics as the graph Allowable Glitch Duration versus Overdrive. The ADJ and the LTC2911-5's V2 pin may be bypassed with a capacitor to increase the filtering in applications that demand it. The resultant RC lowpass filter at the inputs will further reject high frequency components, at the cost of slowing the monitor's response to fault conditions. where, VTRIP_ADJ is the supply threshold when the ADJ pin falls below its 0.5V threshold. For accurate monitoring, the resistor tolerance should be as small as possible. Resistor tolerance of 0.1% or some trimming of components should be considered for R2/R1 in applications that require an accurate trip point. Resistor Selection for PFI Resistor Selection for ADJ The threshold of the supply monitored by the ADJ pin is configured with an external resistive divider (R2 and R1) connected between the supply and ground. The tap point for the divider is connected to the adjustable input (ADJ) which has a 0.5V threshold. (See Figure 2) Normally, the user selects a trip voltage based on the supply and acceptable tolerances, and a value of R1 based on current drawn. For a given current, I, R1 is given by: R1= V R2 = R1* TRIP_ ADJ - 1 0.5V An external resistive divider (R3 and R4) connected between the supply and ground configures the threshold of the supply monitored by the power-fail comparator. The tap point for the divider is connected to the PFI input which has a 0.5V threshold. (See Figure 3a) Resistor selection follows a process similar to that for the ADJ pin. R3 is given by: 0.5V I R3 = 0.5V I VTRIP R2 - ADJ R1 LTC2911 + 0.5V + - 2911 F02 Figure 2. Setting the Adjustable (ADJ) Trip Point 2911f 11 LTC2911 APPLICATIONS INFORMATION R5 V1 VTRIP R4 V1 LTC2911 114k - PFI R3 VTRIP PFO + 0.5V R4 LTC2911 - PFI R3 + - 114k V1 PFO R6 + 0.5V 2911 F03a + - 2911 F03b Figure 3a. Setting the Power-Fail (PFI) Trip Point Figure 3b. Increasing Power-Fail Hysteresis Again, to minimize errors arising from the PFI input bias current, a value of less than 100k is recommended for R3. R4 can be chosen either using the PFI falling threshold or the PFI rising threshold. For the falling edge threshold, use the equation: V R4 = R3 * TRIP_ PFI_ FALL - 1 0.5V Alternatively, for the rising edge threshold, use the equation: V R4 = R3 * TRIP_ PFI_ RISE - 1 0.515V where VTRIP_PFI_FALL is the supply threshold when the PFI pin falls below the 0.5V falling threshold, and VTRIP_PFI_RISE is the supply threshold when the PFI pin rises above the 0.515V rising threshold. Note that VTRIP_PFI_RISE is typically 3% above the VTRIP_PFI_FALL due to the fact that the PFI 515mV rising threshold is 3% above its 500mV falling threshold. edges. The nominal threshold is 500mV at the falling edge and 515mV at the rising edge. The hysteresis prevents oscillation when the monitored voltage passes through the thresholds. If the PFI pin is connected to an external resistive divider, it may be bypassed with a capacitor for additional noise filtering. Increasing the Power-Fail Hysteresis The power-fail comparator hysteresis can be increased by adding two resistors, R5 and R6, as shown in Figure 3b. When PFO is low, R5 sinks current from the center tap of the R3 and R4 resistive divider. The upper threshold is therefore given by: R4 R4 VH = 0.515V 1+ + R3 R5 When PFO is high, the series combination of R5 and R6 sources current into the center tap of the R3 and R4 resistive divider. This leads to a lower threshold of: R4 ( 3.3V - 0.5V )R4 VL = 0.5V 1+ - R3 R5 +R6 In applications that require an accurate trip point, the R4 and R3 resistors should have small tolerances. The addition of R5 and R6 increases the hysteresis to: Hysteresis for Power-Fail Comparator VHYST = VH - VL The power-fail comparator uses a positive 3% accurate hysteresis to combat spurious triggering while maintaining accurate thresholds for both the rising and falling R4 R4 ( 3.3V - 0.5V )R4 = 0.015 1+ + 0.515 + R3 R5 R5 +R6 2911f 12 LTC2911 APPLICATIONS INFORMATION Resistor Selection for Combined Reset and Power-Fail Divider When the power-fail and reset signals are based on the same supply, the PFI and ADJ inputs may be connected to a single resistive divider formed from three resistors. The configuration is shown in Figure 4. For a given bias current I, RA, RB and RC can be calculated from: 0.5V I V RB = R A * TRIP_ PFI_ FALL - 1 VTRIP _ ADJ RA = V V RC = R A * TRIP_ ADJ - 1 * TRIP_ PFI_ FALL 0.5V VTRIP_ ADJ For example, consider monitoring a 5V, 5% supply with VTRIP_PFI_FALL = 4.5V and VTRIP_ADJ = 4V. The resulting VTRIP_PFI_RISE is equal to 4.63V or 3% above VTRIP_PFI_FALL. The maximum VTRIP_PFI_RISE should not overlap the minimum power supply voltage level for PFO to deassert when the supply recovers. Mathematically, after factoring in the sum of the power supply tolerance and the LTC2911 tolerance, the VTRIP_PFI_RISE should be lower than 5V - 6.5%. Setting the Reset Timeout RST goes high after the V1, V2 and ADJ inputs are above their thresholds for a reset timeout period. Connecting the TMR pin to V1 enables the internal 200ms timer. To configure a different reset timeout period connect a capacitor between the TMR pin and ground. The following formula approximates the value of capacitor needed for a particular timeout: CTMR = tRST * 106.5 [pF/ms] Leaving the TMR pin open with no external capacitor generates a reset timeout of approximately 400s. Larger capacitors may be used to increase the timeout, but the capacitor leakage current must not exceed 500nA. Otherwise, the timer accuracy will be severely affected. Suitable values of CTMR for a given tRST may be selected from Figure 5. 10000 VTRIP - ADJ LTC2911 1000 EXTERNAL TIMEOUT, tRST (ms) RC See Threshold Accuracy section for more details. In the design, if we wish to consume about 5A in the divider, RA = 100k. We then find RB = 12.4k and RC = 787k (nearest 1% standard values). + RB - PFI RA + 0.5V + - 100 10 1 0.1 10p 2911 F04 Figure 4. Combining PFI/ADJ Monitoring of One Supply with Three Resistors 100p 1n 10n CTMR (F) 100n 1 2911 F05 Figure 5. External Timeout vs CTMR 2911f 13 LTC2911 APPLICATIONS INFORMATION Reset Latch Mode At any time, the TMR pin can be pulled low to latch the RST pin status, overriding the reset operation. This feature is useful when testing a system at supply voltages that might otherwise cause the RST pin to assert. If the RST pin is unasserted (high) before the latch is enabled (by pulling the TMR pin low), RST will remain unasserted after the TMR pin is released. This is true provided that all reset monitor inputs are valid when TMR releases, regardless of their state while the TMR pin was low. However, if RST was unasserted before TMR was pulled low, and now one of the inputs is invalid when TMR is released, RST will assert after a tPL,LR propagation delay (see Figure 6a). Conversely, if RST was asserted (low) before TMR was pulled low, and all inputs are valid when TMR is released, RST will deassert (go high) after a tRST delay (see Figures 6b and 6c). The RST pin remains asserted for a full tRST timeout after the TMR pin is released, regardless of the state of the tRST timer before the latch was enabled. The reset latch mode is useful for performing supply margining tests without resetting the system (see Figure 6d). At least 2.9A of pull-up or pull-down current is required to hold the TMR pin high or low to configure the internal timer or reset latch mode. However, during the timer mode transition, 100A will be required to switch the TMR floating state to ground or V1. Connecting the TMR pin to any voltage other than ground or V1 may have unpredictable results. LATCH RELEASE TMR ADJ, V1, V2 LATCH RELEASE VTMR(LATCH) + VTMR VTMR(LATCH) TMR VRTX VTRM(LATCH) ADJ, V1, V2 RST 1.0V t > tSU,MON VRTX RST tP,LR Figure 6c. Timer Latched Before Timeout. After Latch Release, RST Stays Low for a Full Timeout Before Going High LATCH RELEASE VTMR(LATCH) + VTMR VTMR(LATCH) TMR VRTX ADJ, V1, V2 t > tSU,MON RST 1.0V 2911 F06c LATCH RELEASE ADJ, V1, V2 tRST t < tRST 2911 F06a Figure 6a. Input Toggled Low While Timer Latched. RST Goes Low tP,LR After Latch Release TMR VTMR(LATCH) + VTMR tRST 1.0V RST MARGINING VTRX t > tHD,MON tRST 1.0V 2911 F06b t > tRST Figure 6b. Input Toggled High While Timer Latched. RST Goes High tRST After Latch Release VTMR(LATCH) + VTMR VTRM(LATCH) t > tSU,MON 2911 F06d NO RECOUNTING Figure 6d. Timer Latched After Timeout and RST High. RST Stays High After Margining if Inputs are Restored Before Release 2911f 14 LTC2911 APPLICATIONS INFORMATION During power-up, with a capacitor connected to the TMR pin, the part remains in the reset latch mode described above until the 2.2A flowing out of the TMR pin charges the capacitor beyond the VTMR(LATCH) threshold. For this reason, large capacitors will extend the RST timeout during power-up. For example, if CTMR = 1F, the LTC2911 leaves the reset latch mode 90ms after power-up and the RST pin goes high after a 9 second timeout. Figures 7a and 7b show how the TMR pin can be driven low to latch the state of the RST pin or floated or driven high for external and internal reset timing, respectively. TMR SYSTEM LOGIC Figure 7a. Open-Drain (or Three-State Buffer) Output. Grounds TMR to Latch the State of RST. Floats TMR for External Reset Timing V1 TMR 2911 F07b Figure 7b. V1 Powered Inverter. Grounds TMR to Latch the State of RST. Drives TMR High for Internal Reset Timing The open-drain output pins (RST and PFO) contain weak pull-up circuitry to V1. Use an external pull-up resistor when the outputs need to pull beyond V1 and/or require a faster rise time. Use external pull-up resistor values of 100k or less. When output pins are externally pulled up to voltages higher than V1, an internal network automatically protects the weak pull-up circuitry from reverse currents. For a given external load capacitance or CLOAD, the rise and fall times can be estimated using Figure 9. The output pins have very strong pull-down capability. With a 150pF load capacitance the reset line can pull down in about 30ns. 10m VCC = 0.5V 1m 1600 tRISE LTC2911-1 100 tFALL OR tRISE (s) VOLTAGE OUTPUT LOW (mV) 2000 The DC characteristics of the RST and PFO pull-down strength are shown in the Typical Performance Characteristics. The circuits that drive the pull-down of the output pins are powered by the internal VCC (the greater voltage of V1 or V2). During power-up, a VCC of at least 0.5V ensures a low output state. The VOL voltage depends on the current sunk by RST and PFO as shown in the Figure 8. The open-drain nature of the RST and PFO pins allows for wire-ORed connections. For example, multiple LTC2911s may be wire-ORed to monitor additional supplies, or opendrain logic can be connected to allow other conditions to issue the reset and/or power-fail signals. Output Pin Rise and Fall Time 2911 F07a SYSTEM LOGIC Output Pin Characteristics 1200 800 10 1 tFALL LTC2911-1 100n 400 0 10n 0 10 20 30 40 50 60 70 80 90 100 ISINK (A) 2911 F08 Figure 8. Voltage Output Low vs ISINK at VCC = 0.5V 1n 10p 100p 1n 10n CLOAD (F) 2911 F09 Figure 9. tRISE and tFALL vs CLOAD 2911f 15 LTC2911 TYPICAL APPLICATIONS Triple Supply Monitor and Overtemperature Signal 3.3V 3.3V 5V 5V 12V 12V VTRIP = 10.75V V1 RESET RST LTC2911-1 0.1F R4 200k OVERTEMP PFO TRIP TEMPERATURE = 90C RECOVER TEMPERATURE = 89C PFI R2 2.05M C1** 10nF R3 R31* 270k V2 ADJ TMR CTMR 2.2nF GND R1 100k 2911 TA02 tRST = 20ms *THERMISTOR MURATA NTC NCP15WM474J03RC TOLERANCE 5%. NTC RESISTANCE IS 474k AT ROOM, 35.8k AT 85C **OPTIONAL BYPASS CAPACITOR FOR SUPPLY TRANSIENT NOISE FILTERING Quad Supply Monitor 3.3V V1 0.1F 2.5V 12V VTRIP = 10.5V R6 383k VTRIP = 4.53V R1 100k D1 BAS119 RESET LTC2911-2 V2 R4 806k 5V R5 1.62M RST PFO PFI R3 100k ADJ TMR GND CTMR 2.2nF tRST = 20ms 2911 TA03 2911f 16 LTC2911 TYPICAL APPLICATIONS 48V Telecom UV/OV Monitor with Hysteresis VIN 36V TO 72V RCC 27k 0.25W R2A 1.43M 0.1F 16V 5.6V M1 R2B 169k 5V TMR V1 V2 R4 1.87M LTC2911-1 R1 18.7k ADJ RST PFI PFO R3 13.7k UV RPU1 10k OV GND 2911 TA04 M1: FDG6301N OR SIMILAR VUV(RISING) = 43.3V VUV(FALLING) = 38.7V VOV(RISING) = 70.8V VOV(FALLING) = 68.8V 4-Cell NiMH Stack Voltage Monitor with Input Overvoltage Signaling FROM CHARGER 1N5817 + + + + 0.1F 1.2V 1.2V R2 576k V1 V2 TMR LTC2911-2 R4 1.18M 1.2V 1.2V ADJ RST PFI PFO R3 102k R1 100k LOBAT OV GND tRST = 200ms BATTERY LOW RESET THRESHOLD = 3.38V OVERVOLTAGE TRIP THRESHOLD = 6.47V OVERVOLTAGE RECOVER THRESHOLD = 6.28V 2911 TA05 4-Cell Alkaline Stack Voltage Monitor with Early Power-Fail Warning + + + + 0.1F 1.5V 1.5V 1.5V 1.5V RC 665k RB 15k RA 100k V1 V2 TMR LTC2911-2 ADJ RST PFI PFO RESET LOBAT GND tRST = 200ms 2911 TA06 POWER-FAIL FALLING THRESHOLD = 3.90V POWER-FAIL RISING THRESHOLD = 4.02V RESET THRESHOLD = 3.39V 2911f 17 LTC2911 PACKAGE DESCRIPTION TS8 Package 8-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1637) 0.52 MAX 2.90 BSC (NOTE 4) 0.65 REF 1.22 REF 1.4 MIN 3.85 MAX 2.62 REF 2.80 BSC 1.50 - 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.22 - 0.36 8 PLCS (NOTE 3) 0.65 BSC 0.80 - 0.90 0.20 BSC 0.01 - 0.10 1.00 MAX DATUM `A' 0.30 - 0.50 REF 0.09 - 0.20 (NOTE 3) NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 1.95 BSC TS8 TSOT-23 0802 2911f 18 LTC2911 PACKAGE DESCRIPTION DDB Package 8-Lead Plastic DFN (3mm x 2mm) (Reference LTC DWG # 05-08-1702 Rev B) 0.61 0.05 (2 SIDES) 0.70 0.05 2.55 0.05 1.15 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.20 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3.00 0.10 (2 SIDES) R = 0.115 TYP 5 R = 0.05 TYP 0.40 0.10 8 2.00 0.10 (2 SIDES) PIN 1 BAR TOP MARK (SEE NOTE 6) 0.56 0.05 (2 SIDES) 0.200 REF 0.75 0.05 0 - 0.05 4 0.25 0.05 1 PIN 1 R = 0.20 OR 0.25 x 45 CHAMFER (DDB8) DFN 0905 REV B 0.50 BSC 2.15 0.05 (2 SIDES) BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 2911f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC2911 TYPICAL APPLICATION Triple Supply Monitor with Early Power-Fail Warning (With Manual Reset and Latchable Reset for Margining) 3.3V 1.8V DC/DC CONVERTER 1.0V SYSTEM LOGIC VTRIP = 0.88V V1 0.1F RESD* 10k VTRIP = 3.37V + Li-Ion R2 76.8k RST RESET LTC2911-3 V2 PFO LOBAT ADJ R1 100k R4 1.43M PFI R3 249k TMR GND VN2222 CTMR 2.2nF 2911 TA07 *OPTIONAL RESISTOR FOR ADDED ESD PROTECTION RST_LATCH SIGNAL HIGH TO PERFORM MARGINING RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1326/LTC1326-2.5 Micropower Precision Triple Supply Monitor for 5V/2.5V, 3.3V and ADJ 4.725V, 3.118V, 1V Threshold (0.75%) LTC1536 Precision Triple Supply Monitor for PCI Applications Meets PCI tFAIL Timing Specifications LTC1726-2.5/LTC1726-5 Micropower Triple Supply Monitor for 2.5V/5V, 3.3V and ADJ Adjustable Reset and Watchdog Timeouts LTC1727/LTC1728 Micropower Triple Supply Monitor With Open-Drain Reset Individual Monitor Outputs in MSOP/5-Lead SOT-23 LTC1985-1.8 Micropower Triple Supply Monitor with Push-Pull Reset Output 5-Lead SOT-23 Package LTC2909 Precision, Triple/Dual Input UV, OV and Negative Voltage Monitor 8-Lead SOT-23 and DFN Packages LTC2912/LTC2913/ LTC2914 Single/Dual/Quad UV and OV Voltage Monitors Separate VCC Pin, Adjustable Reset Timer, H-Grade Temperature Range LTC2915/LTC2916/ LTC2917/LTC2918 Single Voltage Monitor With 27 Unique Thresholds Manual Reset, Watchdog, TSOT-8/MSOP-10 and 3mm x 2mm DFN Packages, H-Grade Temperature Range LTC2919 Precision, Triple/Dual Input UV, OV and Negative Voltage Monitor 10-Lead 3mm x 2mm and MSOP Packages, H-Grade Temperature Range (Individual Outputs for ADJ Comparators and System RST) 2911f 20 Linear Technology Corporation LT 0910 * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com LINEAR TECHNOLOGY CORPORATION 2010