TS8388BCG - Atmel Corporation

Product Specification

MAIN FEATURES

 8-bit resolution.

 ADC gain adjust.

 1.8 GHz full power input bandwidth.

 1 Gsps (min) sampling rate.

 SINAD = 44.3 dB (7.2 Effective Bits) SFDR = 58 dBc

@ FS = 1 Gsps, FIN = 20 MHz :

 SINAD = 42.9 dB (7.0 Effective Bits) SFDR = 52 dBc

@ FS = 1 Gsps, FIN = 500 MHz :

 SINAD = 40.3dB (6.8 Effective Bits) SFDR = 50 dBc

@ FS = 1 Gsps, FIN = 1000 MHz (-3 dB FS)

 2-tone IMD : -52dBc (489 MHz, 490 MHz) @ 1GSPS.

 DNL = 0.4 LSB INL = 0.7 LSB.

 Low Bit Error Rate (10-13 ) @ 1 Gsps

 Very low input capacitance : 3 pF

 500 mVpp differential or single-ended analog inputs.

 Differential or single-ended 50Ω ECL compatible clock inputs.

 ECL or LVDS/HSTL output compatibility.

 Data ready output with asynchronous reset.

 Gray or Binary selectable output data ; NRZ output mode.

 Power consumption : 3.9 W @ Tj = 70°C typical

APPLICATIONS

 Digital Sampling Oscilloscopes.

 Satellite receiver.

 Electronic countermeasures / Electronic warfare.

 Direct RF down–conversion.

 Very High Speed Data Acquisition board

SCREENING

 Atmel-Grenoble standard screening level

 Temperature range: up to 0°C < Tc ; Tj < +90°C

DESCRIPTION

The TS8388BG is a monolithic 8–bit analog–to–digital converter, designed for

digitizing wide bandwidth analog signals at very high sampling rates of up to 1

Gsps.

The TS8388BG is using an innovative architecture, including an on chip Sample

and Hold (S/H), and is fabricated with an advanced high speed bipolar process

(B6HF from Siemens).

The on–chip S/H has a 1.8 GHz full power input bandwidth, providing excellent

dynamic performance in undersampling applications (High IF digitizing).

G Suffix : CBGA 72

Ceramic Ball Grid Array

With R and C decoupling on the package

ADC 8-bit 1 Gsps

TS8388BG

1/ Die form : JTS8388B

2/ Evaluation board :

TSEV8388BG

Detailed specification on request.

3/ Demultiplexer :

TS81102G0 : companion device available

January 2002

2TS8388BG

Product Specification

TABLE OF CONTENTS

1. SIMPLIFIED BLOCK DIAGRAM....................................................................................................................................3

2. FUNCTIONAL DESCRIPTION ........................................................................................................................................3

3. SPECIFICATIONS..............................................................................................................................................................4

3.1. ABSOLUTE MAXIMUM RATINGS (SEE NOTES BELOW).................................................................................................................... 4

3.2. RECOMMENDED CONDITIONS OF USE ............................................................................................................................................. 4

1.3. ELECTRICAL OPERATING CHARACTERISTICS ................................................................................................................................. 5

1.4. TIMING DIAGRAMS................................................................................................................................................................................ 9

1.5. EXPLANATION OF TEST LEVELS ...................................................................................................................................................... 10

1.6. FUNCTIONS DESCRIPTION................................................................................................................................................................ 10

1.7. DIGITAL OUTPUT CODING ................................................................................................................................................................. 10

4. PACKAGE DESCRIPTION. ............................................................................................................................................11

4.1. TS8388BG PIN DESCRIPTION ............................................................................................................................................................ 11

4.2. TS8388BG PINOUT OF CBGA72 PACKAGE ...................................................................................................................................... 12

4.3. TS8388BG CAPACITIES AND RESISTANCES IMPLANT .................................................................................................................. 13

4.4. OUTLINE DIMENSIONS - 72 PINS CBGA ........................................................................................................................................... 14

4.5. THERMAL AND MOISTURE CHARACTERISTICS ................................................................................................................................... 15

5. TYPICAL CHARACTERIZATION RESULTS .............................................................................................................16

5.1. STATIC LINEARITY – FS = 50 MSPS / FIN = 10 MHZ......................................................................................................................... 16

5.2. EFFECTIVE NUMBER OF BITS VERSUS POWER SUPPLIES VARIATION ..................................................................................... 17

5.3. TYPICAL FFT RESULTS ...................................................................................................................................................................... 18

5.4. SPURIOUS FREE DYNAMIC RANGE VERSUS INPUT AMPLITUDE ................................................................................................ 19

5.5. DYNAMIC PERFORMANCE VERSUS ANALOG INPUT FREQUENCY ............................................................................................. 21

5.6. EFFECTIVE NUMBER OF BITS (ENOB) VERSUS SAMPLING FREQUENCY .................................................................................. 22

5.7. SFDR VERSUS SAMPLING FREQUENCY ......................................................................................................................................... 22

5.8. TS8388BG ADC PERFORMANCES VERSUS JUNCTION TEMPERATURE ..................................................................................... 23

5.9. TYPICAL FULL POWER INPUT BANDWIDTH .................................................................................................................................... 24

5.10. ADC STEP RESPONSE................................................................................................................................................................... 25

6. DEFINITION OF TERMS ................................................................................................................................................26

7. TS8388BG MAIN FEATURES .........................................................................................................................................28

7.1. TIMING INFORMATIONS ..................................................................................................................................................................... 28

7.2. PRINCIPLE OF DATA READY SIGNAL CONTROL BY DRRB INPUT COMMAND............................................................................ 29

7.3. ANALOG INPUTS (VIN) (VINB) ............................................................................................................................................................ 29

7.4. CLOCK INPUTS (CLK) (CLKB) ............................................................................................................................................................ 30

7.5. NOISE IMMUNITY INFORMATIONS.................................................................................................................................................... 33

7.6. DIGITAL OUTPUTS .............................................................................................................................................................................. 33

7.7. OUT OF RANGE BIT ............................................................................................................................................................................ 36

7.8. GRAY OR BINARY OUTPUT DATA FORMAT SELECT...................................................................................................................... 36

7.9. DIODE PIN K1....................................................................................................................................................................................... 36

7.10. ADC GAIN CONTROL PIN K6 ......................................................................................................................................................... 37

8. EQUIVALENT INPUT / OUTPUT SCHEMATICS ......................................................................................................38

8.1. EQUIVALENT ANALOG INPUT CIRCUIT AND ESD PROTECTIONS ................................................................................................ 38

8.2. EQUIVALENT ANALOG CLOCK INPUT CIRCUIT AND ESD PROTECTIONS................................................................................... 38

8.3. EQUIVALENT DATA OUTPUT BUFFER CIRCUIT AND ESD PROTECTIONS .................................................................................. 39

ADC GAIN ADJUST EQUIVALENT INPUT CIRCUITS AND ESD PROTECTIONS.......................................................................................... 39

8.5. GORB EQUIVALENT INPUT SCHEMATIC AND ESD PROTECTIONS.............................................................................................. 40

8.6. DRRB EQUIVALENT INPUT SCHEMATIC AND ESD PROTECTIONS .............................................................................................. 40

9. TSEV8388BG : DEVICE EVALUATION BOARD........................................................................................................41

10. ORDERING INFORMATION .....................................................................................................................................42

10.1. PACKAGE DEVICE .......................................................................................................................................................................... 42

10.2. EVALUATION BOARD ..................................................................................................................................................................... 42

Product Specification

TS8388BG

1. SIMPLIFIED BLOCK DIAGRAM

2. FUNCTIONAL DESCRIPTION

The TS8388BG is an 8 bit 1GSPS ADC based on an advanced high speed bipolar technology featuring a cutoff frequency of 25 GHz.

The TS8388BG includes a front-end master/slave Track and Hold stage (S/H), followed by an analog encoding stage and interpolation circuitry.

Successive banks of latches are regenerating the analog residues into logical data before entering an error correction circuitry and a

resynchronization stage followed by 75 Ω differential output buffers.

The TS8388BG works in fully differential mode from analog inputs up to digital outputs.

The TS8388BG features a full power input bandwidth of 1.8 GHz.

Control pin GORB is provided to select either Gray or Binary data output format.

Gain control pin is provided in order to adjust the ADC gain.

A Data Ready output asynchronous reset (DRRB) is available on TS8388BG.

The TS8388BG uses only vertical isolated NPN transistors together with oxide isolated polysilicon resistors, which allow enhanced radiation

tolerance (no performance drift measured at 150kRad total dose).

VIN,VINB

CLK, CLKB

G=2 T/H G=1 T/H G=1

CLOCK

BUFFER

RESISTOR

CHAIN

ANALOG

ENCODING

BLOCK

INTERPOLATION

STAGES

REGENERATION

LATCHES

ERROR CORRECTION &

DECODE LOGIC

OUTPUT LATCHES &

BUFFERS

GAIN

DRRB DR,DRB GORB DATA,DATAB OR,ORB

MASTER/SLAVE TRACK & HOLD AMPLIFIER

4TS8388BG

Product Specification

3. SPECIFICATIONS

3.1. ABSOLUTE MAXIMUM RATINGS (SEE NOTES BELOW)

Parameter Symbol Comments Value Unit

Positive supply voltage VCC GND to 6 V

Digital negative supply

voltage

DVEE GND to -5.7 V

Digital positive supply

voltage

VPLUSD GND-0.3 to 2.8 V

Negative supply voltage VEE GND to -6 V

Maximum difference

between negative supply

voltages

DVEE to VEE 0.3 V

Analog input voltages VIN or VINB -1 to +1 V

Maximum difference

between VIN and VINB

VIN - VINB -2 to +2 V

Digital input voltage VDGORB -0.3 to VCC +0.3 V

Digital input voltage VDDRRB VEE -0.3 to +0.9 V

Digital output voltage Vo VPLUSD-3 to VPLUSD -0.5 V

Clock input voltage VCLK or VCLKB -3 to +1.5 V

Maximum difference

between VCLK and VCLKB

VCLK - VCLKB -2 to +2 V

Maximum junction

temperature

Tj+135 oC

Storage temperature Tstg -65 to +150 oC

Lead temperature

(soldering 10s)

Tleads For dry pack

(see chapter 4.5)

+300 oC

Notes : Absolute maximum ratings are limiting values (referenced to GND=0V), to be applied individually, while other parameters are within

specified operating conditions. Long exposure to maximum rating may affect device reliability.

The use of a thermal heat sink is mandatory (see Thermal characteristics).

3.2. RECOMMENDED CONDITIONS OF USE

Parameter Symbol Comments Min. Typ. Max. Unit

Positive supply voltage VCC 4.75 +5 5.25 V

Positive digital supply voltage VPLUSD ECL output compatibility GND V

VPLUSD LVDS output compatibility +1.4 +2.4 +2.6 V

Negative supply voltages VEE, DVEE -5.25 -5.0 -4.75 V

Differential analog input voltage

(Full Scale)

VIN, VINB

VIN -VINB

50 Ω differential or single-ended ±113

450

±125

500

±137

550

mVpp

Clock input power level PCLK PCLKB 50 Ω single–ended clock input 3 4 10 dBm

Operating temperature range TJCommercial grade: “C” 0 < Tc ; Tj < 90 oC

Product Specification

TS8388BG

3.3. ELECTRICAL OPERATING CHARACTERISTICS

VEE = DVEE = -5 V ; VCC = +5 V ; VIN -VINB = 500 mVpp Full Scale differential input ;

Digital outputs 75 or 50 Ω differentially terminated ;

Tj (typical) = 70°C.

Parameter Symb Test

level

Min Typ Max Unit

POWER REQUIREMENTS

Positive supply voltage Analog

Digital (ECL)

Digital (LVDS)

VCC

VPLUSD

4.5

1.4

2.4

5.5

2.6

Positive supply current Analog

Digital

ICC

IPLUSD

420

130

445

145

Negative supply voltage VEE 1-5.5 -5 -4.5 V

Negative supply current Analog

Digital

AIEE

DIEE

185

160

200

180

Nominal power dissipation PD 13.9 4.1 W

Power supply rejection ratio (note 2) PSRR 40.5 2mV/V

RESOLUTION 8bits

ANALOG INPUTS

Full Scale Input Voltage range (differential mode)

( 0 Volt common mode voltage )

VIN

VINB

4-125

-125

125

Full Scale Input Voltage range (single–ended input option )

(see Application

Notes)

VIN

VINB

4-250

250 mV

Analog input capacitance CIN 4 3 3.5 pF

Input bias current IIN 410 20 µA

Input Resistance RIN 40.5 1 MΩ

Full Power input Bandwidth FPBW 41.5 1.8 GHz

Small Signal input Bandwidth (10 % full scale) SSBW 41.5 1.7 GHz

CLOCK INPUTS

Logic compatibility for clock inputs (note 10 )

(see Application Notes)

ECL or specified clock input

power level in dBm

ECL Clock inputs voltages (VCLK or VCLKB) : 4

• Logic “0” voltage VIL -1.5 V

• Logic “1” voltage VIH -1.1 V

• Logic “0” current IIL 550 µA

• Logic “1” current IIH 550 µA

Clock input power level into 50 Ω termination DBm into 50 Ω

Clock input power level 4-2 410 dBm

Clock input capacitance CCLK 4 3 3.5 pF

6TS8388BG

Product Specification

Parameter Symb Test

level

Min Typ Max Unit

DIGITAL OUTPUTS (notes 1,6)

Single ended or differential input mode, 50 % clock duty cycle (CLK,CLKB), Binary output data format,

Tj (typical) = 70°C. Full temperature range : 0°C < Ta ; Tj < +90°C

Logic compatibility for digital outputs

( Depending on the value of VPLUSD )

(see Application Notes)

ECL or LVDS

Differential output voltage swings ( assuming VPLUSD = 0V) :

75 Ω open transmission lines ( ECL levels )

75 Ω differentially terminated

50 Ω differentially terminated

1.50

0.70

0.54

1.620

0.825

0.660

Output levels ( assuming VPLUSD = 0V)

75 Ω open transmission lines (note 6)

• Logic “0” voltage VOL -1.62 -1.54 V

• Logic “1” voltage VOH -0.88 -0.8 V

Output levels ( assuming VPLUSD = 0V)

75 Ω differentially terminated (note 6)

• Logic “0” voltage VOL -1.41 -1.34 V

• Logic “1” voltage VOH -1.07 -1 V

Output levels ( assuming VPLUSD = 0V)

50 Ω differentially terminated (note 6)

• Logic “0” voltage VOL 1, 2 -1.40 -1.32 V

• Logic “1” voltage VOH 1, 2 -1.16 -1.10 V

Differential Output Swing DOS 4270 300 mV

Output level drift with temperature 41.6 mV/°C

DC ACCURACY

Single ended or differential input mode, 50 % clock duty cycle (CLK,CLKB), Binary output data format,

Tj (typical) = 70°C.

Differential non linearity (notes 2,3) DNL- 1-0.6 -0.4 LSB

DNL+ 10.4 0.6 LSB

Integral non linearity (notes 2,3) INL- 1-1.2 -0.7 LSB

INL+ 10.7 1.2 LSB

No missing codes (note 3) Guaranteed over specified temperature range

Gain error 1, 2 -10 -2 10 % FS

Input offset voltage 1, 2 -26 -5 26 mV

Gain error drift

Offset error drift

100

125

150

ppm/°C

Product Specification

TS8388BG

Parameter Symb Test

level

Min Typ Max Unit

TRANSIENT PERFORMANCE

Bit Error Rate (notes 2, 4)

FS = 1 Gsps Fin = 62.5 MHz

BER 41E-12 Error/

sample

ADC settling time (note 2)

VIn -VinB = 400 mVpp

TS 40.5 1ns

Overvoltage recovery time (note 2) TOR 40.5 1ns

AC PERFORMANCE

Single ended or differential input and clock mode, 50 % clock duty cycle (CLK,CLKB), Binary output data format,

Tj. = 70°C, Full temperature range : 0°C < Ta ; Tj < +90°C, unless otherwise specified.

Signal to Noise and Distortion ratio (note 2) SINAD

FS = 1 Gsps Fin = 20 MHz 442 44 dB

FS = 1 Gsps Fin = 500 MHz 441 43 dB

FS = 1 Gsps Fin = 1000 MHz (-1dB Fs) 438 40 dB

FS = 50 Msps Fin = 25 MHz 140 44 dB

Effective Number Of bits ENOB

FS = 1 Gsps Fin = 20 MHz 47.0 7.2 Bits

FS = 1 Gsps Fin = 500 MHz 46.6 6.8 Bits

FS = 1 Gsps Fin = 1000 MHz (-1dBFs) 46.2 6.4 Bits

FS = 50 Msps Fin = 25 MHz 17.0 7.2 Bits

Signal to Noise Ratio (note 2) SNR

FS = 1 Gsps Fin = 20 MHz 442 45 dB

FS = 1 Gsps Fin = 500 MHz 441 44 dB

FS = 1 Gsps Fin = 1000 MHz (-1dBFs) 441 44 dB

FS = 50 Msps Fin = 25 MHz 144 45 dB

Total Harmonic Distortion (note 2) THD

FS = 1 Gsps Fin = 20 MHz 450 54 dB

FS = 1 Gsps Fin = 500 MHz 446 50 dB

FS = 1 Gsps Fin = 1000 MHz (-1dBFs) 442 46 dB

FS = 50 Msps Fin = 25 MHz 146 45 dB

Spurious Free Dynamic Range (note 2) SFDR

FS = 1 Gsps Fin = 20 MHz 452 57 dBc

FS = 1 Gsps Fin = 500 MHz 447 52 dBc

FS = 1 Gsps Fin = 1000 MHz (-1dBFs) 442 47 dBc

FS = 1 Gsps Fin = 1000 MHz (-3dBFs) 445 50 dBc

FS = 50 Msps Fin = 25 MHz 140 54 dBc

Two-tone inter-modulation distortion (note 2) IMD 4

FIN1 = 489 MHz @ FS = 1 Gsps - 47 - 52 dBc

FIN2 = 490 MHz @ FS = 1 Gsps

8TS8388BG

Product Specification

Parameter Symb Test

level

Min Typ Max Unit

SWITCHING PERFORMANCE AND CHARACTERISTICS – See Timing Diagrams Figure 1, Figure 2

Maximum clock frequency (Note 14) FS11.4 Gsps

Minimum clock frequency (Note 15) FS410 50 Msps

Minimum Clock pulse width (high) TC1 40.280 0.500 50 ns

Minimum Clock pulse width (low) TC2 40.350 0.500 50 ns

Aperture delay (Note 2) TA 4100 +250 400 ps

Aperture uncertainty (Notes 2, 5) Jitter 40.4 0.6 ps (rms)

Data output delay (Notes 2, 10, 11, 12) TOD 41150 1360 1660 ps

Output rise/fall time for DATA (20 % – 80 %)

(note 11)

TR/TF 4250 350 550 ps

Output rise/fall time for DATA READY

(20 % – 80 % ) (note 11)

TR/TF 4250 350 550 ps

Data ready output delay (Notes 2,10, 11, 12) TDR 41110 1320 1620 ps

Data ready reset delay TRDR 4720 1000 ps

Data to data ready – clock low pulse width

(See timing diagram, notes 9, 13,14)

TOD-

TDR

4 0 40 80 ps

Data to data ready output delay (50% duty cycle)

(See timing diagram, notes 2, 15) @ 1Gsps

TD1 4420 460 500 ps

Data pipeline delay TPD 4 4 clock

cycles

Note 1 : Differential output buffers are internally loaded by 75 Ω resistors. Buffer bias current = 11 mA.

Note 2 : See definition of terms

Note 3 : Histogram testing based on sampling of a 10 MHz sinewave at 50 MSPS.

Note 4 : Output error amplitude < ± 4 LSB around worst code.

Note 5 : Maximum jitter value obtained for single–ended clock input on the JTS8388B die (chip on board) : 200 fs.

(500 fs expected on TS8388BG)

Note 6 : Digital output back termination options depicted in Application Notes figures 3,4,5 .

Note 7 : With a typical value of TD = 465 ps, at 1 Gsps, the timing safety margin for the data storing using the ECLinPS 10E452 output

registers from Motorola is of ± 315 ps, equally shared before and after the rising edge of the Data Ready signals (DR, DRB).

Note 8 : The clock inputs may be indifferently entered in differential or single–ended, using ECL levels or 4 dBm typical power level into the

50 Ω termination resistor of the inphase clock input.

(4 dBm into 50 Ω clock input correspond to 10 dBm power level for the clock generator.)

Note 9 : At 1GSPS, 50/50 clock duty cycle, TC2 = 500 ps (TC1). TDR - TOD = -100 ps (typ) does not depend on the sampling rate.

Note 10 : Specified loading conditions for digital outputs :

- 50 Ω or 75 Ω controlled impedance traces properly 50 / 75 Ω terminated, or unterminated 75 Ω controlled impedance traces.

- Controlled impedance traces far end loaded by 1 standard ECLinPS register from Motorola.( e.g. : 10E452 ) ( Typical input parasitic

capacitance of 1.5 pF including package and ESD protections. )

Note 11 : Termination load parasitic capacitance derating values :

- 50 Ω or 75 Ω controlled impedance traces properly 50 / 75 Ω terminated : 60 ps / pF or 75 ps per additionnal ECLinPS load.

- Unterminated ( source terminated ) 75 Ω controlled impedance lines : 100 ps / pF or 150 ps per additionnal ECLinPS termination

load.

Note 12 : apply proper 50 / 75 Ω impedance traces propagation time derating values : 6 ps / mm (155 ps/inch) for TSEV8388BG Evaluation

Board.

Note 13 : Values for TOD and TDR track each other over temperature, ( 1 % variation for TOD - TDR per 100 oC. temperature variation ).

Therefore TOD - TDR variation over temperature is negligible. Moreover, the internal ( onchip ) and package skews between each

Data TODs and TDR effect can be considered as negligible.Consequently, minimum values for TOD and TDR are never more than

100 ps apart. The same is true for the TOD and TDR maximum values (see Advanced Application Notes about TOD - TDR variation

over temperature in section 7).

Note 14 : Min value guaranties performance. Max value guaranties functionality.

Note 15 : Min value guaranties functionality. Max value guaranties performance.

Product Specification

TS8388BG

3.4. TIMING DIAGRAMS

TC1 TC2

TA= 250 ps

N+1

N+2

XN+3

Figure 1 : TS8388BG TIMING DIAGRAM ( 1 GSPS CLOCK RATE )

Data Ready Reset , Clock held at LOW level

DIGITAL

OUTPUTS

(VIN, VINB )

Data Ready

(DR, DRB)

(CLK, CLKB)

1. N+5

TD1=TC1+TDR-TOD

= TC1-40 ps = 460 ps

DATA

N-4

DATA

N-3 DATA N

DATA

-1

DATA

N-2

TC=1000 ps

N+4

TOD = 1360 ps

1360 ps

DRRB

1ns (min)

TDR = 1320 ps

TPD: 4.0 Clock periods

1000 ps

TRDR = 720 ps

N-1

TD2 = TC2+TOD-TDR

= TC2+40ps = 540 ps

TDR = 1320 ps

DATA

N-5

DATA

N+1

TC1 TC2

TA= 250ps

X3.

N+1

XN+2

XN+3

Figure 2 : TS8388BG TIMING DIAGRAM ( 1 GSPS CLOCK RATE )

Data Ready Reset , Clock held at HIGH level

DIGITAL

OUTPUTS

(VIN, VINB )

Data Ready

(DR, DRB)

(CLK, CLKB)

2. N+5

TD1=TC1+TDR-TOD

= TC1-40 ps = 460 ps

DATA

N-4 DATA

N-3 DATA N

DATA

N-1

DATA

N-2

TC = 1000 ps

N+4

TOD = 1360 ps

1360 ps

DRRB 1ns (min)

TDR = 1320 ps

TPD: 4.0 Clock periods

1000 ps

TRDR = 720ps

N-1

TD2 = TC2+TOD-TDR

= TC2+40ps = 540 ps

TDR = 1120 ps

DATA

N-5

DATA

N+1

10 TS8388BG

Product Specification

3.5. EXPLANATION OF TEST LEVELS

1100% production tested at +25°C (1) (for “C” Temperature range (2) ).

2100 % production tested at +25°C (1), and sample tested at specified temperatures (for “V” and “M” Temperature ranges (2) ).

3Sample tested only at specified temperatures

4Parameter is guaranteed by design and characterization testing (thermal steady-state conditions at specified temperature).

5Parameter is a typical value only

Only MIN and MAX values are guaranteed (typical values are issuing from characterization results).

(1) Unless otherwise specified, all tests are pulsed tests : therefore Tc = Ta where Tc and Ta are case and ambient temperature.

(2) Refer to ORDERING INFORMATION chapter.

3.6. FUNCTIONS DESCRIPTION

Name Function

VCC Positive power supply

VEE Analog negative power supply

VPLUSD Digital positive power supply

GND Ground

VIN, VINB Differential analog inputs

CLK, CLKB Differential clock inputs

<D0:D7>

<D0B:D7B>

Differential output data port

DR ; DRB Differential data ready outputs

OR ; ORB Out of range outputs

GAIN ADC gain adjust

GORB Gray or Binary digital output select

DIOD/DRRB Die junction temp. measurement/

asynchronous data ready reset

3.7. DIGITAL OUTPUT CODING

NRZ (Non Return to Zero) mode, ideal coding : does not include gain, offset, and linearity voltage errors.

Differential

analog input

Voltage level Digital output Out of

Range

Binary

GORB = VCC or floating

Gray

GORB = GND

> +251 mV > Positive full scale + 1/2 LSB 11111111 10000000 1

+251 mV

+249 mV

Positive full scale + 1/2 LSB

Positive full scale – 1/2 LSB

11111111

11111110

10000000

10000001

+126 mV

+124 mV

Positive 1/2 scale + 1/2 LSB

Positive1/2 scale – 1/2 LSB

11000000

10111111

10100000

11100000

+1 mV

-1 mV

Bipolar zero + 1/2 LSB

Bipolar zero - 1/2 LSB

10000000

01111111

11000000

01000000

-124 mV

-126 mV

Negative 1/2 scale + 1/2 LSB

Negative 1/2 scale - 1/2 LSB

01000000

00111111

01100000

00100000

-249 mV

-251 mV

Negative full scale + 1/2 LSB

ative full scale - 1/2 LSB

00000001

00000000

00000001

00000000

< -251 mV < Negative full scale - 1/2 LSB 00000000 00000000 1

VPLUSD = +0 V (ECL)

VPLUSD=+2.4V (LVDS)

VIN

VINB

CLK

CLKB

D0 → D7

D0B → D7B

VEE=-5V

VCC = +5 V

TS8388BG

ORB

GND

GORB

GAIN

DVEE=-5V

DIOD/

DRRB

DRB

Product Specification

TS8388BG

4. PACKAGE DESCRIPTION.

4.1. TS8388BG PIN DESCRIPTION

Symbol Pin number Function

GND A2, A5, B1, B5, B10, C2, C9, D2,

E1, E2, E11, F1, F2, G11, J3, J9,

K2, K3, K4, K5, K10, L2, L5

Ground pins.

To be connected to external ground plane.

VCC A4, A6, B2, B4, B6, C3, H1, H2,

L6, L7

+5 V positive supply.

VEE A3, B3, G1, G2, J1, J2 5 V analog negative supply

DVEE F10, F11 -5 V digital negative supply.

VIN L3 In phase (+) analog input signal of the sample and Hold

differential preamplifier.

VINB L4 Inverted phase (-) of ECL clock input signal (CLK).

CLK)C1 In phase (+) ECL clock input signal. The analog input is sampled

and held on the rising edge of the CLK signal.

CLKB D1 Inverted phase (-) of ECL clock input signal (CLK).

B0, B1, B2, B3, B4, B5, B6,

A8, A9, A10, D10, H11, J11, K9,

In phase (+) digital outputs.

B0 is the LSB. B7 is the MSB.

B0B, B1B, B2B, B3B, B4B,

B5B, B6B, B7B

B7, B8, B9, C11, G10, H10, L10,

Inverted phase (-) Digital outputs.

B0B is the inverted LSB. B7B is the inverted MSB.

OR K7 In phase (+) Out of Range Bit.

Out of Range is high on the leading edge of code 0 and code 256.

ORB L8 Inverted phase (+) of Out of Range Bit (OR).

DR E10 In phase (+) output of Data Ready Signal.

DRB D11 Inverted phase (-) output of Data Ready Signal (DR).

GORB A7 Gray or Binary select output format control pin.

– Binary output format if GORB is floating or VCC.

– Gray output format if GORB is connected at ground (0 V).

GAIN K6 ADC gain adjust pin.

The gain pin is by default grounded, the ADC gain transfer

function is nominally close to one.

DIOD/DRRB K1 Die function temperature measurement pin and asynchronous

data ready reset active low, single ended ECL input.

VPLUSD B11, C10, J10, K11 + 2.4 V for LVDS output levels otherwise to GND (1)

NC A1, A11, L1, L11 Not connected.

Note 1 : The common mode level of the output buffers is 1.2V below the positive digital supply.

For ECL compatibility the positive digital supply must be set at 0V (ground ).

For LVDS compatibility (output common mode at +1.2V) the positive digital supply must be set at 2.4V.

If the subsequent LVDS circuitry can withstand a lower level for input common mode, it is recommended to lower the positive digital

supply level in the same proportion in order to spare power dissipation.

12 TS8388BG

Product Specification

4.2. TS8388BG PINOUT OF CBGA72 PACKAGE

BOTTOM VIEW

Product Specification

TS8388BG

4.3. TS8388BG CAPACITIES AND RESISTANCES IMPLANT

100 pF

100 pF 100 pF

Ohm

100 pF100 pF 100 pF 50

Ohm

100 pF 100 pF

Ohm

100 pF

Only on-package marking

Electrically isolated

14 TS8388BG

Product Specification

4.4. OUTLINE DIMENSIONS - 72 PINS CBGA

100

Product Specification

TS8388BG

4.5. THERMAL AND MOISTURE CHARACTERISTICS

4.5.1. THERMAL RESISTANCE FROM JUNCTION TO AMBIENT : RTHJA

The following table lists the convector thermal performances parameters of the device itself, with no external heatsink added.

4.5.2. THERMAL RESISTANCE FROM JUNCTION TO CASE : RTHJC

Typical value for Rthjc is given to 1.56°C/W.

This value does not include thermal contact resistance between package and external component (heatsink or PCBoard).

As an example, 2.0°C/W can be taken for 50 µm of thermal grease.

4.5.3. CBGA72 BOARD ASSEMBLY WITH EXTERNAL HEATSINK

It is recommended to use an external heatsink or PCBoard special design.

Cooling system efficiency can be monitored using the Temperature Sensing Diode, integrated in the device.

Note: The measures are given in mm.

4.5.4. MOISTURE CHARACTERISTICS

This device is very sensitive to the moisture (MSL6 according JEDEC standard).

When receiving the devices (in dry pack), you must follow strictly the instructions on the sticker.

The devices must be mounted within 6 hours at factory conditions of ≤ 30°C/60% RH.

These devices, if subjected to infrared reflow, vapor-phase reflow, or equivalent processing (peak package body temp. 220°C), must be baked

before mounting for :

- 192 hours at 40°C + 5°C/-0°C and <5% RH for low-temperature device containers, or

- 24 hours at 125°C ± 5°C for high-temperature device containers.

Note : in case of reworking of a component on a board containing this device, the board could need to be heated. In this case and to preserve

the TS8388BG, it is important to bake the board first, according to the instructions above.

012345

Air flow (m/s)

Rthja (deg.C/W)

Air flow Estimated ja thermal resistance

(m/s) (oC / W)

045

0,5 35,8

1 30,8

1,5 27,4

2 24,9

2,5 23

3 21,5

4 19,3

5 17,7

16 TS8388BG

Product Specification

5. TYPICAL CHARACTERIZATION RESULTS

5.1. STATIC LINEARITY – FS = 50 MSPS / FIN = 10 MHZ

5.1.1. INTEGRAL NON LINEARITY

5.1.2. DIFFERENTIAL NON LINEARITY

LSB

INL = +/- 0.7 LSB

code

Signal Frequency = 10MHzClock Frequency = 50Msps

Positive peak : 0.78 LSB Negative peak : -0.73 LSB

LSB

DNL = +/- 0.4 LSB

code

Signal Frequency = 10MHzClock Frequency = 50Msps

Positive peak : 0.3 LSB Negative peak : -0.39 LSB

Product Specification

TS8388BG

5.2. EFFECTIVE NUMBER OF BITS VERSUS POWER SUPPLIES VARIATION

-7 -6,5 -6 -5,5 -5 -4,5 -4

Effective number of bits = f

(

VEEA

)

; Fs = 500 MSPS ; Fin = 100 MHz

VEEA (V)

ENOB (bits)

3 3,5 4 4,5 5 5,5 6 6,5 7

Effective number of bits = f

(

VCC

)

; Fs = 500 MSPS ; Fin = 100 MHz

VCC (V)

ENOB (bits)

-6 -5,5 -5 -4,5 -4 -3,5 -3

Effective number of bits = f

(

VEED

)

; Fs = 500 MSPS ; Fin = 100 MHz

VEED

(

)

ENOB (bits)

18 TS8388BG

Product Specification

5.3. TYPICAL FFT RESULTS

5.3.1 FS = 1 GSPS, FIN=20 MHZ

5.3.2. FS = 1 GSPS, FIN = 495 MHZ

5.3.3. FS = 1 GSPS, FIN = 995 MHZ ( -3DB FULL SCALE INPUT)

Single Ended or

differential

Fs =1 GSPS

Fin = 20 MHz

Eff. Bits =7.2

SINAD = 44.3 dB

SNR = 44.7dB

THD = -54dBc

SFDR = -57 dBc

H3H2

clock duty cycle = 50 %

Binary output coding

H11

H12

Single Ended or

differential

Fs =1 GSPS

Fin=495MHz

Eff. Bits =6.8

SINAD =43 dB

SNR = 44.1 dB

THD = -50 dBc

SFDR= -52 dBc

clock duty cycle = 50 %

H11

H14

H12

Binary output coding

Single Ended or

differential

Fs =1 GSPS

Fin=995 MHz

Eff. Bits =6.6

SINAD =40.8 dB

SNR = 44 dB

THD = -48 dBc

SFDR= -50 dBc

clock duty cycle = 50 %

Binary output coding

H10

Product Specification

TS8388BG

5.4. SPURIOUS FREE DYNAMIC RANGE VERSUS INPUT AMPLITUDE

5.4.1. SAMPLING FREQUENCY FS=1 GSPS ; INPUT FREQUENCY FIN=995 MHZ ; GRAY OR BINARY OUTPUT CODING

Fs = 1 GSPS Fin = 995 MHz Full Scale

ENOB

SINAD

40 dB

SNR

44dB

THD

46 dBc

SFDR

47 dBc

Full Scale

magnitude (code)

SFDR = -47 dBc

20 TS8388BG

Product Specification

-3dB Full Scale

Fs = 1 GSPS Fin = 995 MHz (-3 dB Full Scale)

ENOB = 6.6 SINAD = 40.8 dB SNR = 44dB SFDR = -50dBc

magnitude (code)

THD = -48dBc

SFDR = -50 dBc

Product Specification

TS8388BG

5.5. DYNAMIC PERFORMANCE VERSUS ANALOG INPUT FREQUENCY

Fs=1 Gsps, Fin = 0 up to 1600 MHz, Full Scale input (FS), FS -3 dB

Clock duty cycle 50 / 50, Binary/Gray output coding, fully differential or single-ended analog and clock inputs

0 200 400 600 800 1000 1200 1400 1600 1800

Input frequency (MHz)

ENOB (dB)

-3 dB FS

0 200 400 600 800 1000 1200 1400 1600 1800

Input frequency (MHz)

SNR (dB)

-3 dB FS

-60

-55

-50

-45

-40

-35

-30

-25

-20

0 200 400 600 800 1000 1200 1400 1600 1800

Input frequency (MHz)

SFDR (dBc)

-3 dB FS

22 TS8388BG

Product Specification

5.6. EFFECTIVE NUMBER OF BITS (ENOB) VERSUS SAMPLING FREQUENCY

Analog Input Frequency : Fin = 495 MHz and Nyquist conditions ( Fin = Fs / 2 )

Clock duty cycle 50 / 50 , Binary output coding

5.7. SFDR VERSUS SAMPLING FREQUENCY

Analog Input Frequency : Fin = 495 MHz and Nyquist conditions ( Fin = Fs / 2 )

Clock duty cycle 50 / 50 , Binary output coding

0 200 400 600 800 1000 1200 1400 1600

Sampling frequency (Msps)

ENOB (dB)

Fin= FS/2

Fin=500 MHz

-60

-55

-50

-45

-40

-35

-30

-25

-20

0 200 400 600 800 1000 1200 1400 1600

Sampling frequency (Msps)

SFDR (dBc)

Fin= FS/2

Fin=500 MHz

Product Specification

TS8388BG

5.8. TS8388BG ADC PERFORMANCES VERSUS JUNCTION TEMPERATURE

-40 -20 0 20 40 60 80 100 120 140 160

Effective number of bits versus junction temperature

Fs = 1 GSPS ; Fin = 500 MHz ; Duty cycle = 50%

Temperature ( oC)

ENOB (bits)

-60 -40 -20 0 20 40 60 80 100 120

Signal to noise ratio versus junction temperature

Fs = 1 GSPS ; Fin = 507 MHz ; Differential clock, Single-ended analog input (Vin=-1dBFs)

Temperature ( oC)

SNR (dB)

-60 -40 -20 0 20 40 60 80 100 120

Total harmonic distorsion versus junction temperature

Fs = 1 GSPS ; Fin = 507 MHz ; Differential clock, Single-ended analog input (Vin=-1dBFs)

Temperature ( oC)

THD (dB)

24 TS8388BG

Product Specification

5.9. TYPICAL FULL POWER INPUT BANDWIDTH

1.8 GHz at -3 dB (-2dBm full power input)

-40 -20 0 20 40 60 80 100 120 140 160

Power consumption versus junction temperature

Fs = 1 GSPS ; Fin = 500 MHz ; Duty cycle = 50%

Tem perature (

oC)

Power consumption (W

-6

-5

-4

-3

-2

-1

800 1000 1200 1400 1600 1800

Frequency (MHz)

Magnitude (dB)

2000

600

400

Product Specification

TS8388BG

ADC STEP RESPONSE

Test pulse input characteristics : 20% to 80% input full scale and rise time ~ 200ps.

Note : This step response was obtained with the TSEV8388B chip on board (device in die form).

5.9.1. TEST PULSE DIGITIZED WITH 20 GHZ DSO

5.9.2. SAME TEST PULSE DIGITIZED WITH TS8388BG ADC

N.B. : ripples are due to the test setup (they are present on both measurements)

50 mV/div

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.00

time (ns)

Vpp ~ 260 mV

Tr ~ 240 ps

50 mV/div

500 ps/div

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.00

200

150

100

ADC code

time (ns)

Tr ~ 280 ps

50 codes/div (Vpp ~260 mV)

500 ps/div

ADC calculated rise time : between 150 and 200

26 TS8388BG

Product Specification

6. DEFINITION OF TERMS

(BER) Bit Error Rate Probability to exceed a specified error threshold for a sample. An error code is a code that differs

by more than +/- 4 LSB from the correct code.

(BW) Full power input

bandwidth

Analog input frequency at which the fundamental component in the digitally reconstructed output

has fallen by 3 Db with respect to its low frequency value (determined by FFT analysis) for input

at Full Scale.

(SINAD) Signal to noise and

distortion ratio

Ratio expressed in Db of the RMS signal amplitude, set to 1Db below Full Scale, to the RMS

sum of all other spectral components, including the harmonics except DC.

(SNR) Signal to noise ratio Ratio expressed in Db of the RMS signal amplitude, set to 1Db below Full Scale, to the RMS

sum of all other spectral components excluding the five first harmonics.

(THD) Total harmonic

distorsion

Ratio expressed in dBc of the RMS sum of the first five harmonic components, to the RMS value

of the measured fundamental spectral component.

(SFDR) Spurious free dynamic

range

Ratio expressed in Db of the RMS signal amplitude, set at 1Db below Full Scale, to the RMS

value of the next highest spectral component (peak spurious spectral component). SFDR is the

key parameter for selecting a converter to be used in a frequency domain application ( Radar

systems, digital receiver, network analyzer ….). It may be reported in dBc (i.e., degrades as

signal levels is lowered), or in dBfs (i.e. always related back to converter full scale).

(ENOB) Effective Number Of Bits Where A is the actual input amplitude and V

is the full scale range of the ADC under test

(DNL) Differential non

linearity

The Differential Non Linearity for an output code i is the difference between the measured step

size of code i and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL is the maximum

value of all DNL (i). DNL error specification of less than 1 LSB guarantees that there are no

missing output codes and that the transfer function is monotonic.

(INL) Integral non linearity The Integral Non Linearity for an output code i is the difference between the measured input

voltage at which the transition occurs and the ideal value of this transition.

INL (i) is expressed in LSBs, and is the maximum value of all |INL (i)|.

(DG) Differential gain The peak gain variation (in percent) at five different DC levels for an AC signal of 20% Full

Scale peak to peak amplitude. FIN = 5 MHz. (TBC)

(DP) Differential phase Peak Phase variation (in degrees) at five different DC levels for an AC signal of 20% Full Scale

peak to peak amplitude. FIN = 5 MHz. (TBC)

(TA) Aperture delay Delay between the rising edge of the differential clock inputs (CLK,CLKB) (zero crossing point),

and the time at which (VIN,VINB) is sampled.

(JITTER) Aperture uncertainty Sample to sample variation in aperture delay. The voltage error due to jitter depends on the slew

rate of the signal at the sampling point.

(TS) Settling time Time delay to achieve 0.2 % accuracy at the converter output when a 80% Full Scale step

function is applied to the differential analog input.

(ORT) Overvoltage recovery

time

Time to recover 0.2 % accuracy at the output, after a 150 % full scale step applied on the input is

reduced to midscale.

(TOD) Digital data

Output delay

Delay from the falling edge of the differential clock inputs (CLK,CLKB) (zero crossing point) to

the next point of change in the differential output data (zero crossing) with specified load.

(TD1) Time delay from Data to

Data Ready

Time delay from Data transition to Data ready.

(TD2) Time delay from Data

Ready to Data

General expression is TD1 = TC1 + TDR – TOD with TC = TC1 + TC2 = 1 encoding clock

period.

(TC) Encoding clock period TC1 = Minimum clock pulse width (high) TC = TC1 + TC2

TC2 = Minimum clock pulse width (low)

(TPD) Pipeline Delay Number of clock cycles between the sampling edge of an input data and the associated output

data being made available, (not taking in account the TOD). For the TS8388BG the TPD is 4

clock periods.

(TRDR) Data Ready reset delay Delay between the falling edge of the Data Ready output asynchronous Reset signal (DDRB)

and the reset to digital zero transition of the Data Ready output signal (DR).

SINAD - 1.76 + 20 log (A/V/2)

ENOB = 

6.02

Product Specification

TS8388BG

(TR) Rise time Time delay for the output DATA signals to rize from 20% to 80% of delta between low level and

high level.

(TF) Fall time Time delay for the output DATA signals to fall from 80% to 20% of delta between low level and

high level.

(PSRR) Power supply

rejection ratio

Ratio of input offset variation to a change in power supply voltage.

(NRZ) Non return to zero When the input signal is larger than the upper bound of the ADC input range, the output code is

identical to the maximum code and the Out of Range bit is set to logic one. When the input

signal is smaller than the lower bound of the ADC input range, the output code is identical to the

minimum code, and the Out of range bit is set to logic one. (It is assumed that the input signal

amplitude remains within the absolute maximum ratings).

(IMD) InterModulation Distortion The two tones intermodulation distortion ( IMD ) rejection is the ratio of either input tone to the

worst third order intermodulation products. The input tones levels are at – 7Db Full Scale.

(NPR) Noise Power Ratio The NPR is measured to characterize the ADC performance in response to broad bandwidth

signals. When using a notch-filtered broadband white-noise generator as the input to the ADC

under test, the Noise Power Ratio is defined as the ratio of the average out-of-notch to the

average in-notch power spectral density magnitudes for the FFT spectrum of the ADC output

sample test.

28 TS8388BG

Product Specification

7. TS8388BG MAIN FEATURES

7.1. TIMING INFORMATIONS

7.1.1. TIMING VALUE FOR TS8388BG

Timing values as defined in 3.3 are advanced data, issuing from electric simulations and first characterization results fitted with measurements.

Timing values are given for CBGA72 package inputs/outputs, taking into account package internal controlled impedance traces propagation

delays, and specified termination loads.

Propagation delays in 50/75 ohms impedance traces are NOT taken into account for TOD and TDR.

Apply proper derating values corresponding to termination topology.

The min/max timing values are valid over the full temperature range in the following conditions :

Note 1 : Specified Termination Load (Differential output Datas and Data Ready) :

50 ohms resistor in parallel with 1 standard ECLinPS register from Motorola, (e.g : 10E452)

(Typical ECLinPS inputs shows a typical input capacitance of 1.5 pF (including package and ESD protections)

If addressing an output Dmux, take care if some Digital outputs do not have the same termination load and apply corresponding derating value

given below.

Note 2 : Output Termination Load derating values for TOD and TDR :

~ 35 ps/pF or 50 ps per additional ECLinPS load.

Note 3 :Propagation time delay derating values have also to be applied for TOD and TDR :

~ 6 ps/mm (155 ps/inch) for TSEV8388B Evaluation Board.

Apply proper time delay derating value if a different dielectric layer is used.

7.1.2. PROPAGATION TIME CONSIDERATIONS

TOD and TDR Timing values are given from pin to pin and DO NOT include the additional propagation times between device pins and

input/output termination loads. For the TSEV8388B Evaluation Board, the propagation time delay is 6ps/mm (155ps/inch) corresponding to 3.4

(@10GHz) dielectric constant of the RO4003 used for the Board.

If a different dielectric layer is used (for instance Teflon), please use appropriate propagation time values.

TD does NOT depend on propagation times because it is a differential data.

(TD is the time difference between Data Ready output delay and digital Data output delay)

TD is also the most straightforward data to measure, again because it is differential :

TD can be measured directly onto termination loads, with matched Oscilloscopes probes.

7.1.3. TOD - TDR VARIATION OVER TEMPERATURE

Values for TOD and TDR track each other over temperature (1 percent variation for TOD - TDR per 100 degrees Celsius temperature variation).

Therefore TOD - TDR variation over temperature is negligible. Moreover, the internal (onchip) and package skews between each Data TODs

and TDR effect can be considered as negligible.

Consequently, minimum values for TOD and TDR are never more than 100 ps apart. The same is true for the TOD and TDR maximum values.

In other terms :

If TOD is at 1150 ps, TDR will not be at 1620 ps ( maximum time delay for TDR ).

If TOD is at 1660 ps, TDR will not be at 1110 ps ( minimum time delay for TDR ) However, external TOD - TDR values may be dictated by total

digital datas skews between every TODs (each digital data) and TDR :

MCM Board , bonding wires and output lines lengths differences, and output termination impedance mismatches.

The external (on board) skew effect has NOT been taken into account for the specification of the minimum and maximum values for TOD-TDR.

7.1.4. PRINCIPLE OF OPERATION

The Analog input is sampled on the rising edge of external clock input (CLK,CLKB) after TA (aperture delay) of typically 250ps .

The digitized data is available after 4 clock periods latency (pipeline delay (TPD)), on clock rising edge, after 1360 ps typical propagation delay

TOD.

The Data Ready differential output signal frequency (DR,DRB) is half the external clock frequency, that is it switches at the same rate as the

digital outputs.

The Data Ready output signal (DR,DRB) switches on external clock falling edge after a propagation delay TDR of typically 1320 ps.

A Master Asynchronous Reset input command DRRB ( ECL compatible single-ended input) is available for initializing the differential Data

Ready output signal ( DR,DRB ) .This feature is mandatory in certain applications using interleaved ADCs or using a single ADC with

demultiplexed outputs. Actually, without Data Ready signal initialization, it is impossible to store the output digital datas in a defined order.

Product Specification

TS8388BG

7.2. PRINCIPLE OF DATA READY SIGNAL CONTROL BY DRRB INPUT COMMAND

7.2.1. DATA READY OUTPUT SIGNAL RESET

The Data Ready signal is reset on falling edge of DRRB input command, on ECL logical low level (-1.8V). DRRB may also be tied to VEE = - 5V

for Data Ready output signal Master Reset. So long DRRB remains at logical low level, (or tied to VEE = - 5V), the Data Ready output remains

at logical zero and is independent of the external free running encoding clock.

The Data Ready output signal (DR,DRB) is reset to logical zero after TRDR= 920 ps typical.

TRDR is measured between the -1.3V point of the falling edge of DRRB input command and the zero crossing point of the differential Data

Ready output signal (DR,DRB).

The Data Ready Reset command may be a pulse of 1 ns minimum time width.

7.2.2. DATA READY OUTPUT SIGNAL RESTART

The Data Ready output signal restarts on DRRB command rising edge, ECL logical high levels (-0.8V).

DRRB may also be Grounded, or is allowed to float, for normal free running Data Ready output signal.

The Data Ready signal restart sequence depends on the logical level of the external encoding clock, at DRRB rising edge instant :

1) The DRRB rising edge occurs when external encoding clock input (CLK,CLKB) is LOW :

The Data Ready output first rising edge occurs after half a clock period on the clock falling edge, after a delay time TDR = 1320 ps already

defined hereabove.

2) The DRRB rising edge occurs when external encoding clock input (CLK,CLKB) is HIGH :

The Data Ready output first rising edge occurs after one clock period on the clock falling edge, and a delay TDR = 1320ps.

Consequently, as the analog input is sampled on clock rising edge, the first digitized data corresponding to the first acquisition ( N ) after Data

Ready signal restart ( rising edge ) is always strobed by the third rising edge of the data ready signal.

The time delay (TD1) is specified between the last point of a change in the differential output data (zero crossing point) to the rising or falling

edge of the differential Data Ready signal (DR,DRB) (zero crossing point).

Note 1 : For normal initialization of Data Ready output signal, the external encoding clock signal frequency and level must be controlled.

It is reminded that the minimum encoding clock sampling rate for the ADC is 10 MSPS and consequently the clock cannot be stopped.

Note 2 : One single pin is used for both DRRB input command and die junction temperature monitoring.

Pin denomination will be DRRB/DIOD.( On former version denomination was DIOD. )

Temperature monitoring and Data Ready control by DRRB is not possible simultaneously.

7.3. ANALOG INPUTS (VIN) (VINB)

The analog input Full Scale range is 0.5 Volts peak to peak (Vpp), or -2 dBm into the 50 ohms termination resistor.

In differential mode input configuration, that means 0.25 Volt on each input, or +/- 125 mV around zero volt. The input common mode is

GROUND.

The typical input capacitance is 3 pF for TS8388BG in CBGA package.

The input capacitance is mainly due to the package.

Differential inputs voltage span

-125

125

[mV]

-250 mV250 mV

VIN

500mV

Full Scale

analog input

VINB

(VIN,VINB) = +/- 250 mV = 500 mV diff

0 Volt

30 TS8388BG

Product Specification

Differential versus single ended analog input operation

The TS8388BG can operate at full speed in either differential or single ended configuration.

This is explained by the fact the ADC uses a high input impedance differential preamplifier stage, (preceding the Sample and hold stage), which

has been designed in order to be entered either in differential mode or single–ended mode.

This is true so long as the out of phase analog input pin VINB is 50 ohms terminated very closely to one of the neighboring shield ground pins

(52, 53, 58, 59) which constitute the local ground reference for the inphase analog input pin (VIN).

Thus the differential analog input preamplifier will fully reject the local ground noise ( and any capacitively and inductively coupled noise) as

common mode effects.

In typical single–ended configuration, enter on the (VIN) input pin, with the inverted phase input pin (VINB) grounded through the 50 ohms

termination resistor.

In single–ended input configuration, the in-phase input amplitude is 0.5 Volt peak to peak, entered on 0V. (or -2 dBm into 50 ohms.)

The inverted phase input is at ground potential through the 50 ohms termination resistor.

However, dynamic performances can be somewhat improved by entering either analog or clock inputs in differential mode.

Typical Single ended analog input configuration

VIN or VINB VIN or VINB double pad

50 Ω

(on package)

50 Ω reverse termination

1MΩ 3 pF

-250

250

[mV]

500 mV

Full Scale

analog input

VINB

VIN

VINB = 0V

VIN = +/- 250 mV ⇔ 500 mV diff

7.4. CLOCK INPUTS (CLK) (CLKB)

The TS8388BG can be clocked at full speed without noticeable performance degradation in either differential or single ended configuration.

This is explained by the fact the ADC uses a differential preamplifier stage for the clock buffer, which has been designed in order to be entered

either in differential or single–ended mode.

Recommended sinewave generator characteristics are typically -120 dBc/Hz phase noise floor spectral density, @ 1 KHz from carrier ,

assuming a single tone 4 dBm input for the clock signal.

7.4.1. SINGLE ENDED CLOCK INPUT (GROUND COMMON MODE)

Although the clock inputs were intended to be driven differentially with nominal -0.8V / -1.8V ECL levels, the TS8388BG clock buffer can

manage a single–ended sinewave clock signal centered around 0 Volt. This is the most convenient clock input configuration as it does not

require the use of a power splitter.

No performance degradation ( e.g. : due to timing jitter) is observed in this particular single–ended configuration up to 1.2GSPS Nyquist

conditions ( Fin = 600 MHz ).

This is true so long as the inverted phase clock input pin is 50 ohms terminated very closely to one of the neighboring shield ground pin, which

constitutes the local Ground reference for the inphase clock input.

Thus the TS8388BG differential clock input buffer will fully reject the local ground noise ( and any capacitively and inductively coupled noise) as

common mode effects.

Moreover, a very low phase noise sinewave generator must be used for enhanced jitter performance.

The typical inphase clock input amplitude is 1 Volt peak to peak, centered on 0 Volt (ground) common mode.

This corresponds to a typical clock input power level of 4 dBm into the 50 ohms termination resistor.

Do not exceed 10 dBm to avoid saturation of the preamplifier input transistors.

The inverted phase clock input is grounded through the 50 ohms termination resistor.

Product Specification

TS8388BG

Single ended Clock input (Ground common mode)

VCLK common mode = 0 Volt

VCLKB=0 Volt

4 dBm typical clock input power level

(into 50 ohms termination resistor)

[V]

VCLK

VCLKB = ( 0 V )

-0.5V

+0.5V CLK or CLKB

50 Ω

(on package)

50 Ω reverse termination

1MΩ 0.4 pF

CLK or CLKB double pad (pins 37, 38 or 39, 40)

Note 1 : Do not exceed 10 dBm into the 50 ohms termination resistor for single clock input power level.

7.4.2. DIFFERENTIAL ECL CLOCK INPUT

The clock inputs can be driven differentially with nominal –0.8V / -1.8V ECL levels.

In this mode, a low phase noise sinewave generator can be used to drive the clock inputs, followed by a power splitter (hybrid junction) in order

to obtain 180 degrees out of phase sinewave signals. Biasing tees can be used for offseting the common mode voltage to ECL levels.

Note : As the biasing tees propagation times are not matching, a tunable delay line is required in order to ensure the signals to be 180 degrees

out of phase especially at fast clock rates in the GSPS range.

Differential Clock inputs (ECL Levels)

-0.8V

[mV]

-1.8V

VCLKB

VCLK

Common mode = -1.3 V

CLK or CLKB

50 Ω reverse termination

1MΩ 0.4 pF

GND

50 Ω

(on package)

CLK or CLKB double pad (pins 37, 38 or 39, 40)

7.4.3. SINGLE ENDED ECL CLOCK INPUT

In single–ended configuration enter on CLK ( resp. CLKB ) pin , with the inverted phase Clock input pin CLKB (respectively CLK) connected to -

1.3V through the 50 ohms termination resistor.

The inphase input amplitude is 1 Volt peak to peak, centered on -1.3 Volt common mode.

Single ended Clock input (ECL):

VCLK common mode = -1.3 Volt.

VCLKB = -1.3 Volt

32 TS8388BG

Product Specification

-0.8V

[V]

-1.8V

VCLK

VCLKB = -1.3 V

Product Specification

TS8388BG

7.5. NOISE IMMUNITY INFORMATIONS

Circuit noise immunity performance begins at design level.

Efforts have been made on the design in order to make the device as insensitive as possible to chip environment perturbations resulting from

the circuit itself or induced by external circuitry.

(Cascode stages isolation, internal damping resistors, clamps, internal (onchip) decoupling capacitors.)

Furthermore, the fully differential operation from analog input up to the digital outputs provides enhanced noise immunity by common mode

noise rejection.

Common mode noise voltage induced on the differential analog and clock inputs will be canceled out by these balanced differential amplifiers.

Moreover, proper active signals shielding has been provided on the chip to reduce the amount of coupled noise on the active inputs :

The analog inputs and clock inputs of the TS8388BG device have been surrounded by ground pins, which must be directly connected to the

external ground plane.

7.6. DIGITAL OUTPUTS

The TS8388BG differential output buffers are internally 75 ohms loaded. The 75 ohms resistors are connected to the digital ground pins through

a -0.8v level shift diode (see Figures 3,4,5 on next page).

The TS8388BG output buffers are designed for driving 75 ohms (default) or 50 ohms properly terminated impedance lines or coaxial cables.

An 11 mA bias current flowing alternately into one of the 75 ohms resistors when switching ensures a 0.825 V voltage drop across the resistor

(unterminated outputs).

The VPLUSD positive supply voltage allows the adjustment of the output common mode level from -1.2V (VPLUSD=0V for ECL output

compatibility) to +1.2V (VPLUSD=2.4V for LVDS output compatibility).

Therefore, the single ended output voltages vary approximately between -0.8V and -1.625V, ( outputs unterminated ), around -1.2V common

mode voltage.

Three possible line driving and back-termination scenarios are proposed (assuming VPLUSD=0V) :

1 ) 75 Ohms impedance transmission lines, 75 ohms differentially terminated (Fig. 3) :

Each output voltage varies between -1V and -1.42V (respectively +1.4V and +1V), leading to +/- 0.41V =0.825 V in differential, around -1.21 V

(respectively +1.21V) common mode for VPLUSD=0V (respectively 2.4V).

2 ) 50 ohms impedance transmission lines, 50 ohms differentially termination (Fig. 4) :

Each output voltage varies between -1.02V and -1.35V (respectively +1.38V and +1.05V), leading to +/- 0.33V=660 mV in differential, around -

1.18V (respectively +1.21V) common mode for VPLUSD=0V (respectively 2.4V).

3 ) 75 ohms impedance open transmission lines (Fig. 5) :

Each output voltage varies between -1.6 V and -0.8 V (respectively +0.8V and +1.6V), which are true ECL levels, leading to +/- 0.8V=1.6V in

differential, around -1.2V (respectively +1.2V) common mode for VPLUSD=0V (respectively 2.4V).

Therefore, it is possible to drive directly high input impedance storing registers, without terminating the 75 ohms transmission lines.

In time domain, that means that the incident wave will reflect at the 75 ohms transmission line output and travel back to the generator ( i.e. the

75 ohms data output buffer ). As the buffer output impedance is 75 ohms, no back reflection will occur.

Note : This is no longer true if a 50 ohms transmission line is used, as the latter is not matching the buffer 75 ohms output impedance.

Each differential output termination length must be kept identical .

It is recommended to decouple the midpoint of the differential termination with a 10 nF capacitor to avoid common mode perturbation in case of

slight mismatch in the differential output line lengths.

Too large mismatches ( keep < a few mm ) in the differential line lengths will lead to switching currents flowing into the decoupling capacitor

leading to switching ground noise.

The differential output voltage levels ( 75 or 50 ohms termination ) are not ECL standard voltage levels, however it is possible to drive standard

logic ECL circuitry like the ECLinPS logic line from MOTOROLA.

At sampling rates exceeding 800MSPS, it may be difficult to trigger the HP16500 or any other Acquisition System with digital outputs.

It becomes necessary to regenerate digital data and Data Ready by means of external amplifiers, in order to be able to test the TS8388BG at its

optimum performance conditions.

34 TS8388BG

Product Specification

DIFFERENTIAL OUTPUT LOADING CONFIGURATIONS (LEVELS FOR ECL COMPATIBILITY)



11 mA

DVEE

VPLUSD = 0V

75 Ω75 Ω

75 Ω

impedance 10 nF

75 Ω

Out -1V / -1.41V

OutB -1.41V / -1V

Differential output :

± 0.41V = 0.825V

Common mode level : -1.2V

(-1.2V below VPLUSD level)

Figure 3 : DIFFERENTIAL OUTPUT : 75 Ω TERMINATED

-0.8V



11 mA

DVEE

VPLUSD = 0V

75 Ω75 Ω

50 Ω

impedance 10 nF

50 Ω

Out -1.02V / -1.35V

OutB -1.35V / -1.02V

Differential output :

± 0.33V = 0.660V

Common mode level : -1.2V

(-1.2V below VPLUSD level)

Figure 4 : DIFFERENTIAL OUTPUT : 50 Ω TERMINATED

-0.8V

11 mA

DVEE

VPLUSD = 0V

75 Ω75 Ω

75 Ω

impedance

Out -0.8V / -1.6V

OutB -1.6V / -0.8V

Differential output :

± 0.8V = 1.6V

Common mode level : -1.2V

(-1.2V below VPLUSD level)

Figure 5 : DIFFERENTIAL OUTPUT : OPEN LOADED

-0.8V

Product Specification

TS8388BG

DIFFERENTIAL OUTPUT LOADING CONFIGURATIONS (LEVELS FOR LVDS COMPATIBILITY)



11 mA

DVEE

VPLUSD = 2.4V

75 Ω75 Ω

75 Ω

impedance 10 nF

75 Ω

Out 1.4V / 0.99V

OutB 0.99V / 1.4V

Differential output :

± 0.41V = 0.825V

Common mode level : -1.2V

(-1.2V below VPLUSD level)

Figure 6 : DIFFERENTIAL OUTPUT : 75 Ω TERMINATED

1.6V



11 mA

DVEE

VPLUSD = 2.4V

75 Ω75 Ω

50 Ω

impedance 10 nF

50 Ω

Out 1.38V / 1.05V

OutB 1.05V / 1.38V

Differential output :

± 0.33V = 0.660V

Common mode level : -1.2V

(-1.2V below VPLUSD level)

Figure 7 : DIFFERENTIAL OUTPUT : 50 Ω TERMINATED

1.6V

11 mA

DVEE

VPLUSD = 2.4V

75 Ω75 Ω

75 Ω

impedance

Out 1.6V / 0.8V

OutB 0.8V / 1.6V

Differential output :

± 0.8V = 1.6V

Common mode level : -1.2V

(-1.2V below VPLUSD level)

Figure 8 : DIFFERENTIAL OUTPUT : OPEN LOADED

1.6V

36 TS8388BG

Product Specification

7.7. OUT OF RANGE BIT

An Out of Range (OR,ORB) bit is provided that goes to logical high state when the input exceeds the positive full scale or falls below the

negative full scale.

When the analog input exceeds the positive full scale, the digital output datas remain at high logical state, with (OR,ORB) at logical one.

When the analog input falls below the negative full scale, the digital outputs remain at logical low state, with (OR,ORB) at logical one again.

7.8. GRAY OR BINARY OUTPUT DATA FORMAT SELECT

The TS8388BG internal regeneration latches indecision (for inputs very close to latches threshold) may produce errors in the logic encoding

circuitry and leading to large amplitude output errors.

This is due to the fact that the latches are regenerating the internal analog residues into logical states with a finite voltage gain value (Av) within

a given positive amount of time ∆(t) :

Av= exp(∆(t)/τ) , with τ the positive feedback regeneration time constant.

The TS8388BG has been designed for reducing the probability of occurrence of such errors to approximately 10-13 (targeted for the TS8388BG

at 1GSPS).

A standard technique for reducing the amplitude of such errors down to +/-1 LSB consists to output the digital datas in Gray code format.

Though the TS8388BG has been designed for featuring a Bit Error Rate of 10-13 with a binary output format, it is possible for the user to select

between the Binary or Gray output data format, in order to reduce the amplitude of such errors when occurring, by storing Gray output codes.

Digital Datas format selection :

BINARY output format if GORB is floating or VCC.

GRAY output format if GORB is connected to ground (0V).

7.9. DIODE PIN K1

One single pin is used for both DRRB input command and die junction monitoring. The pin denomination is DRRB/DIOD. Temperature

monitoring and Data Ready control by DRRB is not possible simultaneously.

(See section 7.2 for Data Ready Reset input command).

The operating die junction temperature must be kept below145°C, therefore an adequate cooling system has to be set up.

The diode mounted transistor measured Vbe value versus junction temperature is given below.

600

640

680

720

760

800

840

880

920

960

1000

-55 -35 -15 5 25 45 65 85 105 125

Junction temperature (deg.C)

VBE (mV)

Product Specification

TS8388BG

7.10. ADC GAIN CONTROL PIN K6

The ADC gain is adjustable by the means of the pin K6 (input impedance is 1MΩ in parallel with 2pF)

The gain adjust transfer function is given below :

0,80

0,85

0,90

0,95

1,00

1,05

1,10

1,15

1,20

-500 -400 -300 -200 -100 0 100 200 300 400 500

Vgain (command voltage) (mV)

ADC Gain

Please refer to the document "ADCs and DEMUX APPLICATION NOTES" for more information.

38 TS8388BG

Product Specification

8. EQUIVALENT INPUT / OUTPUT SCHEMATICS

8.1. EQUIVALENT ANALOG INPUT CIRCUIT AND ESD PROTECTIONS

8.2. EQUIVALENT ANALOG CLOCK INPUT CIRCUIT AND ESD PROTECTIONS

GND=0V

VCC=+5V

VCLAMP= +2.4V

+1.65V

-1.55V

VEE VEE

VCC

GND

VIN VINB

VEE=-5V

Pad

capacitance

340fF

Pad

capacitance

340fF

-0.8V

-5.8V

5.8V

0.8V

200 Ω200 Ω

50 Ω50 Ω

Note : the ESD protection equivalent capacitance is 150 fF.

E21VE21V

-0.8V

-5.8V

VCC=+5V

+0.8V

GND=0V

VEE

VEE=-5V

CLK

VCC

VEE

CLKB

Pad

capacitance

340fF

Pad

capacitance

340fF

-5.8V

-5.8V -5.8V

-5.8V

5.8V5.8V

0.8V 0.8V

150 Ω150 Ω

380 µA 380 µA

Note : the ESD protection equivalent capacitance is 150 fF.

Product Specification

TS8388BG

8.3. EQUIVALENT DATA OUTPUT BUFFER CIRCUIT AND ESD PROTECTIONS

8.4. ADC GAIN ADJUST EQUIVALENT INPUT CIRCUITS AND ESD PROTECTIONS

VPLUSD=0V to 2.4V

DVEE=-5V VEE=-5VVEE=-5V

VEE VEE

OUT OUTB

-5.8V -5.8V

5.8V 5.8V

0.8V

0.8V 0.8V

0.8V

I=11mA

75 Ω75 Ω

-3.7V

Pad

capacitance

180 fF

Pad

capacitance

180 fF

Note : the ESD protection equivalent capacitance is 150 fF.

VEE

VEE VEE=-5V

VCC=+5V

+1.6V

Pad

capacitance

180 fF

-0.8 V

-5.8 V

-0.8 V

-5.8 V

0.8V

5.8V

0.8V

5.8V

1 kΩ1 kΩ

2 pF 2 pF

GND GND

VEE

VCC

Pad

capacitance

180 fF

500 µA500

GA GAB

NP1032C2 NP1032C2

Note : the ESD protection equivalent capacitance is 150 fF.

40 TS8388BG

Product Specification

8.5. GORB EQUIVALENT INPUT SCHEMATIC AND ESD PROTECTIONS

GORB: gray or binary select input; floating or tied to VCC -> binary

8.6. DRRB EQUIVALENT INPUT SCHEMATIC AND ESD PROTECTIONS

VCC=+5V

VEE=-5V GND=0V

-0.8V

-5.8V

5.8V

5 kΩ

1 kΩ1 kΩ

1 kΩ

250

A 250

Pad

capacitance

180fF

GORB

VEE

Note : the ESD protection equivalent capacitance is 150 fF.

VEE=-5V

VEE

VCC=+5V

GND=0V

-1.3V

-2.6V

10 kΩ

200 Ω

DRRB

5.8 V

Pad

capacitance

180 fF

Actual protection range: 6.6V above VEE,

In fact stress above GND are clipped by

the CB diode used for Tj monitoring

0.8 V

NP1032C2

Note : the ESD protection equivalent capacitance is 150 fF.

Product Specification

TS8388BG

9. TSEV8388BG : DEVICE EVALUATION BOARD

For complete specification, see separate TSEV8388BG document.

GENERAL DESCRIPTION

The TSEV8388BG Evaluation Board (CEB) is a board which has been designed in order to facilitate the evaluation and the characterization of

the TS8388BG device up to its 1.8 GHz full power bandwidth at up to 1 Gsps in the military temperature range.

The high speed of the TS8388BG requires careful attention to circuit design and layout to achieve optimal performance.

This four metal layer board with internal ground plane has the adequate functions in order to allow a quick and simple evaluation of the

TS8388BG ADC performances over the temperature range.

The TSEV8388BG Evaluation Board is very straightforward as it only implements the TS8388BG ADC, SMA connectors for input / output

accesses and a 2.54 mm pitch connector compatible with HP16500C high frequency probes.

The board also implements a de–embedding fixture in order to facilitate the evaluation of the high frequency insertion loss of the input microstrip

lines, and a die junction temperature measurement setting.

The board is constituted by a sandwich of two dielectric layers, featuring low insertion loss and enhanced thermal characteristics for operation in

the high frequency domain and extended temperature range.

The board dimensions are 130 mm x 130 mm.

The board set comes fully assembled and tested, with the TS8388BG and its heatsink installed.

42 TS8388BG

Product Specification

10. ORDERING INFORMATION

10.1. PACKAGE DEVICE

10.2. EVALUATION BOARD

The evaluation board is delivered with an ADC and includes the heat sink.

For more details for the Evaluation board, please refer to the TSEV8388BG data sheet.

Manufacturer prefix

Device or family

Temperature range : Package :

C : 0 < Tc ; Tj < 90°CG : CBGA72 with C and R

TS 8388B C G

Screening level :

___ : standard

TS EV 8388B C G ZA2

ZA2 : with MC100EL16

digital receivers

_: without receivers

Evaluation board prefix G : CBGA72 with C and R

Temperature range :

C : 0 < Tc ; Tj < 90°C

Product Specification

TS8388BG

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