1
4144K-AERO-04/07
Features
First-in First-out Dual Port Memory
16384 bits x 9 Organization
Fast Flag and Access Times: 15, 30 ns
Wide Temperature Range: -55°C to +125°C
Programmable Half Full Flag
Fully Expandable by Word Width or Depth
Asynchronous Read/Write Operations
Empty, Full and Half Flags in Single Device Mode
Retransmit Capability
Bi-directional Applications
Battery Back-up Operation: 2V Data Retention
TTL Compatible
Single 5V + 10% Power Supply
No Single Event Latch Up Below an LET threshold of 80 MeV/mg/cm
2
Tested up to a Total Dose of 30 Krads (according to MIL-STD-883 TM1019)
Quality grades: QML Q and V with SMD 5962-93177 and ESSC with Specification
9301/48
Description
The M672061H implements a first-in first-out algorithm, featuring asynchronous
read/write operations. The FULL and EMPTY flags prevent data overflow and under-
flow. The Expansion logic allows unlimited expansion in word size and depth with no
timing penalties. Twin address pointers automatically generate internal read and write
addresses, and no external address information are required for the Atmel FIFOs.
Address pointers are automatically incremented with the write pin and read pin. The 9
bits wide data are used in data communications applications where a parity bit for
error checking is necessary. The Retransmit pin resets the Read pointer to zero with-
out affecting the write pointer. This is very useful for retransmitting data when an error
is detected in the system.
Using an array of eight transistors (8T) memory cell, the M672061H combines an
extremely low standby supply current (typ = 0.1 µA) with a fast access time at 15 ns
over the full temperature range. All versions offer battery backup data retention capa-
bility with a typical power consumption at less than 2 µW.
For military/space applications that demand superior levels of performance and reli-
ability the M672061H is processed according to the methods of the latest revision of
the MIL PRF 38535 (Q and V) or ESCC 9000.
Rad. Tolerant
High Speed
16 Kb x 9
Parallel FIFO with
Programmable
Flag
M672061H
2
M672061H
4144K-AERO-04/07
Block Diagram
Pin Configuration
DIL ceramic 28-pin 300 mils
FP 28-pin 400 mils
3
M672061H
4144K-AERO-04/07
Pin
Description
Data In (I
0
- I
8
)
Data inputs for 9-bit data
Reset (RS)
Reset occurs whenever the Reset (RS) input is taken to a low state. Reset returns both
internal read and write pointers to the first location. A reset is required after power-up
before a write operation can be enabled. Both the Read Enable (R) and Write Enable
(W) inputs must be in the high state during the period shown in Figure 2 (i.e. t
RSS
before
the rising edge of RS) and should not change until tRSR after the rising edge of RS.
Otherwise, pulse write (or read) low during the reset operation loads the Programmable
Half Full Flag register from the data Inputs I0 - I8 (or data outputs Q0 - Q8) (shown in fig-
ure 2). In these two cases the Full Flag and the Programmable Half Full Flag are
reseted to high and the Empty Flag to low.
Figure 1. Reset (no write to Programmable Half Full Flag register)
Notes: 1. EF, FF and HF may change status during reset, but flags will be valid at t
RSC
.
2. W and R = VIH around the rising edge of RS.
Pin Name Description
I0 - 8 Inputs
Q0 - 8 Outputs
W Write Enable
R Read Enable
RS Reset
EF Empty Flag
FF Full Flag
XO/HF Expansion Out/Half-Full Flag
XI Expansion IN
FL/RT First Load/Retransmit
VCC Power Supply
GND Ground
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M672061H
4144K-AERO-04/07
Figure 2. Reset (write (read) to Programmable Half Full Flag register)
Write Enable (W)
A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set.
Data set-up and hold times must be maintained in the rise time of the leading edge of
the Write Enable (W). Data is stored sequentially in the Ram array, regardless of any
current read operation.
Once half the memory is filled, and during the falling edge of the next write operation,
the Half-Full Flag (HF) will be set to low and remain in this state until the difference
between the write and read pointers is less than or equal to half of the total available
memory in the device. The Half-Full Flag (HF) is then reset by the rising edge of the
read operation.
To prevent data overflow, the Full Flag (FF) will go low, inhibiting further write opera-
tions. On completion of a valid read operation, the Full Flag (FF) will go high after TRFF,
allowing a valid write to begin. When the FIFO stack is full, the internal write pointer is
blocked from W, so that external changes to W will have no effect on the full FIFO stack.
Read Enable (R)
A read cycle is initiated on the falling edge of the Read Enable (R) provided that the
Empty Flag (EF) is not set. The data is accessed on a first in/first out basis, not including
any current write operations. After Read Enable (R) goes high, the Data Outputs
(Q0 - Q8) will return to a high impedance state until the next Read operation. When all
the data in the FIFO stack has been read, the Empty Flag (EF) will go low, allowing the
“final” read cycle, but inhibiting further read operations while the data outputs remain in
a high impedance state. Once a valid write operation has been completed, the Empty
Flag (EF) will go high after tWEF and a valid read may then be initiated. When the FIFO
stack is empty, the internal read pointer is blocked from R, so that external changes to R
will have no effect on the empty FIFO stack.
First Load/Retransmit
(FL/RT)
This is a dual-purpose input. In the Depth Expansion Mode, this pin is connected to
ground to indicate that it is the first loaded (see Operating Modes). In the Single Device
Mode, this pin acts as the retransmit input. The Single Device Mode is initiated by con-
necting the Expansion In (XI) to ground.
The M672061H can be set to retransmit data when the Retransmit Enable Control (RT)
input is pulsed low. A retransmit operation will set the internal read point to the first loca-
tion and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be
in the high state during retransmit. The retransmit feature is intended for use when a
number of writes are equal to or less than the depth of the FIFO has occured since the
last RS cycle. The retransmit feature is not compatible with the Depth Expansion Mode
and will affect the Half-Full Flag (HF), in accordance with the relative locations of the
read and write pointers.
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M672061H
4144K-AERO-04/07
Expansion In (XI)
This input is a dual-purpose pin. Expansion In (XI) is connected to GND to indicate an
operation in the single device mode. Expansion In (XI) is connected to Expansion Out
(XO) of the previous device in the Depth Expansion or Daisy Chain modes.
Full Flag (FF)
The Full Flag (FF) will go low, inhibiting further write operations when the write pointer is
one location less than the read pointer, indicating that the device is full. If the read
pointer is not moved after Reset (RS), the Full Flag (FF) will go low after 16384 writes.
Empty Flag (EF)
The Empty Flag (EF) will go low, inhibiting further read operations when the read pointer
is equal to the write pointer, indicating that the device is empty.
Expansion Out/Half-full
Flag (XO/HF)
This is a dual-purpose output. In the single device mode, when Expansion In (XI) is con-
nected to ground, this output acts as an indication of a half-full memory.
The M672061H offers a variable offset for the Half Full condition. The offset is loaded
into a register during a reset cycle. When RS is low, the Programmable Half Full Flag
(PHF) can be loaded from the DATA inputs I
0
- I
8
by pulsing W low or from the DATA
outputs Q
0
- Q
8
by pulsing R low. The offset options are listed in table 1. If PHF is not
loaded during the reset cycle, the default offset will be the half of the total memory of the
device.
The Programmable Half-Full Flag (PHF) will be set to low and will remain set until the
difference between the write and read pointers is less than or equal to the Programma-
ble offset (if the Half Full Flag register has been loaded during the reset cycle) or the half
of the total memory (if the Half Full register has not been loaded during the reset cycle).
After half the memory is filled and on the falling edge of the next write operation, the
Half-Full Flag (HF) will be set to low and will remain set until the difference between the
write and read pointers is less than or equal to half of the total memory of the device.
The Half-Full Flag (HF) is then reset by the rising edge of the read operation.
In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of
the previous device. This output acts as a signal to the next device in the Daisy Chain by
providing a pulse to the next device when the previous device reaches the last memory
location.
Data Output (Q
0
- Q
8
)
DATA output for 9-bit wide data. This data is in a high impedance condition whenever
Read (R) is in a high state.
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M672061H
4144K-AERO-04/07
Functional Description
Single Device Mode
A single M672061H may be used when the application requirements are for 16384
words or less. The M672061H is in a Single Device Configuration when the Expansion In (XI)
control input is grounded (see Figure 3). In this mode the Half-Full Flag (HF), which is an active
low output, is shared with Expansion Out (XO).
Figure 3. Block Diagram of Single 16384 × 9
Width Expansion Mode
Word width may be increased simply by connecting the corresponding input control sig-
nals of multiple devices. Status flags (EF, FF and HF) can be detected from any device.
Figure 4 demonstrates an 18-bit word width by using two M672061H. Any word width can be
attained by adding additional M672061H.
Figure 4. Block Diagram of 16384 bits x 18 FIFO Memory Used in Width Expansion Mode
Note: Flag detection is accomplished by monitoring the FF, EF and the HF signals on either (any) device used in the width expansion
configuration. Do not connect any output control signals together.
(HALF-FULL FLAG)
WRITE (W)(R) READ
DATAIN
9
(I) DATAOUT
9
(Q)
FULL FLAG
RESET
(FF)
(RS)
EMPTY FLAG
RETRANSMIT
(EF)
(RT)
EXPANSION IN (XI)
HF
M672061H
HF
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M672061H
4144K-AERO-04/07
Note: 1. Pointer will increment if flag is high.
Note: 1. XI is connected to XO of previous device.
See Figure 5.
Table 1. Programmable Half Full Flag Offset
I
8
I
7
I
6
I
5
I
4
I
3
I
2
I
1
I
0
Offset
000000000 0
000000001 32
000000010 64
...
100000000 8192 (Half Full)
Default Offset
...
1 1 1 1 1 1 1 1 0 16384-64
1 1 1 1 1 1 1 1 1 16384-32
Table 2. Reset and Retransmit Single Device Configuration/Width Expansion Mode
Mode
Inputs Internal Status Outputs
RS RT XI Read Pointer Write Pointer EF FF HF
Reset 0 X 0 Location Zero Location Zero 0 1 1
Retransmit 1 0 0 Location Zero Unchanged X X X
Read/Write 1 1 0 Increment
(1)
Increment
(1)
X X X
Table 3. Reset and First Load Truth Table
Depth Expansion/Compound Expansion Mode
Mode
Inputs Internal Status Outputs
RS FL XI Read Pointer Write Pointer EF FF
Reset First Device 0 0
(1)
Location Zero Location Zero 0 1
Reset All Other Devices 0 1
(1)
Location Zero Location Zero 0 1
Read/Write 1 X
(1)
X X X X
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M672061H
4144K-AERO-04/07
Depth Expansion (Daisy
Chain) Mode
The M672061H can be easily adapted for applications which require more than 16384
words. Figure 5 demonstrates Depth Expansion using three M672061H. Any depth can
be achieved by adding additional 672061H.
The M672061H operates in the Depth Expansion configuration if the following condi-
tions are met:
1. The first device must be designated by connecting the First Load (FL) control
input to ground.
2. All other devices must have FL in the high state.
3. The Expansion Out (XO) pin of each device must be connected to the Expansion In
(XI) pin of the next device. See Figure 5.
4. External logic is needed to generate a composite Full Flag (FF) and Empty Flag
(EF). This requires that all EFs and all FFs be ORed (i.e. all must be set to generate the
correct composite FF or EF). See Figure 5.
5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in the Depth
Expansion Mode.
Compound Expansion
Module
It is quite simple to apply the two expansion techniques described above together to cre-
ate large FIFO arrays (see Figure 6).
Bidirectional Mode
Applications which require data buffering between two systems (each system being
capable of Read and Write operations) can be created by coupling M672061H as shown
in Figure 7 Care must be taken to ensure that the appropriate flag is monitored by each
system (i.e. FF is monitored on the device on which W is in use; EF is monitored on the device
on which R is in use). Both Depth Expansion and Width Expansion may be used in this mode.
Data Flow – Through
Modes
Two types of flow-through modes are permitted: a read flow-through and a write flow-
through mode. In the read flow-through mode (Figure 18) the FIFO stack allows a single
word to be read after one word has been written to an empty FIFO stack. The data is
enabled on the bus at (tWEF + tA) ns after the leading edge of W which is known as the
first write edge and remains on the bus until the R line is raised from low to high, after which the
bus will go into a three-state mode after tRHZ ns. The EF line will show a pulse indicating tem-
porary reset and then will be set. In the interval in which R is low, more words may be written to
the FIFO stack (the subsequent writes after the first write edge will reset the Empty Flag) ; how-
ever, the same word (written on the first write edge) presented to the output bus as the read
pointer will not be incremented if R is low. On toggling R, the remaining words written to the
FIFO will appear on the output bus in accordance with the read cycle timings.
In the write flow-through mode (Figure 19), the FIFO stack allows a single word of data
to be written immediately after a single word of data has been read from a full FIFO
stack. The R line causes the FF to be reset, but the W line, being low, causes it to be set again
in anticipation of a new data word. The new word is loaded into the FIFO stack on the leading
edge of W. The W line must be toggled when FF is not set in order to write new data into the
FIFO stack and to increment the write pointer.
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M672061H
4144K-AERO-04/07
Figure 5. Block Diagram of 49152 x 9 FIFO Memory (Depth Expansion)
Figure 6. Compound FIFO Expansion
Notes: 1. For depth expansion block see section on Depth Expansion and Figure 4.
2. For Flag detection see section on Width Expansion and Figure 3
Figure 7. Bidirectional FIFO Mode
M672061H
M672061H
M672061H
H
H
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M672061H
4144K-AERO-04/07
Electrical Characteristics
Absolute Maximum Ratings
DC Parameters
Notes: 1. Icc measurements are made with outputs open.
2. R = W = RS = FL/RT = VIH.
3. All input = Vcc
Notes: 1. 0.4 Vin Vcc.
2. R = VIH, 0.4 VOUT VCC.
3. VIH max = Vcc + 0.3V. VIL min = -0.3V or -1V pulse width 50 ns. For XI input, VIH= 2.8V
4. Vcc min, IOL = 8 mA, IOH = -2 mA
5. Guaranteed but not tested.
Supply voltage (VCC - GND):............................. -0.5V to 7.0V
Input or Output voltage applied: ... (GND -0.3V) to (Vcc +0.3V)
Storage temperature:.................................... -65 °C to +150°C
*NOTICE: Stresses beyond those listed under "Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions
beyond those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
Table 4. DC Test Conditions
TA = -55°C to +125°C; Vss = 0V; Vcc = 4.5V to 5.5V
Parameter Description M672061H-30 M672061H-15 Unit Value
I
CCOP (1)
Operating supply current 110 120 mA Max
I
CCSB(2)
Standby supply current 5 5 mA Max
I
CCPD(3)
Power down current 400 400 µA Max
Parameter Description M672061H Unit Value
ILI
(1)
Input leakage current ± 1 µA Max
ILO
(2)
Output leakage current ± 1 µA Max
VIL
(3)
Input low voltage 0.8 V Max
VIH
(3)
Input high voltage 2.2 V Min
VOL
(4)
Output low voltage 0.4 V Max
VOH
(4)
Output high voltage 2.4 V Min
C IN
(5)
Input capacitance 8 pF Max
C OUT
(5)
Output capacitance 8 pF Max
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M672061H
4144K-AERO-04/07
AC Parameters
AC Test Conditions
Input pulse levels: Gnd to 3.0V
Input rise/Fall times: 5 ns
Input timing reference levels: 1.5V
Output reference levels: 1.5V
Output load: See Figure 8
Figure 8. Output Load
Note: 1. Includes jig and scope capacitance.
(1)
Table 5. AC Test Conditions
Symbol
(1)
Symbol
(2)
Parameter
(3) (4)
M672061H- 30 M672061H- 15 Unit
Min Max Min Max
Read Cycle
TRLRL tRC Read cycle time 40 - 25 - ns
TRLQV tA Access time - 30 - 15 ns
TRHRL tRR Read recovery time 10 - 10 - ns
TRLRH tRPW Read pulse width
(5)
30 - 15 - ns
TRLQX tRLZ Read low to data low Z
(6)
0 - 0 - ns
TWHQX tWLZ Write low to data low Z
(6) (7)
5 - 3 - ns
TRHQX tDV Data valid from read high 5 - 5 - ns
TRHQZ tRHZ Read high to data high Z
(6)
- 20 - 15 ns
Write Cycle
TWLWL tWC Write cycle time 40 - 25 - ns
TWLWH tWPW Write pulse width
(5)
30 - 15 - ns
TWHWL tWR Write recovery time 10 - 10 - ns
TDVWH tDS Data set-up time 18 - 9 - ns
TWHDX tDH Data hold time 0 - 0 - ns
Reset Cycle
TRSLWL tRSC Reset cycle time 40 - 25 - ns
TRSLRSH tRS Reset pulse width
(5)
30 - 15 - ns
TWHRSH tRSS Reset set-up time 30 - 20 - ns
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M672061H
4144K-AERO-04/07
TRSHWL tRSR Reset recovery time 10 10 ns
Retransmit Cycle
TRTLWL tRTC Retransmit cycle time 40 25 ns
TRTLRTH tRT Retransmit pulse width
(5)
30 15 ns
TWHRTH tRTS Retransmit set-up time
(6)
30 15 ns
TRTHWL tRTR Retransmit recovery time 10 10 ns
Flags
TRSLEFL tEFL Reset to EF low 30 25 ns
TRSLFFH tHFH, tFFH Reset to HF/FF high 30 25 ns
TRLEFL tREF Read low to EF low 30 25 ns
TRHFFH tRFF Read high to FF high 30 25 ns
TEFHRH tRPE Read width after EF high 30 15 ns
TWHEFH tWEF Write high to EF high 30 15 ns
TWLFFL tWFF Write low to FF low 30 20 ns
TWLHFL tWHF Write low to HF low 30 30 ns
TRHHFH tRHF Read high to HF high 30 30 ns
TFFHWH tWPF Write width after FF high 30 15 ns
Expansion
TWLXOL tXOL Read/Write to XO low 30 15 ns
TWHXOH tXOH Read/Write to XO high 30 15 ns
TXILXIH tXI XI pulse width 30 15 ns
TXIHXIL tXIR XI recovery time 10 10 ns
TXILRL tXIS XI set-up time 10 10 ns
1. STD symbol.
2. ALT symbol.
3. Timings referenced as in ac test conditions.
4. All parameters tested only.
5. Pulse widths less than minimum value are not allowed.
6. Values guaranteed by design, not currently tested.
7. Only applies to read data flow-through mode.
Table 5. AC Test Conditions (Continued)
Symbol
(1)
Symbol
(2)
Parameter
(3) (4)
M672061H- 30 M672061H- 15 Unit
Min Max Min Max
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M672061H
4144K-AERO-04/07
Figure 9. Asynchronous Write and Read Operation
Figure 10. Full Flag from Last Write to First Read
Figure 11. Empty Flag from Last Read to First Write
14
M672061H
4144K-AERO-04/07
Figure 12. Retransmit
Note: 1. EF, FF and PHF may change status during Retransmit, but flags will be valid at t
RTC
Figure 13. Empty Flag Timing
Figure 14. Full Flag Timing
W
EF
R
t
WEF
t
RPE
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M672061H
4144K-AERO-04/07
Figure 15. Programmable Half-Full Flag Timing
Figure 16. Expansion Out
Figure 17. Expansion In
16
M672061H
4144K-AERO-04/07
Figure 18. Read Data Flow - Through Mode
Figure 19. Write Data Flow - Through Mode
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M672061H
4144K-AERO-04/07
Ordering Information
Note: 1. Contact Atmel for availability.
Reference Number Temperature Range Speed Package Quality Flow
MMCP-672061HV-15-E
(1)
25°C 15 ns SB28.3 Engineering Samples
SMCP-672061HV-15SCC -55 to +125°C 15 ns SB28.3 ESCC
SMCP-672061HV-30SCC -55 to +125°C 30 ns SB28.3 ESCC
5962-9317710QTC -55 to +125°C 15 ns SB28.3 QML Q
5962-9317709QTC -55 to +125°C 30 ns SB28.3 QML Q
5962-9317710VTC -55 to +125°C 15 ns SB28.3 QML V
5962-9317709VTC -55 to +125°C 30 ns SB28.3 QML V
5962D9317710VTC -55 to +125°C 15 ns SB28.3 QML V RHA
5962D9317709VTC -55 to +125°C 30 ns SB28.3 QML V RHA
MMDP-672061HV-15-E 25°C 15 ns FP28.4 Engineering Samples
SMDP-672061HV-15SCC -55 to +125°C 15 ns FP28.4 ESCC
SMDP-672061HV-30SCC -55 to +125°C 30 ns FP28.4 ESCC
5962-9317710QNC -55 to +125°C 15 ns FP28.4 QML Q
5962-9317709QNC -55 to +125°C 30 ns FP28.4 QML Q
5962-9317710VNC -55 to +125°C 15 ns FP28.4 QML V
5962-9317709VNC -55 to +125°C 30 ns FP28.4 QML V
5962D9317710VNC -55 to +125°C 15 ns FP28.4 QML V RHA
5962D9317709VNC -55 to +125°C 30 ns FP28.4 QML V RHA
MM0 -672061HV-15-E
(1)
25°C 15 ns Die Engineering Samples
MM0 -672061HV-15SV
(1)
-55 to +125°C 15 ns Die QML V
18
M672061H
4144K-AERO-04/07
Package Drawings
28-lead Side Braze (300 mils)
19
M672061H
4144K-AERO-04/07
28-lead Flat Pack (400 mils)
Printed on recycled paper.
Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard
warranty which is detailed in Atmels Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any
errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and
does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are
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