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Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. "Typical" parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 74VHC161 4-Bit Binary Counter with Asynchronous Clear tm Features General Description High Speed: fMAX = 185MHz (Typ.) at TA = 25C Synchronous counting and loading The VHC161 is an advanced high-speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The VHC161 is a high-speed synchronous modulo-16 binary counter. This device is synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The VHC161 has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW. An input protection circuit insures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. High-speed synchronous expansion Low power dissipation: ICC = 4A (Max.) at TA = 25C High noise immunity: VNIH = VNIL = 28% VCC (Min.) Power down protection provided on all inputs Low noise: VOLP = 0.8V (Max.) Pin and function compatible with 74HC161 Ordering Information Package Number Package Description 74VHC161M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74VHC161SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Order Number 74VHC161MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering number. Connection Diagram Pin Description Pin Names (c)1993 Fairchild Semiconductor Corporation 74VHC161 Rev. 1.4 Description CEP Count Enable Parallel Input CET Count Enable Trickle Input CP Clock Pulse Input MR Asynchronous Master Reset Input P0-P3 Parallel Data Inputs PE Parallel Enable Inputs Q0-Q3 Flip-Flop Outputs TC Terminal Count Output www.fairchildsemi.com 74VHC161 4-Bit Binary Counter with Asynchronous Clear May 2007 (CET)--determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. The VHC161 uses D-type edge-triggered flip-flops and changing the PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. IEEE/IEC The Terminal Count (TC) output is HIGH when CET is HIGH and counter is in state 15. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Figure 1 shows the connections for simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min to start its final cycle. Since this final cycle requires 16 clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that limits the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters. Functional Description The VHC161 counts in modulo-16 binary sequence. From state 15 (HHHH) it increments to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs (except due to Master Reset of the VHC161) occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: asynchronous reset, parallel load, count-up and hold. Five control inputs--Master Reset, Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle Logic Equations: Count Enable = CEP * CET * PE TC = Q0 * Q1 * Q2 * Q3 * CET Figure 1. Multistage Counter with Ripple Carry Figure 2. Multistage Counter with Lookahead Carry (c)1993 Fairchild Semiconductor Corporation 74VHC161 Rev. 1.4 www.fairchildsemi.com 2 74VHC161 4-Bit Binary Counter with Asynchronous Clear Logic Symbols 74VHC161 4-Bit Binary Counter with Asynchronous Clear Mode Select Table State Diagram Action on the Rising Clock Edge ( ) MR PE L X X X Reset (Clear) H L X X Load (Pn Qn) H H H H Count (Increment) H H L X No Change (Hold) H H X L No Change (Hold) CET CEP H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Block Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. (c)1993 Fairchild Semiconductor Corporation 74VHC161 Rev. 1.4 www.fairchildsemi.com 3 Symbol Parameter Rating VCC Supply Voltage -0.5V to +7.0V VIN DC Input Voltage -0.5V to +7.0V VOUT DC Output Voltage -0.5V to VCC + 0.5V IIK Input Diode Current -20mA IOK Output Diode Current 20mA IOUT DC Output Current 25mA ICC DC VCC / GND Current TSTG TL 50mA Storage Temperature -65C to +150C Lead Temperature (Soldering, 10 seconds) 260C Recommended Operating Conditions(1) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter VCC Supply Voltage VIN Input Voltage VOUT Output Voltage TOPR Operating Temperature tr , tf Rating 2.0V to +5.5V 0V to +5.5V 0V to VCC -40C to +85C Input Rise and Fall Time, VCC = 3.3V 0.3V 0ns/V 100ns/V VCC = 5.0V 0.5V 0ns/V 20ns/V Note: 1. Unused inputs must be held HIGH or LOW. They may not float. (c)1993 Fairchild Semiconductor Corporation 74VHC161 Rev. 1.4 www.fairchildsemi.com 4 74VHC161 4-Bit Binary Counter with Asynchronous Clear Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA = -40C to +85C TA = 25C Symbol Parameter VCC (V) VIH HIGH Level Input Voltage 2.0 Conditions Min. 1.50 3.0-5.5 0.7 x VCC VIL LOW Level Input Voltage VOH HIGH Level Output Voltage 3.0 LOW Level Output Voltage Min. 0.50 IOH = -50A 2.0 1.9 V 2.9 3.0 2.9 4.4 4.5 4.4 IOH = -4mA 2.58 2.48 IOH = -8mA 3.94 3.80 VIN = VIH or VIL IOL = 50A 4.5 0.0 0.1 0.1 0.0 0.1 0.1 0.0 IOL = 4mA 3.0 IOL = 8mA 4.5 V 0.3 x VCC 1.9 4.5 3.0 V 0.3 x VCC VIN = VIH or VIL Units 0.7 x VCC 3.0 2.0 Max. 0.50 3.0-5.5 2.0 Max. 1.50 2.0 4.5 VOL Typ. 0.1 0.1 0.36 0.44 V 0.36 0.44 IIN Input Leakage Current 0-5.5 VIN = 5.5V or GND 0.1 1.0 A ICC Quiescent Supply Current 5.5 VIN = VCC or GND 4.0 40.0 A Noise Characteristics TA = 25C Symbol (2) Parameter VCC (V) Conditions Typ. Limits Units Quiet Output Maximum Dynamic VOL 5.0 CL = 50pF 0.4 0.8 V VOLV(2) Quiet Output Minimum Dynamic VOL 5.0 CL = 50pF -0.4 -0.8 V VIHD(2) Minimum HIGH Level Dynamic Input Voltage 5.0 CL = 50pF 3.5 V VILD(2) Maximum LOW Level Dynamic Input Voltage 5.0 CL = 50pF 1.5 V VOLP Note: 2. Parameter guaranteed by design. (c)1993 Fairchild Semiconductor Corporation 74VHC161 Rev. 1.4 www.fairchildsemi.com 5 74VHC161 4-Bit Binary Counter with Asynchronous Clear DC Electrical Characteristics TA = -40 to +85C TA = 25C Symbol Parameter VCC (V) tPLH, tPHL Propagation Delay Time (CP-Qn) 3.3 0.3 5.0 0.5 tPLH, tPHL Propagation Delay Time (CP-TC, Count) 3.3 0.3 5.0 0.5 tPLH, tPHL Propagation Delay Time (CP-TC, Load) 3.3 0.3 5.0 0.5 tPLH, tPHL Propagation Delay Time (CET-TC) 3.3 0.3 5.0 0.5 tPHL Propagation Delay Time (MR -Qn) 3.3 0.3 5.0 0.5 tPHL Propagation Delay Time (MR -TC) 3.3 0.3 5.0 0.5 fMAX Maximum Clock Frequency 3.3 0.3 5.0 0.5 CIN Input Capacitance CPD Power Dissipation Capacitance Conditions Min. Typ. Max. Min. Max. Units CL = 15pF 8.3 12.8 1.0 15.0 CL = 50pF 10.8 16.3 1.0 18.5 CL = 15pF 4.9 8.1 1.0 9.5 CL = 50pF 6.4 10.1 1.0 11.5 CL = 15pF 8.7 13.6 1.0 16.0 CL = 50pF 11.2 17.1 1.0 19.5 CL = 15pF 4.9 8.1 1.0 9.5 CL = 50pF 6.4 10.1 1.0 11.5 CL = 15pF 11.0 17.2 1.0 20.0 CL = 50pF 13.5 20.7 1.0 23.5 CL = 15pF 6.2 10.3 1.0 12.0 CL = 50pF 7.7 12.3 1.0 14.0 CL = 15pF 7.5 12.3 1.0 14.5 CL = 50pF 10.5 15.8 1.0 18.0 CL = 15pF 4.9 8.1 1.0 9.5 CL = 50pF 6.4 10.1 1.0 11.5 CL = 15pF 8.9 13.6 1.0 16.0 CL = 50pF 11.2 17.1 1.0 19.5 CL = 15pF 5.5 9.0 1.0 10.5 CL = 50pF 7.0 11.0 1.0 12.5 CL = 15pF 8.4 13.2 1.0 15.5 CL = 50pF 10.9 16.7 1.0 19.0 CL = 15pF 5.0 8.6 1.0 10.0 CL = 50pF 6.5 10.6 1.0 12.0 CL = 15pF 80 130 70 CL = 50pF 55 85 50 CL = 15pF 135 185 115 CL = 50pF 95 125 85 VCC (3) = Open 4 10 ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz 10 23 pF pF Note: 3. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD * VCC * fIN + ICC When the outputs drive a capacitive load, total current consumption is the sum of CPD, and ICC which is obtained from the following formula: CQ0-CQ3 and CTC are the capacitances at Q0-Q3 and TC, respectively. FCP is the input frequency of the CP. (c)1993 Fairchild Semiconductor Corporation 74VHC161 Rev. 1.4 www.fairchildsemi.com 6 74VHC161 4-Bit Binary Counter with Asynchronous Clear AC Electrical Characteristics TA = 25C Symbol tS tS tS tH tH tH Parameter VCC (V)(4) Minimum Setup Time (Pn-CP) Minimum Setup Time (PE -CP) Minimum Setup Time (CEP or CET-CP) Minimum Hold Time (Pn-CP) Minimum Hold Time (PE -CP) Minimum Hold Time (CEP or CET-CP) tW(L), tW(H) Minimum Pulse Width CP (Count) tW(L) tREC Minimum Pulse Width (MR) Minimum Removal Time Typ. TA = -40C to +85C Guaranteed Minimum 3.3 5.5 6.5 5.0 4.5 4.5 3.3 8.0 9.5 5.0 5.0 6.0 3.3 7.5 9.0 5.0 5.0 6.0 3.3 1.0 1.0 5.0 1.0 1.0 3.3 1.0 1.0 5.0 1.0 1.0 3.3 1.0 1.0 5.0 1.0 1.0 3.3 5.0 5.0 5.0 5.0 5.0 3.3 5.0 5.0 5.0 5.0 5.0 3.3 2.5 2.5 5.0 1.5 1.5 Units ns ns ns ns ns ns ns ns ns Note: 4. VCC is 3.3 0.3V or 5.0 0.5V. (c)1993 Fairchild Semiconductor Corporation 74VHC161 Rev. 1.4 www.fairchildsemi.com 7 74VHC161 4-Bit Binary Counter with Asynchronous Clear AC Operating Requirements 74VHC161 4-Bit Binary Counter with Asynchronous Clear Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 3. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A (c)1993 Fairchild Semiconductor Corporation 74VHC161 Rev. 1.4 www.fairchildsemi.com 8 74VHC161 4-Bit Binary Counter with Asynchronous Clear Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 4. 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D (c)1993 Fairchild Semiconductor Corporation 74VHC161 Rev. 1.4 www.fairchildsemi.com 9 5.000.10 4.55 5.90 4.45 7.35 0.65 4.40.1 1.45 5.00 0.11 12 MTC16rev4 Figure 5. 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 (c)1993 Fairchild Semiconductor Corporation 74VHC161 Rev. 1.4 www.fairchildsemi.com 10 74VHC161 4-Bit Binary Counter with Asynchronous Clear Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. (R) ACEx Across the board. Around the world.TM ActiveArrayTM BottomlessTM Build it NowTM CoolFETTM CROSSVOLTTM CTLTM Current Transfer LogicTM DOMETM 2 E CMOSTM (R) EcoSPARK EnSignaTM FACT Quiet SeriesTM (R) FACT (R) FAST FASTrTM FPSTM (R) FRFET GlobalOptoisolatorTM GTOTM HiSeCTM i-LoTM ImpliedDisconnectTM IntelliMAXTM ISOPLANARTM MICROCOUPLERTM MicroPakTM MICROWIRETM Motion-SPMTM MSXTM MSXProTM OCXTM OCXProTM (R) OPTOLOGIC (R) OPTOPLANAR PACMANTM PDP-SPMTM POPTM (R) Power220 (R) Power247 PowerEdgeTM PowerSaverTM Power-SPMTM (R) PowerTrench Programmable Active DroopTM (R) QFET QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM RapidConnectTM ScalarPumpTM SMART STARTTM (R) SPM STEALTHTM SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TCMTM (R) The Power Franchise TinyBoostTM TinyBuckTM (R) TinyLogic TINYOPTOTM TinyPowerTM TinyWireTM TruTranslationTM SerDesTM (R) UHC UniFETTM VCXTM WireTM TM DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD'S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Definition Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only. Rev. I26 (c)1993 Fairchild Semiconductor Corporation 74VHC161 Rev. 1.4 www.fairchildsemi.com 11 74VHC161 4-Bit Binary Counter with Asynchronous Clear TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. 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