LTC3895
1
3895fa
For more information www.linear.com/LTC3895
Typical applicaTion
FeaTures DescripTion
150V Low IQ, Synchronous
Step-Down DC/DC Controller
The LT C
®
3895 is a high performance step-down switching
regulator DC/DC controller that drives an all N-channel
synchronous power MOSFET stage that can operate from
input voltages up to 140V. A constant frequency current
mode architecture allows a phase-lockable frequency of
up to 850kHz.
The gate drive voltage can be programmed from 5V to 10V
to allow the use of logic or standard-level FETs to maxi-
mize efficiency. An integrated switch in the top gate driver
eliminates the need for an external bootstrap diode. An
internal charge pump allows for 100% duty cycle operation.
The low 40μA no-load quiescent current extends operating
run time in battery-powered systems. OPTI-LOOP
®
com-
pensation allows the transient response to be optimized
over a wide range of output capacitance and ESR values.
The LTC3895 features a precision 0.8V reference and
power good output indicator. The output voltage can be
programmed between 0.8V to 60V using external resistors
or pin-programmed for a fixed 5V or 3.3V.
High Efficiency High Voltage 12V Output Step-Down Regulator Efficiency and Power Loss
vs Load Current
applicaTions
n Wide VIN Range: 4V to 140V (150V Abs Max)
n Wide Output Voltage Range: 0.8V to 60V
n Adjustable Gate Drive Level: 5V to 10V (OPTI-DRIVE)
n Low Operating IQ: 40μA (Shutdown = 10μA)
n 100% Duty Cycle Operation
n No External Bootstrap Diode Required
n Selectable Gate Drive UVLO Thresholds
n Onboard LDO or External NMOS LDO for DRVCC
n EXTVCC LDO Powers Drivers from VOUT
n Phase-Lockable Frequency (75kHz to 850kHz)
n Programmable Fixed Frequency (50kHz to 900kHz)
n Selectable Continuous, Pulse-Skipping or Low Ripple
Burst Mode
®
Operation at Light Loads
n Adjustable Burst Clamp and Current Limit
n Adjustable or Fixed (5V/3.3V) Output Voltage
n Power Good Output Voltage Monitor
n Programmable Input Overvoltage Lockout
n 38-Lead TSSOP High Voltage Package
n Automotive and Industrial Power Systems
n High Voltage Battery Operated Systems
n Telecommunications Power Systems
L, LT, LTC, LTM, Burst Mode, OPTI-LOOP, PolyPhase, Linear Technology and the Linear logo
are registered trademarks of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents including 5481178, 5705919,
5929620, 6144194, 6177787, 6580258.
0.1µF
4.7µF
6mΩ
511k
150µF
36.5k
1nF
0.1µF
0.1µF
10k
4.7nF
100pF
100µF
33µH
30.1k
V
IN
INTV
CC
CPUMP_EN
ITH
SS
FREQ
GND
LTC3895
TG
SW
BG
SENSE+
SENSE–
EXTV
CC
VFB
BOOST
RUN
NDRV
DRV
CC
V
IN
7V to 140V
V
OUT
12V*
5A
x3
*VOUT FOLLOWS VIN WHEN VIN < 12V
POWER LOSS
V
IN
= 48V
EFFICIENCY
V
IN
= 24V
LOAD CURRENT (A)
0.0001
0.001
0.01
0.1
1
10
0
10
20
30
40
50
60
70
80
90
100
1
10
100
1k
10k
EFFICIENCY (%)
POWER LOSS (mW)
3895 TA01b
LTC3895
2
3895fa
For more information www.linear.com/LTC3895
pin conFiguraTionabsoluTe MaxiMuM raTings
Input Supply Voltage (VIN) ....................... –0.3V to 150V
Top Side Driver Voltage BOOST ............... –0.3V to 150V
Switch Voltage (SW) ................................... –5V to 150V
DRVCC, (BOOST-SW) Voltages ....................–0.3V to 11V
BG, TG ............................................................... (Note 8)
RUN Voltage............................................. –0.3V to 150V
SENSE+, SENSE– Voltages ......................... –0.3V to 65V
PLLIN, PGOOD Voltages .............................. –0.3V to 6V
MODE, DRVUV Voltages .............................. –0.3V to 6V
ILIM, VPRG, FREQ, PHASMD Voltages ........ –0.3V to 6V
DRVSET, CPUMP_ EN Voltages ..................... –0.3V to 6V
NDRV ................................................................. (Note 9)
EXTVCC Voltage ......................................... –0.3V to 14V
ITH, VFB Voltages ......................................... –0.3V to 6V
SS, OVLO Voltages ...................................... –0.3V to 6V
Operating Junction Temperature Range (Notes 2, 3)
LTC3895E, LTC3895I ......................... –40°C to 125°C
LTC3895H .......................................... –40°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
(Note 1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
TOP VIEW
FE PACKAGE
VARIATION: FE38(31)
38-LEAD PLASTIC TSSOP
38
37
36
34
32
30
28
26
24
22
21
20
39
GND
OVLO
VPRG
SENSE+
SENSE–
SS
VFB
ITH
MODE
GND
CPUMP_EN
CLKOUT
GND
PLLIN
PGOOD
GND
NC
FREQ
DRVSET
DRVUV
INTVCC
ILIM
PHASMD
RUN
EXTVCC
VIN
NDRV
DRVCC
BG
BOOST
SW
TG
TJMAX = 150°C, θJA = 28°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE
SOLDERED TO PCB FOR RATED ELECTRICAL AND
THERMAL CHARACTERISTICS
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3895EFE#PBF LTC3895EFE#TRPBF LTC3895FE 38-Lead Plastic TSSOP –40°C to 125°C
LTC3895IFE#PBF LTC3895IFE#TRPBF LTC3895FE 38-Lead Plastic TSSOP –40°C to 125°C
LTC3895HFE#PBF LTC3895HFE#TRPBF LTC3895FE 38-Lead Plastic TSSOP –40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear
.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
http://www.linear.com/product/LTC3895#orderinfo
LTC3895
3
3895fa
For more information www.linear.com/LTC3895
elecTrical characTerisTics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Input Supply Operating Voltage Range (Note 10) DRVUV = 0V l4 140 V
VOUT Regulated Output Voltage Set Point 0.8 60 V
VFB Regulated Feedback Voltage (Note 4); ITH Voltage = 1.2V
0°C to 85°C, VPRG = FLOAT
VPRG = FLOAT
VPRG = 0V
VPRG = INTVCC
l
l
l
0.792
0.788
3.220
4.875
0.800
0.800
3.300
5.000
0.808
0.812
3.380
5.125
V
V
V
V
IFB Feedback Current (Note 4)
VPRG = FLOAT
VPRG = 0V or INTVCC
–0.006
4
±0.050
6
µA
µA
Reference Voltage Line Regulation (Note 4) VIN = 4.5V to 150V 0.002 0.02 %/V
Output Voltage Load Regulation (Note 4) Measured in Servo Loop,
∆ITH Voltage = 1.2V to 0.7V
l
0.01
0.1
%
(Note 4) Measured in Servo Loop,
∆ITH Voltage = 1.2V to 1.6V
l
–0.01
–0.1
%
gmTransconductance Amplifier gm (Note 4) ITH = 1.2V, Sink/Source 5µA 2.2 mmho
IQInput DC Supply Current (Note 5) VDRVSET = 0V
Pulse Skip or Forced Continuous Mode VFB = 0.83V (No Load) 2.5 mA
Sleep Mode VFB = 0.83V (No Load) 40 55 µA
Shutdown RUN = 0V 10 20 µA
UVLO Undervoltage Lockout DRVCC Ramping Up
DRVUV = 0V
DRVUV = INTVCC, DRVSET = INTVCC
l
l
4.0
7.5
4.2
7.8
V
V
DRVCC Ramping Down
DRVUV = 0V
DRVUV = INTVCC, DRVSET = INTVCC
l
l
3.6
6.4
3.8
6.7
4.0
7.0
V
V
VRUN ON RUN Pin ON Threshold VRUN Rising l1.1 1.2 1.3 V
VRUN Hyst RUN Pin Hysteresis 80 mV
OVLO Overvoltage Lockout Threshold VOVLO Rising l1.1 1.2 1.3 V
OVLO Hyst OVLO Hysteresis 100 mV
OVLO Delay 1 µs
Feedback Overvoltage Protection Measured at VFB, Relative to Regulated VFB 7 10 13 %
ISENSE+ SENSE+ Pin Current ±1 µA
ISENSE– SENSE– Pin Current SENSE– < VINTVCC – 0.5V
SENSE– > VINTVCC + 0.5V
850
±1 µA
µA
Maximum Duty Factor In Dropout
CPUMP_EN = 0V, FREQ = 0V
CPUMP_EN = INTVCC
98
100
99
%
ISS Soft-Start Charge Current VSS = 0V 8 10 12 µA
VSENSE(MAX) Maximum Current Sense Threshold VFB = 0.7V, VSENSE– = 3.3V
ILIM = FLOAT
ILIM = 0V
ILIM = INTVCC
l
l
l
66
43
90
75
50
100
84
57
109
mV
mV
mV
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, VRUN = 5V, VEXTVCC = 0V, VDRVSET = 0V,
VPRG = FLOAT unless otherwise noted.
LTC3895
4
3895fa
For more information www.linear.com/LTC3895
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Gate Driver
TG Pull-up On-Resistance
TG Pull-down On-Resistance
VDRVSET = INTVCC 2.2
1.0
Ω
Ω
BG Pull-up On-Resistance
BG Pull-down On-Resistance
VDRVSET = INTVCC 2.0
1.0
Ω
Ω
BOOST to DRVCC Switch On-Resistance VSW = 0V, VDRVSET = INTVCC 11 Ω
TG Transition Time:
Rise Time
Fall Time
(Note 6) VDRVSET = INTVCC
CLOAD = 3300pF
CLOAD = 3300pF
25
15
ns
ns
BG Transition Time:
Rise Time
Fall Time
(Note 6) VDRVSET = INTVCC
CLOAD = 3300pF
CLOAD = 3300pF
25
15
ns
ns
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
CLOAD = 3300pF each driver, VDRVSET = INTVCC
55
ns
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
CLOAD = 3300pF each driver, VDRVSET = INTVCC
50
ns
tON(MIN) TG Minimum On-Time (Note 7) VDRVSET = INTVCC 80 ns
Charge Pump for High Side Driver Supply
ICPUMP Charge Pump Output Current VBOOST =16V, VSW = 12V, VFREQ = 0V
VBOOST =19V, VSW = 12V, VFREQ = 0V
65
55
µA
µA
DRVCC LDO Regulator
DRVCC Voltage from NDRV LDO
Regulator
NDRV Driving External NFET, VEXTVCC = 0V
7V < VIN < 150V, DRVSET = 0V
11V < VIN < 150V, DRVSET = INTVCC
5.8
9.6
6.0
10.0
6.2
10.4
V
V
DRVCC Load Regulation from NDRV
LDO Regulator
NDRV Driving External NFET
ICC = 0mA to 50mA, VEXTVCC = 0V
0
1.0
%
DRVCC Voltage from Internal VIN LDO NDRV = DRVCC, VEXTVCC = 0V
7V < VIN < 150V, DRVSET = 0V
11V < VIN < 150V, DRVSET = INTVCC
5.6
9.5
5.85
9.85
6.1
10.3
V
V
DRVCC Load Regulation from VIN LDO ICC = 0mA to 50mA, VEXTVCC = 0V
DRVSET = 0V
DRVSET = INTVCC
1.4
0.9
2.5
2.0
%
%
DRVCC Voltage from Internal EXTVCC
LDO
7V < VEXTVCC < 13V, DRVSET = 0V
11V < VEXTVCC < 13V, DRVSET = INTVCC
5.8
9.6
6.0
10.0
6.2
10.4
V
V
DRVCC Load Regulation from Internal
EXTVCC LDO
ICC = 0mA to 50mA
DRVSET = 0V, VEXTVCC = 8.5V
DRVSET = INTVCC, VEXTVCC = 13V
0.7
0.5
2.0
2.0
%
%
EXTVCC LDO Switchover Voltage EXTVCC Ramping Positive
DRVUV = 0V
DRVUV = INTVCC, DRVSET = INTVCC
4.5
7.4
4.7
7.7
4.9
8.0
V
V
EXTVCC Hysteresis 250 mV
Programmable DRVCC RDRVSET = 50k
NDRV Driving External NFET, VEXTVCC = 0V
5.0
V
Programmable DRVCC RDRVSET = 70k
NDRV Driving External NFET, VEXTVCC = 0V
6.4
7.0
7.6
V
Programmable DRVCC RDRVSET = 90k
NDRV Driving External NFET, VEXTVCC = 0V
9.0
V
elecTrical characTerisTics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, VRUN = 5V, VEXTVCC = 0V, VDRVSET = 0V,
VPRG = FLOAT unless otherwise noted.
LTC3895
5
3895fa
For more information www.linear.com/LTC3895
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
INTVCC LDO Regulator
VINTVCC INTVCC Voltage ICC = 0mA to 2mA 4.7 5.0 5.2 V
Oscillator and Phase-Locked Loop
Programmable Frequency RFREQ = 25k, PLLIN = DC Voltage 105 kHz
Programmable Frequency RFREQ = 65k, PLLIN = DC Voltage 375 440 505 kHz
Programmable Frequency RFREQ =105k, PLLIN = DC Voltage 835 kHz
Low Fixed Frequency VFREQ = 0V, PLLIN = DC Voltage 320 350 380 kHz
High Fixed Frequency VFREQ = INTVCC, PLLIN = DC Voltage 485 535 585 kHz
fSYNC Synchronizable Frequency PLLIN = External Clock l75 850 kHz
PLLIN Input High Level
PLLIN Input Low Level
PLLIN = External Clock
PLLIN = External Clock
l
l
2.8
0.5
V
V
PGOOD Output
VPGL PGOOD Voltage Low IPGOOD = 2mA 0.02 0.04 V
IPGOOD PGOOD Leakage Current VPGOOD = 3.3V 10 µA
PGOOD Trip Level VFB with Respect to Set Regulated Voltage
VFB Ramping Negative
Hysteresis
–13
–10
2.5
–7
%
%
VFB with Respect to Set Regulated Voltage
VFB Ramping Positive
Hysteresis
7
10
2.5
13
%
%
Delay for Reporting a Fault 40 µs
elecTrical characTerisTics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, VRUN = 5V, VEXTVCC = 0V, VDRVSET = 0V,
VPRG = FLOAT unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Ratings for extended periods may affect device reliability and
lifetime.
Note 2: The LTC3895 is tested under pulsed load conditions such that TJ ≈
TA. The LTC3895E is guaranteed to meet performance specifications from
0°C to 85°C. Specifications over the –40°C to 125°C operating junction
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3895I is guaranteed over the
–40°C to 125°C operating junction temperature range and the LTC3895H
is guaranteed over the –40°C to 150°C operating junction temperature
range. Note that the maximum ambient temperature consistent with
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal impedance
and other environmental factors. High temperatures degrade operating
lifetimes; operating lifetime is derated for junction temperatures greater
than 125ºC. The junction temperature (TJ, in °C) is calculated from the
ambient temperature (TA, in °C) and power dissipation (PD, in Watts)
according to the formula:
TJ = TA + (PD • θJA)
where θJA = 28°C/W for the TSSOP package.
Note 3: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 4: The LTC3895 is tested in a feedback loop that servos VITH to a
specified voltage and measures the resultant VFB. The specification at 85°C
is not tested in production and is assured by design, characterization and
correlation to production testing at other temperatures (125°C for the
LTC3895E and LTC3895I, 150°C for the LTC3895H). For the LTC3895I
and LTC3895H, the specification at 0°C is not tested in production and is
assured by design, characterization and correlation to production testing
at –40°C.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See the Applications information
section.
Note 6: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 7: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current >40% of IMAX (See Minimum On-Time
Considerations in the Applications Information section).
Note 8: Do not apply a voltage or current source to these pins. They must
be connected to capacitive loads only, otherwise permanent damage may
occur.
Note 9: Do not apply a voltage or current source to the NDRV pin, other
than tying NDRV to DRVCC when not used. If used it must be connected
to capacitive loads only (see DRVCC Regulators in the Applications
Information section), otherwise permanent damage may occur.
Note 10: The minimum input supply operating range is dependent on the
DRVCC UVLO thresholds as determined by the DRVUV pin setting.
LTC3895
6
3895fa
For more information www.linear.com/LTC3895
Typical perForMance characTerisTics
Load Step Burst Mode
Operation
Load Step
Pulse-Skipping Mode
Load Step Forced
Continuous Mode
Inductor Current at Light Load Soft Start-Up
Regulated Feedback Voltage
vs Temperature
Efficiency and Power Loss
vs Load Current Efficiency vs Load Current Efficiency vs Input Voltage
BURST EFFICIENCY
V
IN
= 24V
V
OUT
= 12V
PULSE–SKIPPING
LOSS
PULSE–SKIPPING
EFFICIENCY
FCM LOSS
FCM EFFICIENCY
FIGURE 13 CIRCUIT
BURST LOSS
LOAD CURRENT (A)
0.0001
0.001
0.01
0.1
1
10
0
10
20
30
40
50
60
70
80
90
100
1
10
100
1k
10k
EFFICIENCY (%)
POWER LOSS (mW)
3895 G01
V
OUT
= 12V
V
IN
= 24V
V
IN
= 48V
V
IN
= 100V
V
IN
= 140V
LOAD CURRENT (A)
0.0001
0.001
0.01
0.1
1
10
0
10
20
30
40
50
60
70
80
90
100
EFFICIENCY (%)
3895 G02
FIGURE 13 CIRCUIT
V
OUT
= 12V
I
LOAD
= 4A
INPUT VOLTAGE (V)
20
40
60
80
100
120
140
80
82
84
86
88
90
92
94
96
98
100
EFFICIENCY (%)
3895 G03
FIGURE 13 CIRCUIT
200µs/DIV
VOUT
100mV/DIV
AC COUPLED
IL
1A/DIV
3895 G04
VIN = 24V
FIGURE 13 CIRCUIT
200µs/DIV
VOUT
100mV/DIV
AC COUPLED
IL
1A/DIV
3895 G04
VIN = 24V
FIGURE 13 CIRCUIT
200µs/DIV
VOUT
100mV/DIV
AC COUPLED
IL
1A/DIV
3895 G06
VIN = 24V
FIGURE 13 CIRCUIT
200µs/DIV
FORCED
CONTINUOUS
MODE
BURST MODE
OPERATION
2A/DIV
PULSE
SKIPPING
MODE
3895 G07
VIN = 24V
FIGURE 13 CIRCUIT
2ms/DIV
VOUT
2V/DIV
RUN
2V/DIV
3895 G08
VIN = 24V
FIGURE 13 CIRCUIT
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
792
794
796
798
800
802
804
806
808
REGULATED FEEDBACK VOLTAGE (V)
3895 G09
LTC3895
7
3895fa
For more information www.linear.com/LTC3895
Typical perForMance characTerisTics
SENSE– Pin Input Current
vs VSENSE Voltage
SENSE– Pin Input Bias Current
vs Temperature
Undervoltage Lockout Threshold
vs Temperature
Foldback Current Limit
Maximum Current Sense
Threshold vs ITH Voltage
RUN/OVLO Threshold
vs Temperature
DRVCC and EXTVCC
vs Load Current
EXTVCC Switchover and DRVCC
Voltages vs Temperature
EXTVCC Switchover and DRVCC
Voltages vs Temperature
EXTV
CC
= 5V
V
IN
LDO (No NDRV FET),
EXTV
CC
= 0V
NDRV LDO (NDRV FET),
EXTVCC = 0V
EXTV
CC
= 8.5V
DRVUV = DRVSET = 0V
LOAD CURRENT (mA)
0
20
40
60
80
100
4.0
4.5
5.0
5.5
6.0
6.5
DRV
CC
VOLTAGE (V)
3895 G10
DRVUV = DRVSET = 0V
EXTV
CC
RISING
EXTV
CC
FALLING
EXTV
CC
= 8.5V
NDRV LDO (NDRV FET),
EXTV
CC
= 0V
V
IN
LDO (No NDRV FET),
EXTV
CC
= 0V,
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
4.0
4.5
5.0
5.5
6.0
6.5
DRV
CC
VOLTAGE (V)
3895 G11
DRVUV = DRVSET = INTV
CC
EXTV
CC
RISING
EXTV
CC
FALLING
EXTV
CC
= 8.5V
NDRV LDO (NDRV NFET),
EXTV
CC
= 0V
V
IN
LDO (No NDRV NFET),
EXTV
CC
= 0V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
DRV
CC
VOLTAGE (V)
3895 G12
V
SENSE
COMMON MODE VOLTAGE (V)
0
5
10
15
20
25
30
35
40
45
50
55
60
65
0
100
200
300
400
500
600
700
800
900
1000
SENSE
–
CURRENT (µA)
3895 G13
V
OUT
≥ INTV
CC
+ 0.5V
V
OUT
≤ INTV
CC
– 0.5V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
100
200
300
400
500
600
700
800
900
1000
SENSE
–
CURRENT (µA)
3895 G14
RISING
RISING
FALLING
FALLING
DRVUV = INTV
CC
DRVUV = 0V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
DRV
CC
VOLTAGE (V)
3895 G15
ILIM
= FLOAT
ILIM
= GND
ILIM
= INTV
CC
FEEDBACK VOLTAGE (mV)
0
100
200
300
400
500
600
700
800
0
10
20
30
40
50
60
70
80
90
100
MAXIMUM CURRENT SENSE VOLTAGE (mV)
3895 G16
5% DUTY CYCLE
PULSE–SKIPPING
BURST MODE
OPERATION
ILIM
= GND
ILIM
= INTV
CC
ILIM
= FLOAT
FORCED CONTINUOUS
V
ITH
(V)
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
–40
–20
0
20
40
60
80
100
CURRENT SENSE VOLTAGE (mV)
3895 G17
OVLO RISING
RUN RISING
RUN FALLING
OVLO FALLING
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
RUN/OVLO PIN VOLTAGE (V)
3895 G18
LTC3895
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For more information www.linear.com/LTC3895
Typical perForMance characTerisTics
Quiescent Current vs Temperature
Oscillator Frequency
vs Temperature
SS Pull-Up Current
vs Temperature
Boost Charge Pump Voltage
vs SW Voltage
BOOST Charge Pump Charging
Current vs Frequency
BOOST Charge Pump Charging
Current vs SW Voltage
DRVCC Line Regulation Shutdown Current vs Temperature
Shutdown Current
vs Input Voltage
DRVSET = INTV
CC
DRVSET = 0V
No NDRV FET
EXTV
CC
= 0V
NDRV FET
INPUT VOLTAGE (V)
0
15
30
45
60
75
90
105
120
135
150
5
6
7
8
9
10
11
DRV
CC
VOLTAGE (V)
3895 G19
V
IN
= 12V
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
2
4
6
8
10
12
14
16
18
20
SHUTDOWN CURRENT (µA)
3895 G20
V
IN
= 6.3V
INPUT VOLTAGE (V)
0
15
30
45
60
75
90
105
120
135
150
0
5
10
15
20
25
30
SHUTDOWN CURRENT (µA)
3895 G21
V
IN
= 12V
BURST MODE OPERATION
DRVSET = 70kΩ
DRVSET = 0V
DRVSET = INTV
CC
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
0
10
20
30
40
50
60
70
80
90
100
QUIESCENT CURRENT (µA)
3895 G22
FREQ = 0V
FREQ = INTV
CC
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
300
350
400
450
500
550
600
FREQUENCY (kHz)
3895 G23
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
8.0
8.5
9.0
9.5
10.0
10.5
11.0
11.5
12.0
SS CURRENT (µA)
3895 G24
FREQ = 350kHz
10MΩ BETWEEN BOOST AND SW
150°C
25°C
–55°C
SW VOLTAGE (V)
0
5
10
15
20
25
30
35
40
45
50
55
60
65
0
1
2
3
4
5
6
7
8
9
10
(BOOST - SW) VOLTAGE (V)
3895 G25
V
BOOST
= 16V
V
SW
= 12V
150°C
25°C
–55°C
OPERATING FREQUENCY (kHz)
0
100
200
300
400
500
600
700
800
900
1000
0
10
20
30
40
50
60
70
80
90
100
CHARGE PUMP CHARGING CURRENT (µA)
3895 G26
FREQ = 350kHz
VBOOST - VSW = 7V
150°C
25°C
–55°C
SW VOLTAGE (V)
0
5
10
15
20
25
30
35
40
45
50
55
60
65
0
10
20
30
40
50
60
70
80
90
100
CHARGE PUMP CHARGING CURRENT (µA)
3895 G27
VBOOST - VSW = 4V
LTC3895
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For more information www.linear.com/LTC3895
pin FuncTions
OVLO (Pin 1): Overvoltage Lockout Input. A voltage on
this pin above 1.2V disables switching of the controller.
The DRVCC and INTVCC supplies maintain regulation during
an OVLO event. Exceeding the OVLO threshold triggers a
soft-start reset. If the OVLO function is not used, connect
this pin to GND.
VPRG (Pin 2): Output Voltage Control Pin. This pin sets
the regulator in adjustable output mode using external
feedback resistors or fixed 5V/3.3V output mode. Floating
this pin allows the output to be programmed from 0.8V
to 60V with an external resistor divider on the VFB pin,
regulating VFB to 0.8V. Tying this pin to INTVCC or GND
programs the output to 5V or 3.3V, respectively, through
an internal resistor divider on VFB.
SENSE+ (Pin 3): The (+) Input to the Differential Current
Comparator. The ITH pin voltage and controlled offsets
between the SENSE– and SENSE+ pins in conjunction with
RSENSE set the current trip threshold.
SENSE– (Pin 4): The (–) Input to the Differential Current
Comparator. When SENSE– is greater than INTVCC, the
SENSE– pin supplies power to the current comparator.
SS (Pin 5): Soft-Start Input. The LTC3895 regulates the
VFB voltage to the smaller of 0.8V or the voltage on the
SS pin. An internal 10μA pull-up current source is con-
nected to this pin. A capacitor to ground at this pin sets
the ramp time to final regulated output voltage. The SS
pin is also used for the Regulator Shutdown (REGSD)
feature. A 5μA/1μA pull-down current can be connected
on SS depending on the state of the EXTVCC LDO and the
voltage on SS. See Regulator Shutdown in the Operation
section for more information. To defeat the REGSD feature,
place a 330k or smaller resistor between INTVCC and SS.
See Soft-Start Pin in the Applications Information section
for more information on defeating REGSD.
VFB (Pin 6): Feedback Input. If the VPRG pin is floating,
the VFB pin receives the remotely sensed feedback volt-
age from an eternal resistor divider across the output. If
VPRG is tied to GND or INTVCC, the VFB pin receives the
remotely sensed output voltage directly.
ITH (Pin 7): Error Amplifier Output and Switching Regulator
Compensation Point. The current comparator trip point
increases with this control voltage.
MODE (Pin 8): Mode Select and Burst Clamp Adjust In-
put. This input determines how the LTC3895 operates at
light loads. Pulling this pin to ground selects Burst Mode
operation with the burst clamp level defaulting to 25% of
VSENSE(MAX). Tying this pin to a voltage between 0.5V and
1.0V selects Burst Mode operation and adjusts the burst
clamp between 10% and 60%. Tying this pin to INTVCC
forces continuous inductor current operation. Tying this pin
to a voltage greater than 1.4V and less than INTVCC – 1.3V
selects pulse-skipping operation.
GND (Pins 9, 12, 15, Exposed Pin 39): Ground. All GND
pins must be tied together for operation. The exposed pad
must be soldered to PCB ground for rated electrical and
thermal performance.
CPUMP_EN (Pin 10): Charge Pump Enable Pin for the Top
Gate Driver Boost Supply. Tying this pin to INTVCC enables
the boost supply charge pump and allows for 100% duty
cycle operation in dropout. Tying this pin to GND disables
the charge pump and enables boost refresh, allowing for
99% duty cycle operation in dropout. Do not float this pin.
CLKOUT (Pin 11): Output Clock Signal. This signal is
available to daisy-chain other controller ICs for additional
MOSFET driver stages/phases. The output levels swing
from INTVCC to ground.
PLLIN (Pin 13): External Synchronization Input to Phase
Detector. When an external clock is applied to this pin,
the phase-locked loop will force the rising TG signal to be
synchronized with the rising edge of the external clock. If
the MODE pin is set to Forced Continuous Mode or Burst
Mode operation, then the regulator operates in Forced
Continuous Mode when synchronized. If the MODE pin is
set to pulse-skipping mode, then the regulator operates
in pulse-skipping mode when synchronized.
PGOOD (Pin 14): Open-Drain Logic Output. PGOOD is
pulled to ground when the voltage on the VFB pin is not
within ±10% of its set point.
NC (Pin 16): No connect. Float this pin or connect to GND.
LTC3895
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pin FuncTions
FREQ (Pin 17): Frequency Control Pin for the Internal VCO.
Connecting the pin to GND forces the VCO to a fixed low
frequency of 350kHz. Connecting the pin to INTVCC forces
the VCO to a fixed high frequency of 535kHz. Other fre-
quencies between 50kHz and 900kHz can be programmed
by using a resistor between FREQ and GND. An internal
20µA pull-up current develops the voltage to be used by
the VCO to control the frequency.
DRVSET (Pin 18): DRVCC Regulation Program Pin. This
pin sets the regulated output voltage of the DRVCC linear
regulator. Tying this pin to GND sets DRVCC to 6.0V. Ty-
ing this pin to INTVCC sets DRVCC to 10V. Other voltages
between 5V and 10V can be programmed by placing a
resistor (50k to 100k) between the DRVSET pin and GND.
An internal 20µA pull-up current develops the voltage to
be used as the reference to the DRVCC LDO.
DRVUV (Pin 19): DRVCC UVLO Program Pin. This pin
determines the higher or lower DRVCC UVLO and EXTVCC
switchover thresholds, as listed on the Electrical Character-
istics table. Connecting DRVUV to GND chooses the lower
thresholds whereas tying DRVUV to INTVCC chooses the
higher thresholds. Do not float this pin.
TG (Pin 20): High Current Gate Drives for Top N-Channel
MOSFET. This is the output of floating high side driver
with a voltage swing equal to DRVCC superimposed on
the switch node voltage SW.
SW (Pin 21): Switch Node Connection to Inductor.
BOOST (Pin 22): Bootstrapped Supply to the Topside
Floating Driver. A capacitor is connected between the
BOOST and SW pins. Voltage swing at the BOOST pin is
from approximately DRVCC to (VIN + DRVCC).
BG (Pin 24): High Current Gate Drive for Bottom (Syn-
chronous) N-Channel MOSFET. Voltage swing at this pin
is from ground to DRVCC.
DRVCC (Pin 26): Output of the Internal or External Low
Dropout Regulators. The gate drivers are powered from this
voltage source. The DRVCC voltage is set by the DRVSET
pin. Must be decoupled to ground with a minimum of 4.7µF
ceramic or other low ESR capacitor, as close as possible
to the IC. Do not use the DRVCC pin for any other purpose.
NDRV (Pin 28): Drive Output for External Pass Device
of the NDRV LDO Linear Regulator for DRVCC. Connect
this pin to the gate of an external NMOS pass device. An
internal charge pump allows NDRV to regulate above VIN
for low dropout performance. To disable this external
NDRV LDO, tie NDRV to DRVCC.
VIN (Pin 30): Main Supply Pin. A bypass capacitor should
be tied between this pin and the GND pins.
EXTVCC (Pin 32): External Power Input to an Internal LDO
linear regulator Connected to DRVCC. This LDO supplies
DRVCC power from EXTVCC, bypassing the internal LDO
powered from VIN or the external NDRV LDO whenever
EXTVCC is higher than its switchover threshold (4.7V or
7.7V depending on the DRVUV pin). See DRVCC Regulators
in the Applications Information section. Do not exceed 14V
on this pin. Do not connect EXTVCC to a voltage greater
than VIN. Connect to GND if not used.
RUN (Pin 34): Run Control Input. Forcing this pin below
1.12V shuts down the controller. Forcing this pin below
0.7V shuts down the entire LTC3895, reducing quiescent
current to approximately 10µA. This pin can be tied to VIN
for always-on operation. Do not float this pin.
PHASMD (Pin 36): Control Input to Phase Selector. This
determines the CLKOUT phase relationships with respect
to TG. Pulling this pin to ground forces CLKOUT to be
out of phase 90° with respect to TG. Connecting this pin
to INTVCC forces CLKOUT to be out of phase 120° with
respect to TG. Floating this pin forces CLKOUT to be out
of phase 180° with respect to TG.
ILIM (Pin 37): Current Comparator Sense Voltage Range
Input. Tying this pin to GND or INTVCC or floating it sets
the maximum current sense threshold to one of three
different levels (50mV, 100mV, and 75mV, respectively).
INTVCC (Pin 38): Output of the Internal 5V Low Dropout
Regulator. CLKOUT and many of the low voltage analog and
digital circuits are powered from this voltage source. A low
ESR 0.1µF ceramic bypass capacitor should be connected
between INTVCC and GND, as close as possible to the IC.
LTC3895
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FuncTional DiagraM
20µA
10µA
3V
5µA/1uA
2mV
R2
4R
R
100k
15M
R1
R
A
R
B
C
C2
C
C1
R
C
C
IN
CB
L
R
SENSE
C
OUT
V
OUT
C
SS
20µA
PGOOD
EA–
0.88V
0.72V
OVLO
RUN
1.2V
CLKOUT
PHASMD
VCO
FREQ
PFD
PLLIN
ILIM
DRVSET
V
IN
NDRV
DRV
CC
SS
ITH
V
FB
VPRG
SENSE–
SENSE+
GND
BG
SW
TG
BOOST
CURRENT
LIMIT
SYNC
DET
CHARGE
PUMP
DRV
CC
LDO/UVLO
CONTROL
INTV
CC
EXTV
CC
DRVUV
INTV
CC
LDO
4.7V/
7.7V
MODE
CPUMP_EN
NDRV LDO
V
IN
LDO
EXTV
CC
LDO
3.5V
CHARGE
PUMP
DROPOUT
DETECT
SWITCH
LOGIC
DRV
CC
DRV
CC
TOP
BOT
BOT
EN
TOPON
Q
S
R
EA
ICMP
IR
SLEEP
0.88V
REGSD
CLK
SHDN
1.8V
0.425V
SLOPE COMP
BCLAMP
0.80V
SS
V
IN
V
IN
2.0V
1.2V
EN
EN
EN
VPRG
FLOAT
GND
INTVCC
0
625k
1.05M
∞
200k
200k
ADJUSTABLE
3.3V FIXED
5V FIXED
VOUT
R1
R2
EA–
LTC3895
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For more information www.linear.com/LTC3895
operaTion
Main Control Loop
The LTC3895 uses a constant frequency, current mode
step-down architecture. During normal operation, the
external top MOSFET is turned on when the clock sets
the RS latch, and is turned off when the main current
comparator, ICMP, resets the RS latch. The peak inductor
current at which ICMP trips and resets the latch is con-
trolled by the voltage on the ITH pin, which is the output
of the error amplifier
, EA. The error amplifier compares
the output voltage feedback signal at the VFB pin (which
is generated with an external resistor divider connected
across the output voltage, VOUT, to ground) to the internal
0.800V reference voltage. When the load current increases,
it causes a slight decrease in VFB relative to the reference,
which causes the EA to increase the ITH voltage until the
average inductor current matches the new load current.
After the top MOSFET is turned off each cycle, the bottom
MOSFET is turned on until either the inductor current starts
to reverse, as indicated by the current comparator IR, or
the beginning of the next clock cycle.
DRVCC/EXTVCC/INTVCC Power
Power for the top and bottom MOSFET drivers is derived
from the DRVCC pin. The DRVCC supply voltage can be
programmed from 5V to 10V by setting the DRVSET pin.
Two separate LDOs (low dropout linear regulators) can
provide power from VIN to DRVCC. The internal VIN LDO
uses an internal P-channel pass device between the VIN and
DRVCC pins. To prevent high on-chip power dissipation in
high input voltage applications, the LTC3895 also includes
an NDRV LDO that utilizes the NDRV pin to supply power
to DRVCC by driving the gate of an external N-channel
MOSFET acting as a linear regulator with its source con-
nected to DRVCC and drain connected to VIN. The NDRV
LDO includes an internal charge pump that allows NDRV
to be driven above VIN for low dropout performance.
When the EXTVCC pin is tied to a voltage below its swi-
tchover voltage (4.7V or 7.7V depending on the DRVUV
pin), the VIN and NDRV LDOs are enabled and one of
them supplies power from VIN to DRVCC. The VIN LDO
has a slightly lower regulation point than the NDRV LDO.
If the NDRV LDO is being used with an external N-channel
MOSFET, the gate of the MOSFET tied to the NDRV pin
is driven such that DRVCC regulates above the VIN LDO
regulation point, causing all DRVCC current to flow through
the external N-channel MOSFET, bypassing the internal VIN
LDO pass device. If the NDRV LDO is not being used, all
DRVCC current flows through the internal P-channel pass
device between the VIN and DRVCC pins.
If EXTVCC is taken above its switchover voltage, the VIN
and NDRV LDOs are turned off and an EXTVCC LDO is
turned on. Once enabled, the EXTVCC LDO supplies power
from EXTVCC to DRVCC. Using the EXTVCC pin allows the
DRVCC power to be derived from a high efficiency external
source such as the LTC3895 switching regulator output.
The INTVCC supply powers most of the other internal circuits
in the LTC3895. The INTVCC LDO regulates to a fixed value
of 5V and its power is derived from the DRVCC supply.
Top MOSFET Driver and Charge Pump (CPUMP_EN Pin)
The top MOSFET driver is biased from the floating boot-
strap capacitor, CB, which normally recharges during each
cycle through an internal switch whenever SW goes low.
If the input voltage decreases to a voltage close to its output,
the loop may enter dropout and attempt to turn on the top
MOSFET continuously. The LTC3895 includes an internal
charge pump that allows the top MOSFET to be turned on
continuously at 100% duty cycle. This charge pump deliv-
ers current to CB and is enabled when the CPUMP_EN pin
is tied to INTVCC. Tying CPUMP_EN to GND disables the
charge pump and causes the dropout detector to force the
top MOSFET off for about one twelfth of the clock period
every tenth cycle to allow CB to recharge, resulting in an
effective 99% max duty cycle.
Shutdown and Start-Up (RUN, SS Pins)
The LTC3895 can be shut down using the RUN pin. Con-
necting the RUN pin below 1.12V shuts down the main
control loop. Connecting the RUN pin below 0.7V disables
the controller and most internal circuits, including the
DRVCC and INTVCC LDOs. In this state, the LTC3895 draws
only 10μA of quiescent current.
LTC3895
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operaTion
The RUN pin has no internal pull-up current, so the pin
must be externally pulled up or driven directly by logic.
The RUN pin can tolerate up to 150V (absolute maximum),
so it can be conveniently tied to VIN in always-on applica-
tions where the controller is enabled continuously and
never shut down.
The start-up of the controller’s output voltage VOUT is
controlled by the voltage on the SS pin. When the voltage
on the SS pin is less than the 0.8V internal reference, the
LTC3895 regulates the VFB voltage to the SS pin voltage
instead of the 0.8V reference. This allows the SS pin to
be used to program a soft-start by connecting an exter-
nal capacitor from the SS pin to GND. An internal 10μA
pull-up current charges this capacitor creating a voltage
ramp on the SS pin. As the SS voltage rises linearly from
0V to 0.8V (and beyond), the output voltage VOUT rises
smoothly from zero to its final value.
Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping or Forced Continuous Mode) (MODE Pin)
The LTC3895 can be enabled to enter high efficiency
Burst Mode operation, constant frequency pulse-skipping
mode, or forced continuous conduction mode at light load
currents. To select Burst Mode operation, tie the MODE
pin to GND or a voltage between 0.5V and 1.0V. To select
forced continuous operation, tie the MODE pin to INTVCC.
To select pulse-skipping mode, tie the MODE pin to a DC
voltage greater than 1.4V and less than INTVCC – 1.3V.
This can be done with a simple resistor divider off INTVCC,
with both resistors being 100k.
When the controller is enabled for Burst Mode operation,
the minimum peak current in the inductor (burst clamp) is
adjustable and can be programmed by the voltage on the
MODE pin. Tying the MODE pin to GND sets the default
burst clamp to approximately 25% of the maximum sense
voltage even when the voltage on the ITH pin indicates a
lower value. A voltage between 0.5V and 1.0V on the MODE
pin programs the burst clamp linearly between 10% and
60% of the maximum sense voltage.
In Burst Mode operation, if the average inductor current
is higher than the load current, the error amplifier, EA, will
decrease the voltage on the ITH pin. When the ITH volt-
age drops below 0.425V, the internal sleep signal goes
high (enabling sleep mode) and both external MOSFETs
are turned off. The ITH pin is then disconnected from the
output of the EA and parked at 0.450V.
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC3895 draws
to only 40μA. In sleep mode, the load current is supplied
by the output capacitor. As the output voltage decreases,
the EA’s output begins to rise. When the output voltage
drops enough, the ITH pin is reconnected to the output
of the EA, the sleep signal goes low, and the controller
resumes normal operation by turning on the top external
MOSFET on the next cycle of the internal oscillator.
When the controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator (IR) turns off the bottom external
MOSFET just before the inductor current reaches zero,
preventing it from reversing and going negative. Thus,
the controller operates discontinuously.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by
the voltage on the ITH pin, just as in normal operation.
In this mode, the efficiency at light loads is lower than in
Burst Mode operation. However, continuous operation
has the advantage of lower output voltage ripple and less
interference to audio circuitry. In forced continuous mode,
the output ripple is independent of load current.
When the MODE pin is connected for pulse-skipping mode,
the LTC3895 operates in PWM pulse-skipping mode at
light loads. In this mode, constant frequency operation
is maintained down to approximately 1% of designed
maximum output current. At very light loads, the current
comparator, ICMP, may remain tripped for several cycles
and force the external top MOSFET to stay off for the same
number of cycles (i.e., skipping pulses). The inductor cur-
rent is not allowed to reverse (discontinuous operation).
LTC3895
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This mode, like forced continuous operation, exhibits low
output ripple as well as low audio noise and reduced RF
interference as compared to Burst Mode operation. It pro-
vides higher low current efficiency than forced continuous
mode, but not nearly as high as Burst Mode operation.
At high output voltages, the efficiency in pulse-skipping
mode is comparable to force continuous mode.
If the PLLIN pin is clocked by an external clock source to
use the phase-locked loop (see Frequency Selection and
Phase-Locked Loop section), then the LTC3895 operates
in forced continuous operation when the MODE pin is
set to forced continuous or Burst Mode operation. The
controller operates in pulse-skipping mode when clocked
by an external clock source with the MODE pin set to
pulse-skipping mode.
Frequency Selection and Phase-Locked Loop (FREQ
and PLLIN Pins)
The selection of switching frequency is a trade-off between
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC3895 can be selected
using the FREQ pin.
If the PLLIN pin is not being driven by an external clock
source, the FREQ pin can be tied to GND, tied to INTVCC
or programmed through an external resistor. Tying FREQ
to GND selects 350kHz while tying FREQ to INTVCC se-
lects 535kHz. Placing a resistor between FREQ and GND
allows the frequency to be programmed between 50kHz
and 900kHz, as shown in Figure 12.
A phase-locked loop (PLL) is available on the LTC3895
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN pin. The LTC3895’s
phase detector adjusts the voltage (through an internal
lowpass filter) of the VCO input to align the turn-on of the
external top MOSFET to the rising edge of the synchroniz-
ing signal.
operaTion
The VCO input voltage is prebiased to the operating fre-
quency set by the FREQ pin before the external clock is
applied. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the rising edge of TG. The ability to
prebias the loop filter allows the PLL to lock-in rapidly
without deviating far from the desired frequency.
The typical capture range of the LTC3895’s phase-locked
loop is from approximately 55kHz to 1MHz, with a guaran-
tee to be between 75kHz and 850kHz. In other words, the
LTC3895’s PLL is guaranteed to lock to an external clock
source whose frequency is between 75kHz and 850kHz.
It is recommended that the external clock source swing
from ground (0V) to at least 2.8V.
PolyPhase
®
Applications (CLKOUT and PHASMD Pins)
The LTC3895 features two pins (CLKOUT and PHASMD)
that allow other controller ICs to be daisy-chained with
the LTC3895 in PolyPhase applications. The clock output
signal on the CLKOUT pin can be used to synchronize
additional power stages in a multiphase power supply
solution feeding a single, high current output or multiple
separate outputs. The PHASMD pin is used to adjust the
phase of the CLKOUT signal. Pulling this pin to ground
forces CLKOUT to be out of phase 90° with respect to TG.
Connecting this pin to INTVCC forces CLKOUT to be out
of phase 120° with respect to TG. Floating this pin forces
CLKOUT to be out of phase 180° with respect to TG.
Input Supply Overvoltage Lockout (OVLO Pin)
The LTC3895 implements a protection feature that inhibits
switching when the input voltage rises above a program-
mable operating range. By using a resistor divider from the
input supply to ground, the OVLO pin serves as a precise
input supply voltage monitor. Switching is disabled when
the OVLO pin rises above 1.2V, which can be configured to
limit switching to a specific range of input supply voltage.
When switching is disabled, the LTC3895 can safely sus-
tain input voltages up to the absolute maximum rating of
150V. Input supply overvoltage events trigger a soft-start
reset, which results in a graceful recovery from an input
supply transient.
LTC3895
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For more information www.linear.com/LTC3895
operaTion
Output Overvoltage Protection
An overvoltage comparator guards against transient over-
shoots as well as other more serious conditions that may
overvoltage the output. When the VFB pin rises by more
than 10% above its regulation point of 0.800V, the top
MOSFET is turned off and the bottom MOSFET is turned
on until the overvoltage condition is cleared.
Power Good Pin
The PGOOD pin is connected to an open drain of an internal
N-channel MOSFET. The MOSFET turns on and pulls the
PGOOD pin low when the VFB pin voltage is not within
±10% of the 0.8V reference voltage. The PGOOD pin is also
pulled low when the RUN pin is low (shut down). When
the VFB pin voltage is within the ±10% requirement, the
MOSFET is turned off and the pin is allowed to be pulled
up by an external resistor to a source no greater than 6V.
Foldback Current
When the output voltage falls to less than 70% of its
nominal level, foldback current limiting is activated, pro-
gressively lowering the peak current limit in proportion to
the severity of the overcurrent or short-circuit condition.
Foldback current limiting is disabled during the soft-start
interval (as long as the VFB voltage is keeping up with the
SS voltage). Foldback current limiting is intended to limit
power dissipation during overcurrent and short-circuit fault
conditions. Note that the LTC3895 continuously monitors
the inductor current and prevents current runaway under
all conditions.
Regulator Shutdown (REGSD)
High input voltage applications typically require using the
EXTVCC LDO to keep power dissipation low. Fault conditions
where the EXTVCC LDO becomes disabled (EXTVCC below
the switchover threshold) for an extended period of time
could result in overheating of the IC (or overheating the
external N-channel MOSFET if the NDRV LDO is used). In
the cases where EXTVCC is tied to the regulator output, this
event could happen during overload conditions such as an
output short to ground. The LTC3895 includes a regulator
shutdown (REGSD) feature that shuts down the regulator
to substantially reduce power dissipation and the risk of
overheating during such events.
The REGSD circuit monitors the EXTVCC LDO and the SS
pin to determine when to shut down the regulator. Refer
to the timing diagram in Figure 1. Whenever SS is above
2.2V and the EXTVCC LDO is not switched over (the EXTVCC
pin is below the switchover threshold), the internal 10μA
pull-up current on SS turns off and a 5μA pull-down cur-
rent turns on, discharging SS. Once SS discharges to 2.0V
and the EXTVCC pin remains below the EXTVCC switchover
threshold, the pull-down current reduces to 1μA and the
regulator shuts down, eliminating all DRVCC switching
current. Switching stays off until the SS pin discharges
to approximately 200mV, at which point the 10μA pull-up
current turns back on and the regulator re-enables switch-
ing. If the short-circuit persists, the regulator cycles on
and off at a low duty cycle interval of about 12%.
TG/BG
START-UP INTO
SHORT-CIRCUIT
VOUT/EXTVCC
SHORT REMOVED
FROM VOUT
ISS = 5µA
(SINK)
ISS = 10µA
(SOURCE)
ISS = 10µA
(SOURCE)
ISS = 1µA
(SINK)
EXTVCC SWITCHOVER
THRESHOLD (FALLING)
SS
3895 F01
SHORT-CIRCUIT EVENT
0V
2.2V
2.0V
0.8V
0.2V
0V
Figure 1. Regulator Shutdown Operation
LTC3895
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The Typical Application on the first page is a basic LTC3895
application circuit. LTC3895 can be configured to use
either DCR (inductor resistance) sensing or low value
resistor sensing. The choice between the two current
sensing schemes is largely a design trade-off between
cost, power consumption and accuracy. DCR sensing
is becoming popular because it saves expensive current
sensing resistors and is more power efficient, especially
in high current applications. However, current sensing
resistors provide the most accurate current limits for the
controller. Other external component selection is driven
by the load requirement, and begins with the selection of
RSENSE (if RSENSE is used) and inductor value. Next, the
power MOSFETs are selected. Finally, input and output
capacitors are selected.
Current Limit Programming
The ILIM pin is a three-state logic input which sets the
maximum current limit of the controller. When ILIM is
grounded, the maximum current limit threshold voltage of
the current comparator is programmed to be 50mV. When
ILIM is floated, the maximum current limit threshold is
75mV. When ILIM is tied to INTVCC, the maximum current
limit threshold is set to 100mV.
SENSE+ and SENSE– Pins
The SENSE+ and SENSE– pins are the inputs to the cur-
rent comparator. The common mode voltage range on
these pins is 0V to 65V (absolute maximum), enabling
the LTC3895 to regulate output voltages up to a nominal
set point of 60V (allowing margin for tolerances and tran-
sients). The SENSE+ pin is high impedance over the full
common mode range, drawing at most ±1μA. This high
impedance allows the current comparators to be used in
inductor DCR sensing. The impedance of the SENSE– pin
changes depending on the common mode voltage. When
SENSE– is less than INTVCC – 0.5V, a small current of less
than 1μA flows out of the pin. When SENSE– is above
INTVCC + 0.5V, a higher current (≈850μA) flows into the
pin. Between INTVCC – 0.5V and INTVCC + 0.5V, the current
transitions from the smaller current to the higher current.
applicaTions inForMaTion
Filter components mutual to the sense lines should be
placed close to the LTC3895, and the sense lines should
run close together to a Kelvin connection underneath the
current sense element (shown in Figure 2). Sensing cur-
rent elsewhere can effectively add parasitic inductance
and capacitance to the current sense element, degrading
the information at the sense terminals and making the
programmed current limit unpredictable. If DCR sensing
is used (Figure 3b), resistor R1 should be placed close to
the switching node, to prevent noise from coupling into
sensitive small-signal nodes.
Figure 2. Sense Lines Placement with Inductor or Sense Resistor
3895 F02
TO SENSE FILTER
NEXT TO THE CONTROLLER
INDUCTOR OR RSENSE
CURRENT FLOW
COUT
Low Value Resistor Current Sensing
A typical sensing circuit using a discrete resistor is shown
in Figure 3a. RSENSE is chosen based on the required
output current.
The current comparator has a maximum threshold
VSENSE(MAX) determined by the ILIM setting. The current
comparator threshold voltage sets the peak of the induc-
tor current, yielding a maximum average output current,
IMAX, equal to the peak value less half the peak-to-peak
ripple current, ∆IL. To calculate the sense resistor value,
use the equation:
RSENSE =
V
SENSE(MAX)
IMAX +ΔIL
2
Normally in high duty cycle conditions, the maximum
output current level will be reduced due to the internal
compensation required to meet stability criterion operating
at greater than 50% duty factor. The LTC3895, however,
uses a proprietary circuit to nullify the effect of slope
compensation on the current limit performance.
LTC3895
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For more information www.linear.com/LTC3895
applicaTions inForMaTion
Inductor DCR Sensing
For applications requiring the highest possible efficiency
at high load currents, the LTC3895 is capable of sensing
the voltage drop across the inductor DCR, as shown in
Figure 3b. The DCR of the inductor represents the small
amount of DC winding resistance of the copper, which
can be less than 1mΩ for today’s low value, high current
inductors. In a high current application requiring such
an inductor, power loss through a sense resistor would
cost several points of efficiency compared to inductor
DCR sensing.
(3a) Using a Resistor to Sense Current
(3b) Using the Inductor DCR to Sense Current
Figure 3. Current Sensing Methods
3895 F03a
LTC3895
BOOST
TG
SW
BG
GND
SENSE–
SENSE+
VIN
VOUT
RSENSE
CAP
PLACED NEAR SENSE PINS
3895 F03b
LTC3895
VIN
VOUT
C1* R2
*PLACE C1 NEAR SENSE PINS RSENSE(EQ) = DCR(R2/(R1+R2))
L DCR
INDUCTOR
R1
(R1||R2) • C1 = L/DCR
BOOST
TG
SW
BG
GND
SENSE–
SENSE+
If the external (R1||R2) • C1 time constant is chosen to be
exactly equal to the L/DCR time constant, the voltage drop
across the external capacitor is equal to the drop across
the inductor DCR multiplied by R2/(R1 + R2). R2 scales the
voltage across the sense terminals for applications where
the DCR is greater than the target sense resistor value.
To properly dimension the external filter components, the
DCR of the inductor must be known. It can be measured
using a good RLC meter, but the DCR tolerance is not
always the same and varies with temperature; consult
the manufacturers’ data sheets for detailed information.
Using the inductor ripple current value from the Inductor
Value Calculation section, the target sense resistor value is:
RSENSE(EQUIV) =
V
SENSE(MAX)
IMAX +ΔIL
2
To ensure that the application will deliver full load current
over the full operating temperature range, choose the
minimum value for VSENSE(MAX) in the Electrical Charac-
teristics table.
Next, determine the DCR of the inductor. When provided,
use the manufacturer’s maximum value, usually given at
20°C. Increase this value to account for the temperature
coefficient of copper resistance, which is approximately
0.4%/°C. A conservative value for TL(MAX) is 100°C.
To scale the maximum inductor DCR to the desired sense
resistor value (RD), use the divider ratio:
RD=
R
SENSE(EQUIV)
DCRMAX at T
L(MAX)
C1 is usually selected to be in the range of 0.1μF to 0.47μF.
This forces R1|| R2 to around 2k, reducing error that might
have been caused by the SENSE+ pin’s ±1μA current.
The equivalent resistance R1||R2 is scaled to the tempera-
ture inductance and maximum DCR:
R1||R2 =
L
(DCR at 20°C)•C1
LTC3895
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The values for R1 and R2 are:
R1=
R1||R2
RD
; R2 =
R1•R
D
1−RD
The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at the maximum input
voltage:
PLOSS R1=V
IN(MAX) −VOUT
( )
•VOUT
R1
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
sense resistors. Light load power loss can be modestly
higher with a DCR network than with a sense resistor, due
to the extra switching losses incurred through R1. However,
DCR sensing eliminates a sense resistor, reduces conduc-
tion losses and provides higher efficiency at heavy loads.
Peak efficiency is about the same with either method.
Inductor Value Calculation
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET switching and gate charge losses. In addition to
this basic trade-off, the effect of inductor value on ripple
current and low current operation must also be considered.
The inductor value has a direct effect on ripple current. The
inductor ripple current, ∆IL, decreases with higher induc-
tance or higher frequency and increases with higher VIN:
ΔIL=1
(f)(L) VOUT 1−VOUT
V
IN
⎛
⎝
⎜⎞
⎠
⎟
applicaTions inForMaTion
Accepting larger values of ∆IL allows the use of low in-
ductances, but results in higher output voltage ripple and
greater core losses. A reasonable starting point for setting
ripple current is ∆IL = 0.3(IMAX). The maximum ∆IL occurs
at the maximum input voltage.
The inductor value also has secondary effects. The tran-
sition to Burst Mode operation begins when the average
inductor current required results in a peak current below
the burst clamp, which can be programmed between 10%
and 60% of the current limit determined by RSENSE. (For
more information see the Burst Clamp Programming sec-
tion.) Lower inductor values (higher ∆IL) will cause this
to occur at lower load currents, which can cause a dip in
efficiency in the upper range of low current operation. In
Burst Mode operation, lower inductance values will cause
the burst frequency to decrease.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite or molypermalloy
cores. Actual core loss is independent of core size for a
fixed inductor value, but it is very dependent on inductance
value selected. As inductance increases, core losses go
down. Unfortunately, increased inductance requires more
turns of wire and therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
for high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates hard, which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Power MOSFET Selection
T
wo external power MOSFETs must be selected for the
LTC3895 controller: one N-channel MOSFET for the top
(main) switch, and one N-channel MOSFET for the bottom
(synchronous) switch.
LTC3895
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applicaTions inForMaTion
The peak-to-peak drive levels are set by the DRVCC volt-
age. This voltage can range from 5V to 10V depending on
configuration of the DRVSET pin. Therefore, both logic-level
and standard-level threshold MOSFETs can be used in
most applications depending on the programmed DRVCC
voltage. Pay close attention to the BVDSS specification for
the MOSFETs as well.
The LTC3895’s ability to adjust the gate drive level between
5V to 10V (OPTI-DRIVE) allows an application circuit to
be precisely optimized for efficiency. When adjusting the
gate drive level, the final arbiter is the total input current
for the regulator. If a change is made and the input cur-
rent decreases, then the efficiency has improved. If there
is no change in input current, then there is no change in
efficiency.
Selection criteria for the power MOSFETs include the
on-resistance RDS(ON), Miller capacitance CMILLER, input
voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in VDS. This result is
then multiplied by the ratio of the application applied VDS
to the gate charge curve specified VDS. When the IC is
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
M
AIN SWITCH DUTY CYCLE =
V
OUT
V
IN
SYNCHRONOUS SWITCH DUTY CYCLE =
V
IN −
V
OUT
V
IN
The MOSFET power dissipations at maximum output
current are given by:
P
MAIN =
V
OUT
V
IN
IOUT(MAX)
( )
21+ δ
( )
RDS(ON) +
(V
IN )2IOUT(MAX)
2
⎛
⎝
⎜⎞
⎠
⎟(RDR )(CMILLER )•
1
VDRVCC −VTHMIN
+1
VTHMIN
⎡
⎣
⎢⎤
⎦
⎥(f)
P
SYNC =V
IN −VOUT
V
IN
IOUT(MAX)
( )
21+ δ
( )
RDS(ON)
where δ is the temperature dependency of RDS(ON) and
RDR (approximately 2Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. VTHMIN is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I2R losses while the main N-channel
equations include an additional term for transition losses,
which are highest at high input voltages. For VIN < 20V
the high current efficiency generally improves with larger
MOSFETs, while for VIN > 20V the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CMILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
The term (1+ δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
CIN and COUT Selection
The selection of CIN is usually based off the worst-case RMS
input current. The highest (VOUT)(IOUT) product needs to
be used in the formula shown in Equation 1 to determine
the maximum RMS capacitor current requirement.
LTC3895
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In continuous mode, the source current of the top MOSFET
is a square wave of duty cycle (VOUT)/(VIN). To prevent
large voltage transients, a low ESR capacitor sized for the
maximum RMS current must be used. The maximum RMS
capacitor current is given by:
CIN Required IRMS ≈
I
MAX
V
IN
(VOUT )(V
IN −VOUT )
[ ]
1/2
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that capacitor manufacturers’ ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3895, ceramic capacitors
can also be used for CIN. Always consult the manufacturer
if there is any question.
A small (0.1μF to 1μF) bypass capacitor between the chip
VIN pin and ground, placed close to the LTC3895, is also
suggested. A small (≤10Ω) resistor placed between CIN
(C1) and the VIN pin provides further isolation.
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (∆VOUT) is approximated by:
ΔVOUT ≈ ΔILESR+1
8•f•COUT
⎛
⎝
⎜⎞
⎠
⎟
where f is the operating frequency, COUT is the output
capacitance and ∆IL is the ripple current in the inductor.
The output ripple is highest at maximum input voltage
since ∆IL increases with input voltage.
applicaTions inForMaTion
Setting Output Voltage
The LTC3895 output voltage is set by an external feed-
back resistor divider carefully placed across the output,
as shown in Figure 4a. The regulated output voltage is
determined by:
VOUT =0.8V 1+RB
RA
⎛
⎝
⎜⎞
⎠
⎟
To improve the frequency response, a feedforward ca-
pacitor, CFF, may be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line.
The LTC3895 also has the option to be programmed to
a fixed 5V or 3.3V output through control of the VPRG
pin. Figure 4b shows how the VFB pin is used to sense
the output voltage in fixed output mode. Tying VPRG to
INTVCC or GND programs VOUT to 5V or 3.3V, respectively.
Floating VPRG sets VOUT to adjustable output mode using
external resistors.
3895 F04a
LTC3895
VFB
RBCFF
RA
VOUT
3895 F04b
LTC3895
VFB
VPRG
INTVCC/GND
COUT
VOUT
5V/3.3V
(4a) Setting Adjustable Output Voltage
(4b) Setting Output to Fixed 5V/3.3V Voltage
Figure 4. Setting Output Voltage
LTC3895
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applicaTions inForMaTion
Figure 5. Adjustable UV and OV Lockout
RUN Pin and Overvoltage/Undervoltage Lockout
The LTC3895 is enabled using the RUN pin. It has a rising
threshold of 1.2V with 80mV of hysteresis. Pulling the RUN
pin below 1.12V shuts down the main control loop. Pull-
ing it below 0.7V disables the controller and most internal
circuits, including the DRVCC and INTVCC LDOs. In this
state the LTC3895 draws only 10μA of quiescent current.
The RUN pin is high impedance below 3V and must be
externally pulled up/down or driven directly by logic. The
RUN pin can tolerate up to 150V (absolute maximum), so
it can be conveniently tied to VIN in always-on applications
where the controller is enabled continuously and never
shut down. Above 3V, the RUN pin has approximately a
15MΩ impedance to an internal 3V clamp.
The RUN and OVLO pins can alternatively be configured as
undervoltage (UVLO) and overvoltage (OVLO) lockouts on
the VIN supply with a resistor divider from VIN to ground.
A simple resistor divider can be used as shown in Figure
5 to meet specific VIN voltage requirements.
RUN
3895 F05
R3
VIN
LTC3895
R4
R5
OVLO
The individual values of R3, R4 and R5 can be calculated
from the following equations:
R5 =RTOTAL •
1.20V
RISING V
IN OVLO THRESHOLD
R4 =RTOTAL •1.20V
RISING V
IN OVLO THRESHOLD −R5
R3 =RTOTAL −R5−R4
For applications that do not require a precise OVLO, the
OVLO pin can be tied directly to ground. The RUN pin in
this type of application can be used as an external UVLO
using the previous equations with R5 = 0Ω.
Similarly, for applications that do not require a precise
UVLO, the RUN pin can be tied to VIN. In this configura-
tion, the UVLO threshold is limited to the internal DRVCC
UVLO thresholds as shown in the Electrical Characteristics
table. The resistor values for the OVLO can be computed
using the previous equations with R3 = 0Ω.
Soft-Start (SS) Pin
The start-up of VOUT is controlled by the voltage on the
SS pin. When the voltage on the SS pin is less than the
internal 0.8V reference, the LTC3895 regulates the VFB pin
voltage to the voltage on the SS pin instead of the internal
reference. The SS pin can be used to program an external
soft-start function.
Soft-start is enabled by simply connecting a capacitor from
the SS pin to ground, as shown in Figure 6. An internal
10μA current source charges the capacitor, providing a
linear ramping voltage at the SS pin. The LTC3895 will
regulate its feedback voltage (and hence VOUT) according
to the voltage on the SS pin, allowing VOUT to rise smoothly
from 0V to its final regulated value. The total soft-start
time will be approximately:
tSS =CSS •
0.8V
10µA
The current that flows through the R3-R4-R5 divider will
directly add to the shutdown, sleep, and active current of
the LTC3895, and care should be taken to minimize the
impact of this current on the overall efficiency of the ap-
plication circuit. Resistor values in the megaohm range
may be required to keep the impact on quiescent shutdown
and sleep currents low. To pick resistor values, the sum
total of R3 + R3+ R5 (RTOTAL) should be chosen first based
on the allowable DC current that can be drawn from VIN.
LTC3895
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The SS pin also controls the timing of the regulator
shutdown (REGSD) feature (as discussed in Regulator
Shutdown of the Operation section). If the application does
not require the use of the EXTVCC LDO (the EXTVCC pin
is grounded), the REGSD feature must be defeated with
a pull-up resistor between SS and INTVCC, as shown in
Figure 7. Any resistor 330k or smaller between SS and
INTVCC defeats the 5μA pull-down current on SS that
turns on once SS reaches 2.2V (with the EXTVCC LDO
not enabled), preventing SS from discharging to 2.0V
and shutting down the regulator. Note the current through
this pull-up resistor adds to the internal 10μA SS pull-up
current at start-up, causing the total soft-start time to
be shorter than what it is calculated without the pull-up
resistor. The total soft-start time with the pull-up resistor
is approximately:
tSS ≈CSS •
0.8V
10µA +4.6V
RSS
⎛
⎝
⎜⎞
⎠
⎟
where RSS is the value of the resistor between the SS and
INTVCC pins.
applicaTions inForMaTion
Figure 6. Using the SS Pin to Program Soft-Start
3895 F06
LTC3895
SS
GND
CSS
Figure 7. Using the SS Pin to Program Soft-Start
with EXTVCC Unused/Grounded to Defeat REGSD
3895 F07
LTC3895
SS
GND
INTVCC
EXTVCC
CSS
RSS
DRVCC Regulators (OPTI-DRIVE)
The LTC3895 features three separate low dropout linear
regulators (LDO) that can supply power at the DRVCC pin.
The internal VIN LDO uses an internal P-channel pass device
between the VIN and DRVCC pins. The internal EXTVCC LDO
uses an internal P-channel pass device between the EXTVCC
and DRVCC pins. The NDRV LDO utilizes the NDRV pin to
drive the gate of an external N-channel MOSFET acting as
a linear regulator with its drain connected to VIN.
The NDRV LDO provides an alternative method to supply
power to DRVCC from the input supply without dissipating
the power inside the LTC3895 IC. It has an internal charge
pump that allows NDRV to be driven above the VIN sup-
ply, allowing for low dropout performance. The VIN LDO
has a slightly lower regulation point than the NDRV LDO,
such that all DRVCC current flows through the external N-
channel MOSFET (and not through the internal P-channel
pass device) once DRVCC reaches regulation.
When laying out the PC board, care should be taken to
route NDRV away from any switching nodes, especially
SW, TG, and BOOST. Coupling to the NDRV node could
cause its voltage to collapse and the NDRV LDO to lose
regulation. If this occurs, the internal VIN LDO would
take over and maintain DRVCC voltage at a slightly lower
regulation point. However, internal heating of the IC would
become a concern. High frequency noise on the drain of
the external NFET could also couple into the NDRV node
(through the gate-to-drain capacitance of the NDRV NFET)
and adversely affect NDRV regulation. The following are
methods that could mitigate this potential issue (refer to
Figure 8a).
1. Add local decoupling capacitors right next to the drain
of the external NDRV NFET in the PCB layout.
2. Insert a resistor (~100Ω) in series with the gate of the
NDRV NFET.
3. Insert a small capacitor (~1nF) between the gate and
source of the NDRV NFET.
When testing the application circuit, be sure the NDRV
voltage does not collapse over the entire input voltage
and output current operating range of the buck regulator.
LTC3895
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applicaTions inForMaTion
3895 F08a
LTC3895
C2*
C1*
R1*
*R1, C1 AND C2 ARE OPTIONAL
VIN
VIN
DRVCC
GND
NDRV
3895 F08b
LTC3895
VIN
VIN
DRVCC
GND
NDRV
Figure 8a. Configuring the NDRV LDO
Figure 8b. Disabling the NDRV LDO
If the NDRV LDO is not being used, connect the NDRV pin
to DRVCC (Figure 8b).
The DRVCC supply is regulated between 5V to 10V, de-
pending on how the DRVSET pin is set. The internal VIN
and EXTVCC LDOs can supply a peak current of at least
50mA. The DRVCC pin must be bypassed to ground with
a minimum of 4.7μF ceramic capacitor. Good bypassing
is needed to supply the high transient currents required
by the MOSFET gate drivers.
The DRVSET pin programs the DRVCC supply voltage and
the DRVUV pin selects different DRVCC UVLO and EXTVCC
switchover threshold voltages. Table 1a summarizes the
different DRVSET pin configurations along with the volt-
age settings that go with each configuration. Table 1b
summarizes the different DRVUV pin settings. Tying the
DRVSET pin to INTVCC programs DRVCC to 10V. Tying the
DRVSET pin to GND programs DRVCC to 6V. Placing a 50k
to 100k resistor between DRVSET and GND the programs
DRVCC between 5V to 10V, as shown in Figure 9.
Table 1a.
DRVSET PIN DRVCC VOLTAGE
GND 6V
INTVCC 10V
Resistor to GND 50k to 100k 5V to 10V
Table 1b.
DRVUV
DRVCC UVLO
RISING/FALLING
THRESHOLDS
EXTVCC SWITCHOVER
RISING/FALLING
THRESHOLD
GND 4.0V/3.8V 4.7V/4.45V
INTVCC 7.5V/6.7V 7.7V/7.45V
NDRV LDO
or EXTV
CC
LDO
INTERNAL VIN LDO
DRVSET PIN RESISTOR (kΩ)
50
55
60
65
70
75
80
85
90
95
100
105
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
DRV
CC
VOLTAGE (V)
3895 F09
Figure 9. Relationship Between DRVCC Voltage
and Resistor Value at DRVSET Pin
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC3895 to be
exceeded. The DRVCC current, which is dominated by the
gate charge current, may be supplied by the VIN LDO,
NDRV LDO or the EXTVCC LDO. When the voltage on the
EXTVCC pin is less than its switchover threshold (4.7V or
7.7V as determined by the DRVUV pin described above),
the VIN and NDRV LDOs are enabled. Power dissipation
in this case is highest and is equal to VIN • IDRVCC. If the
NDRV LDO is not being used, this power is dissipated
inside the IC. The gate charge current is dependent on
operating frequency as discussed in the Efficiency Con-
siderations section.
LTC3895
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The junction temperature can be estimated by using the
equations given in Note 2 of the Electrical Characteristics.
For example, if DRVCC is set to 6V, the DRVCC current is
limited to less than 49mA from a 40V supply when not using
the EXTVCC or NDRV LDOs at a 70°C ambient temperature:
TJ = 70°C + (49mA)(40V)(28°C/W) = 125°C
To prevent the maximum junction temperature from being
exceeded, the VIN supply current must be checked while
operating in forced continuous mode (MODE = INTVCC)
at maximum VIN.
When the voltage applied to EXTVCC rises above its swi-
tchover threshold, the VIN and NDRV LDOs are turned off
and the EXTVCC LDO is enabled. The EXTVCC LDO remains
on as long as the voltage applied to EXTVCC remains above
the switchover threshold minus the comparator hysteresis.
The EXTVCC LDO attempts to regulate the DRVCC voltage to
the voltage as programmed by the DRVSET pin, so while
EXTVCC is less than this voltage, the LDO is in dropout
and the DRVCC voltage is approximately equal to EXTVCC.
When EXTVCC is greater than the programmed voltage,
up to an absolute maximum of 14V, DRVCC is regulated
to the programmed voltage.
Using the EXTVCC LDO allows the MOSFET driver and
control power to be derived from the LTC3895’s switch-
ing regulator output (4.7V/7.7V ≤ VOUT ≤ 14V) during
normal operation and from the VIN or NDRV LDO when the
output is out of regulation (e.g., start-up, short-circuit).
If more current is required through the EXTVCC LDO than
is specified, an external Schottky diode can be added
between the EXTVCC and DRVCC pins. In this case, do not
apply more than 10V to the EXTVCC pin and make sure
that EXTVCC ≤ VIN.
Significant efficiency and thermal gains can be realized
by powering DRVCC from the output, since the VIN cur-
rent resulting from the driver and control currents will be
scaled by a factor of (Duty Cycle)/(Switcher Efficiency).
For 5V to 14V regulator outputs, this means connecting
the EXTVCC pin directly to VOUT. Tying the EXTVCC pin to
an 8.5V supply reduces the junction temperature in the
previous example from 125°C to:
TJ = 70°C + (49mA)(8.5V)(28°C/W) = 82°C
However, for 3.3V and other low voltage outputs, addi-
tional circuitry is required to derive DRVCC power from
the output.
The following list summarizes the five possible connec-
tions for EXTVCC:
1. EXTVCC grounded. This will cause DRVCC to be pow-
ered from the internal VIN or NDRV LDO resulting in
an efficiency penalty of up to 10% at high input volt-
ages. If EXTVCC is grounded, the REGSD feature must
be defeated with a pull-up resistor 330k or smaller
between SS and INTVCC.
2. EXTVCC connected directly to the regulator output. This
is the normal connection for a 5V to 14V regulator and
provides the highest efficiency.
3. EXTVCC connected to an external supply. If an external
supply is available in the 5V to 14V range, it may be
used to power EXTVCC providing it is compatible with
the MOSFET gate drive requirements. Ensure that
EXTVCC ≤ VIN.
4. EXTVCC connected to the regulator output through an
external zener diode. If the output voltage is greater
than 14V, a zener diode can be used to drop the
necessary voltage between VOUT and EXTVCC such
that EXTVCC remains below 14V (Figure 10). In this
configuration, a bypass capacitor on EXTVCC of at least
0.1μF is recommended. An optional resistor between
EXTVCC and GND can be inserted to ensure adequate
bias current through the zener diode.
3895 F10
LTC3895
VOUT > 14V
EXTVCC
GND
EXTVCC < 14V
0.1µF
Figure 10. Using a Zener Diode Between VOUT and EXTVCC
LTC3895
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5. EXTVCC connected to an output-derived boost network
off the regulator output. For 3.3V and other low volt-
age regulators, efficiency gains can still be realized by
connecting EXTVCC to an output-derived voltage that
has been boosted to greater than 4.7V/7.7V. Ensure
that EXTVCC ≤ VIN.
INTVCC Regulator
An additional P-channel LDO supplies power at the INTVCC
pin from the DRVCC pin. Whereas DRVCC powers the gate
drivers, INTVCC powers much of the LTC3895’s internal
circuitry. The INTVCC supply must be bypassed with a
0.1μF ceramic capacitor. INTVCC is also used as a pull-up
to bias other pins, such as MODE, ILIM, VPRG, etc.
Topside MOSFET Driver Supply (CB)
An external bootstrap capacitor CB connected to the BOOST
pin supplies the gate drive voltage for the topside MOSFET.
The LTC3895 features an internal switch between DRVCC
and the BOOST pin. This internal switch eliminates the
need for an external bootstrap diode between DRVCC and
BOOST. Capacitor CB in the Functional Diagram is charged
through this internal switch from DRVCC when the SW
pin is low. When the topside MOSFET is to be turned on,
the driver places the CB voltage across the gate-source
of the MOSFET. This enhances the top MOSFET switch
and turns it on. The switch node voltage, SW, rises to VIN
and the BOOST pin follows. With the topside MOSFET on,
the BOOST voltage is above the input supply: VBOOST =
VIN + VDRVCC. The value of the boost capacitor, CB, needs
to be 100 times that of the total input capacitance of the
topside MOSFET(s).
Burst Clamp Programming
Burst Mode operation is enabled if the voltage on the
MODE pin is 0V or in the range between 0.5V to 1V. The
burst clamp, which sets the minimum peak inductor cur-
rent, can be programmed by the MODE pin voltage. If
the MODE pin is grounded, the burst clamp is set to 25%
of the maximum sense voltage (VSENSE(MAX)). A MODE
applicaTions inForMaTion
pin voltage between 0.5V and 1V varies the burst clamp
linearly between 10% and 60% of VSENSE(MAX) through
the following equation:
BURST CLAMP =
V
MODE −
0.4V
1V
•100
where VMODE is the voltage on the MODE pin and Burst
Clamp is the percentage of VSENSE(MAX). The burst clamp
level is determined by the desired amount of output voltage
ripple at low output loads. As the burst clamp increases,
the sleep time between pulses and the output voltage
ripple increase.
The MODE pin is high impedance and VMODE can be set
by a resistor divider from the INTVCC pin (Figure 11a).
Alternatively, the MODE pin can be tied directly to the
VFB pin to set the burst clamp to 40% (VMODE = 0.8V),
or through an additional divider resistor (R3). As shown
in Figure 11b, this resistor can be placed below VFB to
program the burst clamp between 10% and 40% (VMODE
= 0.5V to 0.8V) or above VFB to program the burst clamp
between 40% and 60% (VMODE = 0.8V to 1.0V).
BURST CLAMP = 10% TO 60%
3895 F11a
LTC3895 R2
R1
INTVCC
MODE
(11a) Using INTVCC to Program the Burst Clamp
BURST CLAMP = 10% TO 40%
VOUT
LTC3895 R3
R1
VFB
MODE
R2
BURST CLAMP = 40% TO 60%
VOUT
3895 F11b
LTC3895 R2
R1
VFB
MODE
R3
(11b) Using VFB to Program the Burst Clamp
Figure 11. Programming the Burst Clamp
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Fault Conditions: Current Limit and Current Foldback
The LTC3895 includes current foldback to help limit
load current when the output is shorted to ground. If
the output voltage falls below 70% of its nominal output
level, then the maximum sense voltage is progressively
lowered from 100% to 40% of its maximum selected
value. Under short-circuit conditions with very low duty
cycles, the LTC3895 will begin cycle skipping in order to
limit the short-circuit current. In this situation the bottom
MOSFET will be dissipating most of the power but less
than in normal operation. The short-circuit ripple current
is determined by the minimum on-time, tON(MIN), of the
LTC3895 (≈80ns), the input voltage and inductor value:
ΔIL(SC) =tON(MIN)
V
IN
L
⎛
⎝
⎜⎞
⎠
⎟
The resulting average short-circuit current is:
ISC =45% •ILIM(MAX) −
1
2
ΔIL(SC)
Fault Conditions: Overvoltage Protection (Crowbar)
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes huge
currents to flow, that blow the fuse to protect against a
shorted top MOSFET if the short occurs while the control-
ler is operating.
A comparator monitors the output for overvoltage condi-
tions. The comparator detects faults greater than 10%
above the nominal output voltage. When this condition
is sensed, the top MOSFET is turned off and the bottom
MOSFET is turned on until the overvoltage condition is
cleared. The bottom MOSFET remains on continuously for
as long as the overvoltage condition persists; if VOUT returns
to a safe level, normal operation automatically resumes.
A shorted top MOSFET will result in a high current condition
which will open the system fuse. The switching regulator
will regulate properly with a leaky top MOSFET by altering
the duty cycle to accommodate the leakage.
Fault Conditions: Overtemperature Protection
At higher temperatures, or in cases where the internal
power dissipation causes excessive self heating on chip,
the overtemperature shutdown circuitry will shut down
the LTC3895. When the junction temperature exceeds ap-
proximately 175°C, the overtemperature circuitry disables
the DRVCC LDO, causing the DRVCC supply to collapse and
effectively shutting down the entire LTC3895 chip. Once
the junction temperature drops back to the approximately
155°C, the DRVCC LDO turns back on. Long term over-
stress (TJ > 125°C) should be avoided as it can degrade
the performance or shorten the life of the part.
Phase-Locked Loop and Frequency Synchronization
The LTC3895 has an internal phase-locked loop (PLL)
comprised of a phase frequency detector, a lowpass filter,
and a voltage-controlled oscillator (VCO). This allows
the turn-on of the top MOSFET to be locked to the rising
edge of an external clock signal applied to the PLLIN pin.
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
If the external clock frequency is greater than the inter-
nal oscillator’s frequency, fOSC, then current is sourced
continuously from the phase detector output, pulling up
the VCO input. When the external clock frequency is less
than fOSC, current is sunk continuously, pulling down the
VCO input.
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If the external and internal frequencies are the same but
exhibit a phase difference, the current sources turn on for
an amount of time corresponding to the phase difference.
The voltage at the VCO input is adjusted until the phase
and frequency of the internal and external oscillators are
identical. At the stable operating point, the phase detector
output is high impedance and the internal filter capacitor,
CLP, holds the voltage at the VCO input.
Note that the LTC3895 can only be synchronized to an
external clock whose frequency is within range of the
LTC3895’s internal VCO, which is nominally 55kHz to 1MHz.
This is guaranteed to be between 75kHz and 850kHz. The
LTC3895 is guaranteed to synchronize to an external clock
that swings up to at least 2.8V and down to 0.5V or less.
Rapid phase-locking can be achieved by using the FREQ
pin to set a free-running frequency near the desired
synchronization frequency. The VCO’s input voltage is
prebiased at a frequency corresponding to the frequency
set by the FREQ pin. Once prebiased, the PLL only needs
to adjust the frequency slightly to achieve phase lock and
synchronization. Although it is not required that the free-
running frequency be near the external clock frequency,
doing so will prevent the operating frequency from passing
through a large range of frequencies as the PLL locks.
Table 2 summarizes the different states in which the FREQ
pin can be used. When synchronized to an external clock,
the LTC3895 operates in forced continuous mode at light
loads if the MODE pin is set to Burst Mode operation or
forced continuous operation. If the MODE pin is set to
pulse-skipping operation, the LTC3895 maintains pulse-
skipping operation when synchronized.
Table 2.
FREQ PIN PLLIN PIN FREQUENCY
0V DC Voltage 350kHz
INTVCC DC Voltage 535kHz
Resistor to GND DC Voltage 50kHz to 900kHz
Any of the Above External Clock
75kHz to 850kHz
Phase Locked to
External Clock
Minimum On-Time Considerations
Minimum on-time tON(MIN) is the smallest time duration
that the LTC3895 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
tON(MIN) <
V
OUT
V
IN(f)
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC3895 is approximately
80ns. However, as the peak sense voltage decreases
the minimum on-time gradually increases up to about
130ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a significant amount of cycle skipping can occur
with correspondingly larger current and voltage ripple.
FREQ PIN RESISTOR (kΩ)
15
FREQUENCY (kHz)
600
800
1000
35 45 5525
3895 F12
400
200
500
700
900
300
100
065 75 85 95 105 115 125
Figure 12. Relationship Between Oscillator Frequency
and Resistor Value at the FREQ Pin
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Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3895 circuits: 1) IC VIN current, 2) DRVCC
regulator current, 3) I2R losses, 4) Topside MOSFET
transition losses.
1. The VIN current is the DC supply current given in the
Electrical Characteristics table, which excludes MOS-
FET driver and control currents. VIN current typically
results in a small (< 0.1%) loss.
2. DRVCC current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched
from low to high to low again, a packet of charge, dQ,
moves from DRVCC to ground. The resulting dQ/dt is
a current out of DRVCC that is typically much larger
than the control circuit current. In continuous mode,
IGATECHG = f(QT + QB), where QT and QB are the gate
charges of the topside and bottom side MOSFETs.
Supplying DRVCC from an output-derived source
power through EXTVCC will scale the VIN current re-
quired for the driver and control circuits by a factor
of (Duty Cycle)/(Efficiency). For example, in a 20V
to 5V application, 10mA of DRVCC current results in
approximately 2.5mA of VIN current. This reduces the
midcurrent loss from 10% or more (if the driver was
powered directly from VIN) to only a few percent.
3. I2R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resis-
tor and input and output capacitor ESR. In continuous
mode the average output current flows through L and
RSENSE, but is chopped between the topside MOSFET
and the synchronous MOSFET. If the two MOSFETs
have approximately the same RDS(ON), then the resis-
tance of one MOSFET can simply be summed with the
resistances of L, RSENSE and ESR to obtain I2R losses.
For example, if each RDS(ON) = 30mΩ, RL = 50mΩ,
RSENSE = 10mΩ and RESR = 40mΩ (sum of both
input and output capacitance losses), then the total
resistance is 130mΩ. This results in losses ranging
from 3% to 13% as the output current increases from
1A to 5A for a 5V output, or a 4% to 20% loss for a
3.3V output. Efficiency varies as the inverse square
of VOUT for the same external components and output
power level. The combined effects of increasingly
lower output voltages and higher currents required
by high performance digital systems is not doubling
but quadrupling the importance of loss terms in the
switching regulator system!
4. Transition losses apply only to the top MOSFET(s) and
become significant only when operating at high input
voltages (typically 20V or greater). Transition losses
can be estimated from:
Transition Loss = (1.7) • VIN2 • IO(MAX) • CRSS • f
Other hidden losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these system level losses during the
design phase. The internal battery and fuse resistance
losses can be minimized by making sure that CIN has ad-
equate charge storage and very low ESR at the switching
frequency. A 25W supply will typically require a minimum of
20μF to 40μF of capacitance having a maximum of 20mΩ
to 50mΩ of ESR. Other losses including Schottky conduc-
tion losses during dead-time and inductor core losses
generally account for less than 2% total additional loss.
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Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by an
amount equal to ∆ILOAD (ESR), where ESR is the effective
series resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery
time VOUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. OPTI-
LOOP compensation allows the transient response to be
optimized over a wide range of output capacitance and
ESR values. The availability of the ITH pin not only allows
optimization of control loop behavior, but it also provides
a DC coupled and AC filtered closed-loop response test
point. The DC step, rise time and settling at this test
point truly reflects the closed-loop response. Assuming
a predominantly second order system, phase margin and/
or damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The ITH
external components shown in the first page circuit will
provide an adequate starting point for most applications.
The ITH series RC-CC filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
to optimize transient response once the final PC layout is
done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selected because the various types and values determine
the loop gain and phase. An output current pulse of 20%
to 80% of full-load current having a rise time of 1μs to
10μs will produce output voltage and ITH pin waveforms
applicaTions inForMaTion
that will give a sense of the overall loop stability without
breaking the feedback loop.
Placing a power MOSFET directly across the output ca-
pacitor and driving the gate with an appropriate signal
generator is a practical way to produce a realistic load step
condition. The initial output voltage step resulting from
the step change in output current may not be within the
bandwidth of the feedback loop, so this signal cannot be
used to determine phase margin. This is why it is better
to look at the ITH pin signal which is in the feedback loop
and is the filtered and compensated control loop response.
The gain of the loop will be increased by increasing RC
and the bandwidth of the loop will be increased by de-
creasing CC. If RC is increased by the same factor that CC
is decreased, the zero frequency will be kept the same,
thereby keeping the phase shift the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual overall
supply performance.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • CLOAD. Thus a 10μF capacitor would
require a 250μs rise time, limiting the charging current
to about 200mA.
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Design Example
As a design example, assume VIN = 12V (nominal), VIN =
22V (max), VOUT = 3.3V, IMAX = 5A, VSENSE(MAX) = 75mV
and f = 350kHz. The inductance value is chosen first based
on a 30% ripple current assumption. The highest value
of ripple current occurs at the maximum input voltage.
Tie the FREQ pin to GND, generating 350kHz operation.
The inductor ripple current can be calculated from the
following equation:
ΔIL=VOUT
(f)(L) 1−VOUT
V
IN(NOM)
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
A 4.7μH inductor will produce 29% ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 5.73A. Increasing the ripple
current will also help ensure that the minimum on-time
of 80ns is not violated. The minimum on-time occurs at
maximum VIN:
tON(MIN) =
V
OUT
V
IN(MAX)(f) =
3.3V
22V(350kHz) =429ns
The equivalent RSENSE resistor value can be calculated by
using the minimum value for the maximum current sense
threshold (66mV):
RSENSE ≤
66mV
5.73A
0.01Ω
Choosing 1% resistors: RA = 24.9k and RB = 78.7k yields
an output voltage of 3.33V.
The power dissipation on the topside MOSFET can be
easily estimated. Choosing a Fairchild FDS6982S dual
MOSFET results in: RDS(ON) = 0.035Ω/0.022Ω, CMILLER
= 215pF. With 6V gate drive and maximum input voltage
with T(estimated) = 50°C:
P
MAIN =
3.3V
22V (5A)21+(0.005)(50°C−25°C
[ ]
(0.035Ω)+(22V)25A
2(2.5Ω)(215pF) •
1
6V −2.3V +1
2.3V
⎡
⎣
⎢⎤
⎦
⎥(350kHz) =308mW
A short-circuit to ground will result in a folded back cur-
rent of:
ISC =34mV
0.01Ω−1
2
80ns(22V)
4.7µH
⎛
⎝
⎜⎞
⎠
⎟=3.21A
with a typical value of RDS(ON) and δ = (0.005/°C)(25°C)
= 0.125. The resulting power dissipated in the bottom
MOSFET is:
PSYNC = (3.21A)2 (1.125) (0.022Ω) = 255mW
which is less than under full-load conditions. CIN is chosen
for an RMS current rating of at least 3A at temperature.
COUT is chosen with an ESR of 0.02Ω for low output ripple.
The output ripple in continuous mode will be highest at
the maximum input voltage. The output voltage ripple due
to ESR is approximately:
VORIPPLE = RESR (∆IL) = 0.02Ω (1.45A) = 29mVP-P
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC.
1. Are the signal and power grounds kept separate?
The combined IC signal ground pin and the ground
return of CDRVCC must return to the combined COUT
(–) terminals. The path formed by the top N-channel
MOSFET, bottom N-channel MOSFET and the CIN ca-
pacitor should have short leads and PC trace lengths.
The output capacitor (–) terminals should be connected
as close as possible to the (–) terminals of the input
capacitor by placing the capacitors next to each other.
2. Does the LTC3895 VFB pin’s resistive divider connect
to the (+) terminal of COUT? The resistive divider must
be connected between the (+) terminal of COUT and
signal ground. The feedback resistor connections
should not be along the high current input feeds from
the input capacitor(s).
3. Are the SENSE– and SENSE+ leads routed together
with minimum PC trace spacing? The filter capacitor
between SENSE+ and SENSE– should be as close as
possible to the IC. Ensure accurate current sensing
with Kelvin connections at the SENSE resistor.
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4. Is the DRVCC and decoupling capacitor connected close
to the IC, between the DRVCC and the ground pin? This
capacitor carries the MOSFET drivers’ current peaks.
5. Keep the SW, TG, and BOOST nodes away from sensi-
tive small-signal nodes. All of these nodes have very
large and fast moving signals and therefore should be
kept on the output side of the LTC3895 and occupy
minimum PC trace area.
6. Use a modified star ground technique: a low impedance,
large copper area central grounding point on the same
side of the PC board as the input and output capacitors
with tie-ins for the bottom of the DRVCC decoupling
capacitor, the bottom of the voltage feedback resistive
divider and the GND pin of the IC.
PC Board Layout Debugging
It is helpful to use a DC-50MHz current probe to monitor
the current in the inductor while testing the circuit. Monitor
the output switching node (SW pin) to synchronize the
oscilloscope to the internal oscillator and probe the actual
output voltage as well. Check for proper performance over
the operating voltage and current range expected in the
application. The frequency of operation should be main-
tained over the input voltage range down to dropout and
until the output load drops below the low current opera-
tion threshold—typically 25% of the maximum designed
current level in Burst Mode operation.
The duty cycle percentage should be maintained from cycle
to cycle in a well-designed, low noise PCB implementation.
Variation in the duty cycle at a subharmonic rate can sug-
gest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
applicaTions inForMaTion
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required.
Reduce VIN from its nominal level to verify operation of
the regulator in dropout. Check the operation of the un-
dervoltage lockout circuit by further lowering VIN while
monitoring the output to verify operation.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between CIN, the top MOSFET and
the bottom MOSFET to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
GND pin of the IC.
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still
be maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
LTC3895
32
3895fa
For more information www.linear.com/LTC3895
Typical applicaTions
High Efficiency 140V to 3.3V Step-Down Converter
470µF
C
OUTA
100µF
C
OUTB
R
SENSE
3mΩ
MBOT
C
B
0.1µF
L1
3.3µH
C
SNS
1nF
C
ITHA
6.8nF
C
ITHB
100pF
C
SS
0.1µF
C
INTV
CC
0.1µF
R
PGOOD
100k
C
DRV
CC
4.7µF
100µF
C
INA
0.47µF
C
INB
R
ITH
4.99k
MNDRV
R
FREQ
34k
R
B
267k
R
A
196k
L2
470µH
3895 TA02
4.7µF
C
OUT2
0.47µF
C
INC
V
IN
INTV
CC
CPUMP_EN
DRVSET
DRVUV
ITH
SS
GND
LTC3895
TG
SW
BG
SENSE+
SENSE–
EXTV
CC
V
FB
BOOST
NDRV
DRV
CC
V
IN
12V to 140V
V
OUT
3.3V
10A
OVLO
PHASMD
PLLIN
PGOOD
VPRG
ILIM
CLKOUT
GND
RUN
FREQ
GND
GND
MTOP, MBOT: BSC520N15NS3G
MNDRV: IPD320N20N3
L1: WURTH 7443310330
C
OUTA
: KEMET T520D477M0O6A1E015
L2: COILCRAFT MSS1048T-474KLB
MTOP
x2
x3
MODE
PINS NOT USED IN THIS CIRCUIT
V
IN
LTC3639
RUN
OVLO
ISET
FBO
GND
GND
GND
SW
V
FB
VPRG1
VPRG2
SS
x2
Efficiency and Power Loss
vs Load Current Efficiency vs Load Current Efficiency vs Input Voltage
BURST EFFICIENCY
V
IN
= 24V
V
OUT
= 3.3V
PULSE–SKIPPING
EFFICIENCY
PS LOSS
FCM LOSS
FCM
EFFICIENCY
BURST LOSS
LOAD CURRENT (A)
0.0001
0.001
0.01
0.1
1
10
0
10
20
30
40
50
60
70
80
90
100
1
10
100
1k
10k
100k
EFFICIENCY (%)
POWER LOSS (mW)
3895 TA02b
V
OUT
= 3.3V
V
IN
= 12V
V
IN
= 24V
V
IN
= 48V
V
IN
= 100V
V
IN
= 140V
LOAD CURRENT (A)
0.0001
0.001
0.01
0.1
1
10
0
10
20
30
40
50
60
70
80
90
100
EFFICIENCY (%)
3895 TA02c
V
OUT
= 3.3V
M
BOT
: BSC190N15NS3G, I
LOAD
= 5A
M
BOT
: BSC190N15NS3G, I
LOAD
= 10A
M
BOT
: BSC520N15NS3G, I
LOAD
= 5A
M
BOT
: BSC520N15NS3G, I
LOAD
= 10A
INPUT VOLTAGE (V)
0
20
40
60
80
100
120
140
50
55
60
65
70
75
80
85
90
EFFICIENCY (%)
3895 TA02d
LTC3895
33
3895fa
For more information www.linear.com/LTC3895
Typical applicaTions
High Efficiency Switching Surge Stopper
39µF
C
OUTA
22µF
C
OUTB
R
SENSE
6mΩ
MBOT
MTOP
C
B
0.1µF
L1
15µH
C
SNS
1nF
C
ITHA
4.7nF
C
ITHB
100pF
C
SS
0.1µF
C
INTV
CC
0.1µF
C
DRV
CC
4.7µF
100µF
C
INA
0.47µF
C
INB
R
ITH
10k
MNDRV
R
FREQ
42.2k
R
OVLOB
1M
R
OVLOA
34.9k
R
SS
100k
C
OVLO
3.3µF
R
A
46.4k
R
B
1M
R
OVLOC
1M
V
IN
INTV
CC
CPUMP_EN
DRVSET
DRVUV
ITH
SS
3895 TA03
GND
LTC3895
TG
SW
BG
SENSE+
SENSE-
EXTV
CC
V
FB
BOOST
NDRV
DRV
CC
V
IN
12V*
V
OUT
12V**
5A
OVLO
PHASMD
PLLIN
VPRG
ILIM
CLKOUT
GND
RUN
FREQ
GND
GND
MTOP: BSC190N15NS3G
MBOT: BSC520N15NS3G
MNDRV: IPD320N20N3
L1: WURTH 74435571500
C
OUTA
: OS-CON 35SVPF39M
x4
MODE
PINS NOT USED
IN THIS CIRCUIT
PGOOD
**VOUT FOLLOWS VIN WHEN VIN < 18V,
VOUT REGULATES TO 18V WHEN VIN > 18V
*SURGES TO 140V,
OVLO TIMER LIMITS
SWITCHING TIME
ABOVE 36V TO 4 SECONDS
100µs/DIV
GND
VIN
20V/DIV
VOUT
20V/DIV
3895 TA03a 20ms/DIV
GND
VIN
20V/DIV
VOUT
20V/DIV
3895 TA03b
LTC3895
34
3895fa
For more information www.linear.com/LTC3895
Typical applicaTions
3895 TA04
68µF
C
OUTA
10µF
C
OUTB
MBOT
MTOP
C
B
0.1µF
L1
33µH
C
SNS
1nF
C
ITHA
3.3nF
C
ITHB
100pF
C
SS
0.1µF
C
INTV
CC
0.1µF
C
DRV
CC
4.7µF
100µF
C
INA
0.47µF
C
INB
R
ITH
23.7k
R
A
28k
R
B
806k
D
EXT
12V
R
SENSE
6mΩ
R
FREQ
36.5k
C
EXT
1µF
V
IN
INTV
CC
CPUMP_EN
DRVSET
DRVUV
ITH
SS
GND
LTC3895
TG
SW
BG
SENSE+
SENSE–
V
FB
BOOST
NDRV
DRV
CC
V
IN
8V to 140V
V
OUT
24V*
5A
OVLO
PHASMD
PLLIN
VPRG
ILIM
CLKOUT
GND
RUN
FREQ
GND
GND
MTOP, MBOT: BSC520N15NS3G
DEXT: DIODES INC. SMAZ12-13-F
L1: WURTH 7443633300
C
OUTA
: SUNCON 35CE68LX
x4
MODE
PINS NOT USED IN THIS CIRCUIT
PGOOD
*V
OUT
follows V
IN
when
x2
V
IN
< 24V
V
OUT
EXTV
CC
High Efficiency 140V to 24V Step-Down Converter
LTC3895
35
3895fa
For more information www.linear.com/LTC3895
3895 TA05
470µF
C
OUTA
MBOT
MTOP
C
B
0.1µF
C
SNS
470nF
C
ITHA
3.3nF
C
ITHB
100pF
C
SS
0.1µF
C
INTV
CC
0.1µF
C
DRV
CC
4.7µF
100µF
C
INA
0.47µF
C
INB
R
ITH
4.99k
R
FREQ
36.5k
R
OVLOB
1M
R
OVLOA
18.7k
R
SS
330k
R
SNS
2.43k
L1
4.7µH
V
IN
INTV
CC
CPUMP_EN
DRVSET
DRVUV
ITH
SS
GND
LTC3895
TG
SW
BG
SENSE+
SENSE–
EXTV
CC
V
FB
BOOST
NDRV
DRV
CC
V
IN
8V to 60V*
V
OUT
5V
10A
OVLO
PHASMD
PLLIN
PGOOD
VPRG
ILIM
CLKOUT
GND
RUN
FREQ
GND
GND
MTOP: BSC520N15NS3G
MBOT: BSC042NE7NS3G
L1: COILCRAFT XAL1010-472ME
C
OUTA
: KEMET T520D477M006ATE015
x3
PINS NOT USED IN THIS CIRCUIT
*Surges to 140V,
OVLO stops switching
when V
IN
> 65V
x2
100µF
C
OUTB
x2
MODE
High Efficiency 60V to 5V Step-Down Converter with Surge Protection to 140V
Typical applicaTions
LTC3895
36
3895fa
For more information www.linear.com/LTC3895
package DescripTion
Please refer to http://www.linear.com/product/LTC3895#packaging for the most recent package drawings.
4.75
(.187) REF
FE38 (AB) TSSOP REV B 0910
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
119
PIN NUMBERS 23, 25, 27, 29, 31, 33 AND 35 ARE REMOVED
20
REF
9.60 – 9.80*
(.378 – .386)
38
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.50
(.0196)
BSC 0.17 – 0.27
(.0067 – .0106)
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.315 ±0.05
0.50 BSC
4.50 REF
6.60 ±0.10
1.05 ±0.10
4.75 REF
2.74 REF
2.74
(.108)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
FE Package
Package Variation: FE38 (31)
38-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1865 Rev B)
Exposed Pad Variation AB
LTC3895
37
3895fa
For more information www.linear.com/LTC3895
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
A 09/16 Changed VRUN = 5V in the Electrical Characteristics table. 5
LTC3895
38
3895fa
For more information www.linear.com/LTC3895
LINEAR TECHNOLOGY CORPORATION 2016
LT 0916 REV A • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3895
relaTeD parTs
Typical applicaTion
PART NUMBER DESCRIPTION COMMENTS
LTC3891 60V, Low IQ, Synchronous Step-Down
DC/DC Controller with 99% Duty Cycle
PLL Fixed Frequency 50kHz to 900kHz
4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 24V, IQ = 50μA
LTC3810 100V Synchronous Step-Down DC/DC Controller Constant On-Time Valley Current Mode
4V ≤ VIN ≤ 100V, 0.8V ≤ VOUT ≤ 0.93 VIN, SSOP-28
LTC3703 100V Synchronous Switching Regulator Controller Fixed Frequency 100kHz to 600kHz, Voltage Mode Control 9.3V ≤ VIN ≤ 100V,
0.8V ≤ VOUT ≤ 0.93VIN, SSOP-16/SSOP-28
LTC3892/
LTC3892-1
60V Low IQ, Dual, 2-Phase Synchronous Step-Down
DC/DC Controller with 29µA Burst Mode IQ
PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 60V,
0.8V ≤ VOUT ≤ 0.99 VIN, Adjustable 5V to 10V Gate Drive, IQ = 29μA
LTC3639 High Efficiency, 150V 100mA Synchronous
Step-Down Regulator
Integrated Power MOSFETs, 4V ≤ VIN ≤ 150V,
0.8V ≤ VOUT ≤ VIN, IQ = 12μA, MSOP-16(12)
LTC3638 High Efficiency, 140V 250mA Step-Down Regulator Integrated Power MOSFETs, 4V≤ VIN ≤ 140V,
0.8V ≤ VOUT ≤ VIN, IQ = 12μA, MSOP-16(12)
LTC7138 High Efficiency, 140V 400mA Step-Down Regulator Integrated Power MOSFETs, 4V ≤ VIN ≤ 140V,
0.8V ≤ VOUT ≤ VIN, IQ = 12μA, MSOP-16(12)
LTC3899 60V, Triple Output, Buck/Buck/Boost Synchronous
Controller with 30µA Burst Mode IQ
4.5V (Down to 2.2V After Start-Up) ≤ VIN ≤ 60V,
Buck VOUT Range: 0.8V to 60V, Boost VOUT Up to 60V
LTC7860 High Efficiency Switching Surge Stopper 3.5V ≤ VIN ≤ 60V, Expandable to 200V+, Adjustable VOUT Clamp
and Current Limit, Power Inductor Improves EMI, MSOP-12
LT8631 100V, 1A Synchronous Micropower Step-Down
Regulator
Integrated Power MOSFETs, 3V ≤ VIN ≤ 100V,
0.8V ≤ VOUT ≤ 60V, IQ = 7μA, TSSOP-20
LTC7813 Low IQ, Synchronous Boost + Buck DC/DC Controller 4.5V (Down to 2.2V after Start-Up) ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 60V,
Adjustable 5V to 10V Gate Drive, IQ = 33μA
150µF
C
OUTA
22µF
C
OUTB
R
SENSE
6mΩ
MBOT
MTOP
C
B
0.1µF
L1
33µH
C
SNS
1nF
C
ITHA
4.7nF
C
ITHB
100pF
R
A
36.5k
C
SS
0.1µF
C
INTV
CC
0.1µF
R
PGOOD
100k
C
DRV
CC
4.7µF
100µF
C
INA
0.47µF
C
INB
R
B
511k
R
ITH
10k
MNDRV
R
FREQ
30.1k
R
DRVSET
80.6k
C
B
10pF
V
IN
INTV
CC
CPUMP_EN
DRVSET
DRVUV
ITH
SS
GND
LTC3895
TG
SW
BG
SENSE+
SENSE–
EXTV
CC
V
FB
BOOST
NDRV
DRV
CC
V
IN
7V to 140V
V
OUT
12V*
5A
*V
OUT
FOLLOWS V
IN
WHEN VIN < 12V
OVLO
PHASMD
PLLIN
PGOOD
VPRG
ILIM
CLKOUT
GND
RUN
FREQ
3895 TA06
GND
GND
MTOP, MBOT: BSC520N15NS3G
MNDRV: IPD320N20N3
L1: WURTH 7443633300
C
OUTA
: AVX TPSD157M016R0125
x2
x3
MODE
x3
PINS NOT USED IN THIS CIRCUIT
Figure 13. High Efficiency 140V to 12V Step-Down Converter
