[MHz] 16 Main clock X IN frequency System clock frequency [MHz] 6.25 4.0 2.0 8.0 4.0 1.0 0 1.8 2.0 4.0 4.5 Power source voltage 5.5 [V] 1.0 0 1.8 2.0 4.5 Power source voltage Rev.3.02 Apr 10, 2008 REJ03B0177-0302 Page 97 of 131 5.5 [V] 38D2 Group QzROM VERSION Electrical Characteristics Table 25 Electrical characteristics (1) (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted) Symbol Parameter VOH "H" output voltage P00-P07, P10-P17, P20-P27 VOH "H" output voltage P30-P37, P40-P47, P50-P57, P60-P62 (1) VOL "L" output voltage P00-P07, P10-P17, P20-P27 VOL "L" output voltage P40-P47, P50, P51, P54-P57, P60-P61 (1) VOL "L" output voltage P30-P37, P52, P53 VT+ - VT- Hysteresis CNTR0, CNTR1, INT0-INT2, KW0-KW7 Hysteresis RXD1, RXD2, SCLK1, SCLK2 Hysteresis RESET VT+ - VT- VT+ - VT- Test conditions IOH= -2.5mA IOH= -0.6mA VCC=2.5V IOH= -5mA IOH= -1.25mA IOH= -1.25mA VCC=2.5V IOL=5mA IOL=1.25mA IOL=1.25mA VCC=2.5V IOL=10mA IOL=2.5mA IOL=2.5mA VCC=2.5V IOL=15mA IOL=3.0mA VCC=2.5V Min. VCC-2.0 VCC-1.0 Limits Typ. Max. V VCC-2.0 VCC-0.5 VCC-1.0 VCC = 2.0 V to 5.5 V on RESET Unit V 2.0 0.5 1.0 V 2.0 0.5 1.0 V 2.0 0.8 V 0.5 V 0.5 V 0.5 V IIH "H" input current P00-P07, P10-P17, P20-P27 VI=VCC 5.0 A IIH "H" input current P30-P37, P40-P47, P50-P57, P60-P62 VI=VCC 5.0 A IIH "H" input current RESET, OSCSEL VI=VCC 5.0 A IIH "H" input current XIN VI=VCC IIL "L" input current P00-P07, P10-P17, P20-P27 VI=VSS Pull-up "OFF" VCC=5.0V, VI=VSS Pull-up "ON" VCC=3.0V, VI=VSS Pull-up "ON" VI=VSS Pull-up "OFF" VCC=5.0V, VI=VSS Pull-up "ON" VCC=3.0V, VI=VSS Pull-up "ON" VI=VSS IIL "L" input current P30-P37, P40-P47, P50-P57, P60- P62 IIL "L" input current RESET, OSCSEL IIL "L" input current XIN On-chip oscillator frequency f(OCO) NOTE: -60 -25 -120 -50 -30 -6.5 -70 -25 -5.0 -240 -100 -5.0 -140 -45 -5.0 -4.0 VI=VSS VCC=5.0V, Ta =25C A 4.0 2500 5000 A A A A A A A A 7500 kHz 1. When the port Xc switch bit (bit 4 of address 003B16) of CPU mode register is "1", the drivability of P62 is different from the above. Rev.3.02 Apr 10, 2008 REJ03B0177-0302 Page 98 of 131 38D2 Group QzROM VERSION Table 26 Electrical characteristics (2) (Vcc = 1.8 to 5.5 V, VSS = 0 V, Ta = -20 to 85C, f(XCIN) = 32.768 kHz, output transistors in the cut-off state, A/D converter stopped, unless otherwise noted) Symbol VRAM ICC Parameter Test conditions RAM hold voltage Power source current When clock is stopped Frequency/2 mode VCC=5.0V VCC=2.5V Frequency/4 mode VCC=5.0V VCC=2.5V Frequency/8 mode VCC=5.0V VCC=2.5V Low-speed mode VCC=5.0V VCC=2.5V On-chip oscillator mode f(XIN), f(XCIN) = stop All oscillations stopped (in STP state) Current increased at A/D converter operating Min. 1.8 f(XIN)=12.5MHz f(XIN)=12.5MHz (in WIT state) f(XIN)=4MHz f(XIN)=4MHz f(XIN)=4MHz (in WIT state) f(XIN)=2MHz f(XIN)=12.5MHz f(XIN)=12.5MHz (in WIT state) f(XIN)=4MHz f(XIN)=8MHz f(XIN)=8MHz (in WIT state) f(XIN)=4MHz f(XIN)=12.5MHz f(XIN)=12.5MHz (in WIT state) f(XIN)=4MHz f(XIN)=8MHz f(XIN)=8MHz (in WIT state) f(XIN)=4MHz f(XIN)=stop in WIT state f(XIN)=stop in WIT state VCC=5.0V VCC=2.5V VCC=2.5V (in WIT state) Ta=25C Limits Typ. 6.4 1.5 2.2 0.6 0.3 0.4 3.5 1.5 1.5 0.8 0.3 0.5 2.5 1.5 1.2 0.5 0.3 0.3 17 5.5 7.0 3.5 270 35 25 0.1 1.0 A 10 A Ta=85C f(XIN)=12.5 MHz, VCC=5 V in frequency/2, 4 or 8 mode f(XIN)= stop, VCC = 5 V in on-chip oscillator operating f(XIN) = stop, VCC = 5 V in low-speed mode Unit Max. 5.5 13 3.0 3.0 1.2 0.6 0.8 10 3.0 2.5 2.5 0.6 1.0 5.0 3.0 1.6 1.0 0.6 0.6 26 11 14 7.0 540 90 75 V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA A A A A A A A 0.5 mA 0.5 mA 0.4 mA A/D Converter Characteristics Table 27 A/D converter recommended operating condition (Vcc = 2.0 to 5.5 V, VSS = 0V, Ta = -20 to 85C, output transistors in cut-off state, unless otherwise noted) Symbol Parameter VCC VIH Power source voltage VIL "L" input voltage ADKEY f(AD) AD converter clock frequency (1) (Low-speed * on-chip oscillator mode excluded) Test conditions "H" input voltage ADKEY NOTE: 0 4.5V < VCC 5.5V 4.0V < VCC 4.5V 2.0V < VCC 4.0V 1. Confirm the recommended operating condition for main clock input frequency. Rev.3.02 Apr 10, 2008 REJ03B0177-0302 Page 99 of 131 Min. 2.0 0.9VCC Limits Typ. 5.0 Max. 5.5 VCC Unit V V 0.7 x VCC-0.5 V 6.25 4.0 VCC MHz MHz MHz 38D2 Group QzROM VERSION Table 28 A/D converter characteristics (Vcc = 2.0 to 5.5 V, Ta = -20 to 85C, output transistors in cut-off state, low-speed * on-chip oscillator mode included, unless otherwise noted) Symbol - ABS tCONV RLADDER IVREF IIA Parameter Test conditions Min. Resolution Absolute accuracy 10bitAD 4.5V < VCC 5.5V, AD conversion clock=f(XIN)/2, f(XIN)/8 6.25MHz (quantification error mode excluded) 4.0V < VCC 4.5V, AD conversion clock=f(XIN)/2, f(XIN)/8 4MHz 2.2V VCC 4.0V, AD conversion clock=f(XIN)/2, f(XIN)/8 VccMHz 2.0V VCC 5.5V, AD conversion clock=f(OCO)/8, f(OCO)/32 8bitAD 4.5V < VCC 5.5V, AD conversion clock=f(XIN)/2, f(XIN)/8 6.25MHz mode 4.0V < VCC 4.5V, AD conversion clock=f(XIN)/2, f(XIN)/8 4MHz 2.2V < VCC 4.0V, AD conversion clock=f(XIN)/2, f(XIN)/8 VccMHz 2.0V VCC 2.2V, AD conversion clock=f(XIN)/2, f(XIN)/8 (6Vcc-11)MHz 2.0V VCC 2.2V, AD conversion clock=f(XIN)/8 VccMHz 2.0V VCC 5.5V, AD conversion clock=f(OCO)/8, f(OCO)/32 Conversion time(1) 10bitAD mode 8bitAD mode Ladder resistor Reference input VREF=5.0V current Analog input current Limits Typ. Max. 10 4 Unit Bits LSB 2 tc(AD)x61 tc(AD)x49 12 50 35 150 tc(AD)x62 tc(AD)x50 100 200 k A 5.0 A NOTES: s 1. tc(AD): one cycle of AD conversion clock. AD conversion clock can be selected from SOURCE/2 or SOURCE/8. SOURCE represents the XIN input in the frequency/2, 4 or 8 mode and internal on-chip oscillator divided by 4 in the on-chip oscillator mode or the low-speed mode. When the A/D conversion is executed in the frequency/2 mode, frequency/4 mode, or frequency/8 mode, set f(XIN) 500 kHz. Relationship among AD conversion clock frequency, power source voltage, AD conversion mode and absolute accuracy. AD conversion clock frequency 10bitAD=4LSB 8bitAD=2LSB [MHz] 6.25 4.0 f(XIN)/2 or f(XIN)/8 10bitAD=4LSB 8bitAD=2LSB f(XIN)/2 or f(XIN)/8 8bitAD=2LSB 1.0 (Note) 0 AD conversion clock *frequency/2 mode, frequency/4 and frequency/8 mode: f(XIN)/2 or f(XIN)/8 f(XIN)/8 8bitAD=2LSB 2.2 2.0 1.8 2.0 2.2 4.0 4.5 Power source voltage V CC Note: f(XIN) 500kHz Rev.3.02 Apr 10, 2008 REJ03B0177-0302 AD conversion clock *Low-speed mode and on-chip oscillator mode: f(OCO)/8 or f(OCO)/32 Page 100 of 131 5.5 [V] 38D2 Group QzROM VERSION LCD power supply characteristics Table 29 LCD power supply characteristics (when connecting division resistors for LCD power supply) (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted) Symbol RLCD Parameter Division resister for LCD power supply (1) Test conditions RSEL="10" RSEL="11" LCD drive timing A LCD drive timing B LCD circuit division ratio = RSEL="01" divided by 1 RSEL="00" LCD circuit division ratio = RSEL="01" divided by 2 RSEL="00" LCD circuit division ratio = RSEL="01" divided by 4 RSEL="00" LCD circuit division ratio = RSEL="01" divided by 8 RSEL="00" LCD circuit division ratio = RSEL="01" divided by 1 RSEL="00" LCD circuit division ratio = RSEL="01" divided by 2 RSEL="00" LCD circuit division ratio = RSEL="01" divided by 4 RSEL="00" LCD circuit division ratio = RSEL="01" divided by 8 RSEL="00" NOTE: 1. The value is the average of each one division resistor. Rev.3.02 Apr 10, 2008 REJ03B0177-0302 Page 101 of 131 Min. Limits Typ. 200 5 120 90 150 120 170 150 190 170 150 120 170 150 190 170 190 190 Max. Unit k 38D2 Group QzROM VERSION Timing Requirements and Switching Characteristics Table 30 Timing requirements (1) (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = -20 to 85C, unless otherwise noted) Symbol Parameter tW(RESET) tC(XIN) Reset input "L" pulse width Main clock input cycle time 4.5V VCC 5.5V (1) 4.0V VCC < 4.5V tWH(XIN) Main clock input "H" pulse width 4.5V VCC 5.5V 4.0V VCC < 4.5V tWL(XIN) Main clock input "L" pulse width 4.5V VCC 5.5V (2) 4.0V VCC < 4.5V tC(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tC(SCLK) CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0-INT2 input "H" pulse width INT0-INT2 input "L" pulse width tWH(SCLK) tWL(SCLK) tsu(RXD-SCLK) th(SCLK-RXD) Min. 2 62.5 Limits Typ. Max. Unit s ns 125 25 ns ns 50 25 ns ns 50 250 105 105 80 80 800 ns ns ns ns ns ns ns Serial I/O1, 2 clock input "H" pulse width (3) 370 ns (3) 370 ns 220 100 ns ns (2) Serial I/O1, 2 clock input cycle time (3) Serial I/O1, 2 clock input "L" pulse width Serial I/O1, 2 input setup time Serial I/O1, 2 input hold time NOTES: 1. 80 ns in the frequency/2 mode. 2. 32 ns in the frequency/2 mode. 3. When bit 6 of address 001A16, 001F16 are "1" (clock synchronous). Divide this value by four when bit 6 of address 001A16, 001F16 are "0" (UART). Table 31 Timing requirements (2) (VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) Parameter Reset input "L" pulse width Main clock input cycle time (XIN input) 2.0V VCC 4.0V VCC < 2.0V 2.0V VCC 4.0V VCC < 2.0V Main clock input "L" pulse width 2.0V VCC 4.0V VCC < 2.0V CNTR0, CNTR1 input cycle time 2.0V VCC 4.0V VCC < 2.0V Main clock input "H" pulse width Min. 2 125 Limits Typ. Max. Unit s ns 166 ns 50 ns 70 ns 50 ns 70 ns 1000/VCC ns 1000/(5 x VCC-8) ns tc(CNTR)/2-20 tc(CNTR)/2-20 230 230 2000 ns ns ns ns ns tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tC(SCLK) CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0-INT2 input "H" pulse width INT0-INT2 input "L" pulse width tWH(SCLK) Serial I/O1, 2 clock input "H" pulse width (1) 950 ns tWL(SCLK) (1) 950 ns 400 200 ns ns tsu(RXD-SCLK) th(SCLK-RXD) Serial I/O1, 2 clock input cycle time (1) Serial I/O1, 2 clock input "L" pulse width Serial I/O1, 2 input setup time Serial I/O1, 2 input hold time NOTE: 1. When bit 6 of address 001A16, 001F16 are "1" (clock synchronous). Divide this value by four when bit 6 of address 001A16, 001F are "0" (UART). Rev.3.02 Apr 10, 2008 REJ03B0177-0302 Page 102 of 131 38D2 Group QzROM VERSION Table 32 Switching characteristics (1) (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = -20 to 85C, unless otherwise noted) Symbol Parameter tWH(SCLK) tWL(SCLK) td(SCLK-TxD) Serial I/O1, 2 clock output "H" pulse width Serial I/O1, 2 clock output "L" pulse width tv(SCLK-TxD) Serial I/O1, 2 output valid time (1) Serial I/O1, 2 clock output rising time Serial I/O1, 2 clock output falling time tr(SCLK) tf(SCLK) Min. tc(SCLK)/2-30 tc(SCLK)/2-30 Limits Typ Max. Serial I/O1, 2 output delay time (1) Unit 140 ns ns ns 30 30 ns ns -30 ns NOTE: 1. The P55/TxD1 [P32/TxD2] P-channel output disable bit (bit 4 of address 001B16 [001F16]) of UART control register is "0". Table 33 Switching characteristics (2) (VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted) Symbol Parameter tWH(SCLK) tWL(SCLK) td(SCLK-TxD) tv(SCLK-TxD) tr(SCLK) tf(SCLK) Min. tc(SCLK)/2-80 tc(SCLK)/2-80 Serial I/O1, 2 clock output "H" pulse width Serial I/O1, 2 clock output "L" pulse width Limits Typ Max. Serial I/O1, 2 output delay time (1) 350 ns ns ns 80 80 ns ns -30 (1) Serial I/O1, 2 output valid time Serial I/O1, 2 clock output rising time Serial I/O1, 2 clock output falling time ns NOTE: 1. The P55/TxD1 [P32/TxD2] P-channel output disable bit (bit 4 of address 001B16 [001F16]) of UART control register is "0". 1k Measurement output pin Measurement output pin 100pF CMOS output 100pF N-channel open-drain output (Note) Note: When bit 4 of the UART control register (address 001B16 [address 0FF116]) is "1." (N-channel open-drain output mode) Fig 94. Circuit for measuring output switching characteristics Rev.3.02 Apr 10, 2008 REJ03B0177-0302 Page 103 of 131 Unit 38D2 Group QzROM VERSION tC(CNTR) tWL(CNTR) tWH(CNTR) CNTR0, CNTR1 0.8VCC 0.2VCC tWH(INT) INT0-INT2 tWL(INT) 0.8VCC 0.2VCC tW(RESET) RESET 0.8VCC 0.2VCC tC(XIN) tWL(XIN) tWH(XIN) 0.8VCC XIN 0.2VCC tC(SCLK) SCLK1 SCLK2 tf tWL(SCLK) tWH(SCLK) 0.8VCC 0.2VCC tsu(RXD-SCLK) RXD1 RXD2 th(SCLK-RXD) 0.8VCC 0.2VCC td(SCLK-TXD) TXD1 TXD2 Fig 95. Timing diagram Rev.3.02 Apr 10, 2008 REJ03B0177-0302 tr Page 104 of 131 tV(SCLK-TXD) 38D2 Group FLASH MEMORY VERSION FLASH MEMORY VERSION ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Table 34 Absolute maximum ratings Symbol VCC VI Parameter Power source voltage Input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P62 Ratings -0.3 to 6.5 -0.3 to VCC+0.3 Unit V V VI Input voltage VL1 -0.3 to VL2 V VL1 to VL3 V VI Input voltage VL2 VI Input voltage VL3 VI Input voltage VO Output voltage P00-P07, P10-P17, P20-P27 RESET, XIN, CNVSS At output port Conditions All voltages are based on VSS. When an input voltage is measured, output transistors are cut off. At segment output COM0-COM3 VL2 to 6.5 V -0.3 to VCC+0.3 V -0.3 to VCC+0.3 V -0.3 to VL3+0.3 V -0.3 to VL3+0.3 V VO Output voltage VO Output voltage P30-P37, P40-P47, P50-P57, P60-P62 -0.3 to VCC+0.3 V VO Output voltage -0.3 to VCC+0.3 V Pd Topr Tstg Power dissipation Operating temperature Storage temperature 300 -20 to 85 -40 to 125 mW C C Rev.3.02 Apr 10, 2008 REJ03B0177-0302 XOUT Page 105 of 131 Ta=25C - - 38D2 Group FLASH MEMORY VERSION Recommended Operating Conditions Table 35 Recommended operating conditions (1) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -20 to 85C unless otherwise noted) Symbol VCC Parameter Power source voltage(1) Frequency/2 mode (2) Frequency/4 mode Frequency/8 mode f(XIN) 12.5MHz f(XIN) 8MHz f(XIN) 4MHz f(XIN) 16MHz f(XIN) 8MHz f(XIN) 16MHz f(XIN) 8MHz Min. 4.5 4.0 2.7 4.5 2.7 4.5 Limits Typ. VCC VCC P00-P03, P31, P33, P34, P37, P50, P51, P54- P57, P60, P61 0.8VCC VCC V RESET XIN 0.8VCC VCC V 0.8VCC 0 VCC 0.3VCC V V P00-P03, P31, P33, P34, P37, P50, P51, P54- P57, P60, P61, CNVSS 0 0.2VCC V RESET XIN 0 0.2VCC V 0 0.2VCC V Power source voltage LCD power source voltage A/D converter reference voltage Analog power source voltage Analog input voltage AN0-AN7 "H" input voltage P04-P07, P10-P17, P20-P27, P30, P32, P35, P36, P40-P47, P52, P53, P62 VIH "H" input voltage VIH "H" input voltage VIH VIL "H" input voltage "L" input voltage VIL "L" input voltage VIL "L" input voltage VIL "L" input voltage P04-P07, P10-P17, P20-P27, P30, P32, P35, P36, P40-P47, P52, P53, P62 0 2.5 2.7 1. When the A/D converter is used, refer to the recommended operating conditions of the A/D converter. 2. 12.5 MHz < f(XIN) 16 MHz is not available in the frequency/2 mode. Page 106 of 131 5.5 VCC 0 NOTES: Rev.3.02 Apr 10, 2008 REJ03B0177-0302 V V V V V V AVSS 0.7VCC VSS VL3 VREF AVSS VIA VIH 5.5 5.5 5.5 Unit V V V V V V V V V Low-speed mode On-chip oscillator mode 2.7 2.7 2.7 Max. 5.5 5.5 5.5 5.5 5.5 5.5 38D2 Group FLASH MEMORY VERSION Table 36 Recommended operating conditions (3) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted) Symbol Parameter Min. Limits Typ. Max. -40 Unit IOH(peak) "H" total peak output current (1) P00-P07, P10-P17, P20-P27, P30-P37 IOH(peak) "H" total peak output current (1) P40-P47, P50-P57, P60-P62 -40 mA IOL(peak) "L" total peak output current (1) P00-P07, P10-P17, P20-P27 40 mA IOL(peak) "L" total peak output current (1) P40-P47, P50, P51, P54-P57, P60-P62 40 mA IOL(peak) "L" total peak output current (1) P30-P37, P52, P53 110 mA IOH(avg) "H" total average output current (1) P00-P07, P10-P17, P20-P27, P30-P37 -20 mA IOH(avg) "H" total average output current (1) P40-P47, P50-P57, P60-P62 -20 mA IOL(avg) "L" total average output current (1) P00-P07, P10-P17, P20-P27 20 mA IOL(avg) "L" total average output current (1) P40-P47, P50, P51, P54-P57, P60-P61 20 mA IOL(avg) "L" total average output current (1) P30-P37, P52, P53 90 mA IOH(peak) "H" peak output current (2) P00-P07, P10-P17, P20-P27 -2.0 mA IOH(peak) "H" peak output current (2) P30-P37, P40-P47, P50-P57, P62-P62 -5.0 mA IOL(peak) "L" peak output current (2) P00-P07, P10-P17, P20-P27 5.0 mA IOL(peak) "L" peak output current (2) P40-P47, P50, P51, P54-P57, P60-P62 10 mA IOL(peak) "L" peak output current (2) P30-P37, P52, P53 30 mA IOH(avg) "H" average output current (3) P00-P07, P10-P17, P20-P27 -1.0 mA IOH(avg) "H" average output current (3) P30-P37, P40-P47, P50-P57, P60-P62 -2.5 mA IOL(avg) "L" average output current (3) P00-P07, P10-P17, P20-P27 2.5 mA IOL(avg) "L" average output current (3) P40-P47, P50, P51, P54-P57, P60-P62 5.0 mA IOL(avg) "L" average output current (3) P30-P37, P52, P53 15 mA mA NOTES: 1. The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2. The peak output current is the peak current flowing in each port. 3. The average output current is average value measured over 100 ms. Rev.3.02 Apr 10, 2008 REJ03B0177-0302 Page 107 of 131 38D2 Group FLASH MEMORY VERSION Table 37 Recommended operating conditions (4) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted) Symbol f(CNTR0) f(CNTR1) Parameter Limits Conditions Timer X and Timer Y Input frequency (duty cycle 50%) Min. Typ. Max. 4.5V VCC 5.5V 6.25 4.0V VCC < 4.5V 2xVcc-4 MHz 2.7V VCC < 4.0V Vcc MHz Timer X, Timer Y, Timer 1, Timer 2, 4.5V VCC 5.5V Timer 3, Timer 4 clock input frequency 4.0V VCC < 4.5V (Count source frequency of each timer) 2.7V VCC < 4.0V f(Tclk) f() f(XIN) Main clock input frequency (duty cycle 50%) (2)(3) f(XCIN) Sub-clock oscillation frequency MHz 16 MHz 4xVcc-8 MHz 2xVcc MHz 6.25 MHz 4.0V VCC < 4.5V 4 MHz 2.7V VCC < 4.0V Vcc MHz 4.5V VCC 5.5V System clock frequency (1) Unit 4.5V VCC 5.5V 1.0 16 MHz 2.7V VCC < 4.5V 1.0 8.0 MHz 80 kHz (duty cycle 50%) 32.768 (4)(5) NOTES: Relationship between system clock frequency and power source voltage is shown in the graph below. When the A/D converter is used, refer to the recommended operating conditions of the A/D converter. 12.5 MHz < f(XIN) 16 MHz is not available in the frequency/2 mode. The oscillation start voltage and the oscillation start time differ depending on factors such as the oscillator, circuit constants, and operating temperature range. Note that oscillation start may be particularly difficult at low voltage when using a high-frequency oscillator. 5. When using the microcomputer in low-speed mode, set the clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. 1. 2. 3. 4.

[MHz] 16 [MHz] Main clock XIN frequency System clock frequency 6.25 4.0 2.7 8.0 1.0 0 4.0 2.7 4.5 Power source voltage 5.5 [V] 0 2.7 4.5 Power source voltage Rev.3.02 Apr 10, 2008 REJ03B0177-0302 Page 108 of 131 5.5 [V] 38D2 Group FLASH MEMORY VERSION Electrical Characteristics Table 38 Electrical characteristics (1) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted) Symbol Parameter Test conditions Limits Typ. VOH "H" output voltage P00-P07, P10-P17, P20-P27 IOH= -2.5mA VOH "H" output voltage P30-P37, P40-P47, P50-P57, P60- P62(1) IOH= -5mA IOH= -1.25mA VCC-2.0 VCC-0.5 VOL "L" output voltage P00-P07, P10-P17, P20-P27 "L" output voltage P40-P47, P50, P51, P54-P57, P60- P62(1) 2.0 0.5 2.0 0.5 V VOL IOL=5mA IOL=1.25mA IOL=10mA IOL=2.5mA VOL "L" output voltage P30-P37, P52, P53 Hysteresis CNTR0, CNTR1, INT0-INT2, KW0- KW7 Hysteresis RxD1, RxD2, SCLK1, SCLK2 IOL=15mA 2.0 V VT+-VT- VT+-VT- VT+-VT- Hysteresis RESET Max. Unit Min. VCC-2.0 V V V V 0.5 V 0.5 V 0.5 V IIH "H" input current P00-P07, P10-P17, P20-P27 VI=VCC 5.0 A IIH 5.0 A IIH VI=VCC "H" input current P30-P37, P40-P47, P50-P57, P60-P62 VI=VCC "H" input current RESET, CNVSS 5.0 A IIH "H" input current XIN VI=VCC IIL "L" input current P00-P07, P10-P17, P20-P27 IIL "L" input current RESET, CNVSS VI=VSS Pull-up "OFF" VCC=5.0V, VI=VSS Pull-up "ON" VCC=3.0V, VI=VSS Pull-up "ON" VI=VSS Pull-up "OFF" VCC=5.0V, VI=VSS Pull-up "ON" VCC=3.0V, VI=VSS Pull-up "ON" VI=VSS IIL "L" input current XIN VI=VSS f(OCO) On-chip oscillator frequency IIL "L" input current P30-P37, P40-P47, P50-P57, P60-P67 VCC=5V, Ta=25C A 4.0 -5.0 -60 -120 -240 -25 -50 -100 -5.0 -30 -70 -140 -6.5 -25 -45 5000 A A A A A -5.0 A 7500 kHz -4.0 2500 A A NOTE: 1. When the port Xc switch bit (bit 4 of address 003B16) of CPU mode register is "1", the drivability of P62 is different from the above. Rev.3.02 Apr 10, 2008 REJ03B0177-0302 Page 109 of 131 38D2 Group FLASH MEMORY VERSION Table 39 Electrical characteristics (2) (Vcc = 2.7 to 5.5 V, VSS = 0 V, Ta = -20 to 85C, f(XCIN) = 32.768 kHz, output transistors in the cut-off state, A/D converter stopped, unless otherwise noted) Symbol VRAM ICC Parameter RAM hold voltage Power source current Test conditions When clock is stopped Frequency/2 mode Vcc=5.0V Vcc=2.7V Frequency/4 mode Vcc=5.0V Vcc=2.7V Frequency/8 mode Vcc=5.0V Vcc=2.7V Low-speed mode Vcc=5.0V Limits Typ. Min. 2.2 f(XIN)=12.5MHz f(XIN)=12.5MHz (in WIT state) f(XIN)=4MHz f(XIN)=4MHz f(XIN)=4MHz (in WIT state) f(XIN)=2MHz f(XIN)=12.5MHz f(XIN)=12.5MHz (in WIT state) f(XIN)=4MHz f(XIN)=8MHz f(XIN)=8MHz (in WIT state) f(XIN)=4MHz f(XIN)=12.5MHz f(XIN)=12.5MHz (in WIT state) f(XIN)=4MHz f(XIN)=8MHz f(XIN)=8MHz (in WIT state) f(XIN)=4MHz f(XIN)=stop in WIT state Ta=25C 4.0 2.0 2.0 1.5 1.0 1.0 3.2 1.6 1.6 1.6 1.0 1.0 2.5 1.5 1.5 1.5 1.0 1.0 400 4.0 Ta=85C Vcc=2.7V On-chip oscillator mode f(XIN), f(XCIN): stop All oscillations are stopped (in STP state) Current increased at A/D converter operating f(XIN)=stop in WIT state 300 3.7 Ta=25C Ta=85C Vcc=5.0V Vcc=2.7V Vcc=2.7V (in WIT state) Ta=25C Ta=85C f(XIN)=12.5MHz, VCC=5V in frequency/2, 4 or 8 mode f(XIN)=stop, VCC=5V in on-chip oscillator operating f(XIN)=stop, VCC=5V in low-speed mode 600 500 500 0.6 1.0 1.0 Max. 5.5 7.0 3.5 3.5 3 2.5 2.5 5.6 3.2 3.2 3.2 2.5 2.5 5 3 3 3 2.5 2.5 800 10 20 600 9 18 1200 1000 1000 3.0 Unit V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA A A A A A A A A A mA 1.0 mA 0.8 mA A/D Converter Characteristics Table 40 A/D converter recommended operating condition (Vcc = 2.7 to 5.5 V, Ta = -20 to 85C, output transistors in cut-off state, unless otherwise noted) Symbol Parameter Test conditions VCC Power source voltage VIH "H" input voltage ADKEY VIL "L" input voltage ADKEY f(AD) AD converter clock frequency (1) (Low-speed * on-chip oscillator mode excluded) Limits Min. Typ. 2.7 5.0 5.5 V VCC V 0 0.7 x VCC - 0.5 V 6.25 4.0 VCC MHz MHz MHz 4.5V < VCC 5.5V 4.0V < VCC 4.5V 2.7V < VCC 4.0V 1. Confirm the recommended operating condition for main clock input frequency. Page 110 of 131 Unit 0.9VCC NOTE: Rev.3.02 Apr 10, 2008 REJ03B0177-0302 Max. 38D2 Group FLASH MEMORY VERSION Table 41 A/D converter characteristics (Vcc = 2.7 to 5.5 V, Ta = -20 to 85C, output transistors in cut-off state, low-speed * on-chip oscillator mode included, unless otherwise noted) Symbol - ABS tCONV RLADDER IVREF IIA Parameter Test conditions Min. Resolution Absolute accuracy 10bitAD 4.5V < VCC 5.5V, AD conversion clock=f(XIN)/2, f(XIN)/86.25MHz (quantification error mode excluded) 4.0V < VCC 4.5V, AD conversion clock=f(XIN)/2, f(XIN)/84MHz 2.7V VCC 4.0V, AD conversion clock=f(XIN)/2, f(XIN)/8VccMHz 2.7V VCC 5.5V, f(OCO)/8, f(OCO)/32 8bitAD 4.5V < VCC 5.5V, AD conversion clock=f(XIN)/2, f(XIN)/86.25MHz mode 4.0V < VCC 4.5V, AD conversion clock=f(XIN)/2, f(XIN)/84MHz 2.7V VCC 4.0V, AD conversion clock=f(XIN)/2, f(XIN)/8VccMHz 2.7V VCC 5.5V, f(OCO)/8, f(OCO)/32 Conversion time(1) 10bitAD mode 8bitAD mode Ladder resistor Reference input VREF=5V current Analog input current Limits Typ. Max. 10 4 Unit Bits LSB 2 tc(AD) x 61 tc(AD) x 49 12 50 35 150 tc(AD) x 62 tc(AD) x 50 100 200 s k A 5.0 A NOTES: 1. tc(AD): one cycle of AD conversion clock. AD conversion clock can be selected from SOURCE/2 or SOURCE/8. SOURCE represents the XIN input in the frequency/2, 4 or 8 mode and internal on-chip oscillator divided by 4 in the on-chip oscillator mode or the low-speed mode. When the A/D conversion is executed in the frequency/2 mode, frequency/4 mode, or frequency/8 mode, set f(XIN) 500 kHz. Relationship among AD conversion clock frequency, power source voltage, AD conversion mode and absolute accuracy. 10bitAD=4LSB 8bitAD=2LSB AD conversion clock * Low-speed mode and on-chip oscillator mode: f(OCO)/8 or f(OCO)/32 AD conversion clock frequency [MHz] 6.25 4.0 AD conversion clock * frequency/2 mode, frequency/4 and frequency/8 mode: f(XIN)/2 or f(XIN)/8 2.7 f(XIN)/2 or f(XIN)/8 10bitAD=4LSB 8bitAD=2LSB (Note) 0 2.7 4.0 4.5 Power source voltage VCC Note: f(XIN) 500kHz Rev.3.02 Apr 10, 2008 REJ03B0177-0302 Page 111 of 131 5.5 [V] 38D2 Group FLASH MEMORY VERSION LCD power supply characteristics Table 42 LCD power supply characteristics (when connecting division resistors for LCD power supply) (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted) Symbol RLCD Parameter Division resister for LCD power supply (1) Test conditions RSEL="10" RSEL="11" LCD drive timing A LCD drive timing B LCD circuit division ratio = RSEL="01" divided by 1 RSEL="00" LCD circuit division ratio = RSEL="01" divided by 2 RSEL="00" LCD circuit division ratio = RSEL="01" divided by 4 RSEL="00" LCD circuit division ratio = RSEL="01" divided by 8 RSEL="00" LCD circuit division ratio = RSEL="01" divided by 1 RSEL="00" LCD circuit division ratio = RSEL="01" divided by 2 RSEL="00" LCD circuit division ratio = RSEL="01" divided by 4 RSEL="00" LCD circuit division ratio = RSEL="01" divided by 8 RSEL="00" NOTE: 1. The value is the average of each one division resistor. Rev.3.02 Apr 10, 2008 REJ03B0177-0302 Page 112 of 131 Min. Limits Typ. 200 5 120 90 150 120 170 150 190 170 150 120 170 150 190 170 190 190 Max. Unit k 38D2 Group FLASH MEMORY VERSION Timing Requirements And Switching Characteristics Table 43 Power supply circuit characteristics (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = -20 to 85C, unless otherwise noted) Symbol td(P-R) Parameter Test conditions Internal power source voltage stabilizes time at power-on 2.7 VCC 5.5V Limits Typ. Min. 2 Unit Max. ms Table 44 Timing requirements (1) (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = -20 to 85C, unless otherwise noted) Symbol Parameter tW(RESET) tC(XIN) Reset input "L" pulse width Main clock input cycle time tWH(XIN) Main clock input "H" pulse width 4.5V VCC 5.5V (2) 4.0V VCC < 4.5V tWL(XIN) Main clock input "L" pulse width 4.5V VCC 5.5V (2) 4.0V VCC < 4.5V tC(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tC(SCLK) CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0-INT2 input "H" pulse width INT0-INT2 input "L" pulse width Min. 2 62.5 4.5V VCC 5.5V (1) 4.0V VCC < 4.5V Limits Typ. Max. Unit s ns 125 25 ns ns 50 25 ns ns Serial I/O1, 2 clock input cycle time (3) 50 250 105 105 80 80 800 ns ns ns ns ns ns ns tWH(SCLK) Serial I/O1, 2 clock input "H" pulse width (3) 370 ns tWL(SCLK) Serial I/O1, 2 clock input "L" pulse width (3) Serial I/O1, 2 input setup time Serial I/O1, 2 input hold time 370 ns 220 100 ns ns tsu(RxD-SCLK) th(SCLK-RxD) NOTES: 1. 80 ns in the frequency/2 mode. 2. 32 ns in the frequency/2 mode. 3. When bit 6 of address 001A16, 001F16 are "1" (clock synchronous). Divide this value by four when bit 6 of address 001A16, 001F16 are "0" (UART). Table 45 Timing requirements (2) (VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tC(SCLK) tWH(SCLK) tWL(SCLK) tsu(RXD-SCLK) th(SCLK-RXD) Parameter Reset input "L" pulse width Main clock input cycle time (XIN input) Main clock input "H" pulse width Main clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0-INT2 input "H" pulse width INT0-INT2 input "L" pulse width Serial I/O1, 2 clock input cycle time Serial I/O1, 2 clock input "H" pulse width Serial I/O1, 2 clock input "L" pulse width Serial I/O1, 2 input setup time Serial I/O1, 2 input hold time NOTE: 1. When bit 6 of address 001A16, 001F16 are "1" (clock synchronous). Divide this value by four when bit 6 of address 001A16, 001F16 are "0" (UART). Rev.3.02 Apr 10, 2008 REJ03B0177-0302 Page 113 of 131 Limits Min. Typ. 2 125 50 50 1000/VCC tc(CNTR)/2-20 tc(CNTR)/2-20 230 230 2000 950 950 400 200 Max. Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns 38D2 Group FLASH MEMORY VERSION Table 46 Switching characteristics (1) (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = -20 to 85C, unless otherwise noted) Symbol Parameter tWH (SCLK) tWL (SCLK) td (SCLK-TXD) Serial I/O1, 2 clock output "H" pulse width Serial I/O1, 2 clock output "L" pulse width tV (SCLK-TXD) Serial I/O1, 2 output valid time (1) Serial I/O1, 2 clock output rising time Serial I/O1, 2 clock output falling time tr (SCLK) tf (SCLK) Min. tC(SCLK)/2-30 tC(SCLK)/2-30 Limits Typ Serial I/O1, 2 output delay time (1) Max. Unit 140 ns ns ns 30 30 ns ns -30 ns NOTE: 1. The P55/TxD1 [P32/TxD2] P-channel output disable bit (bit 4 of address 001B16 [0FF116]) of UART control register is "0". Table 47 Switching characteristics (2) (VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = -20 to 85C, unless otherwise noted) Symbol tWH (SCLK) tWL (SCLK) td (SCLK-TXD) tV (SCLK-TXD) tr (SCLK) tf (SCLK) Limits Parameter Min. tC(SCLK)/2-80 tC(SCLK)/2-80 Serial I/O1, 2 clock output "H" pulse width Serial I/O1, 2 clock output "L" pulse width Typ Max. 350 Serial I/O1, 2 output delay time (1) -30 (1) Serial I/O1, 2 output valid time Serial I/O1, 2 clock output rising time Serial I/O1, 2 clock output falling time 80 80 1. The P55/TxD1 [P32/TxD2] P-channel output disable bit (bit 4 of address 001B16 [0FF116]) of UART control register is "0". 1k Measurement output pin 100pF 100pF N-channel open-drain output (Note) CMOS output Note: When bit 4 of the UART control register (address 001B16 [address 0FF116]) is "1." (N-channel open-drain output mode) Fig 96. Circuit for measuring output switching characteristics Rev.3.02 Apr 10, 2008 REJ03B0177-0302 Page 114 of 131 ns ns ns ns NOTE: Measurement output pin Unit ns ns 38D2 Group FLASH MEMORY VERSION tc(CNTR) tWL(CNTR) tWH(CNTR) 0.8VCC CNTR0, CNTR1 0.2VCC tWL(INT) tWH(INT) INT0-INT2 0.8VCC 0.2VCC tw(RESET) RESET 0.8VCC 0.2VCC tc(XIN) tWL(XIN) tWH(XIN) 0.8VCC 0.2VCC XIN tC(SCLK) tf SCLK1 SCLK2 tr tWL(SCLK) 0.8VCC 0.2VCC tsu(RXD-SCLK) R XD1 R XD2 th(SCLK-RXD) 0.8VCC 0.2VCC td(SCLK-TXD) T XD 1 T XD 2 Fig 97. Timing diagram (in single-chip mode) Rev.3.02 Apr 10, 2008 REJ03B0177-0302 tWH(SCLK) Page 115 of 131 tV(SCLK-TXD) 38D2 Group PACKAGE OUTLINE Diagrams showing the latest package dimensions and mounting information are available in the "Packages" section of the Renesas Technology website. JEITA Package Code P-LQFP64-14x14-0.80 RENESAS Code PLQP0064GA-A Previous Code 64P6U-A MASS[Typ.] 0.7g HD *1 D 33 48 49 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 32 bp c Reference Dimension in Millimeters Symbol *2 E HE c1 b1 ZE Terminal cross section 64 17 c Index mark A2 16 ZD A 1 A1 F L D E A2 HD HE A A1 bp b1 c c1 L1 y e Rev.3.02 Apr 10, 2008 REJ03B0177-0302 *3 Detail F bp x Page 116 of 131 e x y ZD ZE L L1 Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.1 0.2 0 0.32 0.37 0.42 0.35 0.09 0.145 0.20 0.125 8 0 0.8 0.20 0.10 1.0 1.0 0.3 0.5 0.7 1.0 38D2 Group JEITA Package Code P-LQFP64-10x10-0.50 RENESAS Code PLQP0064KB-A Previous Code 64P6Q-A / FP-64K / FP-64KV MASS[Typ.] 0.3g HD *1 D 48 33 49 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 32 bp 64 1 c1 Terminal cross section ZE 17 Reference Dimension in Millimeters Symbol c E *2 HE b1 16 Index mark ZD c A *3 A1 y e A2 F bp L x L1 Detail F Rev.3.02 Apr 10, 2008 REJ03B0177-0302 Page 117 of 131 D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Min Nom Max 9.9 10.0 10.1 9.9 10.0 10.1 1.4 11.8 12.0 12.2 11.8 12.0 12.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 8 0 0.5 0.08 0.08 1.25 1.25 0.35 0.5 0.65 1.0 38D2 Group APPENDIX Note on Programming 1. Processor Status Register (1) Initialization of the processor status register It is required to initialize the processor status register (PS) flags which affect program execution. It is particularly essential to initialize the T and D flags because of their effect on calculations. Initialize these flags at the beginning of the program. At a reset, the contents of the processor status register (PS) are undefined except for the I flag which is "1". 2. Decimal Calculations (1) Instructions for decimal calculations To perform decimal calculations, set the decimal mode (D) flag to "1" with the SED instruction and execute the ADC or SBC instruction. In that case, after the ADC or SBC instruction, execute another instruction before the SEC, CLC, or CLD instruction. Set the decimal mode (D) flag to "1" Execute the ADC or SBC instruction Reset NOP Initialize the flags Execute the SEC, CLC, or CLD instruction Main program Fig. 98 Initialization of processor status register flags (2) How to refer the processor status register To refer the contents of the processor status register (PS), execute the PHP instruction once and then read the contents of (S+1). If necessary, execute the PLP instruction to return the stored PS to its original status. (S) (S) + 1 Stored PS Fig. 99 Stack memory contents after PHP instruction execution Rev.3.02 Apr 10, 2008 REJ03B0177-0302 Page 118 of 131 Fig. 100 Instructions for decimal calculations (2) Status flag at decimal calculations When the ADC or SBC instruction is executed in decimal mode (D flag = "1"), three of the status flags (N, V, and Z) are disabled. The carry (C) flag is set to "1" if a carry is generated and is cleared to "0" if a borrow is generated as a result of a calculation, so it can be used to determine whether the calculation has generated a carry or borrow. Initialize the C flag before each calculation. 38D2 Group 3. JMP Instruction When using the JMP instruction (indirect addressing mode), do not specify the address where "FF16" is allocated to the loworder 8 bits as the operand. 4. Multiplication and Division Instructions (1) The MUL and DIV instructions are not affected by the T and D flags. (2) Executing these instructions does not change the contents of the processor status register. 5. Read-Modify-Write Instruction Do not execute any read-modify-write instruction to the read invalid (address) SFR. The read-modify-write instruction reads 1-byte of data from memory, modifies the data, and writes 1-byte the data to the original memory. In the 740 Family, the read-modify-write instructions are the following: (1) Bit handling instructions: CLB, SEB (2) Shift and rotate instructions: ASL, LSR, ROL, ROR, RRF (3) Add and subtract instructions: DEC, INC (4) Logical operation instructions (1's complement): COM Although not the read-modify-write instructions, add and subtract/logical operation instructions (ADC, SBC, AND, EOR, and ORA) when T flag = "1" operate in the way as the readmodify-write instruction. Do not execute them to the read invalid SFR. When the read-modify-write instruction is executed to the read invalid SFR, the following may result: As reading is invalid, the read value is undefined. The instruction modifies this undefined value and writes it back, so the written value will be indeterminate. Notes on Peripheral Functions Notes on I/O Ports 1. Use in Stand-By State When using the MCU in stand-by state* 1 for low-power consumption, do not leave the input level of an I/O port undefined. Be especially careful to the I/O ports for the Nchannel open-drain. In this case, pull-up (connect to Vcc) or pull-down (connect to Vss) these ports through a resistor. When determining a resistance value, note the following: * External circuit * Variation in the output level during ordinary operation When using a built-in pull-up resistor, note variations in current values: * When setting as an input port: Fix the input level * When setting as an output port: Prevent current from flowing out externally. Even if a port is set to output by the direction register, when the content of the port latch is "1", the transistor becomes the OFF state, which allows the port to be in the high-impedance state. This may cause the level to be undefined depending on external circuits. As described above, if the input level of an I/O port is left undefined, the power source current may flow because the potential applied to the input buffer in the MCU will be unstable. *1 Stand-by state: Stop mode by executing the STP instruction Wait mode by executing the WIT instruction 2. Modifying Output Data with Bit Handling Instruction When the port latch of an I/O port is modified with the bit handling instruction* 1 , the value of an unspecified bit may change. I/O ports can be set to input mode or output mode in byte units. When the port register is read or written, the following will be operated: * Port as input mode Read: Read the pin level Write: Write to the port latch * Port as output mode Read: Read the port latch or peripheral function output (specifications vary depending on the port) Write: Write to the port latch (output the content of the port latch from the pin) Meanwhile, the bit handling instructions are the read-modifywrite instructions*2. Executing the bit handling instruction to the port register allows reading and writing a bit unspecified with the instruction at the same time. If an unspecified bit is set to input mode, the pin level is read and the value is written to the port latch. At this time, if the original content of the port latch and the pin level do not match, the content of the port latch changes. If an unspecified bit is set to output mode, the port latch is normally read, but the peripheral function output is read in some ports and the value is written to the port latch. At this time, if the original content of the port latch and the peripheral function output do not match, the content of the port latch changes. *1 Bit handling instructions: CLB, SEB *2 Read-modify-write instruction: Reads 1-byte of data from memory, modifies the data, and writes 1-byte of the data to the original memory. Rev.3.02 Apr 10, 2008 REJ03B0177-0302 Page 119 of 131 38D2 Group 3. Direction Registers The values of the port direction registers cannot be read. This means, it is impossible to use the LDA instruction, memory operation instruction when the T flag is "1", addressing mode using direction register values as qualifiers, and bit test instructions such as BBC and BBS. It is also impossible to use bit operation instructions such as CLB and SEB, and read-modifywrite instructions to direction registers, including calculations such as ROR. To set the direction registers, use instructions such as LDM or STA. 4. Pull-Up Control Only for the pin set to input mode, pull-up is controlled by the PULL register and the segment output disable register. Notes on Termination of Unused Pins 1. Termination of Unused Pins Perform the following at the shortest possible distance (20 mm or less) from the MCU pins. (1) I/O ports Set the ports to input mode and connect each pin to VCC or VSS through a resistor of 1 k to 10 k. An internal pull-up resistor can also be used for the port where the internal pull-up resister is selectable. To set the ports to output mode, leave open at "L" or "H" output. * When setting the ports to output mode and leave open, input mode in the initial state remains until the mode of the ports are switched to output mode by a program after a reset. This may cause the voltage level of the pins to be undefined and the power source current to increase while the ports remains in input mode. For any effects on the system, careful system evaluations should be implemented on the user side. * The direction registers may be changed due to a program runaway or noise, so reset the registers periodically by a program to increase the program reliability. 2. Termination Concerns (1) When setting I/O ports to input mode [1] Do not leave open * The power source current may increase depending on the first-stage circuit. * The ports are more likely affected by noise when compared with the termination shown on the above "1. (1) I/O ports" [2] Do not connect to VCC or VSS directly If the direction registers are changed to output mode due to a program runaway or noise, a short circuit may occur. [3] Do not connect multiple ports in a lump to V CC or V SS through a resistor. If the direction registers are changed to output mode due to a program runaway or noise, a short circuit may occur between the ports. Rev.3.02 Apr 10, 2008 REJ03B0177-0302 Page 120 of 131 38D2 Group 1. Changing Related Register Settings If the interrupt occurrence synchronized with the following settings is not required, take the sequence shown below. * When selecting the external interrupt active edge * When selecting the interrupt source of the interrupt vector address where two or more interrupt sources are allocated 2. Checking Interrupt Request Bit To check the interrupt request bit with the BBC or BBS instruction immediately after this bit is set to "0", take the following sequence. If the BBC or BBS instruction is executed immediately after the interrupt request bit is set to "0", the bit value before being set to "0" is read. Set the corresponding interrupt enable bit to "0" (disabled). Set the interrupt request bit to "0" (no interrupt) Notes on Interrupts Set the interrupt edge selection bit (active edge switch bit) or interrupt (source) selection bit. NOP (one or more instructions) Execute the BBC or BBS instruction NOP (one or more instructions) Fig. 102 Sequence for setting interrupt request bit Set the corresponding interrupt request bit to "0" (no interrupt request). Set the corresponding interrupt enable bit to "1" (enabled). Fig. 101 Sequence for setting related register In the following cases, the interrupt request bit of the corresponding interrupt may be set to "1". * INT0 interrupt edge selection bit (bit 0 of interrupt edge selection register (address 003A16)) * INT1 interrupt edge selection bit (bit 1 of interrupt edge selection register) * INT2 interrupt edge selection bit (bit 2 of interrupt edge selection register) * CNTR0 active edge switch bits (bits 6 and 7 of timer X control register 1 (address 002E16)) * CNTR1 active edge switch bit (bits 6 of timer Y mode register (address 003816)) * INT2/Key input interrupt switch bit (bit 3 of interrupt edge selection register) * Timer Y/CNTR1 interrupt switch bit (bit 4 of interrupt edge selection register) Rev.3.02 Apr 10, 2008 REJ03B0177-0302 Page 121 of 131 3. Setting Unused Interrupts Set the interrupt enable bit of the unused interrupt to "0" (disabled). 38D2 Group Notes on Timers 8. Write Order to Timer X 1. Frequency Divider All timers shares one circuit for the frequency divider to generate the count source. Thus the frequency divider is not initialized when each individual timer is activated. When the frequency divider is selected as the count source, a one-cycle delay of the maximum count source will result between when the timer is activated and when it starts counting or outputs the waveform. The count source cannot be observed externally. (1) When timer mode, pulse output mode, event counter mode, or pulse width measurement mode is set, write to the following registers in the order below: The timer X register (extension) The timer X register (low-order) The timer X register (high-order) Writing to only one of these registers cannot be performed. When either of the above modes is set and timer X operates as a 16-bit counter, if the timer X register (extension) is never set after a reset release, setting the timer X register (extension) is not required. In that case, write the timer X register (low-order) first and the timer X register (high-order) next. However, once the timer X register (extension) is written, note that the value is retained in the reload latch. (2) Write to the timer X register by the 16-bit unit. Do not read the timer X register while write operation is performed. If the write operation is not completed, normal operation will not be performed. (3) When IGBT output mode or PWM mode is set, do not write "1" to the timer X register (extension). If "1" has been already written to the timer X register, be sure to write "0" to the register before use. Write to the following registers in the order below: The compare registers 1, 2, 3 (high- and low-order) The timer X register (extension) The timer X register (low-order) The timer X register (high-order) The compare registers (high- and low-order) can be written in either order. However, be sure to write both the compare registers 1, 2, 3 and the timer X register at the same time. 2. Division Ratio for Timer 1 to 4 The division ratio is 1/(n+1) when the value n (0 to 255) is written to the timer latch. 3. Switching Frequency and Count Source for Timer 1 to 4, X, and Y Switch the frequency division or count source* while the timer count is stopped. *This also applies when the frequency divider output is selected as the timer count source and the count source is switched in conjunction with a transition between operating modes (onchip oscillator mode, X IN mode, or low-speed mode). Be careful when changing settings in the CPU mode register. 4. Setting Timer 1 and 2 When STP Instruction Executed Before executing the STP instruction, first set the wait time at return. 5. Setting Order to Timer 1 to 4 When switching the count source of timer 1 to timer 4, a narrow pulse may be generated at the count input, which causes the timer count value to be undefined. Also, if the timers are used in cascade connection, a narrow pulse may be generated at the output when writing to the pervious timer, which causes the next timer count value to be undefined. Thus set the value from timer 1 in order after setting the count source of timer 1 to timer 4. 6. Write to Timer 2, 3, and 4 When writing to the latch only, if the write timing to the reload latch and the underflow timing are almost the same, the value is set into the timer and the timer latch at the same time. At this time, count is stopped during write operation to the reload latch. 7. Timer 3 PWM0 Mode, Timer 4 PWM1 Mode (1) When PWM output is suspended once it starts, the time to resume outputting may be delayed one section (256 x ts) of the short interval depending on the level of the output pulse at that time: Stop at "H": No output delay Stop at "L": Output is delayed time of 256 x ts (2) When PWM mode is used, the interrupt requests and values of timer 3 and timer 4 are updated every cycle of the long interval (4 x 256 x ts). Rev.3.02 Apr 10, 2008 REJ03B0177-0302 Page 122 of 131 9. Read Order to Timer X (1) In all modes, read the following registers in the order below: The timer X register (extension) The timer X register (high-order) The timer X register (low-order) When reading the timer X register (extension) is not required, read the timer X register (high-order) first and the timer X register (low-order) next. The read order to the compare registers 1, 2, 3 is not specified. (2) Read the timer X register in 16-bit units. Do not write to it during read operation. If read operation is terminated in progress, normal operation will not be performed. 38D2 Group 10. Write to Timer X (1) Timer X can select either writing data to both the latch and the timer at the same time or writing data only by the timer X write control bit (b3) in the timer X mode register (address 002D16). When writing to the latch only, if a value is written to the timer X address, the value is set into the reload latch and the timer is updated at the next underflow. After a reset release, if a value is written to the timer X address, the value is set into the timer and the timer latch at the same time, because they are written simultaneously. When writing to the latch only, if the write timing to the high-order reload latch and the underflow timing are almost the same, the value is set into the timer and the timer latch at the same time. At this time, count is stopped during write operation to the high-order reload latch. (2) Switch the frequency division or count source* while the timer count is stopped. *This also applies when the frequency divider output is selected as the timer count source and the count source is switched in conjunction with a transition between operating modes (onchip oscillator mode, X IN mode, or low-speed mode). Be careful when changing settings in the CPU mode register. 11. Setting Timer X Mode Register When PWM mode or IGBT output mode is set, be sure to set the write control bit in the timer X mode register to "1" (writing to latch only). After writing to the timer X register (high-order), the contents of both registers are simultaneously reflected in the output waveform at the next underflow. 12. Timer X Output Control Functions To use the output control functions (INT1 and INT2 ), set the levels of INT1 and INT2 to "H" for the falling edge active or to "L" for the rising edge active before switching to IGBT output mode. 13. CNTR0 Active Edge Selection (1) Setting the CNTR0 active edge switch bits also affects the interrupt active edge at the same time. (2) When the pulse width is measured, set bit 7 of the CNTR0 active edge switch bits to "0". 14. When Timer X Pulse Width Measurement Mode Used When timer X pulse mode measurement mode is used, enable the event counter wind control data (bit 5 of timer X mode register (address 002D16)) by setting to "0". If the event counter window control data (bit 5 of timer X mode r egister (address 002 D 1 6 )) is set to "1" (disabled) to enable/disable the CNTR0 input, the input is not accepted after the timer 1 underflow. Rev.3.02 Apr 10, 2008 REJ03B0177-0302 Page 123 of 131 15. CNTR1 Active Edge Selection Setting the CNTR 1 active edge switch bits also affects the interrupt active edge at the same time. However, in pulse width HL continuous HL measurement mode, the CNTR 1 interrupt request is generated at both rising and falling edges of the pin regardless of the settings of the CNTR1 active edge switch bits. 16. Read from/Write to Timer Y (1) When reading from/writing to timer Y, read from/write to both the high-order and low-order bytes of timer Y. To read the value, read the high-order bytes first and the low-order bytes next. To write the value, write the low-order bytes first and the high-order bytes next. Writing/reading should be preformed in 16-bit units. If write/read operation is changed in progress, normal operation will not be performed. (2) Timer Y can select either writing data to both the latch and the timer at the same time or writing data only by the timer Y write control bit (b0) in the timer Y control register (address 003916). When writing to the latch only, if a value is written to the timer Y address, the value is set into the reload latch and the timer is updated at the next underflow. After a reset release, if a value is written to the timer Y address, the value is set into the timer and the timer latch at the same time, because they are written simultaneously. When writing to the latch only, if the write timing to the high-order reload latch and the underflow timing are almost the same, the value is set into the timer and the timer latch at the same time. At this time, count is stopped during write operation to the high-order reload latch. (3) Switch the frequency division or count source* while the timer count is stopped. *This also applies when the frequency divider output is selected as the timer count source and the count source is switched in conjunction with a transition between operating modes (onchip oscillator mode, X IN mode, or low-speed mode). Be careful when changing settings in the CPU mode register. 17. Real time port control When switching the setting of the real time port control bits between valid and invalid, write to the timer Y mode register in byte units with the LDM or STA instruction so that both bits are switched at the same time. Also, before using this function, set the P46 and P47 port direction registers to output. 38D2 Group Notes on Serial I/O1 Becaouse the operation of the serial I/O2 is as same as serial I/O1, the following notes are written about the serial I/O1. 1. Write to Baud Rate Generator Write to the baud rate generator while transmission/reception is stopped. 2. Setting Sequence When Serial I/O1 Transmit Interrupt Used To use the serial I/O1 transmit interrupt, if the interrupt occurrence synchronized with settings is not required, take the following sequence: (1) Set the serial I/O1 transmit interrupt enable bit (bit 2 of interrupt control register 2 (address 003F 16 )) to "0" (disabled). (2) Set the transmit enable bit to "1". (3) After one or more instructions have been executed, set the serial I/O1 transmit interrupt request bit (bit 2 of interrupt request register 2 (address 003D16)) to "0" (no interrupt). (4) Set the serial I/O1 transmit interrupt enable bit to "1" (enabled). When the transmit enable bit is set to "1", the transmit buffer empty flag (bit 0 of serial I/O1 status register) and the transmit shift completion flag are set to "1". This allows an interrupt request to be generated regardless of which interrupt occurrence source has been selected by the transmit interrupt source selection bit (bit 3 of serial I/O1 control register) and the serial I/O1 transmit interrupt request bit is set to "1". 3. Data Transmission Control Using Transmit Shift Completion Flag After transmit data is written to the transmit buffer register, the transmit shift completion flag (bit 2 of serial I/O1 status register (address 001916)) changes from "1" to "0" after a delay of 0.5 to 1.5 cycles of the system clock. Thus, after transmit data is written to the transmit buffer register, note this delay when controlling data transmission by referencing the transmit shift completion flag. 4. Setting Serial I/O1 Control Register Before setting the serial I/O1 control register again, first set both the transmit enable bit and the receive enable bit to "0" and initialize the transmission and reception circuits. Set both the transmit enable bit (TE) and the receive enable bit (RE) to "0" Set bits 0 to 3, and 6 of the serial I/O1 control register. Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to "1". Settings can be made with the LDM instruction at the same time Fig. 103 Sequence of setting serial I/O1 control register 5. Pin Status After Transmission Completed After transmission is completed, the TxD pin retains the level when transmission is completed. When the internal clock is selected in clock synchronous serial I/O mode, the SCLK1 pin is set to "H". Rev.3.02 Apr 10, 2008 REJ03B0177-0302 Page 124 of 131 6. Serial I/O1 Enable Bit during Transmit Operation During transmission, if the serial I/O1 enable bit (bit 7 of serial I/O1 control register (address 001A16 )) is set to "0", the pin function is set to an I/O port and the internal transmit operation continues even though transmit data is not output externally. Also, if the transmit buffer register is written in this state, transmit operation starts internally. If the serial I/O1 enable bit is set to "1" at this time, transmit data is output to the TxD pin from that point. 7. Transmission Control When External Clock Selected During data transmission, if the external clock is selected as the synchronous clock, set the transmit enable bit to "1" while SCLK1 is set to "H". Also, write to the transmit buffer register while SCLK1 is set to "H". 8. Receive Operation in Clock Synchronous Serial I/O Mode During reception in clock synchronous serial I/O mode, set both the transmit enable bit and the receive enable bit to "1". Then write dummy data to the transmit buffer register. When the internal clock is selected as the synchronous clock, the synchronous clock is output at this point and receive operation starts. When the external clock is selected, reception is enabled at this point and inputting the external clock starts transmit operation. The P55/TXD1 [P32/TxD2] pin outputs dummy data written in the transmit buffer register. 9. Transmit/Receive Operation in Clock Synchronous Serial I/O Mode In clock synchronous serial I/O mode, set the transmit enable bit and the receive enable bit to "0" simultaneously to stop transmit/receive operations. If only one of the operations is stopped, transmission and reception cannot be synchronized, which will cause a bit error. 38D2 Group Notes on A/D Conversion 1. Analog Input Pin Set the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01 F to 1 F. In addition, operations of application products should be verified thoroughly on the user side. An analog input pin has a built-in capacitor for analog voltage comparison. Thus if a signal from the high impedance signal source is input to the analog input pin, charge and discharge noise will be generated. This may cause the A/D conversion/comparison accuracy to drop. 2. Clock Frequency during A/D Conversion The comparator input consists of a capacity coupling. If the conversion rate is too low, the A/D conversion accuracy may deteriorate due to a charge lost, so set f(XIN) 500 kHz or more for A/D conversion in XIN mode. Also, do not execute the STP or WIT instruction during A/D conversion. In low-speed mode (when on-chip oscillator is selected), as A/D conversion is performed using the internal on-chip oscillator, there is no limit on the minimum frequency for f(XIN). 3. ADKEY Function When the ADKEY enable bit is set to "1", the analog input pin selection bits are disabled. Do not execute the A/D conversion by a program while ADKEY is enabled. Enabling ADKEY does not change bits 0 to 2 of ADCON. 4. A/D Conversion Immediately After ADKEY Function Started In the ADKEY function, A/D conversion is not performed to the analog input voltage immediately after starting the function. This causes the A/D conversion result immediately after starting the function to be undefined. If the A/D conversion result of the analog input voltage applied to the ADKEY pin is required, select the analog input pin corresponding to ADKEY before performing A/D conversion. 5. Input Voltage Applied to ADKEY Pin Set the input to the ADKEY pin into a steep falling waveform and stabilize the input voltage within eight cycles (1 s when f(XIN) = 8 MHz) from the moment the input voltage reaches VIL or lower. The actual threshold voltage for the ADKEY pin is between VIH and VIL. To prevent unnecessary ADKEY operation due to noise or other factors, set the ADKEY pin voltage to VIH (0.9 VCC) or more while the input is waited. Rev.3.02 Apr 10, 2008 REJ03B0177-0302 Page 125 of 131 6. Register Operation during A/D Conversion The A/D conversion operation is not guaranteed if the following are preformed: * The CPU mode register is operated during A/D conversion operation * The AD control register is operated during A/D conversion operation * The STP or WIT instruction is executed during A/D conversion operation 7. A/D Converter Power Source Pin Connect to the A/D converter power source pin to AVSS or VSS whether the A/D conversion function is used or not. If the AVSS pin is left open, the MCU may operate incorrectly because the pin will be affected by noise or other factors. 38D2 Group Notes on LCD Drive Control Circuit 1. Setting Data to LCD Display RAM To write data to the LCD display RAM when the LCD enable bit is set to "1" and while LCD is turned on, set fixed data. Rewriting with temporary data may cause LCD to flicker. The following shows a processing example to write data to the LCD display RAM while LCD is turned on. (1) Ccorrect processing *Content at address 0040 16: "FF16" LCD on Off LCD on or off? On LCD on or off Set LCD display RAM data LRAM0 (address 004016) "FF16" Set LCD display RAM data LRAM0 (address 004016) "0016" Set fixed data to LCD display RAM (2) Incorrect processing *Content at address 0040 16: "FF16" LCD on Set LCD display RAM data LRAM0 (address 004016) "0016" LCD off Set off data to LCD display RAM Off LCD on or off? On LCD on or off Set LCD display RAM data LRAM0 (address 004016) "FF16" Set fixed data to LCD display RAM Fig. 104 Processing example when writing data to LCD display RAM While LCD Turned On Rev.3.02 Apr 10, 2008 REJ03B0177-0302 Page 126 of 131 38D2 Group 2. Executing STP Instruction Execution of the STP instruction sets the LCD enable bit (bit 3 of the LCD mode register) and bits 0 to 5 and bit 7 of the LCD power control register to "0" and the LCD panel turns off. To make the LCD panel turn on after returning from the stop mode, set these bits to "1". 5. Using No ROM Correction Function If the ROM correction function is not used, the ROM correction vector can be used as normal RAM/ROM. When using as normal RAM/ROM, be sure to set bits 1 and 0 of the ROM correction enable register to "0" (disabled). Notes on Clock Generating Circuit 3. VL3 Pin To use the LCD drive control circuit while VL3 is set to the voltage equal to VCC, apply the VCC voltage to the VL3 pin and write "1" to the V L3 connection bit of LCD power control register (address 003816)). 4. LCD Drive Power Supply Power supply capacitor may be insufficient with the division resistance for LCD power supply, and the characteristic of the LCD panel. In this case, there is the method of connecting the bypass capacitor about 0.1 - 0.33 F to V L1 - V L3 pins. The example of a strengthening measure of the LCD drive power supply is shown below. VL3 VL2 * Connect by the shortest possible wiring. * Connect the bypass capacitor to the VL1 -VL3 pins as short as possible. (Referential value:0.1-0.33 F) VL1 Fig. 105 Strengthening measure example of LCD drive power supply Notes on ROM Correction Function 1. Returning to Main Program To return to the main program from the correction program, use the JMP instruction (3-byte instruction). 2. Using ROM Correction Function If the ROM correction function is used, be sure to enable the ROM correction enable bit after setting the ROM correction register. 3. Address Do not set addresses other than the ROM area in the ROM correction address registers. Also, do not set the same address in the ROM correction address 1 register and the ROM correction address 2 register. 4. ROM Correction Process Include the ROM correction process in the program beforehand. Rev.3.02 Apr 10, 2008 REJ03B0177-0302 Page 127 of 131 1. Oscillation Circuit Constants The oscillation circuit constants vary depending on the resonator. Use values recommended by the oscillator manufacturer. A feed-back resistor is implemented between the XIN and XOUT pins (an external feed-back resistor may be required depending on conditions). As no feed-back resistor is implemented between XCIN and XCOUT, add a feedback resistor of about 10 M. 2. Transition between Modes When the MCU transits between on-chip oscillator mode, XIN mode, or low-speed mode, both the XIN and XCIN oscillations must be stabilized. Be especially careful when turning the power on and returning from stop mode. Refer to the clock state transition diagram for a transition between each mode. Also, set the frequency in the condition that f(XIN) 3 x (XCIN). When X IN mode is not used (the X IN -X OUT oscillation or external clock input to XIN is not performed), connect XIN to VCC through a resistor. 3. Oscillation Stabilization Before executing the STP instruction, set the values * to generate the wait time required for oscillation stabilization to timer 1 latch and timer 2 latch (low-order 8 bits of timer 1 and high-order 8 bits of timer 2). *Referential values (Set values according to your oscillator and system) * OSCSEL = "L" in the flash memory and QzROM versions: ..................................................................... 000516 or more * OSCSEL = "H" in the QzROM version: .....................................................................01FF16 or more 4. Low-Speed Mode, XIN Mode To use low-speed mode or X IN mode, wait until oscillation stabilizes after enabling the X IN -X OUT and X CIN -X COUT oscillation, then switch to the mode. 38D2 Group Notes on Flash Memory Mode * CPU Rewrite Mode (1) Operating Speed During CPU rewrite mode, set the system clock to 4.0 MHz or less using the main clock division ratio selection bits (bits 6 and 7 of address 003B16). (2) Prohibited Instructions During CPU rewrite mode, the instructions which reference data in the flash memory cannot be used. (3) Interrupts During CPU rewrite mode, interrupts cannot be used because they reference data in the flash memory. (4) Watchdog Timer If the watchdog timer has been running already, the internal reset by underflow will not occur because the watchdog timer is continuously cleared during program or erase operation. (5) Reset Reset is always valid. If CNVSS = "H" when a reset is released, boot mode is active. The program starts from the address stored in addresses FFFC16 and FFFD16 in boot ROM area. Notes on Watchdog Timer 1. Watchdog Timer Underflow The watchdog timer does not operate in stop mode, but it continues counting during the wait time to release the stop state and in wait mode. Write to the watchdog timer control register so that the watchdog timer will not underflow during these periods. 2. Stopping On-Chip Oscillator Oscillation When the on-chip oscillator is selected by the watchdog timer count source selection bit 2, the on-chip oscillator forcibly oscillates and it cannot be stopped. Also, in this time, set the STP instruction function selection bit to "1" at this time. Select "0" (SOURCE) for the watchdog timer count source selection bit 2 at the system which on-chip oscillator is stopped. 3. Watchdog Timer Control Register Bits 7 to 5 can be rewritten only once after a reset. After writing, rewriting is disabled because they are locked. These bits are set to "0" after a reset. Rev.3.02 Apr 10, 2008 REJ03B0177-0302 Page 128 of 131 Notes on Differences between QzROM Version and Flash Memory Version The flash memory and QzROM versions differ in their manufacturing processes, built-in ROM, memory size, and layout patterns. Because of these differences, characteristic values, operation margins, noise immunity, and noise radiation and oscillation circuit constants may vary within the specified range of electrical characteristics. When switching to the QzROM version, implement system evaluations equivalent to those performed in the flash memory version. Confirm page 11 about the differences of functions. Notes on Power Source Voltage When the power supply voltage value of the MCU is less than the value indicated in the recommended operating conditions, the MCU may not operate normally and perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power is turned off, reset the MCU when the power source voltage is less than the recommended operating conditions, and design the system so that this unstable operation does not cause errors to it. Notes on Handling Power Source Pins Before using the MCU, connect a capacitor suitable for high frequencies as a bypass capacitor between the following: The power source pin (VCC pin) and the GND pin (VSS pin) The power source pin (VCC pin) and the analog power source input pin (AVSS pin). As a bypass capacitor, a ceramic capacitor of 0.01 F to 0.1 F is recommended. Also, use the shortest possible wiring to connect a bypass capacitor between the power source pin and the GND pin and between the power source pin and the analog power source pin. Notes on Memory 1. RAM The RAM content is undefined at a reset. Be sure to set the initial value before use. 38D2 Group Notes on QzROM Version Wiring to OSCSEL pin (1) OSCSEL = L Connect the OSCSEL pin the shortest possible to the GND pattern which is supplied to the VSS pin of the microcomputer. In addition connecting an approximately 5 k resistor in series to the GND could improve noise immunity. In this case as well as the above mention, connect the pin the shortest possible to the GND pattern which is supplied to the V S S pin of the microcomputer. (2) OSCSEL = H Connect the OSCSEL pin the shortest possible to the VCC pattern which is supplied to the V CC pin of the microcomputer. In addition connecting an approximately 5 k resistor in series to the VCC could improve noise immunity. In this case as well as the above mention, connect the pin the shortest possible to the VCC pattern which is supplied to the VCC pin of the microcomputer. The OSCSEL pin is the power source input pin for the built-in QzROM. When programming in the QzROM, the impedance of the OSCSEL pin is low to allow the electric current for writing to flow into the built-in QzROM. Because of this, noise can enter easily. If noise enters the OSCSEL pin, abnormal instruction codes or data are read from the QzROM, which may cause a program runaway. Termination of OSCSEL pin (2) OSCSEL = H (1) OSCSEL = L (1) (1) The shortest The shortest VCC OSCSEL about 5 k about 5 k OSCSEL VSS (1) The shortest (1) The shortest Note 1: It shows the microcomputer's pin QzROM Version Product Shipped in Blank As for the product shipped in blank, Renesas does not perform the writing test to user ROM area after the assembly process though the QzROM writing test is performed enough before the assembly process. Therefore, a writing error of approximate 0.1% may occur. Moreover, please note the contact of cables and foreign bodies on a socket, etc. because a writing environment may cause some writing errors. Ordering QzROM Writing 1. Notes On QzROM Writing Orders When ordering the QzROM product shipped after writing, submit the mask file (extension: .msk) which is made by the mask file converter MM. * Be sure to set the ROM option data* setup when making the mask file by using the mask file converter MM.. The ROM code protect is specified according to the ROM option data* in the mask file which is submitted at ordering. Note that the mask file which has nothing at the ROM option data* or has the data other than "00 16 ", "FE 16 " and "FF 16 " can not be accepted. * Set "FF16" to the ROM code protect address in ROM data regardless of the presence or absence of a protect. When data other than "FF16" is set, we may ask that the ROM data be submitted again. * ROM option data: mask option noted in MM 2. Data Required for QzROM Ordering The following are necessary when ordering a QzROM product shipped after writing: * QzROM Writing Confirmation Form* * Mark Specification Form* * ROM data: Mask file * For the QzROM writing confirmation form and the mark specification form, refer to the "Renesas Technology Corp." Homepage (http://www.renesas.com/homepage.jsp). Note that we cannot deal with special font marking (customer's trademark etc.) in QzROM microcomputer. Fig. 106 Wiring for OSCSEL pin Overvoltage in QzROM Version Make sure that voltage exceeding the VCC pin voltage is not applied to other pins. In particular, ensure that the state indicated by bold lines in figure below does not occur for pin OSCSEL pin (VPP power source pin for QzROM) during power-on or poweroff. Otherwise the contents of QzROM could be rewritten. (1) 1.8V (2) 1.8V VCC pin voltage OSCSEL pin voltage "H" input OSCSEL pin voltage "L" input (1) Input voltage to other MCU pins rises before VCC pin voltage. (2) Input voltage to other MCU pins falls after VCC pin voltage. Note: The internal circuitry is unstable when VCC is below the minimum voltage specification of 1.8 V (shaded portion), so particular care should be exercised regarding overvoltage. Fig. 107 Timing Diagram (Bold-lined periods are applicable) Rev.3.02 Apr 10, 2008 REJ03B0177-0302 Page 129 of 131 3. QzROM Product Receiving Procedure When writing to QzROM is performed by user side, the receiving inspection by the following flow is necessary. 38D2 Group QzROM product shipped after writing QzROM product shipped in blank "protect disabled" "protect enabled to the protect area 1" Renesas Renesas Programming Shipping Verify test Shipping User Receiving inspection (Blank check) User Receiving inspection of unprotected area (Verify test) Programming Programming to unprotected area Verify test for all area Verify test for unprotected area Fig. 108 QzROM receiving procedure Notes on Flash Memory Version CPU Rewrite Mode 1. Operating Speed Rev.3.02 Apr 10, 2008 REJ03B0177-0302 Page 130 of 131 38D2 Group During CPU rewrite mode, set the system clock 4.0 MHz or less using the main clock division ratio selection bits (bits 6 and 7 of address 003B16). 2. Prohibited Instructions The instructions which refer to the internal data of the flash memory cannot be used during the CPU rewrite mode. 3. Interrupts The interrupts cannot be used during the CPU rewrite mode because they refer to the internal data of the flash memory. 4. Watchdog Timer In case of the watchdog timer has been running already, the internal reset generated by watchdog timer underflow does not happen, because of watchdog timer is always clearing during program or erase operation. 5. Reset Reset is always valid. In case of CNVSS = "H" when reset is released, boot mode is active. So the program starts from the address contained in address FFFC16 and FFFD16 in boot ROM area. CNVSS Pin The CNVSS pin determines the flash memory mode. Connect the CNVSS pin the shortest possible to the GND pattern which is supplied to the VSS pin of the microcomputer. In addition connecting an approximately 5 k. resistor in series to the GND could improve noise immunity. In this case as well as the above mention, connect the pin the shortest possible to the GND pattern which is supplied to the V S S pin of the microcomputer. Note. When the boot mode or the standard serial I/O mode is used, a switch of the input level to the CNVSS pin is required. (1) The shortest CNVSS Approx. 5k VSS (1) The shortest Note 1: It shows the microcomputer's pin. Fig. 109 Wiring for CNVSS pin Rev.3.02 Apr 10, 2008 REJ03B0177-0302 Page 131 of 131 REVISION HISTORY 38D2 Group Datasheet Rev. Date Description 1.00 Jan. 23, 2006 - First edition issued 2.00 Mar. 24, 2006 1 FEATURES : Description of reset circuit eliminated and Power source voltage revised. 3 Performance overview: Oscillation frequency and Power source voltage revised. 4 FUNCTIONAL BLOCK DIAGRAM : Description of reset circuit eliminated. 7 Fig. 4 and Table 3 38D29GC, 38D29G8 added. 12 Fig. 9 Memory map diagram revised. 15 Table 7 Non-port function of port P54-P57 revised. Related SFRs of port P40 and P41 revised. 18 Fig. 15 (18) Port P61 revised. 26 Fig. 22 Timer 12 mode register revised. 29 Notes on Timer X: (1), (2) revised. Page 32 * Real Time Port Control revised. 36 Fig. 32 UART control register revised. 38 Fig. 34 Note 1 revised. 42 Fig. 38 Note 2 revised. 48 Fig. 46 Memory map revised. 49 Note 1 revised. 50 Clock output function revised. 51 Reset circuit revised. 53 (1)Stop mode: Description revised. 54 Fig. 58 SOURCE added. 55 Fig. 60 State transitions of system clock: Note 3 revised. 56 Address of oscillation ouput control register revised. 60 65-75 2.01 Nov. 15, 2006 Summary Fig. 64 Connection of XIN and XOUT revised. Electrical characteristics added. 1 DESCRIOTION revised Power dissipation described. 3 Main clock / Sub-clock generating circuits: Built-in feed back resistor Built-in Power dissipation described. 5 AVSS: GND input pin Analog power source input pin 12 ROM and ROM Code Protect Address : Description revised. Fig. 9 is revised. 15 Table 7 : As for CKOUT, non-port function and related SFRs are added. 19 Termination of unused pins : As for I/O ports, description added. VL3 : Terminations 1 and 2 revised. 25 Timer 1, Timer 2 : Description revised. 28 Timer X : Description revised. 29 Fig. 24 : TXCON1 bit 5 = 1 TXCON1 bit 5 = 0 31 Timer Y : Description revised. Fig. 26 : Note added. 37 Fig. 33 : Note and source added. (1/4) REVISION HISTORY Rev. Date 2.01 Nov. 15, 2006 38D2 Group Datasheet Description Page LCD Power Circuit * Description added * Fig. 38 : Note 3 eliminated * Fig. 39 : Bit name described 48 Fig. 46 : Reserved ROM area address revised. ROM CORRECTION FUNCTION : Description added. 49 Fig. 48 : On-chip oscillator On-chip oscillator/4 Note added. Fig. 49 : On-chip oscillator On-chip oscillator/4 source/1024 Count sorce/1024 source/4 Count sorce/4 53 (5) Low-speed Mode : Description added 54 Fig. 58 : Note added and circuit expression is revised. 56 Fig. 61 : Circuit expression is revised. 57 Table 12: As for VREF and AVSS, function revised. 59 to 62 3.01 Sep.18, 2007 Summary 42 Fig. 63 to Fig. 66 added and revised. 71 Table 17 IIH and IIL : OSCSEL added. 75 Table 23: Note revised. - Flash memory version function: added 1 DESCRIPTION: flash memory version contents added FEATURES: flash memory version contents added Power source voltages: flash memory version contents added Power dissipation: flash memory version contents added Flash memory mode: added 2 Fig. 1: Note is added 3 Table 1: Power source voltage: revised and flash memory version contents added Power dissipation: flash memory version contents added 5 Table 2: LED0 to 7 and KW0 to 3 are added to pin name 6 Pin discription table is divided (to Table 2 and Table 3) Table 3: CNVSS pin is added 7 Fig. 3: F (Flash memory) is added to memory type 8 Flash memory size is added Fig. 4: Some "Under developing" are erased 9 Table 3: Flash memory version products are added 10 Table 5 "Differences between QzROM and flash memory versions" and "Notes on Differences between QzROM and Flash Memory Versions" are added 12 Fig. 6: "Push contents of processor status register on stack" position is moved 14 CPU mode register explanation is revised Fig. 7: Some notes are added 15 Fig. 8: Flash memory version flow is added 16 Fig. 9: Flash memory version SRF is added 17 Fig. 10: Flash memory version SRF and notes are added 19 Table 2: LED0 to 7 and KW0 to 3 are added to pin name 24-28 "Interrupt" is wholly revised 32 "Frequency Divider for Timer" is revised 35 "Frequency Divider for Timer" is revised (2/4) REVISION HISTORY Rev. Date 3.01 Sep.18, 2007 38D2 Group Datasheet Description Page Summary 35 "(6) Pulse Width Measurement Mode" is revised 36 "(3) Write To Timer X" is revised 37 "(7) When Timer X Pulse Width Measurement Mode Used" 38 "(5) Real Time Port Control" is added 39 "Notes on Timer Y" is revised 44 "Conparator and Control Circuit" is revised 45 Fig. 37: Revised "ADKEY Control Circuit" is revised 56 "Initial value of watchdog timer" is revised "Bit 6 of Watchdog Timer Control Register" and "" are revised Fig. 51: Revised Fig. 52: Revised 57 Fig. 54: Revised "[RRF register (RRFR)]" is added 58 Explaination is revised Fig. 56: revised Fig. 57: Notes are added 59 Fig. 58: Revised 60 Explanation is revised 62 Fig. 61: Revised 63 Fig. 62: Revised 65 Table 14: Revised 71-88 "Flash Memory Mode" is added 89 Revised to "Notes on Use" from "Notes on Programming" contents 90 Added "NOTES on QzROM VERSION" 91 Added "NOTES on FLASH MEMORY VERSION" and "NOTES ON DIFFERENCES BETWEEN QzROM VERSION AND FLASH MEMORY VERSION" 94 Table 21: Revised 95-101 Table 22 to 29: "VSS=0V" are added to condition 95 Table 22: VIL of XCIN is deleted 98 Table 25: "VCC = 4.0 t o 5.0 V" "VCC = 1.8 to 5.5 V" 100 Table 28: * ABS of 10bitAD mode "2.2V < VCC 4.0V" "2.2V VCC 4.0V" "1.8V VCC 5.5V" "2.0V VCC 5.5V" * ABS of 8bitAD mode "2.2V < VCC 4.0V" "2.2V VCC 4.0V" "1.8V VCC 5.5V" "2.0V VCC 5.5V" * tCONV is separated to 10bitAD mode and 8bitADmode, and note is added 102 Table 30: TC, TwH, and TwL of XIN "4.5 V to 5.5 V" "4.5V VCC 5.5V" "4.0 V to 5.5 V" "4.0V VCC 5.5V" Table 31: TC of XIN and CNTR, and TwH and TwL of XIN "2.0V < VCC 4.0V" "2.0V VCC 4.0V" "VCC 2.0V" "VCC < 2.0V" 104 Fig. 95: XCIN timing is deleted 105-115 Flash memory version electrical characteristics is added (3/4) REVISION HISTORY 38D2 Group Datasheet Rev. Date Description 3.01 Sep.18, 2007 118-131 3.02 Apr. 09, 2008 2 Fig. 1: Revised 3 Table 1: Revised Page Summary Appendix is added 5 Table 2: Revised 18 "Direction Registers": Peripheral output name is added and deleted 21 Fig. 14: Revised 23 Table 9: Revised 25 "External Interrupt Pin Selection" is deleted 26 Fig. 17:Revised 29 Port name is revised 34 Fig. 26: Revised 38 "Timer Y" is revised 44 Fig. 36: Revised 49 Fig. 41: Revised 57 Fig. 53 and 54 are revised 58 Fig. 56: Revised 63 Fig. 63: Revised 64 Fig. 63: Revised 65 Table 14: Revised 66 Fig. 65: Revised 74 Fig. 73: Revised 85 Fig. 80: Revised 86 Fig. 81: Revised 90 Notes On ROM Code Protect is revised 95 Table 22: Revised 99 Table 27: Revised 102 Table 30: Revised 109 NOTE of Table 38: Revised 110 Table 40: Revised 129 Notes On ROM Code Protect is revised (4/4) Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. 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