CYII4SM6600AB-QDC - CYPRESS SEMICONDUCTOR

February, 2013 − Rev. 14

1Publication Order Number:

NOII4SM6600A/D

NOII4SM6600A

6.6 Megapixel CMOS Image

Sensor

Features

•2210 (H) x 3002 (V) Active Pixels

•3.5 mm x 3.5 mm Square Pixels

•1 inch Optical Format

•Monochrome Output

•Frame Rate:

♦5 fps for Active Window of 2210 x 3002

♦89 fps for Active Window of 640 x 480

•High Dynamic Range Modes: Double Slope, Non Destructive

Read out (NDR)

•Electronic Rolling Shutter

•Master Clock: 40 MHz

•Single 2.5 V Supply

•3.3 V Supply for Extended Dynamic Range

•−30°C to +65°C Operational Temperature Range

•68-Pin LCC Package

•Power Dissipation: 225 mW

•These Devices are Pb−Free and are RoHS Compliant

Applications

•Machine Vision

•Biometry

•Document Scanning

Description

The IBIS4-6600 is a solid-state CMOS image sensor that integrates complete analog image acquisition, and a digitizer and

digital signal processing system on a single chip. This image sensor has a resolution of 6.6 MPixel with 2210 x 3002 active

pixels. The image size is fully programmable for user-defined windows. The pixels are on a 3.5 mm pitch.

The user programmable row and column start and stop positions enable windowing down to 2x1 pixel window for digital

zoom. Subsampling reduces resolution while maintaining the constant field of view. The analog video output of the pixel

array is processed by an on-chip analog signal pipeline. Double Sampling (DS) eliminates the fixed pattern noise.

The programmable gain and offset amplifier maps the signal swing to the ADC input range. A 10-bit ADC converts the

analog data to a 10-bit digital word stream. The sensor uses a three-wire Serial-Parallel (SPI) interface. It operates with a

single 2.5 V power supply and requires only one master clock for operation up to 40 MHz. It is housed in a 68-pin ceramic

LCC package.

This data sheet enables the development of a camera system, based on the described timing and interfacing given in the

following sections.

ORDERING INFORMATION

Marketing Part Number Description Package

NOII4SM6600A-QDC Mono with Glass 68 pin LCC

NOTE: For more information, see Ordering Code Definition on page 29.

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Figure 1. IBIS4−6600 Image Sensor

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CONTENTS

Features 1.....................................

Applications 1.................................

Description 1..................................

Ordering Information 1.........................

Contents 2....................................

Specifications 3................................

General Specifications 3.........................

Electro Optical Specifications 3...................

Spectral Response Curve 4......................

Electro Voltaic Response Curve 5................

Electrical Specifications 6......................

Sensor Architecture 7...........................

Floor Plan 7.................................

Pixel 8.....................................

Output Amplifier 8............................

Analog to Digital Converter 11...................

Serial to Parallel Interface (SPI) 11................

Sensor Operation 12.............................

Pixel Rate 12.................................

Region of Interest (ROI) Read Out 12..............

Subsampling Modes 12.........................

Electronic Shutter 15...........................

High Dynamic Range Modes 16..................

Sequencer and Registers 17.......................

Description of Registers 19......................

Timing Diagrams 23.............................

Sequencer Control Signals 23....................

Basic Frame and Line Timing 23..................

Pixel Output Timing 24.........................

ADC Timing 25...............................

Package Information 26..........................

Pin List Description 26.........................

Package Outline Drawing 29.....................

Mechanical Specifications 30......................

Glass Lid 31..................................

Handling Precautions 31.........................

Limited Warranty 31............................

Return Material Authorization (RMA) 31...........

Acceptance Criteria Specification 31...............

Ordering Code Definition 31......................

Acronyms 32...................................

Glossary 33....................................

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SPECIFICATIONS

GENERAL SPECIFICATIONS

Parameter Specification Remarks

Pixel Architecture 3T-Pixel

Pixel Size 3.5 mm x 3.5 mmThe resolution and pixel size results in a 7.74 mm x 10.51 mm

optical active area.

Resolution 2210 x 3002

Pixel Rate 40 MHz Using a 40 MHz system clock and 1 or 2 parallel outputs

Shutter Type Electronic Rolling Shutter

Full Frame Rate 5 frames/second Increases with ROI read out and/or subsampling

ELECTRO OPTICAL SPECIFICATIONS

Parameter Specification Remarks

FPN (local) <0.20%, 2 LSB10 %RMS of saturation signal

PRNU (local) <1.5% RMS of signal level

Conversion Gain 43 mV/e-At output (measured)

Output Signal Amplitude 0.6 V At nominal conditions

Saturation Charge 21500 e-

Sensitivity (peak) 411 V.m2/W.s

4.83 V/lux.s

At 650 nm

(85 lux = 1 W/m2)

Sensitivity (visible) 328 V.m2/W.s

2.01 V/lux.s

400-700 nm

(163 lux = 1 W/m2)

Peak QE * FF

Peak Spectral Response

25%

0.13 A/W

Average QE*FF = 22% (visible range)

Average SR*FF = 0.1 A/W (visible range)

See the section Spectral Response Curve on page 4.

Fill Factor 35% Light sensitive part of pixel (measured)

Dark Current 3.37 mV/s

78 e-/s

Typical value of average dark current of the whole pixel array

(at 21°C)

Dark Signal Non Uniformity 8.28 mV/s

191 e-/s

Dark current RMS value (at 21°C)

Temporal Noise 24 RMS e- Measured at digital output (in the dark)

Signal/Noise Ratio 895:1 (40 dB) Measured at digital output (in the dark)

Dynamic Range 59 dB

Spectral Sensitivity Range 400 - 1000 nm

Optical Cross Talk 15%

To the first neighboring pixel

To the second neighboring pixel

Power Dissipation 225 mW Typical (including ADCs)

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Spectral Response Curve

0.02

0.04

0.06

0.08

0.1

0.12

0.14

400500600700800900 1000

Wavelenght [nm]

Spectral response [A/W]

QE 10%

QE 20%

QE 30%

Figure 2. Spectral Response Curve

Figure 2 shows the characteristics of the spectral response.

The curve is measured directly on the pixels. It includes the

effects of nonsensitive areas in the pixel, for example,

interconnection lines. The sensor is light sensitive between

400 and 1000 nm. The peak QE x FF is 25% approximately

650 nm. In view of a fill factor of 35%, the QE is close to

70% between 500 and 700 nm.

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Electro Voltaic Response Curve

Figure 3. Electro Voltaic Response Curve

0.1

0.2

0.3

0.4

0.5

0.6

0.7

# electrons

Output swing [V]

5000 10000 15000 20000 25000

Figure 3 shows the pixel response curve in linear response

mode. This curve is the relation between the electrons

detected in the pixel and the output signal. The resulting

voltage-electron curve is independent of any parameters, for

example, integration time. The voltage to electrons

conversion gain is 43 mV/electron.

Table 1. FEATURES AND GENERAL SPECIFICATIONS

Feature Specification/Description

Electronic shutter type Rolling shutter

Integration time control 60 ms - 1/frame period

Windowing (ROI) Randomly programmable ROI read out

Sub Sampling Modes Several sub sample modes can be programmed (refer Table 8 on page 12)

Extended Dynamic Range Dual slope (up to 90 dB optical dynamic range) and nondestructive read out mode

Analog Output The output rate of 40 Mpixels/s can be achieved with two analog outputs, each working at

20 Mpixel/s

Digital Output Two on-chip 10-bit ADCs at 20 Msamples/s are multiplexed to one digital 10-bit output at

40 Msamples/s

Supply Voltage VDD Nominal 2.5 V (some supplies require 3.3 V for extended dynamic range)

Logic Levels 2.5 V

Interface Serial Peripheral Interface (SPI)

Package 68-pin LCC

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Electrical Specifications

Table 2. RECOMMENDED OPERATING RATINGS (Notes 1 and 3)

Symbol Description Min Max Units

TJOperating temperature range -30 65 °C

Table 3. ABSOLUTE MAXIMUM RATINGS (Notes 2, 3 and 4)

Symbol Parameter Min Max Units

VDD (Note 5) DC Supply Voltage –0.5 4.3 V

VIN DC Input Voltage –0.5 (VDD + 0.5) V

VOUT DC Output Voltage –0.5 (VDD + 0.5) V

TS (Note 3) Storage Temperature –30 +85 °C

%RH Humidity (Relative) -85% at 85°C

Electrostatic discharge (ESD) Human Body Model (HBM) (Note 3) V

Charged Device Model (CDM)

LU Latch-up (Note 4) mA

1. Operating ratings are conditions in which operation of the device is intended to be functional. All parameters are characterized for DC

conditions after thermal equilibrium is established. Unused inputs must always be tied to an appropriate logic level, for example, VDD or GND.

2. Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade

device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified

is not implied.

3. This device does NOT contain circuitry to protect the inputs against damage caused by high static voltages or electric fields.

ON Semiconductor recommends that customers become familiar with, and follow the procedures in JEDEC Standard JESD625−A. Refer

to Application Note AN52561.

4. The IBIS4−6600 does not have latchup protection.

5. VDD = VDDD = VDDA (VDDD is supply to digital circuit, VDDA to analog circuit).

All parameters are characterized for DC conditions after

thermal equilibrium is established. Unused inputs must

always be tied to an appropriate logic level, for example,

VDD or GND. The IBIS4-6600 is extremely susceptible to

noise on the power supplies. In addition, it has no power

supply filtering on chip. Therefore, all power supplies to the

sensor must be clean with the target being to achieve a low

noise (1 mV). Special attention must be given to the pixel

supplies VPIX, GND_AB, VRESET and VRESET_DS.

Table 4. RECOMMENDED DC OPERATING CONDITIONS

Parameter Description Typical

Dynamic

Currents

Min Typ (V) Max

VDD_PIX VDD of pixel core -5% 2.5 V 5%

VDD_RESET Reset voltage. Highest voltage to the chip. 3.3V for

extended dynamic range or ‘hard reset’

-5% 2.5 V 3.3 V

VDD_RESET_DS Variable reset voltage (dual slope) -5% 2.5 V 5%

VDDA VDD of analog supply 3 mA -5% 2.5 V 5%

VDDA_ADC Analog supply to the ADC 53 mA -5% 2.5 V 5%

VDDAMP VDD of analog output. (Can be connected to VDDA)20 mA -5% 2.5 V 5%

VDDD VDD of digital supply 3 mA -5% 2.5 V 5%

VDDD_ADC Digital supply to the ADC 10 mA -5% 2.5 V 5%

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SENSOR ARCHITECTURE

Floor Plan

re s e t

select

analog output

(2)

eos _yl

eos _yr

tri l

tri r

DAC in

ADC , 10 bit

sequencer

IMAGE CORE

SENSOR

SPI

pixel array

addres s able x−s hift regis ter + s ub−s ampling

addres s able y−shift register + sub−s ampling

column ampliﬁers

re s e t a nd s e le c t drivers

clk_y

sync_yl

Pixel (0,0)

DAC

addressable y−shift register + sub−sampling

clk_y

sync_y

Dig. logic Dig. logic

address &

data bus

Figure 4. Floor Plan

2210 x 3002

(excl. dark +

dummy pixels)

Figure 4 shows the architecture of the designed image

sensor. It consists of the pixel array, shift registers for the

readout in x and y direction, parallel analog output

amplifiers, and column amplifiers that correct for the fixed

pattern noise caused by threshold voltage nonuniformities.

Reading out the pixel array starts by applying a y clock pulse

to select a new row, followed by a calibration sequence to

calibrate the column amplifiers (row blanking time).

Depending on external bias resistors and timing, typically

this sequence takes about seven seconds every line

(baseline). This sequence is necessary to remove the Fixed

Pattern Noise of the pixel and of the column amplifiers

themselves (by a Double Sampling technique). Pixels can

also be read out in a nondestructive manner.

Two DACs are added to make the offset level of the pixel

values adjustable and equal for the two output buses. A third

DAC is used to connect the buses to a stable voltage during

the row blanking period, or reset the buses continuously in

case of a nondestructive readout.

Two 10-bit ADCs running at 20 Msamples/s convert the

analog pixel values. The digital outputs are multiplexed to

one digital 10-bit output at 40 Msamples/s. Note that these

blocks are electrically completely isolated from the sensor

part, except for the multiplexer, for which the settings are

uploaded through the shared address and data bus.

The x and y shift registers have a programmable starting

point. The possibilities of the starting point are limited

because of limitations imposed by subsampling

requirements. The start address is uploaded through the

serial to parallel interface.

Most of the signals for the image core shown in Figure 4

are generated on-chip by the sequencer. This sequencer also

allows running the sensor in basic modes, not fully

autonomous.

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Pixel

Architecture

The pixel architecture is the classic three-transistor pixel,

as shown in Figure 5. The pixel is implemented using the

high fill factor technique patented by FillFactory (US patent

No. 6,225,670 and others)

Figure 5. 3T Pixel Architecture

selec

Vdd

reset

output

(column)

select

FPN and PRNU

Fixed Pattern Noise correction is done on-chip. Raw

images taken by the sensor typically feature a residual

(local) FPN of 0.35% RMS of the saturation voltage.

The Photo Response Non Uniformity (PRNU), caused by

the mismatch of photodiode node capacitances, is not

corrected on chip. Measurements indicate that the typical

PRNU is about 1.5% RMS of the signal level.

Dark and Dummy Pixels

Figure 6 shows a plan of the pixel array. The sensor is

designed in portrait orientation. A ring of dummy pixels

surrounds the active pixels. Black pixels are implemented as

“optical” black pixels.

Figure 6. Floor Plan Pixel Array

Dummy ring of pixels ,

surrounding complete pixel

a rra y. not re a d

Ring of 2 dummy pixels ,

illuminate d, readable

array of active pixels , read

3002x 2210

Ring of dummy pixels ,

covered with black layer,

readable

2222

3014

2210

3002

Output Amplifier

The output amplifier subtracts the reset and signal

voltages from each other to cancel FPN as much as possible

(shown in Figure 7). The DAC that is used for offset

adjustment consists of two DACs. One DAC is used for the

main offset (DAC_raw). The other enables fine tuning to

compensate the offset difference between the signal paths

arriving at the two amplifiers A1 and A2 (DAC_fine). With

the analog multiplexer, the signals S1 and S2 from the two

buses can be combined to one pixel output at full pixel rate

(40 MHz). However, the two analog signals S1 and S2 can

also be available on two separate output pins to allow a

higher pixel rate.

The third DAC (DAC_dark) puts its value on the buses

during the calibration of the output amplifier. In case of

nondestructive readout (no double sampling), bus1_R and

bus2_R are continuously connected to the output of the

DAC_fine to provide a reference for the signals on bus1_S

and bus2_S.

The complete output amplifier can be put in standby by

setting the corresponding bit in the AMPLIFIER register.

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Figure 7. Output Amplifier Architecture

−

bus1_R

bus1 S

bus2_R

bus2 S

DAC_raw /

DAC_fine

Pixel output

Pixel output 2

programmable

gain amplifiers

S1 1

DAC_dark

Stage 1 Stage 2 Stage 3

output

drivers

analog

multiplexer

Stage 1: Offset, FPN Correction, and Multiplexing

In the first stage, the signals from the buses are subtracted

and the offset from the DACs is added. After a system reset,

the analog multiplexer is configured for two outputs (see the

bit settings in the AMPLIFIER register on page 22. ) In case

ONE_OUT is set to 1, the two signals S1 and S2 are

multiplexed to one output (output 1). The amplifiers of Stage

2 and Stage 3 of the second output path are then put in

standby. The speed and power consumption of the first stage

can be controlled through the resistor connected to

CMD_OUT_1.

Stage 2: Programmable Gain Amplifier

The second stage provides the gain, which is adjustable

between 1.36 and 17.38 in steps of approximately 20.25

(~1.2). An overview of the gain settings is given in Table 5.

The speed and power consumption of the second stage can

be controlled through the resistor connected to

CMD_OUT_2.

Table 5. PGA GAIN SETTINGS

Bits DC Gain Bits DC Gain

0000 1.36 1000 5.40

0001 1.64 1001 6.35

0010 1.95 1010 7.44

0011 2.35 1011 8.79

0100 2.82 1100 10.31

0101 3.32 1101 12.36

0110 3.93 1110 14.67

0111 4.63 1111 17.38

Stage 3: Output Drivers

The speed and power consumption of the third stage can

be controlled through the resistor connected to

CMD_OUT_3. The output drivers are designed to drive a 20

pF output load at 40 Msamples/s with a bias resistor of

100 kW.

Offset DACs

Figure 8 shows how the DAC registers influence the black

reference voltages of the two different channels. The offset

is mainly given through DAC_raw. DAC_fine can be used

to shift the reference voltage of bus 2 up or down to

compensate for different offsets in the two channels.

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Figure 8. Offset for the Two Channels through DAC_RAW and DAC_FINE

DAC_raw

DAC_RAW_REG<0:7

out

DAC_fine

VDDA

out

10K

200K

50K

10K

200K

blackref

bus1

blackref

bus2

GNDA

DAC_FINE_REG<0:7

rcal

pad RCAL_DAC_OUT

floating

RCAL

VCAL

Note that in this figure, “K” represents KW

Assume that Voutfull is the voltage that depends on the bit values that are applied to the DAC and ranges from:

Voutfull:0(bitvalues00000000) ³VDDAǒ1 *1

28Ǔ(bitvalues11111111)

Externally, the output range of DAC_raw can be changed by connecting a resistor Rcal to RCAL_DAC_OUT and applying

a voltage Vcal. The output voltage Vout of DAC_raw follows the relation (R = 10 kW).

Vout+R)Rcal

2R)Rcal

Voutfull)R

2R)Rcal

Vcal

Special case:

Rcal = “open” (infinite resistance), then Vout = Voutfull (for example, for DAC_fine)

Rcal = 0 ohms “short” and Vcal = GND, then Vout = Voutfull/2

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Analog to Digital Converter

The IBIS4-6600 has a two 10-bit flash analog digital

converters. The ADCs are electrically separated from the

image sensor. The inputs of the ADC must be tied externally

to the outputs of the output amplifiers. One ADC samples

the even columns and the second ADC samples the odd

columns. Alternatively, one ADC can also sample all the

pixels.

The sensor’s outputs are not designed to drive large loads.

Therefore, to drive a cable or long PCB trace, the outputs of

the sensor should be buffered.

Table 6. ADC SPECIFICATIONS

Parameter Specification

Input Range Set by External Resistors

(Refer the section The internal resist-

ance has a value of approximately

577 W. Only 277 W of this internal

resistance is actually used as reference

for internal ADC.)

Quantization 10 Bits

Nominal Data Rate 20 Msamples/s

DNL Typical: 1.5 LSB10

INL Typical: 5 LSB10

Input Capacitance < 2 pF

Conversion Law Linear/Gamma corrected

The internal resistance has a value of approximately

577 W. Only 277 W of this internal resistance is actually used

as reference for the internal ADC.

Black Calibration

Due to slight variations in the chip fabrication process, the

output analog voltage of the PGA is not perfectly matched

to the input analog range of the ADC. As a result, a reduced

dynamic range is obtained when comparing

sensors/cameras from different lots. This is especially true

in the dark as it is possible that a part of the analog range gets

clipped when it reaches the ADC.

For this reason, black calibration step is required. Because

this is a fixed setting, and varies very slightly with

temperature, the setting can be done at the factory itself.

While grabbing normal images, the settings can be loaded

from an on-board memory.

In the IBIS4-6600 image sensor, black calibration step

also tries to match the output of the odd and even channels.

The steps for black calibration are -

1. Put the sensor in dark.

2. Change DAC_RAW such that no pixel or least

number of pixels (assuming there are defect

pixels) have a zero ADC output value.

3. Change DAC_FINE such that the average of the

odd columns is almost same as the even columns.

4. Change DAC_RAW again such that all pixels have

a non-zero output, but are as close to zero as

possible.

5. Record the DAC_RAW and DAC_FINE values.

6. Load the recorded DAC register values during

operation.

Serial to Parallel Interface (SPI)

To upload the sequencer registers, a dedicated serial to

parallel interface (SPI) is implemented. 16 bits (4 address

bits + 12 data bits) must be uploaded serially. The address

must be uploaded first (MSB first), then the data (also MSB

first).

The elementary unit cell is shown in Figure 9. Sixteen of

these cells are connected in series, having a common

SPI_CLK form the entire uploadable parameter block. Dout

of one cell is connected to SPI_DATA of the next cell

(maximum speed is 20 MHz). The uploaded settings on the

address/data bus are loaded into the correct register of the

sensor on the rising edge of signal REG_CLOCK and

become effective immediately.

Figure 9. SPI Interface

SPI_DATA

To address/data bus

Dout

SPI_CLK

REG_CLOCK

16 outputs to address/data bus

SPI_CLK

SPI_DATA

Unity C ell

Entire uploadable address block

REG_CLOCK

A3A12

REG_CLOCK

SPI_CLK

Internal register

upload

SPI_DATA D0

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SENSOR OPERATION

Pixel Rate

The pixel rate for this sensor is high enough to support a

frame rate greater than 75 Hz for a window size of 640 x 480

pixels (VGA format). With a row blanking time of 7.2 ms (as

baseline, refer the following calculations), requires a

minimum pixel rate of approximately 40 MHz. The

bandwidth of the column amplifiers, gain amplifiers and

output stage are determined by external bias resistors.

Taking into account a pixel rate of 40 MHz, a full frame rate

of a little more than 5 frames/s is obtained

The frame period of the IBIS4-6600 sensor is calculated

as:

=> Frame period = (Nr. Lines * (RBT + pixel period * Nr.

Pixels))

In this equation:

Nr. Lines: Number of Lines read out each frame (Y)

Nr. Pixels: Number of pixels read out each line (X)

RBT: Row Blanking Time = 7.2 ms (typical)

Pixel period: 1/40 MHz = 25 ns

Example: Read out time of the full resolution at nominal

speed (40 MHz pixel rate):

=> Frame period = (3002 * (7.2 ms + 25 ns * 2210)) =

187.5 ms => 5.33 fps.

Region of Interest (ROI) Read Out

Windowing is easily achieved by uploading the starting

point of the x and y-shift registers in the sensor registers

(refer Table 11 on page 17). This downloaded starting point

initiates the shift register in the x and y-direction, triggered

by the Y_START (initiates the Y-shift register) and the

Y_CLK (initiates the X-shift register) pulse. The minimum

step size for the X-address and Y-address is 24 pixels. The

frame rate increases in an almost linear manner when fewer

pixels are read out. Table 7 lists the achievable frame rates

with ROI read out.

Table 7. FRAME RATE VS. RESOLUTION

Image Resolution (Y*X) Frame Rate [frames/s] Frame Readout Time [ms] Comment

3002 x 2210 5 187.5 Full resolution

1501 x 1104 14 67 ROI read out

640 x 480 89 11 11

Subsampling Modes

To increase the frame rate for lower resolution and regions

of interest, several sub sampling modes are implemented.

The possible sub sample modes are listed in Table 8. The bits

can be programmed in the IMAGE_CORE register (refer

Table 11 on page 17). Two adjacent pixels are read in any

mode. The number of pixels that is not read varies from

mode to mode. This is designed as a repeated block 24 pixels

wide, which is the lowest common multiple of the modes

described. Including the dummy pixels and the two

additional rows/columns, the number of starting coordinates

for the x and y shift register is 99 in the X direction and 138

in the Y direction. The total number of pixels, excluding

dummy pixels, is a multiple of 24, and two additional pixels

to have the same window edges independently of the sub

sampling mode.

In the X direction, two columns are always addressed at

the same moment, because the signals from the odd and even

columns must be put simultaneously on the corresponding

bus. In the Y direction, the rows are addressed one by one.

This results in slightly different implementations of the

sub-sampling modes for the two directions (Refer Figure 10

and Figure 11 on page 14).

Table 8. SUBSAMPLE PATTERNS

Mode Bits Read Step Description

A 000 2 2 Default mode

B 001 2 4 (Skip 2)

C 010 2 6 (Skip 4)

D 011 2 8 (Skip 6)

E 1xx 2 12 (Skip 10)

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Shift register Logic selecting 2 collumns

24 column amplifiers

bus1_S

bus1_R

bus2_S

bus2_R

scan direction

Figure 10. X−Sub Sampling

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Figure 11. Y−Sub Sampling

gshift re isters on pixel pitch

Lo ic selectin 1 row

scan direction

Table 9. FRAME RATE VS. SUB SAMPLE MODE

Mode Ratio Resolution (Y*X) Frame time [mS] Frame time [mS]

A 1:1 3002 x 2210 187.4 5.3

B 1:4 1502 x 1106 52.3 19.1

C 1:9 1002 x 738 25.7 38.9

D 1:16 752 x 554 15.8 63.2

63.2 1:36 502 x 370 8.2 121.2

VGA (p) 640 x 480 12.3 81.5

VGA (p) + 23 663 x 503 13.1 76.4

VGA (l) 480 x 640 11.1 89.9

VGA(l) + 23 503 x 663 11.9 83.7

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Electronic Shutter

An electronic shutter similar to a rolling curtain is

implemented on-chip. As shown in Figure 13, there are two

Y shift registers. One shift register points to the row that is

currently being read out. The other shift register points to the

row that is currently being reset. Both pointers are shifted by

the same Y-clock and move over the focal plane. The

integration time is set by the delay between both pointers.

Figure 12. Electronic Shutter

Integration

time

Readout

pointer

Reset

pointer

In case of a mechanical shutter, the two shift registers can

be combined to simultaneously apply the pulses from both

sides of the pixel array. This is to halve the influence of the

parasitic RC times of the reset and select lines in the pixel

array. This can result in a reduction of the row blanking time.

This is the case when FAST_RESET in the SEQUENCER

and 2.

Time axis

Line number Reset sequence

Frame time Integration time

Figure 13. Electronic Rolling Shutter Operation

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High Dynamic Range Modes

Double Slope Integration

The IBIS4-6600 has a feature called double slope

integration to increase the optical dynamic range of the

sensor. The pixel response can be extended over a larger

range of light intensities by using a ”dual slope integration”.

This is obtained by adding charge packets from a long and

a short integration time in the pixel during the same exposure

time. Figure 14 shows the response curve of a pixel in dual

slope integration mode. The curve also shows the response

of the same pixel in linear integration mode at the same light

levels, with a long and short integration time.

Dual slope integration is obtained by feeding a lower

supply voltage to VDD_RESET_DS (for example, apply

2.0 V). Note that for normal (single slope) operation,

VDD_RESET_DS must have the same value as

VDD_RESET. The difference between VDD_RESET_DS

and VDD_RESET determines the range of the high

sensitivity, and as a result the output signal level at which the

transition between high and low sensitivity occurs.

Put the amplifier gain to the lowest value where the analog

output swing covers digital input swing of the ADC.

Increasing the amplification too much may boost the high

sensitivity part over the whole ADC range.

The electronic shutter determines the ratio of integration

times of the two slopes. The high sensitivity ramp

corresponds to “no electronic shutter”, thus maximal

integration time (frame read out time). The low sensitivity

ramp corresponds to the electronic shutter value that is

obtained in normal operation.

Figure 14. Double Slope Response

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

0%20% 40% 60% 80% 100%

Relative exposure (arbitrary scale)

Out put signal [V]

Dual slope operation

Long integration time

Short integration time

NonDestructive Read Out (NDR)

The default mode of operation of the sensor is with FPN

correction (double sampling). However, the sensor can also

be read out in a nondestructive method. After a pixel is

initially reset, it can be read multiple times, without being

reset. The initial reset level and all intermediate signals can

be recorded. High light levels saturate the pixels quickly, but

a useful signal is obtained from the early samples. For low

light levels, use the later or latest samples. Essentially an

active pixel array is read multiple times, and reset only once.

The external system intelligence interprets the data. Table 10

on page 17 summarizes the advantages and disadvantages of

nondestructive readout.

Figure 15. Principle of NonDestructive Read Out

time

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Table 10. NDR: ADVANTAGES AND DISADVANTAGES

Advantages Disadvantages

Low Noise, because it is true CDS. In the order of 10 e- or below. System memory required to record the reset level and the

intermediate samples.

High Sensitivity, because the conversion capacitance is kept rather

low.

Requires multiples readings of each pixel, thus higher data

throughput.

High Dynamic Range, because the results include signals for short

and long integrations times.

Requires system level digital calculations.

SEQUENCER AND REGISTERS

Figure 4 on page 7 showed several control signals that are

needed to operate the sensor in a particular sub sampling

mode, with a certain integration time, output amplifier gain,

and more. Most of these signals are generated on-chip by the

sequencer that uses only a few control signals. These control

signals must be generated by the external system

•SYS_CLOCK, which defines the pixel rate (nominal

40 MHz),

•Y_START pulse, which indicates the start of a new

frame,

•Y_CLOCK, which selects a new row and starts the row

blanking sequence, including the synchronization and

loading of the X-register.

The relative position of the internal pulses is determined

by a number of data bits that are uploaded in internal

registers through a Serial to Parallel interface (SPI).

Internal Registers

Table 11 lists the internal registers with a short

description. The registers are discussed in more detail in the

following sections.

On power-on, all the internal register of the IBIS4-6600

are reset to 0. All the sensor registers must to be loaded

before the sensor is brought out of reset.

Table 11. LIST OF INTERNAL REGISTERS

0 (0000) 11:0 SEQUENCER register Selection of mode, granularity of the X sequencer clock, calibration,

Default value <11:0>:“000100000000”

0 NDR Mode of readout:

NDR = 0: normal readout (double sampling)

NDR = 1: non-destructive readout

1:2 NDR_mode 4 different modes of nondestructive readout (no influence if NDR = 0)

3 RESET_BLACK 0 = normal operation

1 = reset of pixels before readout

4 FAST_RESET 0 = electronic shutter operation

1 = addressing from both sides

5 FRAME_CAL_MODE 0 = fast

1 = slow

6 LINE_CAL_MODE 0 = fast

1 = slow

7 CONT_CHARGE 0 = normal mode

1 = continuous precharge

8 GRAN_X_SEQ_LSB Granularity of the X sequencer clock

9 GRAN_X_SEQ_MSB

10 BLACK 0 = normal mode

1 = disconnects column amplifiers from buses, output of amplifier equals dark refer-

ence level

11 RESET_ALL 0 = normal mode

1 = continuous reset of all pixels

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Table 11. LIST OF INTERNAL REGISTERS

1 (0001) 10:0 NROF_PIXELS Number of pixels to count (X direction). Max. 2222/2 (2210 real + 12 dummy pixels).

Default value <10:0>:“01000000000”

2 (0010) 11:0 NROF_LINES Number of lines to count (Y direction)

Max. 3014 (3002 real + 12 dummy pixels)

Default value <11:0>:“101111000110”

3 (0011) 11:0 INT_TIME Integration time

Default value <11:0>:“000000000001”

4 (0100) 7:0 DELAY Delay of sequencer pulses

Default value <7:0>:“00000011”

0:3 DELAY_PIX_VALID Delay of PIX_VALID pulse

4:7 DELAY_EOL/EOF Delay of EOL/EOF pulses

5 (0101) 6:0 X_REG X start position (0 to 98)

Default value <6:0>:“0000000”

6 (0110) 7:0 Y_REG Y start position (0 to 137)

Default value <7:0>:“00000000”

7 (0111) 7:0 IMAGE CORE register Default value <7:0>:“00000000”

1:0 TEST_mode LSB: odd, MSB: even

0 = normal operation

4:2 X_SUBSAMPLE sub sampling mode in X-direction

7:5 Y_SUBSAMPLE sub sampling mode in X-direction

8 (1000) 9:0 AMPLIFIER register Default value <9:0>:“0000010000”

3:0 GAIN<3:0> Output amplifier gain setting

4 UNITY 0 = gain setting by GAIN<3:0>

1 = unity gain setting

5 ONE_OUT 0 = two analog outputs

1 = multiplexing to one output (out_1)

6 STANDBY 0 = normal operation

1 = amplifier in standby mode

7:9 DELAY_CLK_AMP Delay of pixel clock to output amplifier

9 (1001) 7:0 DAC_RAW_REG Amplifier DAC raw offset

Default value <7:0>:“10000000”

10 (1010) 7:0 DAC_FINE_REG Amplifier DAC fine offset

Default value <7:0>:“10000000”

11 (1011) 7:0 DAC_DARK_REG DAC dark reference on output bus

Default value <7:0>:“10000000”

12 (1100) 10:0 ADC register Default value <10:0>:“00000000000”

0 STANDBY_1 0 = normal operation

1 = ADC in standby

1 STANDBY_2

2 ONE 0 = multiplexing of two ADC outputs

1 = disable multiplexing

3 SWITCH if ONE = 0: delay of output with one (EXT_CLK = 0) or half (EXT_CLK = 1) clock cycle

if ONE = 1: switch between two ADCs

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Table 11. LIST OF INTERNAL REGISTERS

12 (1100) 4 EXT_CLK 0 = internal clock (same as clock to X shift register and output amplifier)

1 = external clock

5 TRISTATE 0 = normal operation

1 = outputs in tristate mode

6:8 DELAY_CLK_ADC Delay of clock to ADCs and digital multiplexer

9 GAMMA 0 = linear conversion

1 = ‘gamma’ law conversion

10 BITINVERT 0 = no inversion of bits

1 = inversion of bits

13 (1101) Reserved

14 (1110) Reserved

15 (1111) Reserved

Description of Registers

SEQUENCER Register

a. NDR (Bit 0)

In normal operation (NDR = 0), the sensor operates in

double sampling mode. At the start of each row readout, the

signals from the pixels are sampled, the row is reset, and the

signals from the pixels are sampled again. The values are

subtracted in the output amplifier.

When NDR is set to 1, the sensor operates in

nondestructive readout (NDR) mode (refer Table 12).

b. NDR_mode (Bit 1 and 2)

These bits only influence the operation of the sensor in

case NDR (bit 0) is set to 1. There are two modes for

nondestructive readout (mode 1 and 2). Each mode needs

two different frame readouts (setting 1 and 2 for mode 1,

setting 3 and 4 for mode 2). a reset/readout sequence

(reset_seq) and then one or several pure readout sequences

(called read_seq hereafter). Table 12 gives an overview of

the different NDR modes.

Table 12. OVERVIEW OF NDR MODES

Setting Bits NDR mode Sequence

1 00 1 reset

2 01 1 read

3 10 2 reset

411 2 read

Mode 1

In this mode, the sensor is readout in the same method as

for the nondestructive readout. However, electronic shutter

control is not possible in this case, that is, the minimal

(integration) time between two readings is equal to the

number of lines that has to be read out (frame read time). The

row lines are clocked simultaneously (left and right clock

pulses are equal).

Mode 2

In this mode, it is possible to have a shorter integration

time than the frame read time. Rows are alternatingly read

out with the left and right pointer. These two pointers can

point to two different rows (see INT_TIME register). The

integration time between two readings of the same row is

equal to the number of lines that is set in the INT_TIME

read time.

In setting 3, the row that is read out by the left pointer is

reset and read out (first Y_CLOCK), and the row that is read

out by the right pointer is read out without being reset

(second Y_CLOCK).

In setting 4, both rows are read out without being reset (on

the first Y_CLOCK the row is read out by the left pointer;

on the second Y_CLOCK the row is read out by the right

pointer).

For both modes, the signals are read out through the same

path as with destructive readout (double sampling), but the

buses that are carrying the reset signals in destructive

readout, are set to the voltage given by DAC_DARK in

nondestructive readout.

c. Reset_black (Bit 3)

If RESET_BLACK is set to 1, each line is reset before it

is read out (except for the row that is read out by the right

pointer in NDR Mode 2). This may be useful to obtain black

pixels.

d. Fast_reset (Bit 4)

The fast reset option (FAST_RESET = 1) might be useful

in case a mechanical camera shutter is used. The fast reset is

done on a row-by-row basis, not by a global reset. A global

reset means charging all the pixels at the same time, which

may result in a huge peak current. Therefore, the rows can

be scanned rapidly while the left and right shift registers are

both controlled identically, so that the reset lines over the

pixel array are driven from both sides. This reduces the reset

(row blanking) time (when FAST_RESET = 1 the smallest

X-granularity can be used). After the row blanking time, the

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row is reset and Y_CLOCK can be asserted to reset the next

row.

After a certain integration time, the read out can be done

in a similar method. The Y shift registers are again

synchronized to the first row. Both shift registers are driven

identically, and all rows and columns are scanned for

(destructive) readout. FAST_RESET = 1 puts the sequencer

in such mode that the left and right shift registers are both

controlled identically.

e. Output Amplifier Calibration (Bit 5 and 6)

Bits FRAME_CAL_MODE and LINE_CAL_MODE

define the calibration mode of the output amplifier.

During every row-blanking period, a calibration is done

of the output amplifier. There are two calibration modes.

The FAST mode (= 0) can force a calibration in one cycle.

However, it is not accurate and suffers from kTC noise,

while the SLOW mode (= 1) can only make incremental

adjustments and is noise free. Approximately 200 or more

“slow” calibrations have the same effect as one “fast”

calibration.

Different calibration modes can be set at the beginning of

the frame (FRAME_CAL_MODE bit) and for every

subsequent row that is read (LINE_CAL_MODE bit).

f. Continuous Charge (Bit 7)

For some applications, it might be necessary to use

continuous charging of the pixel columns instead of a

precharge on every row sample operation.

Setting bit CONT_CHARGE to 1 activates this function.

The resistor connected to pin CMD_COL is used to control

the current level on every pixel column.

g. Internal Clock Granularities

The system clock is divided several times on-chip.

The X-shift-register that controls the column/pixel

readout, is clocked by half the system clock rate. Odd and

even pixel columns are switched to two separate buses. In

the output amplifier, the pixel signals on the two buses can

be combined to one pixel stream at 40 MHz.

The clock that drives the X-sequencer can be a multiple of

2, 4, 8, or 16 times the system clock. Table 13 lists the

settings for the granularity of the X-sequencer clock and the

corresponding row blanking time (for NDR = 0). A row

blanking time of 7.18 ms is the baseline for almost all

applications.

Table 13. GRANULARITY OF X-SEQUENCER CLOCK AND CORRESPONDING ROW BLANKING TIME

(for NDR = 0)

Gran_x_seq_msb/lsb X-Sequencer Clock Row Blanking Time Row Blanking Time [ms]

00 2 x sys_clock 142 x TSYS_CLOCK 3.55

01 4 x sys_clock 282 x TSYS_CLOCK 7.05

10 8 x sys_clock 562 x TSYS_CLOCK 14.05

11 16 x sys_clock 1122 x TSYS_CLOCK 28.05

h. Black (Bit 10)

If BLACK is set to 1, the internal black signal is held high

continuously. As a result, the column amplifiers are

disconnected from the buses, and the buses are set to the

voltage given by DAC_DARK. The output of the amplifier

equals the voltages from the offset DACs.

i. Reset_all (Bit 11)

If RESET_ALL is set to 1, all the pixels are

simultaneously put in a ’reset’ state. In this state, the pixels

behave logarithmically with light intensity. If this state is

combined with one of the NDR modes, the sensor can be

used in a nonintegrating, logarithmic mode with high

dynamic range.

j. Nrof_pixels Register

After the internal X_SYNC is generated (start of the pixel

readout of a particular row), the PIXEL_VALID signal goes

high. The PIXEL_VALID signal goes low when the pixel

counter reaches the value loaded in the NROF_PIXEL

two pixels are addressed at each internal clock cycle, the

amount of pixels read out in one row is 2*(NROF_PIXEL

+ 1).

k. Nrof_lines Register

After the internal YL_SYNC is generated (start of the

frame readout with Y_START), the line counter increases

with each Y_CLOCK pulse until it reaches the value loaded

in the NROF_LINES register and an EOF pulse is generated.

In NDR Mode 2, the line counter increments only every two

Y_CLOCK pulses and the EOF pulse shows up only after

the readout of the row indicated by the right shift register

INT_TIME Register

When the Y_START pulse is applied (start of the frame

readout), the sequencer generates the YL_SYNC pulse for

the left Y-shift register. This loads the left Y-shift register

with the pointer loaded in Y_REG register. At each

Y_CLOCK pulse, the pointer shifts to the next row and the

integration time counter increases (increment only every

two Y_CLOCK pulses in NDR mode 2) until it reaches the

value loaded in the INT_TIME register. At that moment, the

YR_SYNC pulse for the right Y-shift register is generated,

which loads the right Y-shift register with the pointer loaded

in Y_REG register (shown in Figure 16 on page 21).

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Figure 16. Syncing of Y−shift Registers

Line n

Treg_int

Last line, followed by

sync of left shift-register

Tint

cSyn

Sync of right

shift-register

Sync of left

shift-register

Treg_int: Difference between left and right pointer =

integration counter until value in INT_TIME register is

reached = INT_TIME register.

In case of NDR = 0, the actual integration time Tint is

given by

TintL: Integration time [# lines] = NROF_LINES register −

INT_TIME register + 1

In case of NDR = 1, NDR mode 1, the time Tint between

two readings of the same row is given by:

Tint:Integration time [# lines] = NROF_LINES register + 1

In case of NDR = 1, NDR mode 2, the times Tint1 and

Tint2 between two readings of the same row (alternatingly)

are given by:

Tint1: Integration time [# lines] = 2 * INT_TIME register

Tint2: Integration time [# lines] = 2 * (NROF_LINES.

DELAY Register

The DELAY register can be used to delay the

PIXEL_VALID pulse (bits 0:3) and the EOL/EOF pulses

(bits 4:7) to synchronize them to the real pixel values at the

analog output or the ADC output (which give additional

delays depending on their settings). The bit settings and

corresponding delay are indicated in Table 14.

Table 14. ADDED DELAY BY CHANGING THE DELAY REGISTER SETTINGS

Bits Delay [# SYS_CLOCK periods] Bits Delay [# SYS_CLOCK periods]

0000 0 1000 6

0001 0 1001 7

0010 0 1010 8

0011 1 1011 9

0100 2 1100 10

0101 3 1101 11

0110 4 1110 12

0111 5 1111 13

X_REG Register

The X_REG register determines the start position of the

window in the X-direction. In this direction, there are 2208

+ 2 + 12 readable pixels. In the active pixel array, sub

sampling blocks are 24 pixels wide and the columns are read

two by two. Therefore, the number of start positions equals

2208/24 +2/2 +12/2 = 92 + 1 + 6 = 99.

Y_REG Register

The Y_REG register determines the start position of the

window in the Y-direction. In this direction, there are 3000

+ 2 + 12 readable pixels. In the active pixel array, sub

sampling blocks are 24 pixels wide and the rows are read one

by one. Therefore, the number of start positions equals

3000/24 + 2/2 +12 = 125 + 1 + 12 = 138.

Image_core Register

Bits 0:1 of the IMAGE_CORE register defines the several

test modes of the image core. Setting 00 is the default and

normal operation mode. If the bit is set to 1, the odd (bit 0)

or even (bit 1) columns are tight to VDD. These test modes

can be used to tune the sampling point of the ADCs to an

optimal position.

Bits 2:7 of the IMAGE_CORE register define the sub

sampling mode in the X-direction (bits 2:4) and in the

Y-direction (bits 5:7). The sub sampling modes and

corresponding bit setting are shown in “Subsamling Modes”

on page 12.

AMPLIFIER Register

a. Gain (Bits 0:3)

The gain bits determine the gain setting of the output

amplifier. They are effective only if UNITY = 0. The gains

and corresponding bit setting are given in Table 5 on page 9.

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b. Unity (Bit 4)

If UNITY = 1, the gain setting of GAIN is bypassed and

the gain amplifier is put in unity feedback.

c. One_out

If ONE_OUT = 0, the two output amplifiers are active. If

ONE_OUT = 1, the signals from the two buses are

multiplexed to output OUT1. The gain amplifier and output

driver of the second path are put in standby.

d. Standby

If STANDBY = 1, the complete output amplifier is put in

standby. This reduces the power consumption significantly.

e. Delay_clk_amp

The clock that acts on the output amplifier can be delayed

to compensate for any delay that is introduced in the path

from shift register, column selection logic, column

amplifier, and buses to the output amplifier. Setting ’000’ is

used as a baseline.

Table 15. ADDED DELAY BY CHANGING THE

DELAY_CLK_AMP BIT SETTINGS

Bits Delay [ns] Bits Delay [ns]

000 1.7 100 Inversion + 8.3

001 2.9 2.9 Inversion + 9.7

010 4.3 110 Inversion + 11.1

011 6.1 111 Inversion + 12.3

Dac_raw_reg and Dac_fine_reg Register

These registers determine the black reference level at the

output of the output amplifier. Bit setting 11111111 for

DAC_RAW_REG register gives the highest offset voltage;

bit setting 00000000 for DAC_RAW_REG register gives

the lowest offset voltage. Ideally, if the two output paths

have no offset mismatch, the DAC_FINE_REG register

must be set to 10000000. Deviation from this value can be

used to compensate the internal mismatch (see the section

Offset DACs on page 9).

Dac_raw_dark Register

This register determines the voltage level that is put on the

internal buses during calibration of the output stage. This

voltage level is also continuously put on the reset buses in

case of nondestructive readout (as a reset level for the double

sampling FPN correction).

ADC Register

a. Standby_1 and standby_2

If only one or none of the ADCs is used, the other or both

ADCs can be put in standby by setting the bit to 1. This

significantly reduces the power consumption.

b. One

If OUT1 and OUT2 are both used and connected to

ADC_IN1 and ADC_IN2 respectively, ONE must be 0 to

use both ADCs and to multiplex their output to

ADC_D<9:0>. If ONE = 1, the multiplexing is disabled.

c. Switch

If the two ADCs are used (ONE = 0) and internal pixel

clock (EXT_CLK = 0), the ADC output is delayed with one

system clock cycle if SWITCH = 1. If the two ADCs are used

(ONE = 0) and an external ADC clock (EXT_CLK = 1) is

applied, the ADC output is delayed with half ADC clock

cycle if SWITCH = 1.

If only one ADC is used, the digital multiplexing is

disabled by ONE = 1, but SWITCH selects which ADC

output is on ADC_D<9:0> (SWITCH = 0: ADC_1,

SWITCH = 1: ADC_2).

d. Ext_clk

If EXT_CLK = 0, the internal pixel clock (that drives the

X-shift registers and output amplifier, that is, half the system

clock) is used as input for the ADC clock. If EXT_CLK = 1,

an external clock must be applied to pin ADC_CLK_EXT

(pin 46).

e. Tristate

If TRISTATE = 1, the ADC_D<9:0> outputs are in

tri-state mode.

f. Delay_clk_adc

The clock that finally acts on the ADCs can be delayed to

compensate for any delay introduced in the path from the

analog outputs to the input stage of the ADCs. The same

settings apply for the delay that can be given to the clock

acting on the output amplifier (see Table 15). The best

setting also depends on the delay of the output amplifier

clock and the load of the output amplifier. It must be used to

optimize the sampling moment of the ADCs with respect to

the analog pixel input signals. Setting ‘000’ is used as a

baseline.

g. Gamma

If GAMMA is set to 0, the ADC input to output conversion

is linear, otherwise the conversion follows a ’gamma’ law

(more contrast in dark parts of the window, lower contrast in

the bright parts).

h. Bitinvert

If BITINVERT = 0, 0000000000 is the conversion of the

lowest possible input voltage, otherwise the bits are

inverted.

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TIMING DIAGRAMS

Sequencer Control Signals

There are 3 control signals that operate the image sensor:

•SYS_CLOCK

•Y_CLOCK

•Y_START

These control signals must be generated by the external

system with the following time constraints to SYS_CLOCK

(rising edge = active edge):

•TSETUP >7.5 ns

•THOLD > 7.5 ns

It is important that these signals are free of any glitches.

Figure 17. Relative Timing of the Three Control Signals

Basic Frame and Line Timing

The basic frame and line timing of the IBIS4-6600 sensor

is shown in Figure 18.

The pulse width of Y_CLOCK must be a minimum of one

clock cycle and three clock cycles for Y_START. As long as

Y_CLOCK is applied, the sequencer stays in a suspended

state.

T1 Row blanking time: During this period, the X-sequencer generates the control signals to sample the pixel signal and pixel reset

levels, and start the readout of one line. It depends on the granularity of the X-sequencer clock (see Table 13 on page 20).

T2 Pixels counted by pixel counter until the value of Nrof_pixels register is reached. Pixel_valid goes high when the internal X_sync

signal is generated. In other words, when the readout of the pixels is started. Pixel_valid goes low when the pixel counter reaches

the value loaded in the Nrof_pixels register. Eol goes high Sys_clock cycle after the falling edge of Pixel_valid.

T3 EOF goes high when the line counter reaches the value loaded in the NROF_LINES register and the line is read (PIXEL_VALID

goes low).

T4 The time delay between successive Y_CLOCK pulses needs to be equal to avoid any horizontal illumination (integration)

discrepancies in the image.

Both EOF and EOL can be tied to Y_START (EOF) and

Y_CLOCK (EOL) if both signals are delayed with at least

2 SYS_CLOCK periods to let the sensor run automatically.

It must however be noted that on power-on, the FIRST

Y_START and Y_CLOCK must be generated by the

external system.

Figure 18. Basic Frame and Line Timing

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Pixel Output Timing

Using Two Analog Outputs

Figure 19. Pixel Output Timing using Two Analog Outputs

The pixel signal at the OUT1 (OUT2) output becomes

valid after four SYS_CLOCK cycles when the internal

X_SYNC (equal to start of PIXEL_VALID output) appears

(see Figure 19). The PIXEL_VALID and EOL/EOF pulses

can be delayed by the user through the DELAY register.

T1: Row blanking time (see Table 13 on page 20)

T2: 4 SYS_CLOCK cycles.

Multiplexing to One Analog Output

The pixel signal at the OUT1 output becomes valid after

five SYS_CLOCK cycles when the internal X_SYNC

(equal to start of PIXEL_VALID output) appears (see

Figure 20). The PIXEL_VALID and EOL/EOF pulses can

be delayed by the user through the DELAY register.

T1: Row blanking time

T2: 5 SYS_CLOCK cycles.

Figure 20. Pixel Output Timing Multiplexing to One Analog Output

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ADC Timing

Two Analog Outputs

Figure 21 shows the timing of the ADC using two analog

outputs. Internally, the ADCs sample on the falling edge of

the ADC_CLOCK (in case of internal clock, the clock is half

the SYS_CLOCK).

T1: Each ADC has a pipeline delay of 2 ADC_CLOCK

cycles. This results in a total pipeline delay of four pixels.

Figure 21. ADC Timing using Two Analog Outputs

One Analog Output

Figure 22 shows the timing of the ADC using one analog

output. Internally, the ADC samples on the falling edge of

the ADC_CLOCK.

T1: The ADC has a pipeline delay of 2 ADC_CLOCK

cycles.

Figure 22. ADC Timing using One Analog Output

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PACKAGE INFORMATION

Pin List Description

The following table lists all the pins and their functions. There are a total of 68 pins. All pins with the same name can be

connected together.

Table 16. PIN LIST

Pin Pin Name Pin Type Expected Voltage [V] Pin Description

1 CMD_COL_CTU Input 0 Biasing of columns (ctu). Decouple with 100 nF to GNDA.

2 CMD_COL Input 1.08 Biasing of columns. Connect to VDDA with R = 10 kW and

decouple to GNDA with C = 100 nF.

3 CMD_COLAMP Input 0.66 Biasing of column amplifiers. Connect to VDDA with

R = 100 kW and decouple to GNDA with C = 100 nF.

4 CMD_COLAMP_CTU Input 0.37 Biasing of column amplifiers. Connect to VDDA with

R = 10 MW and decouple to GNDA with C = 100 nF.

5 RCAL_DAC_DARK Input 1.27 at code 128

DAC_DARK reg

Biasing of DAC for dark reference. Can be used to set output

range of DAC.

Default: Decouple to GNDA with C = 100 nF

6 RCAL_DAC_OUT Input 0 Biasing of DAC for output dark level. Can be used to set out-

put range of DAC. Default: Connect to GNDA

7 VDDA Power 2.5 VDD of analog part [2.5 V]

8 GNDA Power 0 GND (&substrate) of analog part

9 VDDD Power 2.5 VDD of digital part [2.5 V]

10 GNDD Power 0 GND (&substrate) of digital part

11 CMD_OUT_1 Input 0.78 Biasing of first stage output amplifiers. Connect to VDDAMP

with R = 50 kW and decouple to GNDAMP with C = 100 nF.

12 CMD_OUT_2 Input 0.97 Biasing of second stage output amplifiers. Connect to

VDDAMP with R = 25 kW and decouple to GNDAMP with

C = 100 nF.

13 CMD_OUT_3 Input 0.67 Biasing of third stage output amplifiers. Connect to VDDAMP

with R = 100 kW and decouple to GNDAMP with C = 100 nF.

14 SPI_CLK Input - Clock of digital parameter upload. Shifts on rising edge.

15 SPI_DATA Input - Serial address and data input. 16-bit word. Address first. MSB

first.

16 VDDAMP Power 2.5 VDD of analog output [2.5 V] (Can be connected to VDDA)

17 CMD_FS_ADC Input 0.73 Biasing of first stage ADC. Connect to VDDA_ADC with

R = 50 kW and decouple to GNDA_ADC with C = 100 nF.

18 CMD_SS_ADC Input 0.73 Biasing of second stage ADC. Connect to VDDA_ADC with R

= 50 kW and decouple to GNDA_ADC.

19 CMD_AMP_ADC input 0.59 Biasing of input stage ADC. Connect to VDDA_ADC with

R = 180 kW and decouple to GNDA_ADC with C = 100 nF.

20 GNDAMP Ground 0 GND (&substrate) of analog output

21 OUT1 Output Black level: 1 at code

190 DAC_RAW register

Analog output 1

22 ADC_IN1 Input See OUT1. Analog input ADC 1

23 VDDAMP Power 2.5 VDD of analog output [2.5 V] (Can be connected to VDDA)

24 OUT2 Output Black level: 1 at code

190 DAC_RAW register

Analog output 2

25 ADC_IN2 Input See OUT2. Analog input ADC 2

26 VDDD Power 2.5 VDD of digital part [2.5 V]

27 GNDD Power 0 GND (&substrate) of digital part

28 GNDA Power 0 GND (&substrate) of analog part

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Table 16. PIN LIST

Pin Pin DescriptionExpected Voltage [V]Pin TypePin Name

29 VDDA Power 2.5 VDD of analog part [2.5 V]

30 REG_CLOCK Input - Register clock. Data on internal bus is copied to correspond-

ing registers on rising edge.

31 SYS_CLOCK Input - System clock defining the pixel rate (nominal 40 MHz,

50% ±5% duty cycle)

32 SYS_RESET Input - Global system reset (active high)

33 Y_CLK Input - Line clock

34 Y_START Input - Start frame readout

35 GNDD_ADC Power 0 GND (&substrate) of digital part ADC

36 VDDD_ADC Power 2.5 VDD of digital part [2.5 V] ADC

37 GNDA_ADC Power 0 GND (&substrate) of analog part

38 VDDA_ADC Power 2.5 VDD of analog part [2.5 V]

39 VHIGH_ADC Input 1.5 ADC high reference voltage (for example, connect to

VDDA_ADC with R = 560 W and decouple to GNDA_ADC

with C = 100 nF)

40 VLOW_ADC Input 0.42 ADC low reference voltage (for example, connect to

GNDA_ADC with R = 220 W and decouple to GNDA_ADC

with C = 100 nF)

41 GNDA_ADC Power 0 GND (&substrate) of analog part

42 VDDA_ADC Power 2.5 VDD of analog part [2.5 V]

43 GNDD_ADC Power 0 GND (&substrate) of digital part ADC

44 VDDD_ADC Power 2.5 VDD of digital part [2.5 V] ADC

45 VDD_RESET_DS Power 2.5 (for no dual slope) Variable reset voltage (dual slope)

46 ADC_CLK_EXT Input - External ADC clock

47 EOL Output - Diagnostic end of line signal (produced by sequencer), can be

used as Y_CLK

48 EOF Output - Diagnostic end of frame signal (produced by sequencer), can

be used as Y_START

49 PIX_VALID Output - Diagnostic signal. High during pixel readout

50 TEMP Output - Temperature measurement. Output voltage varies linearly with

temperature.

51 ADC_D<9> Output - ADC data output (MSB)

52 VDD_PIX Power 2.5 VDD of pixel core [2.5 V]

53 GND_AB Power 0 Anti-blooming ground. Set to 1 V for improved anti-blooming

behavior

54 ADC_D<8> Output - ADC data output

55 ADC_D<7> Output - ADC data output

56 ADC_D<6> Output - ADC data output

57 ADC_D<5> Output - ADC data output

58 ADC_D<4> Output - ADC data output

59 ADC_D<3> Output - ADC data output

60 VDD_RESET Power 2.5 Reset voltage [2.5 V]. Highest voltage to the chip. 3.3 V for

extended dynamic range or ‘hard reset’.

61 ADC_D<2> Output - ADC data output

62 ADC_D<1> Output - ADC data output

63 ADC_D<0> Output - ADC data output (LSB)

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Table 16. PIN LIST

Pin Pin DescriptionExpected Voltage [V]Pin TypePin Name

64 BS_RESET Input - Boundary scan (allows debugging of internal nodes): Reset.

Tie to GND if not used.

65 BS_CLOCK Input - Boundary scan (allows debugging of internal nodes): Clock.

Tie to GND if not used.

66 BS_DIN Input - Boundary scan (allows debugging of internal nodes): In. Tie to

GND if not used.

67 BS_BUS Output - Boundary scan (allows debugging of internal nodes): Bus.

Leave floating if not used.

68 CMD_DEC Input 0.74 Biasing of X and Y decoder. Connect to VDDD with R = 50 kW

and decouple to GNDD with C = 100 nF.

Note on Power On Behavior

At power on, the chip is in an undefined state. It is advised

that the power on is accompanied by the assertion of the

SYS_CLOCK and a SYS_RESET pulse that puts all internal

registers in their default state (all bits are set to 0). The

X-shift registers are in a defined state after the first

X_SYNC, which occurs a few microseconds after the first

Y_START and Y_CLOCK pulse. Before this X_SYNC, the

chip may draw more current from the analog power supply

VDDA. It is therefore favorable to have separate analog and

digital supplies. The current spike (if there are any) may also

be avoided by a slower ramp up of the analog power supply

or by disconnecting the resistor on pin 3 (CMD_COLAMP)

at startup.

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Package Outline Drawing

Figure 23. 68 Pin LCC Packaging Outline

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MECHANICAL SPECIFICATIONS

Table 17. MECHANICAL SPECIFICATIONS

Parameters Description Min Typ Max Units

Die (with Pin 1 to the left

center)

Die thickness 0.74 mm

Die Size 9120.1 x

11960.1

Die center, X offset to the center of package (–50) 0 (+50) mm

Die center, Y offset to the center of the package (–50) 0 (+50) mm

Die position, X tilt −1 0 1 deg

Die position, Y tilt −1 0 1 deg

Die placement accuracy in package (–50) (+50) mm

Die rotation accuracy –1 1 deg

Optical center referenced from package center (X−dir) (–50) −155.58 (+50) mm

Optical center referenced from package center (Y−dir) (–50) 446.95 (+50) mm

Pixel (0,0) referenced from package center (x−dir) (–50) −4023 (+50) mm

Pixel (0,0) referenced from package center (y−dir) (–50) −4806 (+50) mm

Distance from PCB plane to top of the die surface 1.562 mm

Distance from the top of the die surface to the top of the glass

lid

2.048 mm

Glass Lid Dimensions 19.5 x 17.5 mm

Thickness 1 mm

Spectral range for window 400 1000 nm

Transmission of the glass lid 92 %

Mechanical shock JESD22-B104C; Condition G 200 G

Vibration JESD22-B103B; Condition 1 20 2000 Hz

Mounting profile Lead−free profile for LCC package if no socket is used

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Glass Lid

The IBIS4-6600 image sensor uses a glass lid without any coatings. Figure 24 shows the transmission characteristics of the

glass lid. As shown in Figure 24, no infrared attenuating filter glass is used. (source: http://www.pgo−online.com).

Figure 24. Transmission Characteristics of the Glass Lid

HANDLING PRECAUTIONS

For proper handling and storage conditions, refer to the ON Semiconductor application note AN52561.

LIMITED WARRANTY

ON Semiconductor’s Image Sensor Business Unit

warrants that the image sensor products to be delivered

hereunder, if properly used and serviced, will conform to

Seller’s published specifications and will be free from

defects in material and workmanship for two (2) years

following the date of shipment. If a defect were to manifest

itself within 2 (two) year period from the sale date,

ON Semiconductor will either replace the product or give

credit for the product.

Return Material Authorization (RMA)

ON Semiconductor packages all of its image sensor

products in a clean room environment under strict handling

procedures and ships all image sensor products in ESD-safe,

clean-room-approved shipping containers. Products

returned to ON Semiconductor for failure analysis should be

handled under these same conditions and packed in its

original packing materials, or the customer may be liable for

the product.

ACCEPTANCE CRITERIA SPECIFICATION

The Product Acceptance Criteria is available on request. This document contains the criteria to which the IBIS4-6600 is

tested before being shipped.

ORDERING CODE DEFINITION

O = Opto

N = ON Semiconductor

IBIS4

M=Mono

Q= LCC package

Commercial Temperature Range

6600MQ

S = Standard Process

6.6 MP Resolution

Additional Functionality

D= 263 Glass

I = Image Sensors

DCN O I4 S A −

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ACRONYMS

Acronym Description

ADC analog-to-digital converter

AFE analog front end

BL black pixel data

CDM Charged Device Model

CDS correlated double sampling

CMOS complementary metal oxide semiconductor

CRC cyclic redundancy check

DAC digital-to-analog converter

DDR double data rate

DFT design for test

DNL differential nonlinearity

DS Double Sampling

DSNU dark signal non-uniformity

EIA Electronic Industries Alliance

ESD electrostatic discharge

FE frame end

FF fill factor

FOT frame overhead time

FPGA Field Programmable Gate Array

FPN fixed pattern noise

FPS frames per second

FS frame start

HBM Human Body Model

IMG regular pixel data

INL integral nonlinearity

Acronym Description

IP intellectual property

LE line end

LS line start

LSB least significant bit

LVDS low-voltage differential signaling

MBS mixed boundary scan

MSB most significant bit

PGA programmable gain amplifier

PLS parasitic light sensitivity

PRBS pseudo-random binary sequence

PRNU pixel random non-uniformity

QE quantum efficiency

RGB red green blue

RMA Return Material Authorization

RMS root mean square

ROI region of interest

ROT row overhead time

S/H sample and hold

SNR signal-to-noise ratio

SPI serial peripheral interface

TBD to be determined

TIA Telecommunications Industry Association

TJJunction Temperature

TR training pattern

% RH Percent Relative Humidity

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GLOSSARY

conversion gain A constant that converts the number of electrons collected by a pixel into the voltage swing of the pixel.

Conversion gain = q/C where q is the charge of an electron (1.602E 19 Coulomb) and C is the capacitance of

the photodiode or sense node.

CDS Correlated double sampling. This is a method for sampling a pixel where the pixel voltage after reset is

sampled and subtracted from the voltage after exposure to light.

DNL Differential nonlinearity (for ADCs)

DSNU Dark signal non-uniformity. This parameter characterizes the degree of non-uniformity in dark leakage cur-

rents, which can be a major source of fixed pattern noise.

fill-factor A parameter that characterizes the optically active percentage of a pixel. In theory, it is the ratio of the actual

QE of a pixel divided by the QE of a photodiode of equal area. In practice, it is never measured.

INL Integral nonlinearity (for ADCs)

IR Infrared. IR light has wavelengths in the approximate range 750 nm to 1 mm.

Lux Photometric unit of luminance (at 550 nm, 1lux = 1 lumen/m2 = 1/683 W/m2)

pixel noise Variation of pixel signals within a region of interest (ROI). The ROI typically is a rectangular portion of the pixel

array and may be limited to a single color plane.

photometric units Units for light measurement that take into account human physiology.

PLS Parasitic light sensitivity. Parasitic discharge of sampled information in pixels that have storage nodes.

PRNU Photo-response non-uniformity. This parameter characterizes the spread in response of pixels, which is a

source of FPN under illumination.

QE Quantum efficiency. This parameter characterizes the effectiveness of a pixel in capturing photons and

converting them into electrons. It is photon wavelength and pixel color dependent.

read noise Noise associated with all circuitry that measures and converts the voltage on a sense node or photodiode into

an output signal.

reset The process by which a pixel photodiode or sense node is cleared of electrons. “Soft” reset occurs when the

reset transistor is operated below the threshold. “Hard” reset occurs when the reset transistor is operated

above threshold.

reset noise Noise due to variation in the reset level of a pixel. In 3T pixel designs, this noise has a component (in units of

volts) proportionality constant depending on how the pixel is reset (such as hard and soft). In 4T pixel designs,

reset noise can be removed with CDS.

responsivity The standard measure of photodiode performance (regardless of whether it is in an imager or not). Units are

typically A/W and are dependent on the incident light wavelength. Note that responsivity and sensitivity are

used interchangeably in image sensor characterization literature so it is best to check the units.

ROI Region of interest. The area within a pixel array chosen to characterize noise, signal, crosstalk, and so on.

The ROI can be the entire array or a small subsection; it can be confined to a single color plane.

sense node In 4T pixel designs, a capacitor used to convert charge into voltage. In 3T pixel designs it is the photodiode

itself.

sensitivity A measure of pixel performance that characterizes the rise of the photodiode or sense node signal in Volts

upon illumination with light. Units are typically V/(W/m2)/sec and are dependent on the incident light

wavelength. Sensitivity measurements are often taken with 550 nm incident light. At this wavelength, 1 683

lux is equal to 1 W/m2; the units of sensitivity are quoted in V/lux/sec. Note that responsivity and sensitivity are

used interchangeably in image sensor characterization literature so it is best to check the units.

spectral response The photon wavelength dependence of sensitivity or responsivity.

SNR Signal-to-noise ratio. This number characterizes the ratio of the fundamental signal to the noise spectrum up

to half the Nyquist frequency.

temporal noise Noise that varies from frame to frame. In a video stream, temporal noise is visible as twinkling pixels.

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copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC

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