© Semiconductor Components Industries, LLC, 2006
March, 2006 − Rev. 2 1Publication Order Number:
J111/D
J111, J112
JFET Chopper Transistors
N−Channel — Depletion
Features
•Pb−Free Packages are Available*
MAXIMUM RATINGS
Rating Symbol Value Unit
Drain−Gate Voltage VDG −35 Vdc
Gate−Source Voltage VGS −35 Vdc
Gate Current IG50 mAdc
Total Device Dissipation @ TA = 25°C
Derate above = 25°CPD350
2.8 mW
mW/°C
Lead Temperature TL300 °C
Operating and Storage Junction
Temperature Range TJ, Tstg −65 to +150 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MARKING DIAGRAM
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TO−92
CASE 29−11
STYLE 5
123
J11x
AYWW G
G
1 DRAIN
2 SOURCE
3
GATE
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
J11x = Device Code
x = 1 or 2
A = Assembly Location
Y = Year
WW = Work Week
G= Pb−Free Package
(Note: Microdot may be in either location)
J111, J112
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2
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic Symbol Min Max Unit
OFF CHARACTERISTICS
Gate−Source Breakdown Voltage
(IG = −1.0 mAdc) V(BR)GSS 35 − Vdc
Gate Reverse Current
(VGS = −15 Vdc) IGSS − −1.0 nAdc
Gate Source Cutoff Voltage
(VDS = 5.0 Vdc, ID = 1.0 mAdc) J111
J112
VGS(off) −3.0
−1.0 −10
−5.0
Vdc
Drain−Cutoff Current
(VDS = 5.0 Vdc, VGS = −10 Vdc) ID(off) − 1.0 nAdc
ON CHARACTERISTICS
Zero−Gate−Voltage Drain Current(1)
(VDS = 15 Vdc) J111
J112
IDSS 20
5.0
2.0
−
−
−
mAdc
Static Drain−Source On Resistance
(VDS = 0.1 Vdc) J111
J112
rDS(on) −
−30
50
W
Drain Gate and Source Gate On−Capacitance
(VDS = VGS = 0, f = 1.0 MHz) Cdg(on)
+
Csg(on)
− 28 pF
Drain Gate Off−Capacitance
(VGS = −10 Vdc, f = 1.0 MHz) Cdg(off) − 5.0 pF
Source Gate Off−Capacitance
(VGS = −10 Vdc, f = 1.0 MHz) Csg(off) − 5.0 pF
1. Pulse Width = 300 ms, Duty Cycle = 3.0%.
ORDERING INFORMATION
Device Package Shipping†
J111RL1 TO−92 2000 Units / Tape & Reel
J111RL1G TO−92
(Pb−Free)
J111RLRA TO−92 2000 Units / Tape & Reel
J111RLRAG TO−92
(Pb−Free)
J111RLRP TO−92 2000 Units / Tape & Reel
J111RLRPG TO−92
(Pb−Free)
J112 TO−92 1000 Units / Bulk
J112G TO−92
(Pb−Free)
J112RL1 TO−92 2000 Units / Tape & Reel
J112RL1G TO−92
(Pb−Free)
J112RLRA TO−92 2000 Units / Tape & Reel
J112RLRAG TO−92
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
J111, J112
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3
tf, FALL TIME (ns) tr, RISE TIME (ns)
td(on), TURN−ON DELAY TIME (ns)
1000
1.0
2.0
5.0
10
20
50
100
200
500
0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50
ID, DRAIN CURRENT (mA)
Figure 1. Turn−On Delay Time
RK = 0
TJ = 25°C
J111
J112
J113
VGS(off) = 12 V
= 7.0 V
= 5.0 V
RK = RD′
1000
1.0
2.0
5.0
10
20
50
100
200
500
0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50
ID, DRAIN CURRENT (mA)
Figure 2. Rise Time
RK = RD′
RK = 0
TJ = 25°C
J111
J112
J113
VGS(off) = 12 V
= 7.0 V
= 5.0 V
1000
1.0
2.0
5.0
10
20
50
100
200
500
0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50
ID, DRAIN CURRENT (mA)
Figure 3. Turn−Off Delay Time
RK = RD′
RK = 0
TJ = 25°C
J111
J112
J113
VGS(off) = 12 V
= 7.0 V
= 5.0 V
td(off), TURN−OFF DELAY TIME (ns)
1000
1.0
2.0
5.0
10
20
50
100
200
500
0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50
ID, DRAIN CURRENT (mA)
Figure 4. Fall Time
RK = RD′
RK = 0
TJ = 25°C
J111
J112
J113
VGS(off) = 12 V
= 7.0 V
= 5.0 V
TYPICAL SWITCHING CHARACTERISTICS
NOTE 1
The switching characteristics shown above were measured using a te
st
circuit similar to Figure 5. At the beginning of the switching interva
l,
the gate voltage is at Gate Supply Voltage (−VGG). The Drain−Sourc
e
Voltage (VDS) is slightly lower than Drain Supply Voltage (VDD) du
e
to the voltage divider. Thus Reverse Transfer Capacitance (Crss) o
r
Gate−Drain Capacitance (Cgd) is charged to VGG + VDS.
During the turn−on interval, Gate−Source Capacitance (Cgs
)
discharges through the series combination of RGen and RK. Cgd mu
st
discharge to VDS(on) through RG and RK in series with the paralle
l
combination of effective load impedance (R′D) and Drain−Sourc
e
Resistance (rds). During the turn−off, this charge flow is reversed.
Predicting turn−on time is somewhat difficult as the channel resistanc
e
rds is a function of the gate−source voltage. While Cgs discharges, VG
S
approaches zero and rds decreases. Since Cgd discharges through rds
,
turn−on time is non−linear. During turn−off, the situation is reverse
d
with rds increasing as Cgd charges.
The above switching curves show two impedance conditions; 1) RK
is equal to RD, which simulates the switching behavior of cascade
d
stages where the driving source impedance is normally the loa
d
impedance of the previous stage, and 2) RK = 0 (low impedance) th
e
driving source impedance is that of the generator.
RGEN
50 W
VGEN
INPUT RK
50 W
RGG
VGG
50 W
OUTPUT
RD
+VDD
RT
SET VDS(off) = 10 V
INPUT PULSE
tr
tf
PULSE WIDTH
DUTY CYCLE
≤ 0.25 ns
≤ 0.5 ns
= 2.0 ms
≤ 2.0%
RGG & RK
RDȀ+ RD(RT)50)
RD)RT)50
Figure 5. Switching Time Test Circuit
J111, J112
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4
rds(on), DRAIN−SOURCE ON−STATE
RESISTANCE (OHMS)
NOTE 2
The Zero−Gate−Voltage Drain Current (IDSS), is the
principle determinant of other J-FET characteristics.
Figure 10 shows the relationship of Gate−Source Off
Voltage (VGS(off) and Drain−Source On Resistance
(rds(on)) t o IDSS. M ost o f t he d evices will b e w ithin ±10%
of t he values shown i n F igure 10. T his d ata will b e u se ful
in predicting t he c haracteristic variations f or a given p art
number.
For example:
Unknown
rds(on) and VGS range for an J112
The e lectrical c haracteristics table i ndicates t hat a n J 1 12
has an IDSS range of 25 to 75 mA. Figure 10, shows
rds(on) = 52 W for IDSS = 25 mA and 30 W for
IDSS = 75 mA. The corresponding VGS values are 2.2 V
and 4.8 V.
yfs, FORWARD TRANSFER ADMITTANCE (mmh
o
C, CAPACITANCE (pF)
rds(on), DRAIN−SOURCE ON−STATE
RESISTANCE (OHMS)
rds(on), DRAIN−SOURCE ON−STATE
RESISTANCE (NORMALIZED)
2.0
3.0
5.0
7.0
10
20
0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50
ID, DRAIN CURRENT (mA)
Figure 6. Typical Forward Transfer Admittance
1.0
1.5
2.0
3.0
5.0
7.0
10
15
0.03 0.05 0.1 0.3 0.5 1.0 3.0 5.0 10 30
VR, REVERSE VOLTAGE (VOLTS)
Figure 7. Typical Capacitance
200
160
120
80
40
00 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
VGS, GATE−SOURCE VOLTAGE (VOLTS)
Figure 8. Effect of Gate−Source Voltage
On Drain−Source Resistance
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
−70 −40 −10 20 50 80 110 140 170
Tchannel, CHANNEL TEMPERATURE (°C)
Figure 9. Effect of Temperature On
Drain−Source On−State Resistance
J113
J112
J111
Tchannel = 25°C
VDS = 15 V
Cgs
Cgd
Tchannel = 25°C
(Cds IS NEGLIGIBLE)
IDSS
= 10
mA
25
mA
50mA 75mA 100mA 125mA
Tchannel = 25°C
ID = 1.0 mA
VGS = 0
10
IDSS, ZERO−GATE−VOLTAGE DRAIN CURRENT (mA)
Figure 10. Effect of IDSS On Drain−Source
Resistance and Gate−Source Voltage
20 30 40 50 60 70 80 90 100 110 120 130 140 150
10
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
100
90
80
70
60
50
40
30
20
10
0
VGS, GATE−SOURCE VOLTAGE (VOLTS)
Tchannel = 25°C
rDS(on) @ VGS = 0
VGS(off)
J111, J112
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5
PACKAGE DIMENSIONS
TO−92 (TO−226)
CASE 29−11
ISSUE AL
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. CONTOUR OF PACKAGE BEYOND DIMENSION R
IS UNCONTROLLED.
4. LEAD DIMENSION IS UNCONTROLLED IN P AND
BEYOND DIMENSION K MINIMUM.
R
A
P
J
L
B
K
G
H
SECTION X−X
C
V
D
N
N
XX
SEATING
PLANE DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.175 0.205 4.45 5.20
B0.170 0.210 4.32 5.33
C0.125 0.165 3.18 4.19
D0.016 0.021 0.407 0.533
G0.045 0.055 1.15 1.39
H0.095 0.105 2.42 2.66
J0.015 0.020 0.39 0.50
K0.500 −−− 12.70 −−−
L0.250 −−− 6.35 −−−
N0.080 0.105 2.04 2.66
P−−− 0.100 −−− 2.54
R0.115 −−− 2.93 −−−
V0.135 −−− 3.43 −−−
1
STYLE 5:
PIN 1. DRAIN
2. SOURCE
3. GATE
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J111/D
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