MC10EP445MNR4G - ON Semiconductor L.L.C.

December, 2012 − Rev. 15

1Publication Order Number:

MC10EP445/D

MC10EP445, MC100EP445

3.3V/5V ECL 8-Bit

Serial/Parallel Converter

Description

The MC10/100EP445 is an integrated 8–bit differential serial to

parallel data converter with asynchronous data synchronization. The

device has two modes of operation. CKSEL HIGH mode is designed

to operate NRZ data rates of up to 3.3 Gb/s, while CKSEL LOW mode

is designed to operate at twice the internal clock data rate of up to

5.0 Gb/s. The conversion sequence was chosen to convert the first

serial bit to Q0, the second bit to Q1, etc. Two selectable differential

serial inputs, which are selected by SINSEL, provide this device with

loop−back testing capability. The MC10/100EP445 has a SYNC pin

which, when held high for at least two consecutive clock cycles, will

swallow one bit of data shifting the start of the conversion data from

Dn to Dn+1. Each additional shift requires an additional pulse to be

applied to the SYNC pin.

Control pins are provided to reset and disable internal clock

circuitry. Additionally, VBB pin is provided for single−ended input

condition.

The 100 Series contains temperature compensation.

Features

•1530 ps Propagation Delay

•5.0 Gb/s Typical Data Rate for CLKSEL LOW Mode

•Differential Clock and Serial Inputs

•VBB Output for Single-Ended Input Applications

•Asynchronous Data Synchronization (SYNC)

•Asynchronous Master Reset (RESET)

•PECL Mode Operating Range: VCC = 3.0 V to 5.5 V

with VEE = 0 V

•NECL Mode Operating Range: VCC = 0 V

with VEE = −3.0 V to −5.5 V

•Open Input Default State

•CLK ENABLE Immune to Runt Pulse Generation

•Pb−Free Packages are Available*

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

LQFP−32

FA SUFFIX

CASE 873A

MARKING

DIAGRAM*

*For additional marking information, refer to

Application Note AND8002/D.

http://onsemi.com

MCxxx

EP445

AWLYYWWG

xxx = 10 or 100

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

G or G= Pb−Free Package

(Note: Microdot may be in either location)

See detailed ordering and shipping information in the package

dimensions section on page 17 of this data sheet.

ORDERING INFORMATION

MCxx

EP445

AWLYYWWG

QFN32

MN SUFFIX

CASE 488AM

MC10EP445, MC100EP445

http://onsemi.com

2526272829303132

1514131211109

MC10EP445

MC100EP445

Q6 Q5 VCC VCC Q4 Q3 VEE

VCC SINA SINA VBB0 VEE SINB SINB SINSEL

VCC

CKSEL

VBB1

CLK

CKEN

RESET

VCC

PCLK

VCC

PCLK

Figure 1. 32−Lead LQFP Pinout (Top View)

SYNC

Warning: All VCC and VEE pins must be externally connected to

Power Supply to guarantee proper operation.

2526272829303132

1514131211109

Figure 2. 32−Lead QFN Pinout (Top View)

MC10EP445

MC100EP445

Q7 Q6 Q5 VCC VCC Q4 Q3 VEE

VCC SINA SINA VBB0 VEE SINB SINB SINSEL

VCC

CKSEL

VBB1

CLK

CKEN

RESET

VCC

PCLK

VCC

PCLK

SYNC

Table 1. PIN DESCRIPTION

SINA*, SINA*

Function

ECL Differential Serial Data Input A

SINSEL*

Q0−Q7 ECL Parallel Data Outputs

ECL Serial Input Selector Pin

CLK*, CLK* ECL Differential Clock Inputs

PCLK, PCLK ECL Differential Parallel Clock Output

SYNC* ECL Conversion Synchronizing Input

CKSEL* ECL Clock Input Selector Pin

VBB0, VBB1 Output Reference Voltage

VCC Positive Supply

VEE Negative Supply

SINB*, SINB* ECL Differential Serial Data Input B

CKEN* ECL Clock Enable Pin

RESET* ECL Reset Pin

* Pins will default logic LOW or differential logic LOW

when left open.

EP The exposed pad (EP) on the QFN−32

package bottom is thermally connected

to the die for improved heat transfer out

of the package. THe exposed pad must

be attached to a heat−sinking conduit.

The pad is electrically connected to

VEE.

Exposed Pad

(EP)

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Table 2. TRUTH TABLE

FUNCTION

High Low

SINSEL Select SINB Input Select SINA Input

CKSEL Q: PCLK = 8:1

CLK: Q = 1:1

CLK

Q: PCLK = 8:1

CLK: Q = 1:2

CLK

CKEN Synchronously Disable Internal Clock Circuitry Synchronously Enable Internal

Clock Circuitry

RESET Asynchronous Master Reset Synchronous Enable

SYNC Asynchronously Applied to Swallow a Data Bit Normal Conversion Process

Figure 3. Logic Diagram

1:2

DEMUX

1:2

DEMUX

1:2

DEMUX

1:2

DEMUX

1:2

DEMUX

1:2

DEMUX

1:2

DEMUX

DIV2DIV2 PCLK

PCLK

SINA

SINB

SINSEL

CKSEL

CKEN

CLK

RESET

SYNC

Control

Logic

VEE

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Table 3. ATTRIBUTES

Characteristics Value

Internal Input Pulldown Resistor 75 k

Internal Input Pull−up Resistor N/A

ESD Protection Human Body Model

Machine Model

Charged Device Model

> 2 kV

> 200 V

> 2 kV

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg Pb−Free Pkg

LQFP−32

QFN−32

Level 2

N/A

Level 2

Level 1

Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

Transistor Count 993 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

Table 4. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

VCC PECL Mode Power Supply VEE = 0 V 6 V

VEE NECL Mode Power Supply VCC = 0 V −6 V

VIPECL Mode Input Voltage

NECL Mode Input Voltage

VEE = 0 V

VCC = 0 V

VI  VCC

VI  VEE

−6

Iout Output Current Continuous

Surge

100

IBB VBB Sink/Source ± 0.5 mA

TAOperating Temperature Range −40 to +85 °C

Tstg Storage Temperature Range −65 to +150 °C

JA Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

32 LQFP

°C/W

JC Thermal Resistance (Junction−to−Case) Standard Board 32 LQFP 12 to 17 °C/W

JA Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

QFN−32

°C/W

JC Thermal Resistance (Junction−to−Case) 2S2P QFN−32 12 °C/W

Tsol Wave Solder Pb

Pb−Free

<2 to 3 sec @ 248°C

<2 to 3 sec @ 260°C

265

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

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Table 5. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 2)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current 95 119 143 98 122 146 100 125 150 mA

VOH Output HIGH Voltage (Note 3) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV

VOL Output LOW Voltage (Note 3) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV

VIH Input HIGH Voltage (Single−Ended) 2090 2415 2155 2480 2215 2540 mV

VIL Input LOW Voltage (Single−Ended) 1365 1690 1460 1755 1490 1815 mV

VBB Output Voltage Reference 1790 1890 1990 1855 1955 2055 1915 2015 2115 mV

VIHCMR Input HIGH Voltage Common Mode

Range (Differential Configuration)

(Note 4)

2.0 3.3 2.0 3.3 2.0 3.3 V

IIH Input HIGH Current 150 150 150 A

IIL Input LOW Current 0.5 0.5 0.5 A

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.

3. All loading with 50  to VCC − 2.0 V.

4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

Table 6. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current (Note 6) 95 119 143 98 122 146 100 125 150 mA

VOH Output HIGH Voltage (Note 7) 3865 3990 4115 3930 4055 4180 3990 4115 4240 mV

VOL Output LOW Voltage (Note 7) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mV

VIH Input HIGH Voltage (Single−Ended) 3790 4115 3855 4180 3915 4240 mV

VIL Input LOW Voltage (Single−Ended) 3065 3390 3130 3455 3190 3515 mV

VBB Output Voltage Reference 3490 3590 3690 3555 3655 3755 3615 3715 3815 mV

VIHCMR Input HIGH Voltage Common Mode

Range (Differential Configuration)

(Note 8)

2.0 5.0 2.0 5.0 2.0 5.0 V

IIH Input HIGH Current 150 150 150 A

IIL Input LOW Current 0.5 0.5 0.5 A

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

5. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V.

6. Required 500 lfpm air flow when using +5 V power supply. For (VCC − VEE) >3.3 V, 5  to 10  in line with VEE required for maximum thermal

protection at elevated temperatures. Recommend VCC−VEE operation at  3.3 V.

7. All loading with 50  to VCC − 2.0 V.

8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

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Table 7. 10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 9)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current (Note 10) 95 119 143 98 122 146 100 125 150 mA

VOH Output HIGH Voltage (Note 11) −1135 −1010 −885 −1070 −945 −820 −1010 −885 −760 mV

VOL Output LOW Voltage (Note 11) −1935 −1810 −1685 −1870 −1745 −1620 −1810 −1685 −1560 mV

VIH Input HIGH Voltage (Single−Ended) −1210 −885 −1145 −820 −1085 −760 mV

VIL Input LOW Voltage (Single−Ended) −1935 −1610 −1870 −1545 −1810 −1485 mV

VBB Output Voltage Reference −1510 −1410 −1310 −1445 −1345 −1245 −1385 −1285 −1185 mV

VIHCMR Input HIGH Voltage Common Mode

Range (Differential Configuration)

(Note 12)

VEE+2.0 0.0 VEE+2.0 0.0 VEE+2.0 0.0 V

IIH Input HIGH Current 150 150 150 A

IIL Input LOW Current 0.5 0.5 0.5 A

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

9. Input and output parameters vary 1:1 with VCC.

10.Required 500 lfpm air flow when using −5 V power supply. For (VCC − VEE) >3.3 V, 5  to 10  in line with VEE required for maximum thermal

protection at elevated temperatures. Recommend VCC−VEE operation at  3.3 V.

11. All loading with 50  to VCC − 2.0 V.

12.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

Table 8. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 13)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current 95 119 143 98 122 146 100 125 150 mA

VOH Output HIGH Voltage (Note 14) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV

VOL Output LOW Voltage (Note 14) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV

VIH Input HIGH Voltage (Single−Ended) 2075 2420 2075 2420 2075 2420 mV

VIL Input LOW Voltage (Single−Ended) 1355 1675 1355 1675 1355 1675 mV

VBB Output Voltage Reference 1775 1875 1975 1775 1875 1975 1775 1875 1975 mV

VIHCMR Input HIGH Voltage Common Mode

Range (Differential Configuration)

(Note 15)

2.0 3.3 2.0 3.3 2.0 3.3 V

IIH Input HIGH Current 150 150 150 A

IIL Input LOW Current 0.5 0.5 0.5 A

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

13.Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.

14.All loading with 50  to VCC − 2.0 V.

15.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

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Table 9. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 16)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current (Note 17) 95 119 143 98 122 146 100 125 150 mA

VOH Output HIGH Voltage (Note 18) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV

VOL Output LOW Voltage (Note 18) 3055 3180 3305 3055 3180 3305 3055 3180 3305 mV

VIH Input HIGH Voltage (Single−Ended) 3775 4120 3775 4120 3775 4120 mV

VIL Input LOW Voltage (Single−Ended) 3055 3375 3055 3375 3055 3375 mV

VBB Output Voltage Reference 3475 3575 3675 3475 3575 3675 3475 3575 3675 mV

VIHCMR Input HIGH Voltage Common Mode

Range (Differential Configuration)

(Note 19)

2.0 5.0 2.0 5.0 2.0 5.0 V

IIH Input HIGH Current 150 150 150 A

IIL Input LOW Current 0.5 0.5 0.5 A

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

16.Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V.

17.Required 500 lfpm air flow when using +5 V power supply. For (VCC − VEE) >3.3 V, 5  to 10  in line with VEE required for maximum thermal

protection at elevated temperatures. Recommend VCC−VEE operation at  3.3 V.

18.All loading with 50  to VCC − 2.0 V.

19.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

Table 10. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 20)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

IEE Power Supply Current (Note 21) 95 119 143 98 122 146 100 125 150 mA

VOH Output HIGH Voltage (Note 22) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV

VOL Output LOW Voltage (Note 22) −1945 −1820 −1695 −1945 −1820 −1695 −1945 −1820 −1695 mV

VIH Input HIGH Voltage (Single−Ended) −1225 −880 −1225 −880 −1225 −880 mV

VIL Input LOW Voltage (Single−Ended) −1945 −1625 −1945 −1625 −1945 −1625 mV

VBB Output Voltage Reference −1525 −1425 −1325 −1525 −1425 −1325 −1525 −1425 −1325 mV

VIHCMR Input HIGH Voltage Common Mode

Range (Differential Configuration)

(Note 23)

VEE + 2.0 0.0 VEE + 2.0 0.0 VEE + 2.0 0.0 V

IIH Input HIGH Current 150 150 150 A

IIL Input LOW Current 0.5 0.5 0.5 A

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

20.Input and output parameters vary 1:1 with VCC.

21.Required 500 lfpm air flow when using −5.0 V power supply. For (VCC − VEE) > 3.3 V, 5  to 10  in line with VEE required for maximum

thermal protection at elevated temperatures. Recommend VCC − VEE operation at v 3.3 V.

22.All loading with 50  to VCC − 2.0 V.

23.VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential

input signal.

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Table 11. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 24)

Symbol Characteristic

−40°C 25°C 85°C

Unit

Min Typ Max Min Typ Max Min Typ Max

fmax Maximum Input CLK Frequency CKSEL = LOW

(See Figure 13. Fmax/JITTER) CKSEL = HIGH

2.0

2.8

2.5

3.3

2.0

2.8

2.5

3.3

1.7

2.8

2.2

3.3

GHz

tPLH,

tPHL

Propagation Delay to CLK to Q

Output Differential CLK TO PCLK

1280

1000

1475

1240

1710

1490

1335

1050

1557

1310

1795

1580

1450

1140

1663

1420

1950

1710

ts Setup Time SINA, B+ TO CLK+ (Figure 5)

CKEN+ TO CLK− (Figure 6)

−400

100

−459

−420

100

−479

−440

100

−492

thHold Time CLK+ TO SINA, B− (Figure 5)

CLK− TO CKEN (Figure 6)

533

474

−35

550

490

−35

560

508

−35

tRR/tRR2 Reset Recovery (Figure 4) 350 180 350 180 350 180 ps

tPW Minimum Pulse Width RESET 400 400 400 ps

tJITTER RMS Random Clock Jitter

@ 2.0 GHz CLK_SEL LOW

@ 2.5 GHz CLK_SELF HIGH

@ 3.0 GHz CLK_SEL HIGH

1.5

1.0

1.5

1.0

2.0

1.5

2.5

VPP Input Voltage Swing (Differential Configuration)

(Note 25)

150 800 1200 150 800 1200 150 800 1200 mV

Output Rise/Fall Times Q/Q

(20% − 80%) PCLK/PCLK

100

180

400

250

100

200

400

300

125

230

425

325

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

24.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50  to VCC − 2.0 V.

25.VPP(min) is the minimum input swing for which AC parameters are guaranteed.

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Figure 4. Reset Recovery

Reset

CLK

tRR

CLK

Figure 5. Data Setup and Hold Time

Data Setup Time

CLK

Figure 6. CKEN Setup and Hold Time

CKEN Setup Time

Data Hold Time −

−

CLK

CKEN Hold Time −

−+

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APPLICATION INFORMATION

The MC10/100EP445 is an integrated 1:8 serial to parallel

converter with two modes of operation selected by

CKSEL (Pin 7). CKSEL HIGH mode only latches data on

the rising edge of the input CLK and CKSEL LOW mode

latches data on both the rising and falling edge of the input

CLK. CKSEL LOW is the open default state. Either of the

two differential input serial data path provided for this

device, SINA and SINB, can be chosen with the SINSEL pin

(pin 25). SINA is the default input path when SINSEL pin

is left floating. Because of internal pull−downs on the input

pins, all input pins will default to logic low when left open.

The two selectable serial data paths can be used for

loop−back testing as well as the bit error testing.

Upon power−up, the internal flip−flops will attain a

random state. To synchronize multiple flip–flops in the

device, the Reset (pin 1) must be asserted. The reset pin will

disable the internal clock signal irrespective of the CKEN

state (CKEN disables the internal clock circuitry). The

device will grab the first stream of data after the falling edge

of RESETÀ, followed by the falling edge of CLKÁ, on

second rising edge of CLKÂ in either CKSEL modes. (See

Figure 6)

CLK

RESET

PCLK

RESET

(Asynchronous Reset) RESET

(Synchronous ENABLE)

Figure 7. Reset Timing Diagram

ÁÂ

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For CKSEL LOW operation, the data is latched on both the rising edge and the falling edge of the clock and the time from

when the serial data is latchedÀ to when the data is seen on the parallel outputÁ is 6 clock cycles (see Figure 8).

Figure 8. Timing Diagram A. 1:8 Serial to Parallel Conversion with CKSEL LOW

CLK

SINA

RESET

CKSEL

PCLK

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24

D0 D8 D16

D1 D9 D17

D2 D10 D18

D3 D11 D19

D4 D12 D20

D5 D13 D21

D6 D14 D22

D7 D15 D23

CKEN

123456

Number of

lock

ycles from Data Latch to

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Similarly, for CKSEL HIGH operation, the data is latched only on the rising edge of the clock and the time from when the

serial data is latchedÀ to when the data is seen on the parallel outputÁ is 12 clock cycles (see Figure 9).

Figure 9. Timing Diagram A. 1:8 Serial to Parallel Conversion with CKSEL HIGH

CLK

SINA

RESET

CKSEL

PCLK

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14

CKEN

123456

Number of Clock Cycles from Data Latch to Q

7 8 9 10 11 12

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To allow the user to synchronize the output byte data

correctly, the start bit for conversion can be moved using the

SYNC input pin (pin 2). Asynchronously asserting the

SYNC pin will force the internal clock to swallow a clock

pulse, effectively shifting a bit from the Qn to the Qn−1 output

as shown in Figure 10 and Figure 11. For CKSEL LOW, a

single pulse applied asynchronously for two consecutive

clock cycles shifts the start bit for conversion from Qn to

Qn−1. The bit is swallowed following the two clock cycle

pulse width of SYNCÀ on the next triggering edge of

clockÁ (either on the rising or the falling edge of the clock).

Each additional shift requires an additional pulse to be

applied to the SYNC pin. (See Figure 10)

Figure 10. Timing Diagram A. 1:8 Serial to Parallel Conversion with SYNC Pulse at CKSEL LOW

CLK

SINA

CKSEL

PCLK

SYNC

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24

D0 D9 D17

D1 D10 D18

D2 D11 D19

D3 D12 D20

D4 D13 D21

D5 D14 D22

D6 D15 D23

D7 D16 D24

2 Clock Cycles for SYNC Next Triggering Edge of Clock

Bit D8 is Swallowed

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For CKSEL HIGH, a single pulse applied asynchronously

for three consecutive clock cycles shifts the start bit for

conversion from Qn to Qn−1. The bit is swallowed following

the three clock cycle pulse width of SYNCÀ on the next

triggering edge of clockÁ (on the rising edge of the clock

only). Each additional shift requires an additional pulse to be

applied to the SYNC pin. (See Figure 11)

Figure 11. Timing Diagram A. 1:8 Serial to Parallel Conversion with SYNC Pulse at CKSEL HIGH

3 Clock Cycles for Sync Next Triggering Edge of Clock

Bit D8 is Swallowed

CLK

SINA

PCLK

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14

SYNC

D15 D16 D17 D18 D19 D20 D21 D22 D23 D24

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

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The synchronous CKEN (pin 3) applied with at least one

clock cycle pulse length will disable the internal clock

signal. The synchronous CKEN will suspend all of the

device activities and prevent runt pulses from being

generated. The rising edge of CKEN followed by the falling

edge of CLK will suspend all activities. The first data bit will

clock on the rising edge, since the falling edge of CKEN

followed by the falling edge of the incoming clock triggers

the enabling of the internal process. (See Figure 12)

CLK

PCLK

Internal Clock

Disabled Internal Clock

Enabled

Figure 12. Timing Diagram with CKEN with CKSEL HIGH

CKSEL

CKEN

The differential PCLK output (pins 22 and 23) is a word

framer and can help the user to synchronize the parallel data

outputs. During CKSEL LOW operation, the PCLK will

provide a divide by 4−clock frequency, which frames the

serial data in period of PCLK output. Likewise during

CKSEL HIGH operation, the PCLK will provide a divide by

8−clock frequency.

The VBB pin, an internally generated voltage supply, is

available to this device only. For single–ended input

conditions, the unused differential input is connected to VBB

as a switching reference voltage. VBB may also rebias AC

coupled inputs. When used, decouple VBB and VCC via a

0.01 F capacitor, which will limit the current sourcing or

sinking to 0.5mA. When not used, VBB should be left open.

Also, both outputs of the differential pair must be terminated

(50  to VTT = VCC – 2 V) even if only one output is used.

MC10EP445, MC100EP445

http://onsemi.com

100

200

300

400

500

600

700

800

900

1000

0 500 1000 1500 2000 2500 3000 3500

Figure 13. Fmax/Jitter

INPUT CLK FREQUENCY (MHz)

VOUTpp (mV)

JITTEROUT ps (RMS)

ÉÉ

ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ

(JITTER)

CKSEL LOW

CKSEL HIGH

Figure 14. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020/D − Termination of ECL Logic Devices.)

Driver

Device

Receiver

Device

Q D

Zo = 50 

50 50 

VTT

VTT = VCC − 2.0 V

MC10EP445, MC100EP445

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ORDERING INFORMATION

Device Package Shipping†

MC10EP445FA LQFP−32 250 Units / Tray

MC10EP445FAG LQFP−32

(Pb−Free)

250 Units / Tray

MC10EP445FAR2 LQFP−32 2000 / Tape & Reel

MC10EP445FAR2G LQFP−32

(Pb−Free)

2000 / Tape & Reel

MC10EP445MNG QFN−32

(Pb−Free)

74 Units / Rail

MC10EP445MNR4G QFN−32

(Pb−Free)

1000 / Tape & Reel

MC100EP445FAG LQFP−32

(Pb−Free)

250 Units / Tray

MC100EP445FAR2 LQFP−32 2000 / Tape & Reel

MC100EP445FAR2G LQFP−32

(Pb−Free)

2000 / Tape & Reel

MC100EP445MNG QFN−32

(Pb−Free)

74 Units / Rail

MC100EP445MNR4G QFN−32

(Pb−Free)

1000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

Resource Reference of Application Notes

AN1405/D −ECL Clock Distribution Techniques

AN1406/D −Designing with PECL (ECL at +5.0 V)

AN1503/D −ECLinPSt I/O SPiCE Modeling Kit

AN1504/D −Metastability and the ECLinPS Family

AN1568/D −Interfacing Between LVDS and ECL

AN1672/D −The ECL Translator Guide

AND8001/D −Odd Number Counters Design

AND8002/D −Marking and Date Codes

AND8020/D −Termination of ECL Logic Devices

AND8066/D −Interfacing with ECLinPS

AND8090/D −AC Characteristics of ECL Devices

MC10EP445, MC100EP445

http://onsemi.com

PACKAGE DIMENSIONS

32 LEAD LQFP

CASE 873A−02

ISSUE C

ÉÉ

DETAIL Y

BASE

METAL

SECTION AE−AE

SEATING

PLANE

0.250 (0.010)

GAUGE PLANE

DETAIL AD

B1 V1

−T−

−Z−

−U−

T-U0.20 (0.008) ZAC

T-U0.20 (0.008) ZAB

0.10 (0.004) AC

−AC−

−AB−

−T−, −U−, −Z−

T-U

0.20 (0.008) ZAC

NOTES:

1. DIMENSIONING AND TOLERANCING

PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION:

MILLIMETER.

3. DATUM PLANE −AB− IS LOCATED AT

BOTTOM OF LEAD AND IS COINCIDENT

WITH THE LEAD WHERE THE LEAD

EXITS THE PLASTIC BODY AT THE

BOTTOM OF THE PARTING LINE.

4. DATUMS −T−, −U−, AND −Z− TO BE

DETERMINED AT DATUM PLANE −AB−.

5. DIMENSIONS S AND V TO BE

DETERMINED AT SEATING PLANE −AC−.

6. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION. ALLOWABLE

PROTRUSION IS 0.250 (0.010) PER SIDE.

DIMENSIONS A AND B DO INCLUDE

MOLD MISMATCH AND ARE

DETERMINED AT DATUM PLANE −AB−.

7. DIMENSION D DOES NOT INCLUDE

DAMBAR PROTRUSION. DAMBAR

PROTRUSION SHALL NOT CAUSE THE

D DIMENSION TO EXCEED 0.520 (0.020).

8. MINIMUM SOLDER PLATE THICKNESS

SHALL BE 0.0076 (0.0003).

9. EXACT SHAPE OF EACH CORNER MAY

VARY FROM DEPICTION.

DIM

MIN MAX MIN MAX

INCHES

7.000 BSC 0.276 BSC

MILLIMETERS

B7.000 BSC 0.276 BSC

C1.400 1.600 0.055 0.063

D0.300 0.450 0.012 0.018

E1.350 1.450 0.053 0.057

F0.300 0.400 0.012 0.016

G0.800 BSC 0.031 BSC

H0.050 0.150 0.002 0.006

J0.090 0.200 0.004 0.008

K0.450 0.750 0.018 0.030

M12 REF 12 REF

N0.090 0.160 0.004 0.006

P0.400 BSC 0.016 BSC

Q1 5 1 5

R0.150 0.250 0.006 0.010

V9.000 BSC 0.354 BSC

V1 4.500 BSC 0.177 BSC

___ _

B1 3.500 BSC 0.138 BSC

A1 3.500 BSC 0.138 BSC

S9.000 BSC 0.354 BSC

S1 4.500 BSC 0.177 BSC

W0.200 REF 0.008 REF

X1.000 REF 0.039 REF

MC10EP445, MC100EP445

http://onsemi.com

PACKAGE DIMENSIONS

QFN32 5*5*1 0.5 P

CASE 488AM−01

ISSUE O

SEATING

32 X

0.15 C

(A3)

916 17

2 X

32 X

BOTTOM VIEW

EXPOSED PAD

TOP VIEW

SIDE VIEW

0.15 C

ÉÉ

PIN ONE

LOCATION

0.10 C

0.08 C

A0.10 B

0.05 C

NOTES:

1. DIMENSIONS AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.25 AND 0.30 MM TERMINAL

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

PLANE

DIM MIN NOM MAX

MILLIMETERS

A0.800 0.900 1.000

A1 0.000 0.025 0.050

A3 0.200 REF

b0.180 0.250 0.300

D5.00 BSC

D2 2.950 3.100 3.250

E5.00 BSC

e0.500 BSC

K0.200 −−− −−−

L0.300 0.400 0.500

2.950 3.100 3.250

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.50 PITCH

3.20

0.28

3.20

32 X

28 X

0.63

32 X

5.30

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,

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reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any

particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without

limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications

and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC

does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for

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PUBLICATION ORDERING INFORMATION

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Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

MC10EP445/D

ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).

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