1/30March 2000
M29W008AT
M29W008AB
8 Mbit (1Mb x8, Boot Block)
Low Voltage Single Supply Flash Memory
■2.7V to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and R EAD OPERATIO NS
■ACCESS TIME: 8 0ns
■PROG RAMMING TIME: 10µs typical
■PROGRAM/ERASE CONTROLLER (P/E.C.)
– Program Byte-by-Byte
– Status Register bits and Ready/B us y Output
■SECURITY PROTECTION MEMORY AREA
■INSTRUCTIONS ADDRESS CODING: 3 di gits
■MEMORY BLOCKS
– Boot Bl ock (Top or Bottom l ocation)
– Parameter and Mai n blocks
■BLOCK, MULTI-BLOCK and CHIP ERA SE
■MULTI BLOCK PROTECTION/T EMPORARY
UNPROTECTION MODES
■ERASE SUSPEND and RESUM E MOD ES
– Read and Program another Block during
Erase Su spend
■LOW POWER CONSUMPTI ON
– Stand-by and A utomatic Stand-by
■100,000 PROGRAM/ERASE CYCL ES per
BLOCK
■20 YEAR S DATA RETENTION
– Defect ivity below 1ppm/y ear
■ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Top Device Code, M29W008AT : D2h
– Bottom Device Code, M29W 008AB : DCh
Figure 1. Logic Diagram
AI02716
20
A0-A19
W
DQ0-DQ7
VCC
M29W008AT
M29W008AB
E
VSS
8
G
RP
RB
TSOP40 (N)
10 x 20mm
M29W008AT, M29W008AB
2/30
Figu re 2. TSOP C onnections
VSS
DQ1
DQ2A7
A1 E
A4
A3
A11
A17
A14
A15
DQ7
A9
A16
G
NC
DQ5
DQ3
NC
VCC
DQ4
DQ6
A8
W
RB
A18
NC
RP
AI02717
M29W008AT
M29W008AB
10
1
11
20 21
30
31
40
A0
A12
A13 A19
A10
A5
A6
VCC
DQ0
VSS
A2
Table 1. Signal Names
A0-A19 Address Inputs
DQ0-DQ7 Data Input/Outputs, Command Inputs
EChip Enable
GOutput Enable
WWrite Enable
RP Reset/Block Temporary Unprotect
RB Ready/Busy Output
VCC Supply Voltage
VSS Ground
NC Not Connected Internally
Organisation
The M29W008A is organised as 1Mb x8. The
memory u ses the addre ss inputs A0-A 19 and the
Data Input/Outputs DQ0-DQ7. Memory control is
provided by Chip Enable E, Out put Enable G and
Write Enable W inputs.
A Reset/Block Temporary Unprotect i on RP tri-lev-
el input provides a hardware reset when pulled
Low, and whe n held High (at VID) temporarily un-
prot ec ts blocks previously pr ot ected allowing them
to be p rogram ed and erased. E rase and Program
operations are controlled by an internal Program/
Erase Controller (P/E.C.). Status Register data
output on DQ7 provides a Data Polling signal, and
DQ6 and DQ2 provide Toggle signals to indicate
the state of the P/E.C operations. A Ready/Busy
RB ou tput indicates the completion of the internal
algorithms.
Memory Blocks
The devices f eature asymmetrically blocked archi -
tecture providing system memory int egration. Both
M29W008AT and M29W008AB devices have an
array of 19 blocks, one Boot Block of 16 Kbytes,
two Parameter Blocks of 8 Kbytes, one Main Block
of 32 Kbytes and fi fteen Main Bl ocks of 64 Kbytes .
The M29W008AT has the Boot Block at the top of
the memory address sp ace and the M2 9W008AB
locates th e Boot B lock s tarting at t he bot tom. T he
memory maps are showed in Tables 3, 4. Each
block can be e rased sepa rately, any co mbination
of blocks can be spec ified for m ulti-block erase or
the entire chip may be erased. The Erase opera-
tions are managed automatically by the P/E.C.
DESCRIPTION
The M29W008A is a non-volatile memory that may
be erased electrically at the block or chip l evel and
programmed in-system on a Byte-by-Byte basis
using only a single 2.7V to 3.6V VCC supply. For
Program and Erase operations the necessary high
voltages are generated internally. The device can
also be programmed i n standard programmers.
The array matri x organis ation allows each block to
be erased and reprogrammed without affecting
ot her blocks. Bl ocks can be protec ted again st pro-
graming and erase on programming equipment,
and temporarily unprotected to make changes in
the application. Each block can be programmed
and erased over 100,000 cycles.
Instructions for Rea d/Reset, Aut o Sel ect for read-
ing the Electronic Signature or Block Protection
status, Programming, Block and Chip Erase,
Erase Sus pend and Resume ar e written t o the de-
vice in cy cl es of com mands to a Co mmand In ter-
face using standard microproces sor write timings.
The device is offered in TSOP40 (10 x 20mm)
package.
3/30
M29W008AT, M29W008AB
Instructions
Seven instructions are defined to perform Read
Array, Auto Select (to read the Electronic Signa-
ture or Block Protection Status), Program, Block
Erase, Chip Er ase, Erase Suspend and Erase Re-
sume. The internal P/E.C. automatically handles
all timing and verification of the Program and
Erase operations. The Status Register Data Poll-
ing, Toggle, Error bits and the R B output may be
read at any time, during programming or erase, to
monitor the progress of the operation.
In stru ctions a re compo se d o f up t o si x cycles. The
first two cycles input a Coded sequence to the
Command Interface which is common to all in-
structions (see Ta ble 9) . The thir d cycl e i nputs the
instruction set-up command. Subsequent cycles
output the addressed data, Electronic Signature or
Block Protection Status for Read operations . In or-
der to give additional data protection, the instruc-
tions fo r Pr ogram and Block or Chip Erase require
further command inputs. For a Program instruc-
tion, the fourth command cycle inputs the address
and data t o be programmed. For an Erase instruc-
tion (Block or Chip), the fourth and fifth cycles in-
put a further Coded sequence before the Erase
confirm com m and on the s ixth c ycle. Eras ure of a
memory block may be suspended, in order to read
data from anot her block or to program data in an-
other block , and t hen resumed.
When power is first applied or if VCC falls below VL-
KO, the command int erface is reset to Read Array.
The block erase operation can be suspended in
order to read from or program to any block not be-
ing erased, and then resumed.
Block protection provides additional data security.
Each block can be separat ely prot ect ed or unpro-
tected agains t Program or Erase on programmi ng
equipmen t. All previously prote cted blocks can be
temporarily unpr otected in the appli cation.
Bus Operation s
The following operations can be performed using
the appropriate bus cycles: Read (Array, Electron-
ic Signature, B lock Pro tection Status ), W rite com-
mand, Output Disable, Stand-by, Reset, Block
Protection, Unprotect ion, Protection Verify, Unpro-
tection Verify and Block Temporary Un protection.
See Tables 5 and 6.
Command Interface
Instructions, made u p of commands wri tten in cy-
cles, can be given to the Program/Erase Controller
through a Command Interface (C.I.). For added
data protection, program or erase execution starts
after 4 or 6 cycles. The first, second, fourth and
fifth cycles are used to input Coded cycles to the
C.I. Thi s Coded seq uence is the same for all Pro-
gram/Erase Controller instructions. The ’Com-
mand’ itself and its confirma tion, when applicable,
are given on the third, fourth or sixth cycles. Any
incorrect command or any improper command se-
quence will reset t he device to Read Array mode.
Table 2. Absolute M axim um Ratings (1)
Note: 1. Exc ept for th e rating " Operating T em perature Ran ge" , stresses a bove th ose lis te d i n the Table "A bsolute Maxi m um Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above thos e ind i cated in the Opera t in g sect i ons of this s pecifi cation is not i mpli ed. Exposure to Absol ut e Maximum R ating condi-
tio ns for extended pe riods may aff ect device re liab ility. Refer also to t he STMicroelectronics SURE Program and other relevant qual-
i ty do cu m ent s .
2. Mini m um Voltage may undershoot to –2V during transit i on and for less tha n 20ns during trans i tions.
3. Depends on range.
Symbol Parameter Value Unit
TAAmbient Operating Temperature (3) –40 to 85 °C
TBIAS Temperature Under Bias –50 to 125 °C
TSTG Storage Temperature –65 to 150 °C
VIO (2) Input or Output Voltage –0.6 to 5 V
VCC Supply Voltage –0.6 to 5 V
V(A 9, E, G, RP) (2) A9, E, G, RP Voltage –0.6 to 13.5 V
M29W008AT, M29W008AB
4/30
Table 3. T op Boot Block Addresses,
M29W008AT
#Size
(Kbytes) Address Range
18 16 FC000h-FFFFFh
17 8 FA000h-FBFFFh
16 8 F8000h-F9FFFh
15 32 F0000h-F7FFFh
14 64 E0000h-EFFFFh
13 64 D0000h-DFFFFh
12 64 C0000h-CFFFFh
11 64 B0000h-BFFFFh
10 64 A0000h-AFFFFh
9 64 90000h-9FFFFh
8 64 80000h-8FFFFh
7 64 70000h-7FFFFh
6 64 60000h-6FFFFh
5 64 50000h-5FFFFh
4 64 40000h-4FFFFh
3 64 30000h-3FFFFh
2 64 20000h-2FFFFh
1 64 10000h-1FFFFh
0 64 00000h-0FFFFh
Table 4. Bo ttom Boo t Block Addresses,
M29W008AB
#Size
(Kbytes) Address Range
18 64 F0000h-FFFFFh
17 64 E0000h-EFFFFh
16 64 D0000h-DFFFFh
15 64 C0000h-CFFFFh
14 64 B0000h-BFFFFh
13 64 A0000h-AFFFFh
12 64 90000h-9FFFFh
11 64 80000h-8FFFFh
10 64 70000h-7FFFFh
9 64 60000h-6FFFFh
8 64 50000h-5FFFFh
7 64 40000h-4FFFFh
6 64 30000h-3FFFFh
5 64 20000h-2FFFFh
4 64 10000h-1FFFFh
3 32 08000h-0FFFFh
2 8 06000h-07FFFh
1 8 04000h-05FFFh
0 16 00000h-03FFFh
5/30
M29W008AT, M29W008AB
SIGNA L DESCRIPTIONS
See Figure 1 and Table 1.
Address Inputs (A0-A19). The address inputs
for the memory array are latched during a write op-
eration on the falling edge of Chip Enable E or
Write Enable W. When A9 is raised to VID, either a
Read Electronic Signature Manufacturer or Device
Code, Block Protection Status or a Write Block
Protection or Block Unprotection is enabled de-
pending on the combination of levels on A0, A1
A6, A12 and A15.
Data Input/Outputs (DQ0-DQ7). The input is
data to b e programm ed in the mem ory array o r a
command t o be written to the C. I. Both are latched
on the rising edge of Chip Enable E or Write En-
able W. The output is data from the Memory Array,
the Electronic Signature Manufacturer or Device
codes, the Block Protection Status or the Status
register Data Polling bit DQ7, the Toggle Bits DQ6
and DQ2, the Error bit DQ5 or the E rase Timer bit
DQ3. Outputs are valid when Chip Enable E and
Output Enable G are active. The output is high im-
pedance when the chip is deselected or the out-
puts are disabled and when RP is at a Low level.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense ampli fiers. E Hi gh deselects the
memory and reduces the power consumption to
the stand-by level. E can also be u se d to control
writing to the comm and register and t o the memo-
ry array, while W r emains a t a low lev e l . The Chip
Enable must be forced to VID during the B lock Un-
protection oper ation.
Output Enable (G). The Output Enable gates the
outputs through t he data buffers dur ing a read op-
eration. Wh en G is High the ou tputs are High im-
pedance. G must be forced to VID level during
Block Prot ection and Unprotection operations.
Write Enable (W). This input controls writing to
the Command Register and Address and Data
latches.
Ready/Busy Output (RB). Ready/Busy is an
open-drain output and gives the internal state of
the P/E.C. of the device. When RB is Low, the de-
vice is Busy with a Program or Erase operation
and it will not accept any additional program or
erase instructions except the Erase Suspend in-
struction.
When RB is High, the device is ready for any
Read, Program or Erase operation. The RB will
also be High when the memory is put in Erase
Suspend or Stand-by modes.
Reset/Block Temporary Unprotect Input (RP).
The RP Input provides hardware reset and pro-
tected block(s) temporary unprotection functions.
Reset of the memory is achieved b y pulli ng RP to
VIL for at least tPLPX. When the reset pulse is giv-
en, if the memory i s in Read or Stand-by modes, it
will be available for new operations in tPHEL after
the rising edge of RP.
If the mem ory is in Eras e, E ra se Suspend or P ro-
gram modes the reset wil l take tPLYH during which
the RB signal will be held at VIL. The end of the
memory reset will be indicated by the rising e dge
of RB. A hard ware reset during an Erase or Pro-
gram operation will corrupt the data being pro-
grammed or the sector(s) being erased. See
Tables 15, 16 and Figure 8.
Temporary block unprotect ion is made by holding
RP at VID. In this condition previously protected
blocks can be programmed or erased. The transi-
tion of RP from VIH to VID must slower than tPH-
PHH. (S ee Tables 17, 18 and Figure 8). When RP
is returned from VID to VIH all blocks temporarily
unprotected will be agai n protected.
VCC Supply Voltage. The power supply for all
operations (Read, Program and Erase).
VSS Ground. VSS is the reference for all voltage
measurements.
M29W008AT, M29W008AB
6/30
DEVICE OPERATIONS
See Tables 5, 6 and 7.
Read. Read operations are used to output the
contents of the Memo ry Array, th e Electronic Sig-
nature, the Stat us Regist er or t he Block P rotection
Status. B oth Chi p E nab le E and Output E nable G
must be low in order to read the output of the mem-
ory. A new read operation is initiated either o n the
falling edge of Chip, Enable E, or on any address
trans it ion with E at VIL.
Write. Write operations are u sed to give Instruc-
tion Commands to the memory or to latch input
data to be programmed. A write operation is initi-
ated when Chip Enabl e E is Low and Write Enabl e
W is Low wi th Output Enable G High. Addresses
are latched on the falling edge of W or E whichever
occurs last. Commands and Input Data are
latched on the rising edge of W or E whichever oc-
cu rs first.
Outp ut Disable. The data outputs are high im-
pedance when the Output Enable G is High with
Write Enable W High.
Stand-by. The memory i s in stand-by wh en Chip
Enable E is High and the P/E.C. is i dle. T he power
consump tio n is reduced to t he stand-by level and
the outputs are high impedance, independent of
the Out put Enable G or Write Enable W inputs.
Automatic Sta nd-by. Aft er 150ns of bus inactivi-
ty (no address transition, E = VIL) and when CMOS
levels are dri ving the addresses, the chip automat-
ically enters a pseudo-stand-by mode where con-
sumption is reduced to the CMOS stand-by value,
while output s st ill dr iv e the bus (if G = VIL).
Electronic Sign ature . Tw o codes identifying the
manufacturer and the device can be read from the
memory. The manufacturer’s code for STMicro-
electronics is 20h, the device code is D2h for the
M29W008AT (Top Boot) and DCh for the
M29W008AB (Bottom Boot). These codes allow
programming equipment or applications to auto-
matically match their interface to the characteris-
tics of the M29W008A. T he Electronic Signature i s
output by a Read operation when the voltage ap-
plied to A9 is at VID and address inputs A 1 is Low.
The manufacturer code is output when the Ad-
dress input A0 is Low and the device code when
this input is High. Other Address inputs are ig-
nored. The Electronic Signature can al so be read,
without raising A9 to VID, by giving the memory the
In stru ction AS.
Block Protection. E ach block can be separately
protected again st Program or Erase o n program-
ming equipment. Block protection provides addi-
tional data security, as it disables all program or
erase operations. This mode is activated when
both A9 and G are raised to VID and an address in
the block is appl ied on A13-A1 9. Block protection
is initiated on the edge of W falling to VIL. T hen af-
ter a delay of 100µs, the edge of W rising to VIH
ends the protection operations. Block protection
verify is achieved by bringing G , E, A0 a nd A6 to
VIL and A1 to VIH, while W is at VIH and A9 at VID.
Under these conditions, reading the data output
will yield 01h if the block defined by the inputs on
A13-A19 is protected. Any attempt to program or
erase a protected block will be ignor ed by the de-
vice.
Block Temporary U nprotection . Any prev iously
protected b lock can be t em poraril y unprot ected in
order to change stored data. The temporary un-
protection mode is activated by bringing RP to VID.
During the temporary unprotection mode the pre-
viously protect ed blocks a re unprotect ed. A block
can be selected and data c an be modif i ed by exe-
cuting the Erase or Program instruction with the
RP signal held at VID. When RP is returned to VIH,
all the previously protected blocks are again pro-
tected.
Block Unprotection. All protected blocks can be
unprotected on programming equipment to allow
updating of bit contents. All blocks must first be
protected bef ore the unprotection operation. Block
unprotection is activated when A9, G and E are at
VID an d A12, A15 at V IH. Un protection is init iated
by the edge of W falling to VIL. After a delay of
10ms, the unprotection operation will end. Unpro-
tection verify is achieved by bringing G and E to
VIL while A0 is at VIL, A6 and A1 are at VIH and A9
remains at VID. In these conditions, reading the
output data will y ield 00h if the block defined by the
inputs A13-A19 has been successfully unprotect-
ed. Each block must be separat ely verified by giv-
ing its address in order to ensure that it has been
unprotected.
7/30
M29W008AT, M29W008AB
Table 5. User Bus Operations (1)
No te: 1. X = V IL or VIH.
2. Block Address must be gi ven an A1 3-A19 bits.
3. See Table 7.
4. Oper a t i on perfor m ed on progra m m i n g equi pm ent.
Table 6. Read Electronic Sign atur e (following AS instru ction or with A9 = V ID)
Table 7. Read Block Protection with AS Instruction
Operation E G W RP A0 A1 A6 A9 A12 A15 DQ0-DQ7
Read Byte VIL VIL VIH VIH A0 A1 A6 A9 A12 A15 Data Output
Write Byte VIL VIH VIL VIH A0 A1 A6 A9 A12 A15 Data Input
Output Disable VIL VIH VIH VIH XXXXXX Hi-Z
Stand-by VIH XX
V
IH XXXXXX Hi-Z
Reset X X X VIL XXXXXX Hi-Z
Block
Protection (2,4) VIL VID VIL Pulse VIH XXX
V
ID XX X
Blocks
Unprotection (4) VID VID VIL Pulse VIH XXX
V
ID VIH VIH X
Block
Protection
Verify (2,4) VIL VIL VIH VIH VIL VIH VIL VID A12 A15 Block
Protect
Status(3)
Block
Unprotection
Verify (2,4) VIL VIL VIH VIH VIL VIH VIH VID A12 A15 Block
Protect
Status(3)
Block
Temporary
Unprotection XX X V
ID XXXXXX X
Code Device E G W A0 A1 Other
Addresses DQ0-DQ7
Manufact. Code VIL VIL VIH VIL VIL Don’t Care 20h
Code E G W A0 A1 A13-A19 Other
Addresses DQ0-DQ7
Protected Block VIL VIL VIH VIL VIH Block Address Don’t Care 01h
Unprotected Block VIL VIL VIH VIL VIH Block Address Don’t Care 00h
M29W008AT, M29W008AB
8/30
Table 8. Commands
Hex Code Command
00h Invalid/Reserved
10h Chip Erase Confirm
20h Reserved
30h Block Erase Resume/Confirm
80h Set-up Erase
90h Read Electronic Signature/
Block Protection Status
A0h Program
B0h Erase Suspend
F0h Read Array/Reset
INSTRUCTIONS AND COMMANDS
The Command Interface latches commands writ-
ten to the mem ory. Instructions are m ade u p from
one or more commands to perform Read Me mory
Array, Read Electronic Signature, Read Block Pro-
tection, Program , Block Eras e, Chip E rase, Erase
Suspend and Erase Resume. Commands are
made of address and data sequences. The in-
structions require from 1 to 6 cycles, t he first or first
three of which are always wri te operations used to
initiate the instruction. They are followed by either
further write cycles t o confirm the first command or
execute the command immediately. Command se-
quencing must be followed exactly. Any invalid
combination of com mands will reset the device t o
Read Array. Th e increase d number of cycles has
been chosen to assure maximum data security. In-
structions are initiali sed by two initial Coded cycles
which unlock the Com ma nd Interface. In addition,
for E rase, i nstruction confirmation is again preced-
ed by the two Coded cycles.
Status Reg ister Bits
P/E.C. status is indicated during execution by Data
Polling on DQ7, detection of Toggl e on DQ6 and
DQ2, or Error on DQ5 and E rase T im er DQ3 bits.
Any read attempt during Program or Erase com-
mand execution will automatically output these
five Status Register bits. The P /E.C. automatically
sets bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other
bits (DQ0, DQ 1 and D Q4) a re reserved for future
use and should be masked. See Tables 10 and 11.
Data Polling Bit (DQ7). When Programming op-
erations are i n progress, this bit out puts the com-
plement of the bit being programmed on DQ7.
During Erase operation, it output s a ’0’. After com-
pletion of the operation, DQ7 will output the bit last
pro gram me d or a ’1 ’ after e rasi ng. Data P ollin g is
valid and only effective during P/E.C. operation,
that is after the fourth W pul se for programmi ng or
after the sixth W pulse for erase. It must be per-
formed at the address being programme d or at an
address within the block being erased. If all the
blocks selected for erasure are protected, DQ7 wil l
be set to '0' for about 100µs, and t hen ret urn to the
previous addressed memory data value . Se e F ig-
ure 10 f or the Data Polling f lowcha rt a nd F igure 9
for the Data Polling waveforms. DQ 7 will also flag
the Eras e Suspend mode by switching from '0' to
'1' at the start of the Erase Suspend. In order to
monitor DQ 7 in the Era se Suspend mode an ad-
dress within a block being erased must be provid-
ed. For a Read Operation in Erase Suspend
mode, DQ 7 will output '1' if the read is attem pted
on a block being erased and the data value on oth-
er blocks. During Program operation in Erase Sus-
pend Mode, DQ7 will have the same behavior as
in the normal program execution outside of the
suspend mod e.
Toggle Bit (DQ6). When Programming or Eras-
ing operations are in progress, successive at-
tempts to read DQ6 will output complementary
data. DQ6 will toggle following toggling of either G ,
or E when G is low. The operation is completed
when two successive reads yield the s ame output
data. The next read will output the bit last pro-
grammed or a '1' af ter eras ing. The toggle bi t DQ6
is valid only during P/E.C. op erations , that i s after
the fourth W pulse for programming or after the
sixth W pulse fo r Era se. If the blocks selected for
erasure are protected, DQ6 will toggle for about
100µs an d then return ba ck to Read. DQ6 will be
set to '1' if a Read operation is attempted on an
Erase Suspend block. When erase is suspended
DQ6 will toggle during programmin g operations in
a block different to the block in Erase Suspend. Ei-
ther E or G toggling will cause DQ6 to toggle. See
Figure 11 for Toggle Bit flowchart and Figure 12
for To gg le Bit wa v e for ms.
9/30
M29W008AT, M29W008AB
Table 9. Instructions (1)
Note: 1. Commands not interpre t ed in this tab le will defau lt to read array mod e.
2. A wait of tPLYH is necessary af ter a Read/Reset command if the memory was in an Erase or Program mode before starting any new
operation (se e T ables 15, 1 6 and Figur e 9).
3. X = Don’t Car e.
4. The first cycles of the RD or A S instructions are followed by read operations. A ny num ber of read cycl es can occur after the com-
ma n d cyc les.
5. Signature A ddress bit s A 0, A1, at VIL will output Manufactu rer code (20h). Add ress bits A0 at VIH and A1, at VIL will output Devic e
code.
6. Block Protec tion Address: A 0, at VIL, A1 at VIH and A13-A19 within th e Block will output the Block Protection status.
7. For C oded cyc l es addres s inputs A15-A19 are don’t car e.
8. Optional, add iti onal B l ocks addresses m ust be entered within the erase timeout delay after last writ e e nt ry, ti m eout statusc a n b e
verified thro ugh DQ3 value (see Erase T imer Bit DQ3 description). When full command is entered , read Data Polling or Tog gle bit
until Erase is completed or suspended.
9. Rea d Data Po l l i ng, T oggle bits or R B unti l Erase co m pl et es.
10. Duri ng Erase Suspend , R ead and Dat a Program functi ons are all owed in bl ocks not bei ng erased.
Mne. Instr. Cyc. 1s t Cyc. 2 nd Cyc. 3 rd C yc. 4th Cyc. 5 th Cyc. 6t h Cyc. 7th Cyc.
RD (2,4) Read/Reset
Memory Array
1+ Addr. (3,7) XRead Memory Array until a new write c ycle is initiated.
Data F0h
3+ Addr. (3,7) 555h 2AAh 555h Read Memory Array until a new write cycle is
initiated.
Data AAh 55h F0h
AS (4) Auto Select 3+ Addr. (3,7) 555h 2AAh 555h Read E le ct ronic Signatur e or Block Protecti on
Status until a ne w write cycle is initiated. See Note 5
and 6.Data AAh 55h 90h
PG Program 4 Addr. (3,7) 555h 2AAh 555h Program
Address Re ad Data Polling or Togg le Bit until
Program com pl et es.
Data AAh 55h A0h P rogram
Data
BE Blo ck Erase 6Addr. (3,7) 555h 2AAh 555h 555h 2AAh Block
Address Additional
Block (8)
Data AAh 55h 80h AAh 55h 30h 30h
CE Chip Erase 6Addr. (3,7) 555h 2AAh 555h 555h 2AAh 555h Note 9
Data AAh 55h 80h AAh 55h 10h
ES (10) Eras e S uspend 1 Addr. (3,7) XRead until Toggl e stops, t hen read al l th e data needed from any Block(s) not
bein g erased then Res um e E rase.
Data B0h
ER Erase Resu me 1 Addr. (3,7) XRead Data Polling or Toggle Bits until Erase completes or Erase is suspended
another time.
Data 30h
M29W008AT, M29W008AB
10/30
Table 10. Status Register Bits
No te : Log i c le vel ’1’ i s High, ’0’ is Low. -0-1-0-0-0-1-1-1 -0- represent bit value in s uccess i ve Read operations.
DQ Name Logic Level Definition Note
7Data
Polling
’1’ Erase Complete or erase block
in Erase Suspend
Indicates the P/E.C. status, check during
Program or Erase, and on completion before
checking bits DQ5 for program or Erase
Success.
’0’ Erase On-going
DQ Program Complete or data of
non erase block during Erase
Suspend
DQ Program On-going
6 Toggle Bit
’-1-0-1-0-1-0-1-’ Erase or Program On-going Successive reads output complementary
data on DQ6 while Programming or Erase
operations are on-going. DQ6 remains at
constant level when P/E.C. operations are
completed or Erase Suspend is
acknowledged.
DQ Program Complete
’-1-1-1-1-1-1-1-’ Erase Complete or Erase
Suspend on currently
addressed block
5 Error Bit ’1’ Program or Erase Error This bit is set to ‘1’ in the case of
Programming or Erase failure.
’0’ Program or Erase On-going
4 Reserved
3Erase
Time Bit
’1’ Erase Timeout Period Expired P/E.C. Erase operation has started. Only
possible command entry is Erase Suspend
(ES).
’0’ Erase Timeout Period On-going An additional block to be erased in parallel
can be entered to the P/E.C.
2 Toggle Bit
’-1-0-1-0-1-0-1-’
Chip Erase, Erase or Erase
Suspend on the currently
addressed block.
Erase Error due to the currently
addressed block
(when DQ5 = ‘1’). Indicates the erase status and allows to
identify the erased block.
1Program on-going, Erase on-
going on another block or
Erase Complete
DQ Erase Suspend read on non
Erase Suspend block
1 Reserved
0 Reserved
11/30
M29W008AT, M29W008AB
confirmation command. The Coded cycles consist
of writing the data AAh at address 555h during the
first cycle. During the second cycle the Coded cy-
cles consist of writing the data 55h at address
2AAh. A0 to A11 are valid, other address lines are
’ don’t care’. The Coded cycles happen on f ir st and
second cycles of the command write or on the
fourth and fifth cycles.
Instructions
See Tabl e 9.
Read/Rese t (RD) In structi on. The Read/Reset
instruction consists of one write cycle giving the
command F0h. It can be optionally preceded by
the two Coded cycles. Subsequent read opera-
tions will read the memory array addressed and
output the data read. A wait state of 10µs is nec-
essary after Read/Re set p rior to any valid read if
the mem ory w as in a n Erase mode when the RD
instruction is given. The Read/Reset comman d is
not accepted during Erase and Erase Suspend.
Auto Select (AS ) Instruction. This instruction
uses the two Coded cycles followed by one write
cycle giving the command 90h t o address 555h for
command set-up. A subsequent read will output
the manufac turer code and the device code or the
block protectio n status depending on the levels of
A0 and A1. The manufacturer code, 20h, is output
when the addresses lines A0 and A1 are Low, the
device code, EAh for Top Boot, EBh for Bottom
Boot is outp ut when A0 is High wi th A1 Low.
The AS instruction also allows access t o the block
protection status. After giving the AS instruction,
A0 and A 6 are set to VIL with A1 at VIH, while A13-
A19 def ine the address of the block to be verified.
A read in these condi tio ns will output a 01h if the
block is prot ec ted and a 00h i f the block is not pro-
tected.
Prog ram (PG ) Instru ct ion. This instruction uses
four write cycles. The Program command A0h is
writ ten to address 555h on the thi rd cycle after two
Coded cycles. A fourth w rite operation latches the
Address on the f alling edge of W or E and the Data
to be written on the rising edge and starts the P/
E.C. Read operations output the Status Register
bits after the programming has started. Memory
programming is made only by writing '0' in place of
'1'. Status bits DQ6 and DQ7 determine if pro-
gramming is on-going and DQ5 allows verificati on
of any possible error. Programm ing at an address
not in blocks being erased i s a lso possible during
erase suspend. In this case, DQ2 will toggle at the
address being programmed.
Tabl e 11. Polling and Toggle Bits
Note: 1. Togg l e i f t he address is with i n a bl ock being erased.
’1 ’ if th e address is withi n a bloc k not being erased.
Mode DQ7 DQ6 DQ2
Program DQ7 Toggle 1
Erase 0 Tog gle Note 1
Erase Suspend Read
(in Erase Suspend
block) 1 1 Toggle
Erase Suspend Read
(outside Erase Suspend
block) DQ7 DQ6 DQ2
Erase Suspend Program DQ7 Toggle N/A
Toggle Bit (DQ2). This toggle bit, together with
DQ6, can be used to det ermine the d evice status
during the Erase operations. It c an also be used to
identify the block being erased. During Erase or
Erase Suspen d a read from a block bei ng erased
will cause D Q2 to toggl e. A read from a block not
being erased will set DQ2 to '1' during erase and
to DQ2 during Erase Suspend. During Chip Erase
a read operation will cause DQ2 to toggle as all
blocks are being er ase d. DQ2 will be set to ' 1' dur-
ing program operation and when erase is com-
plete. After erase completion and if the error bit
DQ5 is set to '1', DQ2 will toggle if the fa ulty block
is address ed.
Error Bi t (DQ5 ). This bit is set to '1' by the P/E.C.
when there is a failure of programming, block
erase, or chip erase that results in invalid data in
the memory block. In case of an error in block
erase or prog ram, the bl oc k in wh ich t he error oc-
curred or to which the program me d dat a belong s,
must be dis ca rded. The DQ5 f ailure condition will
also appear if a u ser t ries t o prog ram a '1' to a lo-
cation that is previously programm ed to '0'. Other
Blocks may still be used. The error bit resets after
a Read/Reset (RD) instr uction. In case of success
of Program or Erase, the error bit wi ll be set to '0'.
Erase Timer Bit (DQ3). This bi t is set to ' 0' by the
P/E.C. when the last block Erase command has
been entered to the Command Interface and it is
awaiting the Erase start. When the erase timeout
period is finished, aft er 50µs to 90µs, DQ3 returns
to '1'.
Coded Cycles
The two Coded cycles unlock the Com mand Inter-
face. They are followed by an input command or a
M29W008AT, M29W008AB
12/30
Figure 3. AC Testing Input Output Waveform
AI01417
3V
0V
1.5V
Figure 4 . AC Testing Load Circuit
AI01968
0.8V
OUT
CL = 30pF or 100pF
CL includes JIG capacitance
3.3kΩ
1N914
DEVICE
UNDER
TEST
Table 13. Capacitance (1) (TA = 25 °C, f = 1 MHz)
No te : Sam pled o nl y, not 10 0% t ested .
Table 14. DC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 2. 7V to 3.6V)
Not e: 1. Sampled only, not 100% tested.
Symbol Parameter Test Condition Min Max Unit
CIN Input Capacitance VIN = 0V 6pF
C
OUT Output Capacitance VOUT = 0V 12 pF
Symbol Parameter Test Condition Min Typ. Max Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA
ILO Output Leaka ge Curren t 0V ≤ VOUT ≤ VCC ±1 µA
ICC1 Supply Curre nt (Read) E = VIL, G = VIH, f = 6MHz 310mA
I
CC2 Supply Curre nt (Read) E = VIL, G = VIL, f = 6MHz 4.5 100 mA
ICC3 Supply Current (Stand-by) E = VCC ±0.2V 30 100 µA
ICC4 (1) Supply Curre nt
(Program or Erase) Byte program, Block or
Chip Erase in progress 20 mA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 0.7 VCC VCC + 0.3 V
VOL Output Low Vol tage IOL = 1.8mA 0.45 V
VOH Output High Voltage CMOS IOH = –100µA VCC –0.4V V
VID A9 Voltage (Electronic Signature) 11.5 12.5 V
IID A9 Current (Electronic Signature) A9 = VID 30 100 µA
VLKO (1) Supply Voltage (Erase and
Program lock-out) 2.0 2.3 V
Table 12. AC Measurement Conditions
Input Rise and Fall Times ≤10ns
Input Pulse Voltages 0 to 3V
Input and Output Timing Ref. Voltages 1.5V
13/30
M29W008AT, M29W008AB
Table 15. Read AC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
Not e: 1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the fallin g edge of E without increa sing tELQV.
3. To be c onsidered only if the Rese t pulse is gi ven whil e the memory is in E rase or Pr ogram mode.
Symbol Alt Parameter Test
Condition
M29W008AT / M29W008AB
Unit
80 90
VCC = 3.0V to 3.6V
CL = 30pF VCC = 3.0V to 3.6V
CL = 30pF
Min Max Min Max
tAVAV tRC Address Valid to Next Address
Valid E = VIL,
G=V
IL 80 90 ns
tAVQV tACC Address Valid to Output Valid E = VIL,
G=V
IL 80 90 ns
tAXQX tOH Address Transition to Output
Transition E = VIL,
G=V
IL 00
ns
tEHQX tOH Chip Enable High to Output
Transition G = VIL 00ns
t
EHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL 30 30 ns
tELQV (2) tCE Chip Enable Low to Output Valid G = VIL 80 90 ns
tELQX (1) tLZ Chip Enable Low to Output
Transition G = VIL 00ns
t
GHQX tOH Output Enable High to Output
Transition E = VIL 00ns
t
GHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL 30 30 ns
tGLQV (2) tOE Output Enable Low to Output Valid E = VIL 35 35 ns
tGLQX (1) tOLZ Output Enable Low to Output
Transition E = VIL 00ns
t
PHEL tRH RP High to Chip Enable Low 50 50 ns
tPLYH(1,3) tRRB
tREADY RP Low to Read Mode 10 10 µs
tPLPX tRP RP Pulse Width 500 500 ns
M29W008AT, M29W008AB
14/30
Table 16. Read AC Characteristics
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
Not e: 1. Sampled only, not 100% tested.
2. G may be delayed by up to tELQV - tGLQV after the fallin g edge of E without increa sing tELQV.
3. To be c onsidered only if the Rese t pulse is gi ven whil e the memory is in E rase or Pr ogram mode.
Symbol Alt Parameter Test
Condition
M29W008AT / M29W008AB
Unit
100 120
VCC = 2.7V to 3.6V
CL = 30pF VCC = 2.7V to 3.6V
CL = 30pF
Min Max Min Max
tAVAV tRC Address Valid to Next Address
Valid E = VIL,
G=V
IL 100 120 ns
tAVQV tACC Address Valid to Output Valid E = VIL,
G=V
IL 100 120 ns
tAXQX tOH Address Transition to Output
Transition E = VIL,
G=V
IL 00
ns
tEHQX tOH Chip Enable High to Output
Transition G = VIL 00ns
t
EHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL 30 30 ns
tELQV (2) tCE Chip Enable Low to Output Valid G = VIL 100 120 ns
tELQX (1) tLZ Chip Enable Low to Output
Transition G = VIL 00ns
t
GHQX tOH Output Enable High to Output
Transition E = VIL 00ns
t
GHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL 30 30 ns
tGLQV (2) tOE Output Enable Low to Output Valid E = VIL 40 50 ns
tGLQX (1) tOLZ Output Enable Low to Output
Transition E = VIL 00ns
t
PHEL tRH RP High to Chip Enable Low 50 50 ns
tPLYH(1,3) tRRB
tREADY RP Low to Read Mode 10 10 µs
tPLPX tRP RP Pulse Width 500 500 ns
15/30
M29W008AT, M29W008AB
Figure 5. Read Mode AC Waveforms
AI02191
tAVAV
tAVQV tAXQX
tELQX tEHQX
tGLQV
tGLQX
tGHQX
VALID
A0-A19
E
G
DQ0-DQ7
tELQV
VALID
ADDRESS VALID
AND CHIP ENABLE OUTPUT ENABLE DATA VALID
tEHQZ
tGHQZ
Note: Wri t e Enabl e (W) = High.
M29W008AT, M29W008AB
16/30
Table 17. Write AC Cha racteristics, W Controlled
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
Not e: 1. Sampled only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
Symbol Alt Parameter
M29W008AT / M29W008AB
Unit
80 90
VCC = 3.0V to 3.6V
CL = 30pF VCC = 3.0V to 3.6V
CL = 30pF
Min Max Min Max
tAVAV tWC Address Valid to Next Address Valid 80 90 ns
tAVWL tAS Address Valid to Write Enable Low 0 0 ns
tDVWH tDS Input Valid to Write Enable High 35 45 ns
tELWL tCS Chip Enable Low to Write Enable Low 0 0 ns
tGHWL Output Enable High to Write Enable Low 0 0 ns
tPHPHH (1, 2) tVIDR RP Rise Time to VID 500 500 ns
tPHWL (1) tRSP RP High to Write Enable Low 4 4 µs
tPLPX tRP RP Pulse Width 500 500 ns
tVCHEL tVCS VCC High to Chip Enable Low 50 50 µs
tWHDX tDH Write Enable High to Input Transition 0 0 ns
tWHEH tCH Write Enable High to Chip Enable High 0 0 ns
tWHGL tOEH Write Enable High to Output Enable Low 0 0 ns
tWHRL (1) tBUSY Program Erase Valid to RB Delay 90 90 ns
tWHWL tWPH Write Enable High to Write Enable Low 30 30 ns
tWLAX tAH Write Enable Low to Address Transition 45 45 ns
tWLWH tWP Write Enable Low to Write Enable High 35 35 ns
Block Erase (BE) Instruction. This instruction
uses a minimum of six write cycles. The Erase
Set-up comma nd 80h is written to a ddress 5555h
on third cycle after the two Coded cycles. The
Block Erase Confirm command 30h is similarly
written on the sixth cycle after another two Coded
cycles. During the input of the second command
an addres s within the b lock to be erased is given
and latched into the memory. Additional block
Erase Confirm commands and block addresses
can be written subsequently to erase other blocks
in parallel, without further Coded cycles. The
erase will s tart after th e erase timeout period ( see
Erase Timer Bit DQ3 description). Thus, additional
Erase Confirm commands for other blocks must
be given within this delay. The input of a new
Erase Confirm command will restart the timeout
period. The status of the internal timer can be
monitored through the level of DQ3, if DQ3 is ’0’
the Block Erase Command has been given and
the timeout is running, if DQ3 is ’ 1’, the timeout has
expired and the P/E.C. is erasing the Block(s). If
the second command given is not an erase con-
firm or if the Coded cycles are wrong, the instruc-
tion aborts, and the device is reset to Read Array.
It is not necessary to program the block with 00h
as the P/E.C. will do this automatically before to
erasing to FFh. Read operations after the sixth ris-
ing edge of W or E output the status register stat us
bits.
17/30
M29W008AT, M29W008AB
Table 18. Write AC Cha racteristics, W Controlled
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
Not e: 1. Sampled only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
Symbol Alt Parameter
M29W008AT / M29W008AB
Unit
100 120
VCC = 2.7V to 3.6V
CL = 30pF VCC = 2.7V to 3.6V
CL = 30pF
Min Max Min Max
tAVAV tWC Address Valid to Next Address Valid 100 120 ns
tAVWL tAS Address Valid to Write Enable Low 0 0 ns
tDVWH tDS Input Valid to Write Enable High 45 50 ns
tELWL tCS Chip Enable Low to Write Enable Low 0 0 ns
tGHWL Output Enable High to Write Enable Low 0 0 ns
tPHPHH (1, 2) tVIDR RP Rise Time to VID 500 500 ns
tPHWL (1) tRSP RP High to Write Enable Low 4 4 µs
tPLPX tRP RP Pulse Width 500 500 ns
tVCHEL tVCS VCC High to Chip Enable Low 50 50 µs
tWHDX tDH Write Enable High to Input Transition 0 0 ns
tWHEH tCH Write Enable High to Chip Enable High 0 0 ns
tWHGL tOEH Write Enable High to Output Enable Low 0 0 ns
tWHRL (1) tBUSY Program Erase Valid to RB Delay 90 90 ns
tWHWL tWPH Write Enable High to Write Enable Low 30 30 ns
tWLAX tAH Write Enable Low to Address Transition 45 50 ns
tWLWH tWP Write Enable Low to Write Enable High 35 50 ns
During the execution of the erase by the P/E.C.,
the memory accepts only the Erase Suspend ES
and Read/Reset RD instructions. Data Polling bit
DQ7 returns ’0’ while the erasure is in progress
and ’ 1’ when it has completed. The Toggle bit DQ2
and DQ6 to ggle during the erase op eration. They
stop when erase is completed. After completion
the Status Register bit DQ5 returns ’1’ if there has
been an erase failure. In such a s ituat ion, the Tog-
gle bit DQ2 can be used to det ermine which bl ock
is not correctly erased. In the case of erase failure,
a Read/Reset RD instruction is necessary i n order
to reset the P/E.C.
Chip Erase (CE) Instruction. This instruction
uses six write cycles. The Erase Set -up command
80h is written to address 555h on the third cycle af-
ter t he two Coded cycles. The Chip Erase Confi rm
command 10h is similarly written on the sixth cycle
after another two Coded cycles. If the second
command given is not an erase confirm or if the
Coded cycles are wrong, the instruction aborts
and the device is reset to Read Array. It is not nec-
essary to program the array with 00h first as the P/
E.C. will auto matically do this before erasing it to
FFh. Read operations after t he si xth rising edge of
W or E output the Status Register bits. During the
execution of the erase by the P/E.C., Data Polling
bit DQ7 returns ’0’, then ’1’ on completion. The
Toggle bits DQ2 and DQ6 toggle during erase op-
eration and stop when erase is completed. After
completion the S tatus Re gister bit DQ5 ret urns ’1’
if there has been an Erase Failure.
M29W008AT, M29W008AB
18/30
Figure 6. Write AC Wavefo rms, W Controlled
Note: Addr ess are lat ched on the fallin g edge of W, Data is latched on the rising edge of W.
AI02192
E
G
W
A0-A19
DQ0-DQ7
VALID
VALID
VCC
tVCHEL
tWHEH
tWHWL
tELWL
tAVWL
tWHGL
tWLAX
tWHDX
tAVAV
tDVWH
tWLWHtGHWL
RB
tWHRL
Erase Suspe nd (ES) Instruction. The Block
Erase operation may be suspended by this in-
struction which consists of writing the command
B0h without any specific address. No Coded cy-
cles are required. It permits reading of data from
another block and programming in another block
while an erase operation is in progress. Erase sus-
pend is accepted only during the Block Erase in-
struction execution. Writing this command during
Erase timeout will, in addition to suspending the
erase, terminate the t imeout. The To ggle bit DQ6
stops toggl ing when the P/E.C. is suspended. The
Toggle bits will stop toggling between 0.1µs and
15µs after the Erase Suspend (E S) command has
been written. The device will then automatically be
set to Rea d Memory Array mode. When erase is
suspended, a Read from blocks being erased wi ll
output DQ2 toggli ng and DQ6 at '1'. A Rea d from
a block not being erased ret urns valid data. During
suspension the memory will respond only to the
Erase Resume ER and the Program PG instruc-
tions. A Program operation can be ini tiated during
erase suspend in one of the blocks not being
erased. It will result in both DQ2 and DQ6 toggling
when the data i s being programmed. A Read/Re-
set command will definitively abort erasure and re-
sult in invalid data in the blocks being erased.
Erase Resu me (ER) In struction. If an Erase
Suspend i nstruction wa s prev iously execut ed, the
erase operation may be resumed by giving the
command 30h, at any address, and without any
Coded cycles.
19/30
M29W008AT, M29W008AB
Table 19. Write AC Cha racteristics, E Controlled
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
Not e: 1. Sampled only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
Symbol Alt Parameter
M29W008AT / M29W008AB
Unit
80 90
VCC = 3.0V to 3.6V
CL = 30pF VCC = 3.0V to 3.6V
CL = 30pF
Min Max Min Max
tAVAV tWC Address Valid to Next Address Valid 80 90 ns
tAVEL tAS Address Valid to Chip Enable Low 0 0 ns
tDVEH tDS Input Valid to Chip Enable High 35 45 ns
tEHDX tDH Chip Enable High to Input Transition 0 0 ns
tEHEL tCPH Chip Enable High to Chip Enable Low 30 30 ns
tEHGL tOEH Chip Enable High to Output Enable Low 0 0 ns
tEHRL (1) tBUSY Program Erase Valid to RB Delay 90 90 ns
tEHWH tWH Chip Enable High to Write Enable High 0 0 ns
tELAX tAH Chip Enable Low to Address Transition 45 45 ns
tELEH tCP Chip Enable Low to Chip Enable High 35 35 ns
tGHEL Outpu t Enable High Chip Enable Low 0 0 ns
tPHPHH (1, 2 ) tVIDR RP Rise TIme to VID 500 500 ns
tPHWL (1) tRSP RP High to Write Enable Low 4 4 µs
tPLPX tRP RP Pulse Width 500 500 ns
tVCHWL tVCS VCC High to Write Enable Low 50 50 µs
tWLEL tWS Write Enable Low to Chip Enable Low 0 0 ns
PO W ER SU PPLY
Power Up
The memory Comman d Interface is res et on pow-
er up to Read Array. The device does not accept
commands o n th e first rising edge of W, if both W
and E are at VIL with G at VIH during power-up.
Any write cycle initiation is blocked when VCC is
below VLKO.
Supply Rails
Normal precaut i ons must be taken fo r supply volt -
age decoupling; each device in a system should
have the VCC rail decoupled with a 0.1µF capacitor
close to the VCC and VSS pins. The PCB trace
widths should be sufficient to carry the VCC pro-
gram and erase currents required.
M29W008AT, M29W008AB
20/30
Table 20. Write AC Cha racteristics, E Controlled
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
Not e: 1. Sampled only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
Symbol Alt Parameter
M29W008AT / M29W008AB
Unit
100 120
VCC = 2.7V to 3.6V
CL = 30pF VCC = 2.7V to 3.6V
CL = 30pF
Min Max Min Max
tAVAV tWC Address Valid to Next Address Valid 100 120 ns
tAVEL tAS Address Valid to Chip Enable Low 0 0 ns
tDVEH tDS Input Valid to Chip Enable High 45 50 ns
tEHDX tDH Chip Enable High to Input Transition 0 0 ns
tEHEL tCPH Chip Enable High to Chip Enable Low 30 20 ns
tEHGL tOEH Chip Enable High to Output Enable Low 0 0 ns
tEHRL (1) tBUSY Program Erase Valid to RB Delay 90 90 ns
tEHWH tWH Chip Enable High to Write Enable High 0 0 ns
tELAX tAH Chip Enable Low to Address Transition 45 50 ns
tELEH tCP Chip Enable Low to Chip Enable High 35 50 ns
tGHEL Outpu t Enable High Chip Enable Low 0 0 ns
tPHPHH (1, 2 ) tVIDR RP Rise TIme to VID 500 500 ns
tPHWL (1) tRSP RP High to Write Enable Low 4 4 µs
tPLPX tRP RP Pulse Width 500 500 ns
tVCHWL tVCS VCC High to Write Enable Low 50 50 µs
tWLEL tWS Write Enable Low to Chip Enable Low 0 0 ns
21/30
M29W008AT, M29W008AB
Figure 7. Write AC Wavefo rms, E Controlled
Note: Addr ess are lat ched on the fallin g edge of E, Dat a i s latche d on the rising edge of E .
Figure 8. Read and Write AC Characteristics, RP Related
AI02193
E
G
W
A0-A19
DQ0-DQ7
VALID
VALID
VCC
tVCHWL
tEHWH
tEHEL
tWLEL
tAVEL
tEHGL
tELAX
tEHDX
tAVAV
tDVEH
tELEHtGHEL
RB
tEHRL
AI02091
RB
W
RP tPLPX
tPHWL
tPLYH
tPHPHH
E
tPHEL
M29W008AT, M29W008AB
22/30
Table 21. Data Pol li ng and Toggle Bi t AC Characteristics (1)
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
Note: 1. All other timings are defined in Read AC Characteristics table.
Table 22. Data Pol li ng and Toggle Bi t AC Characteristics (1)
(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C)
Note: 1. All other timings are defined in Read AC Characteristics table.
Symbol Parameter
M29W008AT / M29W008AB
Unit
80 90
VCC = 3.0V to 3.6V
CL = 30pF VCC = 3.0V to 3.6V
CL = 30pF
Min Max Min Max
tEHQ7V
Chip Enable High to DQ7 Valid
(Program, E Controlled) 10 2400 10 2400 µs
Chip Enable High to DQ7 Valid
(Chip Erase, E Controlled) 1.0 60 1.0 60 sec
tEHQV Chip Enable High to Output Valid (Program) 10 2400 10 2400 µs
Chip Enable High to Output Valid (Chip Erase) 1.0 60 1.0 60 sec
tQ7VQV Q7 Valid to Output Valid (Data Polling) 35 35 ns
tWHQ7V
Write Enable High to DQ7 Valid
(Program, W Controlled) 10 2400 10 2400 ms
Write Enable High to DQ7 Valid
(Chip Erase, W Controlled) 1.0 60 1.0 60 sec
tWHQV Write Enable High to Output Valid (Program) 10 2400 10 2400 µs
Write Enable High to Output Valid (Chip Erase) 1.0 60 1.0 60 sec
Symbol Parameter
M29W008AT / M29W008AB
Unit
100 120
VCC = 2.7V to 3.6V
CL = 30pF VCC = 2.7V to 3.6V
CL = 30pF
Min Max Min Max
tEHQ7V
Chip Enable High to DQ7 Valid
(Program, E Controlled) 10 2400 10 2400 µs
Chip Enable High to DQ7 Valid
(Chip Erase, E Controlled) 1.0 60 1.0 60 sec
tEHQV Chip Enable High to Output Valid (Program) 10 2400 10 2400 µs
Chip Enable High to Output Valid (Chip Erase) 1.0 60 1.0 60 sec
tQ7VQV Q7 Valid to Output Valid (Data Polling) 40 50 ns
tWHQ7V
Write Enable High to DQ7 Valid
(Program, W Controlled) 10 2400 10 2400 ms
Write Enable High to DQ7 Valid
(Chip Erase, W Controlled) 1.0 60 1.0 60 sec
tWHQV Write Enable High to Output Valid (Program) 10 2400 10 2400 µs
Write Enable High to Output Valid (Chip Erase) 1.0 60 1.0 60 sec
23/30
M29W008AT, M29W008AB
Figu re 9. Dat a Po lli ng D Q7 AC Wav e form s
AI02194
E
G
W
A0-A19
DQ7
IGNORE
VALID
DQ0-DQ6
ADDRESS (WITHIN BLOCKS)
DATA OUTPUT VALID
tAVQV
tEHQ7V
tGLQV
tWHQ7V
VALID
tQ7VQV
DQ7
DATA POLLING (LAST) CYCLE MEMORY
ARRAY
READ CYCLE
DATA POLLING
READ CYCLES
LAST WRITE
CYCLE OF
PROGRAM
OR ERASE
INSTRUCTION
tELQV
M29W008AT, M29W008AB
24/30
Table 23. Program , Erase Times and Progr am, Erase E nduran ce Cycl es
(TA = 0 to 70°C; VCC = 2.7V to 3.6V)
Note: 1. Excluded the t ime required to execute bus cycles sequence for program operation.
Parameter M29W008AT / M29W008AB Unit
Min Typ Typical after
100k W/E Cycles Max
Chip Erase (Preprogrammed, VCC = 2.7V) 10 10 sec
Chip Erase (VCC = 2.7V) 15 15 sec
Main Block Erase (VCC = 2.7V) 1.5 15 sec
Chip Program (Byte) (1) 55 sec
Byte Program 10 10 µs
Program/Erase Cycles (per Block) 100,000 cycles
Figure 1 0. Data Polling Flowchart
READ DQ5 & DQ7
at VALID ADDRESS
START
READ DQ7
FAIL PASS
AI01369
DQ7
=
DATA YES
NO
YES
NO
DQ5
= 1
DQ7
=
DATA YES
NO
Figure 11. Data Toggle Flowchart
READ
DQ2, DQ5 & DQ6
START
READ DQ2, DQ6
FAIL PASS
AI01873
DQ2, DQ6
=
TOGGLE NO
NO
YES
YES
DQ5
= 1
NO
YES
DQ2, DQ6
=
TOGGLE
25/30
M29W008AT, M29W008AB
Figure 12. Data Toggle DQ6, DQ2 AC Waveforms
AI02195
E
G
W
A0-A19
DQ6,DQ2
tAVQV
STOP TOGGLE
LAST WRITE
CYCLE OF
PROGRAM
OF ERASE
INSTRUCTION
VALID
VALID
VALID
IGNORE
DATA TOGGLE
READ CYCLE MEMORY ARRAY
READ CYCLE
tWHQV
tEHQV
tELQV
tGLQV
DATA
TOGGLE
READ CYCLE
DQ0-DQ1,DQ3-DQ5,DQ7
N ote: All other ti m i n gs a re as a no rmal Re ad cycl e.
M29W008AT, M29W008AB
26/30
Table 24. Security Block Instruction
No te : 1. Address bits A10-A19 are don’t care f or coded address inputs .
2. Data bits DQ8-DQ15 are don’t ca re for cod ed address inputs .
Mne. Instr. Cyc. Unlock Cycle 2nd Cyc.
1st Cyc.
RDS Read
Security
Data 1Addr. (1) AAh Read OTP Data until a new write cycle is initiated.
Data (2) B8h
Figure 13. Security Block Address Table
Security
Memory Block
AI02740
TOP BOOT BLOCK
000FFh Security
Memory Block
00000h
0E0FFh
0E000h
BOTTOM BOOT BLOCK
SECURIT Y PROTECTION MEMORY AREA
The M29W008A features a security protection
memory area. It consists of a memory bl ock of 256
bytes which is programmed in the ST factory to
store a unique code that uniquely identifies the
part.
This memory bloc k can be read by usi ng the Read
Security Data instruction (RDS) as shown in Table
24.
Read Security Data (RDS) Instruction . This RDS
uses a single write cycle instruction: the command
B8h is written to the address AAh. This sets the
memory to the Read S ecurity mode. Any succes-
sive read attempt will out put th e addressed S ecu-
rity byte until a new write cycle is initiated.
27/30
M29W008AT, M29W008AB
Table 25. Ordering Information Scheme
Devices are shipped from the factory wit h the memory content bits erased t o ’1’.
For a list of availabl e options (S peed, P ack age, et c...) or for further information on any aspect of this de-
vice, pleas e contact the ST Sales Office nearest to you.
Example: M29W008AT 80 N 1 T
Device Type
M29
Operating Voltage
W = 2.7 to 3.6V
Device Function
008A = 8 Mbit (1Mb x8), Boot Block
Array Matrix
T = Top Boot
B = Bottom Boot
Speed
80 = 80 ns
90 = 90 ns
100 = 100 ns
120 = 120 ns
Package
N = TSOP40: 10 x 20 mm
Temperature Range
1 = 0 to 70 °C
5 = –20 to 85°C
6 = –40 to 85 °C
Option
T = Tape & Reel Packing
M29W008AT, M29W008AB
28/30
Table 26. Revision History
Date Description
November 1998 First issue
02/09/00 New document templa te
Document type: from Preliminary Data to Data Sheet
03/06/00 Program Erase Times change (Table 23)
29/30
M29W008AT, M29W008AB
Table 27. TSOP40 - 40 lead Plastic Thin Small Ou tline, 10 x 20mm, Packag e Mech anical Data
Symbol mm inches
Typ Min Max Typ Min Max
A 1.20 0.0472
A1 0.05 0.15 0.0020 0.0059
A2 0.95 1.05 0.0374 0.0413
B 0.17 0.27 0.0067 0.0106
C 0.10 0.21 0.0039 0.0083
D 19.80 20.20 0.7795 0.7953
D1 18.30 18.50 0.7205 0.7283
E 9.90 10.10 0.3898 0.3976
e 0.50 – – 0.0197 – –
L 0.50 0.70 0.0197 0.0276
α0° 5° 0° 5°
N40 40
CP 0.10 0.0039
Figure 14. TSOP 40 - 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline
Drawing is not to scale.
TSOP-a
D1
E
1 N
CP
B
e
A2
A
N/2
D
DIE
C
LA1 α
M29W008AT, M29W008AB
30/30
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