NC7SZ02M5X - FAIRCHILD SEMICONDUCTOR

December 2010

NC7SZ02 • Rev. 1.0.5

NC7SZ02 — TinyLogic

®

UHS Two-Input NOR Gate

NC7SZ02

TinyLogic® UHS Two-Input NOR Gate

Features

 Ultra-High Speed: tPD 2.4ns (Typical) into 50pF at

5V VCC

 High Output Drive: ±24mA at 3V VCC

 Broad VCC Operating Range: 1.65V to 5.5V

 Matches Performance of LCX Operated at 3.3V VCC

 Power Down High-Impedance Inputs/Outputs

 Over-Voltage Tolerance Inputs Facilitate 5V to 3V

Translation

 Proprietary Noise/EMI Reduction Circuitry

 Ultra-Small MicroPak™ Packages

 Space-Saving SOT23 and SC70 Packages

Description

The NC7SZ02 is a single two-input NOR gate from

Fairchild’s Ultra-High Speed (UHS) series of

TinyLogic®. The device is fabricated with advanced

CMOS technology to achieve ultra-high speed with high

output drive while maintaining low static power

dissipation over a broad VCC operating range. The

device is specified to operate over the 1.65V to 5.5V

VCC operating range. The inputs and output are high-

impedance when VCC is 0V. Inputs tolerate voltages up

to 6V, independent of VCC operating voltage.

Ordering Information

Part Number Top Mark Package Packing Method

NC7SZ02M5X 7Z02 5-Lead SOT23, JEDEC MO-178 1.6mm 3000 Units on Tape & Reel

NC7SZ02P5X Z02 5-Lead SC70, EIAJ SC-88a, 1.25mm Wide 3000 Units on Tape & Reel

NC7SZ02L6X JJ 6-Lead MicroPak™, 1.00mm W i de 5000 Units on Tape & Reel

NC7SZ02FHX JJ 6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch 5000 Units on Tape & Reel

NC7SZ02 • Rev. 1.0.5 2

NC7SZ02 — TinyLogic

®

UHS Two-Input NOR Gate

Connection Diagrams

IEEE/IEC

Figure 1. Logic Symbol

Pin Configurations

Figure 2. SC70 and SOT23 (Top View) Figure 3. MicroPak™ (Top Through View)

Pin Definitions

Pin # SC70 / SOT23 Pin # MicroPak™ Name Description

1 1 A Input

2 2 B Input

3 3 GND Ground

4 4 Y Output

5 6 VCC Supply Voltage

5 NC No Connect

Function Table

Y= /A +/B Inputs Output

A B Y

L L H

L H L

H L L

H H L

H = HIGH Logic Level

L = LOW Logic Level

NC7SZ02 • Rev. 1.0.5 3

NC7SZ02 — TinyLogic

®

UHS Two-Input NOR Gate

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device

reliability. The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VCC Supply Voltage -0.5 6.0 V

VIN DC Input Voltage -0.5 6.0 V

VOUT DC Output Voltage -0.5 6.0 V

IIK DC Input Diode Current VIN < -0.5V -50 mA

VIN > 6.0V +20

IOK DC Output Diode Current VOUT < -0.5V -50 mA

VOUT > 6V, VCC=GND +20

IOUT DC Outp ut Current ±50 mA

ICC or IGND DC VCC or Ground Current ±50 mA

TSTG Storage Temperature Range -65 +150 °C

TJ Junction Temperature Under Bias +150 °C

TL Junction Lead Temperature (Soldering, 10 Seconds) +260 °C

PD Power Dissipation at +85°C

SOT-23 200

mW

SC70-5 150

MicroPak™-6 130

MicroPak2™-6 120

ESD Human Body Model, JEDEC:JESD22-A114 4000 V

Charge Device Model, JEDEC:JESD22-C101 2000

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Conditions Min. Max. Unit

VCC Supply Voltage Operating 1.65 5.50 V

Supply Voltage Data Retention 1.5 5.5

VIN Input Voltage 0 5.5 V

VOUT Output Voltage 0 VCC V

TA Operating Temperature -40 +85 °C

tr, tf Input Rise and Fall Times VCC at 1.8V, 2.5V ±0.2V 0 20 ns/V

VCC at 3.3V ± 0.3V 0 10

VCC at 5.0V ± 0.5V 0 5

θJA Thermal Resistance

SOT-23 300

°C/W

SC70-5 425

MicroPak™-6 500

MicroPak2™-6 560

Note:

1. Unused inputs must be held HIGH or LOW. They may not float.

NC7SZ02 • Rev. 1.0.5 4

NC7SZ02 — TinyLogic

®

UHS Two-Input NOR Gate

DC Electrical Characteristics

Symbol Parameter VCC Conditions TA=25°C TA=-40 to +85°C Units

Min. Typ. Max. Min. Max.

VIH HIGH Level I nput

Voltage 1.65 to 1.95 0.75VCC 0.75VCC V

2.30 to 5.50 0.70VCC 0.70VCC

VIL LOW Level I nput

Voltage 1.65 to 1.95 0.25VCC 0.25VCC V

2.30 to 5.50 0.30VCC 0.30VCC

VOH HIGH Level Output

Voltage

1.65

VIN=VIL

IOH=-100µA

1.55 1.65 1.55

V

1.80 1.70 1.80 1.70

2.30 2.20 2.30 2.20

3.00 2.90 3.00 2.90

4.50 4.40 4.50 4.40

1.65 IOH=-4mA 1.29 1.52 1.29

2.30 IOH=-8mA 1.90 2.15 1.90

3.00 IOH=-16mA 2.40 2.80 2.40

3.00 IOH=-24mA 2.30 2.68 2.30

4.50 IOH=-32mA 3.80 4.20 3.80

VOL LOW Level Output

Voltage

1.65

VIN=VIH

IOL=100µA

0.00 0.10 0.10

V

1.80 0.00 0.10 0.10

2.30 0.00 0.10 0.10

3.00 0.00 0.10 0.10

4.50 0.00 0.10 0.10

1.65 IOL=4mA 0.08 0.24 0.24

2.30 IOL=8mA 0.10 0.30 0.30

3.00 IOL=16mA 0.15 0.40 0.40

3.00 IOL=24mA 0.22 0.55 0.55

4.50 IOL=32mA 0.22 0.55 0.55

IIN Input Leakage Current 0 to 5.5 V IN=5.5V, GND ±1 ±10 µA

IOFF Power Off Leakage

Current 0 VIN or VOUT=5.5V 1 10 µA

ICC Quiescent Supply

Current 1.65 to 5.50 VIN=5.5V , GND 2.0 20 µA

NC7SZ02 • Rev. 1.0.5 5

NC7SZ02 — TinyLogic

®

UHS Two-Input NOR Gate

AC Electrical Characteristics

Symbol Parameter VCC Conditions TA=25°C TA=-40 to +85°C Units Figure

Min. Typ. Max. Min. Max.

tPLH, tPHL Propagation Delay

1.65

CL=15pF,

RL=1MΩ

2.0 5.3 11.5 2.0 12.0

ns Figure 4

Figure 5

1.80 2.0 4.4 9.5 2.0 10.0

2.50 ± 0.20 0.8 2.9 6.5 0.8 7. 0

3.30 ± 0.30 0.5 2.3 4.5 0.5 4. 7

5.00 ± 0.50 0.5 1.9 3.9 0.5 4. 1

3.30 ± 0.30 CL=50pF,

RL=500Ω 1.5 2.9 5.0 1.5 5.2

5.00 ± 0.50 0.8 2.4 4.3 0.8 4. 5

CIN Input Capacitance 0 4 pF

CPD Power Dissipati on

Capacitance(2) 3.30 23 pF Figure 6

5.00 30

Note:

2. CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating

current consumption (ICCD) at no output lading and operating at 50% duty cycle. CPD is related to ICCD dynamic

operating current by the expression: ICCD=(CPD)(VCC)(fIN)+(ICCstatic).

Figure 4. AC Test Circuit Figure 5. AC Waveforms

Note:

3. Input=AC Waveform; tr=tf=1.8ns; PRR=10MHz; Duty Cycle=50%.

Figure 6. ICCD Test Circuit

NC7SZ02 • Rev. 1.0.5 6

NC7SZ02 — TinyLogic

®

UHS Two-Input NOR Gate

Physical Dimensions

5

1

4

32

LAND PATTERN RECOMMENDATI ON

B

AL

C

0.10 C

0.20 CAB

0.60 REF

0.55

0.35 SEATING PLANE

0.25

GAGE PLANE

8°

0°

NOTES: UNLESS OTHEWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MO-178, ISSUE B, VARIATION AA,

B) ALL DIMENSIONS ARE IN MILLIMETERS.

1.45 MAX

1.30

0.90

0.15

0.05

1.90

0.95 0.50

0.30

3.00

2.60

1.70

1.50

3.00

2.80

SYMM

C0.950.95

2.60

0.70

1.00

SEE DETAIL A

0.22

0.08

C) MA05Brev5

TOP VIEW

(0.30)

Figure 7. 5-Lead SOT23, JEDEC MO-178 1.6mm

Pack age drawings are provided as a service to customers consideri ng Fai rchild components . Drawings may c hange i n any manner

without notice. P l ease note the revi sion and/or date on t he drawing and contac t a Fairchild S emiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’ s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

Tape and Reel Specifications

Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:

http://www.fairchildsemi.com/packaging/SOT23-5L_tr.pdf.

Package Designator Tape Section Cavity Number Cavity Status Cover Type Status

M5X Leader (Start End) 125 (Typical) Empty Sealed

Carrier 3000 Filled Sealed

Trailer (Hub End) 75 (Typical) Empty Sealed

NC7SZ02 • Rev. 1.0.5 7

NC7SZ02 — TinyLogic

®

UHS Two-Input NOR Gate

Physical Dimensions

Figure 8. 5-Lead, SC70, EIAJ SC-88a, 1.25mm Wide

Pack age drawings are provided as a service to customers consideri ng Fai rchild components . Drawings may c hange i n any manner

without notice. P l ease note the revi sion and/or date on t he drawing and contac t a Fairchild S emiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’ s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

Tape and Reel Specifications

Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:

http://www.fairchildsemi.com/products/analog/pdf/sc70-5_tr.pdf.

Package Designator Tape Section Cavity Number Cavity Status Cover Type Status

P5X Leader (Start End) 125 (Typical) Empty Sealed

Carrier 3000 Filled Sealed

Trailer (Hub End) 75 (Typical) Empty Sealed

NC7SZ02 • Rev. 1.0.5 8

NC7SZ02 — TinyLogic

®

UHS Two-Input NOR Gate

Physical Dimensions

2. DIMENSIONS ARE IN MILLIMETERS

1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD

4. FILENAME AND REVISION: MAC06AREV4

Notes:

3. DRAWING CONFORMS TO ASME Y14.5M-1994

TOP VIEW

RECOMMENED

LAND PATTERN

BOTTOM VIEW

1.45

1.00

A

B

0.05 C

2X

0.55MAX

0.05 C

(0.49)

(1)

(0.75)

(0.52)

(0.30)

6X

1X

6X

PIN 1

DETAIL A

0.075 X 45

CHAMFER

0.25

0.15

0.35

0.25

0.40

0.30

0.5

(0.05)

1.0

5X

DETAIL A

PIN 1 TE RMINAL

0.40

0.30

0.45

0.35

0.10

0.00

0.10 CBA

0.05 C

C0.05 C

0.05

0.00

5X

6X (0.13)

4X

6X

PIN 1 IDENTIFIER

(0.254)

5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY

5

OTHER LINE IN THE MARK CODE LAYOUT.

Figure 9. 6-Lead, MicroPak™, 1.0mm Wide

Pack age drawings are provided as a service to customers consideri ng Fai rchild components . Drawings may c hange i n any manner

without notice. P l ease note the revi sion and/or date on t he drawing and contac t a Fairchild S emiconductor represent ative to v er ify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’ s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

Tape and Reel Specifications

Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:

http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf.

Package Designator Tape Section Cavity Number Cavity Status Cover Type Status

L6X Leader (Start End) 125 (Typical) Empty Sealed

Carrier 5000 Filled Sealed

Trailer (Hub End) 75 (Typical) Empty Sealed

NC7SZ02 • Rev. 1.0.5 9

NC7SZ02 — TinyLogic

®

UHS Two-Input NOR Gate

Physical Dimensions

1.00

B. DIMENSIONS ARE IN MILLIMETERS.

C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994

NOTES:

A. COMPLIES TO JEDEC MO-252 STANDARD

0.05 C A

B

0.55MAX

0.05 C

C

0.35

0.09

0.19

123

0.35

0.25

5X

6X

DETAIL A

0.60

(0.08)

4X

(0.05) 6X

0.40

0.30

0.075X45°

CHAMFER

5X 0.40

0.35

1X 0.45

6X 0.19

TOP VIEW

BOTTOM VIEW

0.66

0.10 CBA

.05 C

0.89

PIN 1

0.05 C

2X

2X 1.00

D. LANDPATTERN RECOMMENDATION IS BASED ON FSC

E. DRAWING FILENAME AND REVISION: MGF06AREV3

0.52

0.73

0.57

0.20 6X

1X

5X

RECOMMENDED LAND PATTERN

FOR SPA CE CONST RAINED PCB

DETAIL A

PIN 1 LEAD SCALE: 2X

ALTERNATIVE LAND PATTERN

FOR UNIVERSAL APPL ICATION

DESIGN.

0.90

MIN 250u M

654

0.35

(0.08) 4X

SIDE VIEW

Figure 10. 6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch

Pack age drawings are provided as a service to customers consideri ng Fai rchild components . Drawings may c hange i n any manner

without notice. P l ease note the revi sion and/or date on t he drawing and contac t a Fairchild S emiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’ s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

Tape and Reel Specifications

Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:

http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf.

Package Designator Tape Section Cavity Number Cavity Status Cover Type Status

FHX Leader (Start End) 125 (Typical) Empty Sealed

Carrier 5000 Filled Sealed

Trailer (Hub End) 75 (Typical) Empty Sealed

NC7SZ02 • Rev. 1.0.5 10

NC7SZ02 — TinyLogic

®

UHS Two-Input NOR Gate