M1Y1G64TU8HA2B / M1Y51264TU88A2B 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM 240pin Unbuffered DDR2 SDRAM MODULE Based on 64Mx8 DDR2 SDRAM Features * JEDEC Standard 240-pin Dual In-Line Memory Module clock edge * 64Mx64 and 128Mx64 DDR2 Unbuffered DIMM based on * Write Latency = Read Latency - 1 64Mx8 DDR2 SDRAM * Programmable Operation: * Performance: - Device CAS Latency: 3, 4, 5 - Burst Type: Sequential or Interleave PC2-5300 Speed Sort 3C * DIMM CAS Latency f CK Clock Frequency t CK Clock Cycle f DQ DQ Burst Frequency - Burst Length: 4, 8 Unit - Operation: Burst Read and Write 5 333 * Auto Refresh (CBR) and Self Refresh Modes MHz 3 ns 667 MHz * Automatic and controlled precharge commands * 14/10/1 Addressing (row/column/bank) - M1Y51264TU88A2B * 14/10/2 Addressing (row/column/bank) - M1Y1G64TU8HA2B * Intended for 333MHz applications * 7.8 s Max. Average Periodic Refresh Interval * Inputs and outputs are SSTL-18 compatible * Serial Presence Detect * VDD = VDDQ = 1.8Volt 0.1 * On Die Termination (ODT) * SDRAMs have 4 internal banks for concurrent operation * Gold contacts * Differential clock inputs * SDRAMs in 60-ball FBGA Package * Data is read or written on both clock edges * RoHs Compliant product * Bi-directional data strobe with one clock cycle preamble and one-half clock post-amble * Address and control signals are fully synchronous to positive Description M1Y51264TU88A2B and M1Y1G64TU8HA2B are 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Unbuffered Dual In-Line Memory Module (UDIMM), organized as a one-rank 64Mx64 and two ranks 128Mx64 high-speed memory array. Modules use eight 64Mx8 (M1Y51264TU88A2B) and sixteen 64Mx8 (M1Y1G64TU8HA2B) DDR2 SDRAMs in FBGA packages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All ELIXIR DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint. The DIMM is intended for use in applications operating up to 333MHz clock speeds and achieves high-speed data transfer rates of up to 667MHz. Prior to any access operation, the device CAS latency and burst / length / operation type must be programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0 and BA1 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. REV 1.0 08/2005 1 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1Y1G64TU8HA2B / M1Y51264TU88A2B 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Ordering Information Part Number Speed Organization M1Y51264TU88A2B-3C Leads Power Gold 1.8V Note 64Mx64 333MHz (3ns @ CL = 5) DDR2-667 PC2-5300 M1Y1G64TU8HA2B-3C 128Mx64 Pin Description CK0, CK0 CKE0, CKE1 Differential Clock Inputs DQ0-DQ63 Clock Enable CB0-CB7 RAS Row Address Strobe CAS Column Address Strobe WE Write Enable DQS0-DQS17 CS0, CS1 Chip Selects VDD Power (1.8V) Address Inputs VREF Ref. Voltage for SSTL_18 inputs A0-A9, A11-A13 A10/AP BA0, BA1 RESET ODT0, ODT1 NC REV 1.0 08/2005 DQS0-DQS8 Data input/output ECC Check Bit Data Input/Output Bidirectional data strobes DM0-DM8/DQS9-17 Input Data Mask/High Data Strobes Column Address Input/Auto-precharge VDDSPD SDRAM Bank Address Inputs VSS Differential data strobes Serial EEPROM positive power supply Ground Reset pin SCL Serial Presence Detect Clock Input Active termination control lines SDA Serial Presence Detect Data input/output No Connect SA0-2 Serial Presence Detect Address Inputs 2 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1Y1G64TU8HA2B / M1Y51264TU88A2B 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Pinout Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back 1 VREF 42 NC 82 VSS 121 VSS 162 NC 202 DM4 2 VSS 43 NC 83 DQS4 122 DQ4 163 VSS 203 NC 3 DQ0 44 VSS 84 DQS4 123 DQ5 164 NC 204 VSS 4 DQ1 45 NC 85 VSS 124 VSS 165 NC 205 DQ38 5 VSS 46 NC 86 DQ34 125 DM0, DQS9 166 VSS 206 DQ39 6 DQS0 47 VSS 87 DQ35 126 DQS9 167 NC 207 VSS 7 DQS0 48 NC 88 VSS 127 VSS 168 NC 208 DQ44 8 VSS 49 NC 89 DQ40 128 DQ6 169 VSS 209 DQ45 9 DQ2 50 VSS 90 DQ41 129 DQ7 170 VDDQ 210 VSS 10 DQ3 51 VDDQ 91 VSS 130 VSS 171 CKE1 211 DM5 11 VSS 52 CKE0 92 DQS5 131 DQ12 172 VDD 212 NC 12 DQ8 53 VDD 93 DQS5 132 DQ13 173 NC 213 VSS 13 DQ9 54 NC 94 VSS 133 VSS 174 NC 214 DQ46 14 VSS 55 NC 95 DQ42 134 DM1, DQS10 175 VDDQ 215 DQ47 15 DQS1 56 VDDQ 96 DQ43 135 DQS10 176 A12 216 VSS 16 DQS1 57 A11 97 VSS 136 VSS 177 A9 217 DQ52 17 VSS 58 A7 98 DQ48 137 CK1 178 VDD 218 DQ53 18 NC 59 VDD 99 DQ49 138 CK1 179 A8 219 VSS 19 NC 60 A5 100 VSS 139 VSS 180 A6 220 CK2 20 VSS 61 A4 101 SA2 140 DQ14 181 VDDQ 221 CK2 21 DQ10 62 VDDQ 102 NC 141 DQ15 182 A3 222 VSS 22 DQ11 63 A2 103 VSS 142 VSS 183 A1 223 DM6 23 VSS 64 VDD 104 DQS6 143 DQ20 184 VDD 224 NC 24 DQ16 105 DQS6 144 DQ21 225 VSS 25 DQ17 65 VSS 106 VSS 145 VSS 185 CK0 226 DQ54 26 VSS 66 VSS 107 DQ50 146 DM2 186 CK0 227 DQ55 27 DQS2 67 VDD 108 DQ51 147 NC 187 VDD 228 VSS 28 DQS2 68 NC 109 VSS 148 VSS 188 A0 229 DQ60 29 VSS 69 VDD 110 DQ56 149 DQ22 189 VDD 230 DQ61 30 DQ18 70 A10/AP 111 DQ57 150 DQ23 190 BA1 231 VSS 31 DQ19 71 BA0 112 VSS 151 VSS 191 VDDQ 232 DM7 32 VSS 72 VDDQ 113 DQS7 152 DQ28 192 RAS 233 NC 33 DQ24 73 WE 114 DQS7 153 DQ29 193 CS0 234 VSS 34 DQ25 74 CAS 115 VSS 154 VSS 194 VDDQ 235 DQ62 KEY KEY 35 VSS 75 VDDQ 116 DQ58 155 DM3 195 ODT0 236 DQ63 36 DQS3 76 CS1 117 DQ59 156 NC 196 A13 237 VSS 37 DQS3 77 ODT1 118 VSS 157 VSS 197 VDD 238 VDDSPD 38 VSS 78 VDDQ 119 SDA 158 DQ30 198 VSS 239 SA0 39 DQ26 79 VSS 120 SCL 159 DQ31 199 DQ36 240 SA1 40 DQ27 80 DQ32 160 VSS 200 DQ37 41 VSS 81 DQ33 161 NC 201 VSS REV 1.0 08/2005 3 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1Y1G64TU8HA2B / M1Y51264TU88A2B 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Input/Output Functional Description Symbol Type Polarity Function CK0, CK1, CK2 (SSTL) The positive line of the differential pair of system clock inputs which drives the input to Positive the on-DIMM PLL. All the DDR2 SDRAM address and control inputs are sampled on the Edge rising edge of their associated clocks. CK0, CK1, CK2 (SSTL) Negative The negative line of the differential pair of system clock inputs which drives the input to Edge the on-DIMM PLL. CKE0, CKE1 (SSTL) Active High Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. CS0, CS1 (SSTL) Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS, WE (SSTL) Active Low When sampled at the positive rising edge of the clock, RAS, CAS, WE define the operation to be executed by the SDRAM. VREF Supply Reference voltage for SSTL-18 inputs VDDQ Supply Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity ODT0, ODT1 Input Active High BA0, BA1 (SSTL) - Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9, A11 defines the column address (CA0-CA10) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. A0 - A9 A10/AP A11 - A13 (SSTL) - DQ0 - DQ63 CB0 - CB7 (SSTL) Active High VDD, VSS Supply DQS0 - DQS8 DQS0 - DQS8 (SSTL) DM0 - DM8 Input On-Die Termination control signals Data and Check Bit Input/Output pins. Check bits are only applicable on the x72 DIMM configurations. Power and ground for the DDR SDRAM input buffers and core logic Negative and Data strobe for input and output data Positive Edge Active High The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not used on x64 modules. SA0 - SA2 - Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. SDA - This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pull-up. SCL - This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pull-up. VDDSPD REV 1.0 08/2005 Supply Serial EEPROM positive power supply. 4 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1Y1G64TU8HA2B / M1Y51264TU88A2B 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Functional Block Diagram (512MB, 1 Rank, 64Mx8 DDR2 SDRAMs) CS0 DQS0 DQS0 DM0 DQS4 DQS4 DM4 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D0 I/O 4 I/O 5 I/O 6 I/O 7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS1 DQS1 DM1 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D1 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS2 DQS2 DM2 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D2 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS3 DQS3 DM3 DQS DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D6 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS DM CS I/O 0 I/O 1 I/O 2 I/O 3 D7 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS7 DQS7 DM7 DQS DM CS I/O 0 I/O 1 I/O 2 I/O 3 D3 I/O 4 I/O 5 I/O 6 I/O 7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 BA0-BA1 : SDRAMs D0-D8 A0-A13 : SDRAMs D0-D8 RAS : SDRAMs D0-D8 CAS : SDRAMs D0-D8 WE : SDRAMs D0-D8 CKE : SDRAMs D0-D8 ODT : SDRAMs D0-D8 BA0-BA1 A0-A13 RAS CAS WE CKE0 ODT0 08/2005 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D5 I/O 4 I/O 5 I/O 6 I/O 7 DQS6 DQS6 DM6 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 REV 1.0 DQS DQS5 DQS5 DM5 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 Notes : DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D4 I/O 4 I/O 5 I/O 6 I/O 7 1. 2. 3. 4. 5. VDDSPD VDDQ VDD VREF VSS VDDID DQ-to-I/O wiring may be changed within a byte. DQ/DQS/DM/CKE/CS relationships are maintained as shown. DQ/DQS/DQS resistors are 22 Ohms +/- 5% BAx, Ax, RAS, CAS, WE resistors are 5.1 Ohms +/- 5% Address and control resistors are 22 Ohms +/- 5% Serial PD D0-D8 D0-D8 D0-D8 D0-D8 Strap : see Note 4 Serial PD SCL WP A0 SA0 A1 A2 SA1 SA2 SDA 5 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1Y1G64TU8HA2B / M1Y51264TU88A2B 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Functional Block Diagram (1GB, 2 Rank, 64Mx8 DDR2 SDRAMs) CS1 CS0 DQS0 DQS0 DM0 DQS4 DQS4 DM4 DQS DM CS I/O 0 I/O 1 I/O 2 I/O 3 D0 I/O 4 I/O 5 I/O 6 I/O 7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS DQS DM CS I/O 0 I/O 1 I/O 2 I/O 3 D8 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS1 DQS1 DM1 DQS DQS DM CS I/O 0 I/O 1 I/O 2 I/O 3 D12 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS DM CS I/O 0 I/O 1 I/O 2 I/O 3 D5 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS DM CS I/O 0 I/O 1 I/O 2 I/O 3 D13 I/O 4 I/O 5 I/O 6 I/O 7 DQS DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D6 I/O 4 I/O 5 I/O 6 I/O 7 DQS DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D14 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS DM CS I/O 0 I/O 1 I/O 2 I/O 3 D7 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS DM CS I/O 0 I/O 1 I/O 2 I/O 3 D15 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQS5 DQS5 DM5 DQS DM CS I/O 0 I/O 1 I/O 2 I/O 3 D1 I/O 4 I/O 5 I/O 6 I/O 7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS DQS DM CS I/O 0 I/O 1 I/O 2 I/O 3 D9 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS2 DQS2 DM2 DQS6 DQS6 DM6 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D2 I/O 4 I/O 5 I/O 6 I/O 7 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 D10 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS3 DQS3 DM3 DQS7 DQS7 DM7 DQS DM CS I/O 0 I/O 1 I/O 2 I/O 3 D3 I/O 4 I/O 5 I/O 6 I/O 7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 Notes : REV 1.0 DQS DQS DM CS I/O 0 I/O 1 I/O 2 I/O 3 D11 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 BA0-BA1 : SDRAMs D0-D17 A0-A13 : SDRAMs D0-D17 RAS : SDRAMs D0-D17 CAS : SDRAMs D0-D17 WE : SDRAMs D0-D17 CKE : SDRAMs D0-D8 CKE : SDRAMs D9-D17 ODT : SDRAMs D0-D8 ODT : SDRAMs D9-D17 BA0-BA1 A0-A13 RAS CAS WE CKE0 CKE1 ODT0 ODT1 08/2005 DQS DM CS I/O 0 I/O 1 I/O 2 I/O 3 D4 I/O 4 I/O 5 I/O 6 I/O 7 1. 2. 3. 4. 5. VDDSPD VDDQ VDD VREF VSS VDDID DQ-to-I/O wiring may be changed within a byte. DQ/DQS/DM/CKE/CS relationships are maintained as shown. DQ/DQS/DQS resistors are 22 Ohms +/- 5% BAx, Ax, RAS, CAS, WE resistors are 5.1 Ohms +/- 5% Address and control resistors are 22 Ohms +/- 5% Serial PD D0-D8 D0-D8 D0-D8 D0-D8 Strap : see Note 4 Serial PD SCL WP A0 SA0 SDA A1 A2 SA1 SA2 6 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1Y1G64TU8HA2B / M1Y51264TU88A2B 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect - Part 1 of 2 (512MB) 64Mx64 1 BANK UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte Description SPD Entry Value Serial PD Data Entry (Hexadecimal) DDR2 -667 (-3C) DDR2 -667 (-3C) 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type 3 Number of Row Addresses on Assembly DDR2-SDRAM 08 14 0E 4 Number of Column Addresses on Assembly 5 Number of DIMM Bank, Package, and Height 10 0A 1 rank, Height=30mm 6 Data Width of this Assembly 60 X64 40 7 Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL_1.8V 05 9 DDR2 SDRAM Device Cycle Time at Maximum Support CAS Latency CL=5 3ns 30 10 DDR2 SDRAM Device Access Time (tac) from Clock at CL=5 0.45ns 45 11 DIMM Configuration Type Non - ECC 00 12 Refresh Rate/Type 7.8s/self 82 13 Primary DDRII SDRAM Width X8 08 14 Error Checking DDRII SDRAM Device Width N/A 00 15 Reserved 16 DDR2 SDRAM Device Attributes: Burst Length Supported 17 18 Undefined 00 4,8 0C DDR2 SDRAM Device Attributes: Number of Device Banks 4 04 DDR2 SDRAM Device Attributes: CAS Latencies Supported 3/4/5 38 19 DIMM Mechanical Characteristics 20 DDR2 SDRAM DIMM Type Information 4.10mm 01 Regular UDIMM (133.35mm) 02 21 DDR2 SDRAM Module Attributes: Normal DIMM 00 22 DDR2 SDRAM Device Attributes: General Support weak driver 03 23 Minimum Clock Cycle at CL=4 3.75ns 3D 24 Maximum Data Access Time (tac) from Clock at CL=4 0.5ns 50 25 Minimum Clock Cycle Time at CL=3 5ns 50 26 Maximum Data Access Time (tac) from Clock at CL=3 0.6ns 60 27 Minimum Row Precharge Time (tRP) 15ns 3C 28 Minimum Row Active to Row Active delay (tRRD) 7.5ns 1E 29 Minimum RAS to CAS delay (tRCD) 15ns 3C 30 Minimum Active to Precharge Time (tRAS) 45ns 2D 512MB 80 0.2ns 20 27 31 Module Bank Density 32 Address and Command Input Setup Time Before Clock (tIS) 33 Address and Command Input Hold Time After Clock (tIH) 0.275ns 34 Data Input Setup Time Before Clock (tDS) 0.10ns 10 35 Data Input Hold Time After Clock (tDH) 0.175ns 17 36 Write Recovery Time (tWR) 15ns 3C 37 Internal Write to Read Command delay (tWTR) 7.5ns 1E 38 Internal Read to Precharge Command delay (tRTP) 7.5ns 1E 39 Memory Analysis Probe Characteristics Undefined 00 REV 1.0 08/2005 Note 7 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1Y1G64TU8HA2B / M1Y51264TU88A2B 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect - Part 2 of 2 (512MB) 64Mx64 1 BANK UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte 40 SPD Entry Value Serial PD Data Entry (Hexadecimal) DDR2 -667 (-3C) DDR2 -667 (-3C) The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns 00 Description Extension of Byte 41 tRC and Byte 42 tRFC 41 Minimum Core Cycle Time (tRC) 60ns 3C 42 Min. Auto Refresh Command Cycle Time (tRFC) 105ns 69 43 Maximum Clock Cycle Time (tCK max) 44 Max. DQS-DQ Skew Factor (tQHS) 45 Read Data Hold Skew Factor (tQHS) 46-61 Reserved 62 SPD Revision 63 Checksum Data Module Manufacturing Location 73-91 Module Part Number 92-255 Reserved 80 18 0.34ns 22 Undefined 00 1.0 10 Checksum Data 6F NANYA 7F7F7F0B00000000 64-71 Manufacturer's JEDEC ID Code 72 8ns 0.24ns Manufacturing code -- Module Part Number in ASCII -- Undefined -- Note 1 Note: 1. M1Y51264TU88A2B-3C I 4D31593531323634545538384132422D3337420 REV 1.0 08/2005 8 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1Y1G64TU8HA2B / M1Y51264TU88A2B 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect -- Part 1 of 2 (1GB) 128Mx64 2 BANKS UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte 0 Description Number of Serial PD Bytes Written during Production SPD Entry Value Serial PD Data Entry (Hexadecimal) DDR2 -667 (-3C) DDR2 -667 (-3C) 128 80 256 08 DDR2-SDRAM 08 1 Total Number of Bytes in Serial PD device 2 Fundamental Memory Type 3 Number of Row Addresses on Assembly 14 0E 4 Number of Column Addresses on Assembly 10 0A 5 Number of DIMM Bank, Package, and Height 2 rank, Height=30mm 61 6 Data Width of this Assembly X64 40 7 Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL_1.8V 05 9 DDR2 SDRAM Device Cycle Time at Maximum Support CAS Latency CL=5 3ns 30 10 DDR2 SDRAM Device Access Time (tac) from Clock at CL=5 0.45ns 45 11 DIMM Configuration Type Non - ECC 00 12 Refresh Rate/Type 7.8s/self 82 13 Primary DDRII SDRAM Width X8 08 14 Error Checking DDRII SDRAM Device Width N/A 00 15 Reserved Undefined 00 16 DDR2 SDRAM Device Attributes: Burst Length Supported 4,8 0C 17 DDR2 SDRAM Device Attributes: Number of Device Banks 4 04 18 DDR2 SDRAM Device Attributes: CAS Latencies Supported 19 DIMM Mechanical Characteristics 20 DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes: 22 DDR2 SDRAM Device Attributes: General 3/4/5 38 4.10mm 01 Regular UDIMM (133.35mm) 02 Normal DIMM 00 Support weak driver 03 23 Minimum Clock Cycle at CL=4 3.75ns 3D 24 Maximum Data Access Time (tac) from Clock at CL=4 0.5ns 50 5ns 50 25 Minimum Clock Cycle Time at CL=3 26 Maximum Data Access Time (tac) from Clock at CL=3 27 0.6ns 60 Minimum Row Precharge Time (tRP) 15ns 3C 28 Minimum Row Active to Row Active delay (tRRD) 7.5ns 1E 29 Minimum RAS to CAS delay (tRCD) 15ns 3C 30 Minimum Active to Precharge Time (tRAS) 45ns 2D 31 Module Bank Density 512MB 80 32 Address and Command Input Setup Time Before Clock (tIS) 0.2ns 20 33 Address and Command Input Hold Time After Clock (tIH) 0.275ns 27 34 Data Input Setup Time Before Clock (tDS) 0.10ns 10 35 Data Input Hold Time After Clock (tDH) 0.175ns 17 36 Write Recovery Time (tWR) 15ns 3C 37 Internal Write to Read Command delay (tWTR) 7.5ns 1E 38 Internal Read to Precharge Command delay (tRTP) 7.5ns 1E REV 1.0 08/2005 Note 9 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1Y1G64TU8HA2B / M1Y51264TU88A2B 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect -- Part 2 of 2 (1GB) 128Mx64 2 BANKS UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD Byte SPD Entry Value Serial PD Data Entry (Hexadecimal) DDR2 -667 (-3C) DDR2 -667 (-3C) Undefined 00 The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns 00 Description 39 Memory Analysis Probe Characteristics 40 Extension of Byte 41 tRC and Byte 42 tRFC 41 Minimum Core Cycle Time (tRC) 60ns 3C 42 Min. Auto Refresh Command Cycle Time (tRFC) 105ns 69 43 Maximum Clock Cycle Time (tCK max) 44 Max. DQS-DQ Skew Factor (tDQs) 45 Read Data Hold Skew Factor (tQHS) 46-61 Reserved 62 SPD Revision 63 Checksum Data Module Manufacturing Location 73-91 Module Part Number 80 18 0.34ns 22 Undefined 00 1.0 10 Checksum data 70 NANYA 7F7F7F0B00000000 64-71 Manufacturer's JEDEC ID Code 72 8ns 0.24ns Manufacturing code -- Module Part Number in ASCII -- Undefined -- 92-255 Reserved Note 1 Note: 1. M1Y1G64TU8HA2B-3C I 4D325931473634545538484132422D33432020 REV 1.0 08/2005 10 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1Y1G64TU8HA2B / M1Y51264TU88A2B 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Absolute Maximum Ratings Symbol Rating Units Voltage on I/O pins relative to Vss -0.5 to 2.3 V Voltage on VDD supply relative to Vss -1.0 to +2.3 V VDDQ Voltage on VDDQ supply relative to Vss -0.5 to +2.3 V HSTG Storage Humidity (without condensation) 5 to 95 % Operating Temperature (Ambient) 0 to +70 C -55 to +100 C VIN, VOUT VDD TA TSTG Parameter Storage Temperature (Plastic) Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC operating Conditions Symbol Parameter Rating Units Note 0 to 95 C 1,2,3 -55 to 100 C Short Circuit Output Current -5 to 5 A TOPR Module Operating Temperature Range (ambient) 0 to 55 C HOPR Operating Humidity (relative) 10 to 90 % TCASE Operating Temperature (Ambient) TSTG Storage Temperature (Plastic) IL Note: 1. 2. 3. Case temperature is measured at top and center side of any DRAMs. tCASE > 85C I tREFI = 3.9 s All DRAM specification only support 0C < tCASE < 85C DC Electrical Characteristics and Operating Conditions (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) Symbol VDD VDDQ VSS, VSSQ VREF Parameter Min Max Supply Voltage 1.7 1.9 V 1 I/O Supply Voltage 1.7 1.9 V 1 Supply Voltage, I/O Supply Voltage I/O Reference Voltage Units 0 0 V 0.49VDDQ 0.51VDDQ Notes V 1, 2 VIH (DC) Input High (Logic1) Voltage VREF + 0.125 VDDQ + 0.3 V 1 VIL (DC) Input Low (Logic0) Voltage -0.3 VREF - 0.125 V 1 Note: 1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. On Die Termination (ODT) Current Symbol Parameter Min IODTO Enabled ODT current per DQ ODT is HIGH; Data Bus inputs are FLOATING IODTT Active ODT current per DQ ODT is HIGH; worst case of Data Bus inputs are STABLE or SWITCHING REV 1.0 08/2005 Max Units EMRS(1) State 5 7.5 mA/DQ A6=0, A2=1 2.5 3.75 mA/DQ A6=1, A2=0 10 15 mA/DQ A6=0, A2=1 5 7.5 mA/DQ A6=1, A2=0 11 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1Y1G64TU8HA2B / M1Y51264TU88A2B 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.8V 0.1V (512MB, 1 Rank, 64Mx8 DDR2 SDRAMs) Symbol Parameter/Condition PC2-5300 (-3C) Unit Notes I DD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 600 mA 1 I DD1 Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 720 mA 1 I DD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 40 mA 1 I DD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 400 mA 1 I DD2Q Precharge quiet standby current; All banks idle; tCK=tCK(IDD); CKE is HIGH; CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. 320 mA 1 I DD3PF Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Fast PDN Exit MRS(12) = 0mA 152 mA 1 I DD3PS Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Slow PDN Exit MRS(12) = 1mA 48 mA 1 I DD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 400 mA 1 I DD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA 1040 mA 1 I DD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) 1120 mA 1 I DD5 Auto-Refresh Current: tRC = tRFC (MIN) 1280 mA 1 I DD6 Self-Refresh Current: CKE 0.2V 40 mA 1 I DD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1360 mA 1 Note: 1. Module IDD was calculated from component IDD. It may different from the actual measurement. REV 1.0 08/2005 12 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1Y1G64TU8HA2B / M1Y51264TU88A2B 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.8V 0.1V (1GB, 2 Ranks, 64Mx8 DDR2 SDRAMs) Symbol Parameter/Condition PC2-5300 (-3C) Unit Notes I DD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 1000 mA 1 I DD1 Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 1120 mA 1 I DD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 80 mA 1 I DD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 800 mA 1 I DD2Q Precharge quiet standby current; All banks idle; tCK=tCK(IDD); CKE is HIGH; CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING. 640 mA 1 I DD3PF Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Fast PDN Exit MRS(12) = 0mA 304 mA 1 I DD3PS Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Slow PDN Exit MRS(12) = 1mA 96 mA 1 I DD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 800 mA 1 I DD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA 1440 mA 1 I DD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) 1520 mA 1 I DD5 Auto-Refresh Current: tRC = tRFC (MIN) 1680 mA 1 I DD6 Self-Refresh Current: CKE 0.2V 80 mA 1 I DD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1760 mA 1 Note: 1. Module IDD was calculated from component IDD. It may different from the actual measurement. REV 1.0 08/2005 13 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1Y1G64TU8HA2B / M1Y51264TU88A2B 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 1 of 2) Symbol tAC tDQSCK -3C Parameter Unit Min. Max. DQ output access time from CK/CK -0.45 +0.45 ns DQS output access time from CK/CK -0.4 +0.4 ns tCH CK high-level width 0.45 0.55 tCK tCL CK low-level width 0.45 0.55 tCK tHP Minimum half clk period for any given cycle; defined by clk high (tCH) or clk low (tCL) time tCH or tCL - tCK CL=3 3 8 ns CL=4, 5 3 8 ns 0.175 - ns 0.1 - ns tCK tCK Clock cycle time tDH DQ and DM input hold time(differential data strobe) tDS DQ and DM input setup time(differential data strobe) tIPW Input pulse width 0.6 - tCK tDIPW DQ and DM input pulse width (each input) 0.35 - tCK tHZ Data-out high-impedance time from CK/CK - tACmax ns tLZ(DQ) Data-out low-impedance time from CK/CK 2tACmin tACmax ns tLZ(DQS) DQS low-impedance time from CK/CK tACmin tACmax ns tDQSQ DQS-DQ skew (DQS & associated DQ signals) 0.24 - ns tQHS Data hold Skew Factor 0.34 - ns tQH Data output hold time from DQS tHP tQHS - ns Write command to 1st DQS latching transition -0.25 +0.25 tCK DQS input low (high) pulse width (write cycle) 0.35 - tCK tDSS DQS falling edge to CK setup time (write cycle) 0.2 - tCK tDSH DQS falling edge hold time from CK (write cycle) 0.2 - tCK tMRD Mode register set command cycle time 2 - tCK tWPST Write postamble 0.40 0.60 tCK Write preamble 0.35 - tCK 0.275 - ns 0.20 - ns tDQSS tDQSL,(H) tWPRE tIH tIS Address and control input hold time Address and control input setup time tRPRE Read preamble 0.90 1.10 tCK tRPST Read postamble 0.40 0.60 tCK tRRD Active bank A to Active bank B command 7.5 tDelay Minimum time clocks remains ON after CKE asynchronously drops Low ns tIS + tCK + tIH - ns Average Periodic Refresh Interval (85C < TCASE 95C) - 3.9 s Average Periodic Refresh Interval (0C TCASE 85C) - 7.8 s tOIT OCD drive mode output delay 0 12 ns tRFC Auto-Refresh to Active/Auto-Refresh command period 105 - ns tCCD CAS to CAS tREFI REV 1.0 08/2005 2 tCK 14 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1Y1G64TU8HA2B / M1Y51264TU88A2B 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 2 of 2) Symbol -3C Parameter Min. Max. 15 - Unit tWR Write recovery time without Auto-Precharge WR Write recovery time with Auto-Precharge tWR/tCK WR+tRP - tCK 7.5 - ns tDAL Auto precharge write recovery + precharge time tWTR Internal write to read command delay tRTP Internal read to precharge command delay tXSNR tXSRD tXP Exit self refresh to a Non-read command Exit self refresh to a Read command ns tCK 7.5 - ns tRFC+10 - ns 200 - tCK 2 - tCK Exit precharge power down to any Non- read command tXARD Exit active power down to read command 2 - tCK tXARDS Exit active power down to read command 7-AL - tCK 3 - tCK 2 2 tCK tCKE CKE minimum pulse width ODT tAOND tAON tAONPD ODT turn-on delay ODT turn-on tAC (min) tAC (max) ns ODT turn-on (Power down mode) tAC (min) +2 2tCK + tAC(max) +1 ns 2.5 2.5 tCK +0.7 tAOFD ODT turn-off delay tAOF ODT turn-off tAC(min) tAC(max) +0.6 ns ODT turn-off (Power down mode) tAC (min)+2 2.5tCK + tAC(max) +1 ns tANPD ODT to power down entry latency 3 - tCK tAXPD ODT power down exit latency 8 - tCK tAOFPD Speed Grade Definition tRAS Row Active Time 45 70,000 ns tRC Row Cycle Time 60 - ns tRCD RAS to CAS delay 15 - ns Row Precharge Time 15 - ns tRP REV 1.0 08/2005 15 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1Y1G64TU8HA2B / M1Y51264TU88A2B 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Package Dimensions (512MB, 1 Rank, 64Mx8 DDR SDRAMs) FRONT 133.35 5.250 131.35 5.171 Detail B 17.80 0.700 Detail A 2.5 0.098 3.0 0.118 10.0 0.394 30.00 1.180 (2X) 4.00 0.157 128.95 5.077 BACK SIDE 3.81 0.125 max. (Front) Detail B 3.80 0.15 4.00 0.157 Detail A 1.50 0.059 0.8 Width 0.031 1.27 0.050 1.00 Pitch 0.039 Note: All dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated. Units: Millimeters (Inches) REV 1.0 08/2005 16 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1Y1G64TU8HA2B / M1Y51264TU88A2B 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Package Dimensions (1GB, 2 Rank, 64Mx8 DDR SDRAMs) FRONT 133.35 5.250 131.35 5.171 Detail B 17.80 0.700 Detail A 2.5 0.098 3.0 0.118 10.0 0.394 30.00 1.180 (2X) 4.00 0.157 128.95 5.077 BACK SIDE 4.00 0.157 max. (Front) Detail B 3.80 0.15 4.00 0.157 Detail A 1.50 0.059 0.8 Width 0.031 1.27 0.050 1.00 Pitch 0.039 Note: All dimensions are typical with tolerances of +/- 0.15 (0.006) unless otherwise stated. Units: Millimeters (Inches) REV 1.0 08/2005 17 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. M1Y1G64TU8HA2B / M1Y51264TU88A2B 1GB: 128M x 64 / 512MB: 64M x 64 Unbuffered DDR2 SDRAM DIMM Revision Log Rev Date 0.1 05/2005 Preliminary Release. Modification 0.2 07/2005 Update SPD, IDD data, Timing Parameter, and Operating condition. 1.0 08/2005 Official release for Elixir Nanya Technology Corporation Hwa Ya Technology Park 669 Fu Hsing 3rd Rd., Kueishan, Taoyuan, 333, Taiwan, R.O.C. Tel: +886-3-328-1688 Please visit our home page for more information: www.elixir-memory.com REV 1.0 08/2005 18 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.