4-45
FAST AND LS TTL DATA
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
The MC74F1 12 contains two independent, high-speed JK flip-flops with Di-
rect Set and Clear inputs. Synchronous state changes are initiated by the fal-
ling edge of the clock. T riggering occurs at a voltage level of the clock and is
not directly related to the transition time. The J and K inputs can change when
the clock is in either state without affecting the flip-flop, provided that they are
in the desired state during the recommended setup and hold times relative to
the falling edge of the clock. A LOW signal on SD or CD prevents clocking and
forces Q or Q HIGH, respectively . Simultaneous LOW signals on SD and CD
force both Q and Q HIGH.
SD1
21 3 4 6 7 8
GND
CP1J1
K1Q1Q1Q2
5
CP
CD
CONNECTION DIAGRAM
SD
J
K Q
1516 14 13 11 10 9
VCC CD1 CD2 CP2J2Q2
12
SD2
K2
QCP
SD
CD
K
J Q
Q
FUNCTION TABLE (Each Half)
Inputs Output
@ tn@ tn + 1
J K Q
L L Qn
L H L
H L H
H H Qn
H = HIGH Voltage Level
L = LOW Voltage Level
tn = Bit time before clock pulse
tn + 1 = Bit time after clock pulse
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16 1
16
1
16 1
D SUFFIX
SOIC
CASE 751B-03
59
MC74FXXXJ Ceramic
MC74FXXXN Plastic
MC74FXXXD SOIC
MC74F112
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
FAST SCHOTTKY TTL
ORDERING INFORMATION
LOGIC SYMBOL
4
6
1
3
15
10
11
13
7
14
VCC = PIN 16
GND = PIN 8
SD
J
CP
Q
Q
SD
J
CP
Q
Q
CD
212
KK
Asynchronous Inputs:
LOW Input to SD sets Q to HIGH level
LOW Input to CD sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q HIGH
4-46
FAST AND LS TTL DATA
MC74F112
SD
Q
K
CP
CD
LOGIC DIAGRAM (one half shown)
J
Q
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 74 4.5 5.0 5.5 V
TAOperating Ambient Temperature Range 74 0 25 70 °C
IOH Output Current — High 74 –1.0 mA
IOL Output Current — Low 74 20 mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage
VIL Input LOW Voltage 0.8 V Guaranteed Input LOW Voltage
VIK Input Clamp Diode Voltage –1.2 V IIN = –18 mA VCC = MIN
74 2.5 3.4 V IOH = –1.0 mA VCC = 4.50 V
VOH Output HIGH Voltage 74 2.7 3.4 V IOH = –1.0 mA VCC = 4.75 V
VOL Output LOW Voltage 0.35 0.5 V IOL = 20 mA VCC = MIN
IIH Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V
100 µA VCC = MAX, VIN = 7.0 V
Input LOW Current
(J and K Inputs) –0.6 mA
IIL (CP Inputs) –2.4 mA VCC = MAX, VIN = 0.5 V
(CD and SD Inputs) –3.0 mA
IOS Output Short Circuit Current (Note 2) –60 –150 mA VCC = MAX, VOUT = 0 V
ICC Power Supply Current 12 19 mA VCC = MAX, VCP = 0 V
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under guaranteed operating ranges.
2. Not more than one output should be shorted at a time, nor for more than 1 second.
4-47
FAST AND LS TTL DATA
MC74F112
AC CHARACTERISTICS
74F 74F
TA = +25°C TA = 0°C to +70°C
VCC = +5.0 V VCC = 5.0 V ± 10%
CL = 50 PF CL = 50 PF
Symbol Parameter Min Max Min Max Unit
fmax Maximum Clock Frequency 110 MHz
tPLH Propagation Delay 2.0 6.5 2.0 7.5
ns
tPHL CPn to Qn or Qn2.0 6.5 2.0 7.5
ns
tPLH Propagation Delay 2.0 6.5 2.0 7.5
ns
tPHL CDn or SDn to Qn or Qn2.0 6.5 2.0 7.5
ns
AC OPERATING REQUIREMENTS
74F 74F
TA = +25°C TA = 0°C to +70°C
VCC = +5.0 V VCC = 5.0 V ± 10%
Symbol Parameter Min Typ Max Min Max Unit
ts (H) Setup Time, HIGH or LOW 4.0 4.0
ns
ts (L) Jn or Kn to CPn3.0 3.0
ns
th (H) Hold Time, HIGH or LOW 0 0
ns
th (L) Jn or Kn to CPn0 0
tw (H) CPn Pulse Width, HIGH 4.5 4.5
ns
tw (L) or LOW 4.5 4.5
ns
tw (L) CDn or SDn Pulse Width, LOW 4.5 4.5 ns
trec Recovery Time
CDn or SDn to CP 4.0 5.0 ns