Publication# 14051 Rev: K
Amendment/0Issue Date: November 1998
MACH 1 and 2 CPLD Families
High-Performance EE CMOS Programmable Logic
FEATURES
◆
High-performance electrically-erasable CMOS PLD families
◆
32 to 128 macrocells
◆
44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages
◆
SpeedLocking™ – guaranteed fixed timing up to 16 product terms
◆
Commercial 5/5.5/6/7.5/10/12/15-ns t
PD
and Industrial 7.5/10/12/14/18-ns t
PD
◆
Configurable macrocells
— Programmable polarity
— Registered or combinatorial outputs
— Internal and I/O feedback paths
— D-type or T-type flip-flops
— Output Enables
— Choice of clocks for each flip-flop
— Input registers for MACH 2 family
◆
JTAG (IEEE 1149.1)-compatible, 5-V in-system programming available
◆
Peripheral component interconnect (PCI) compliant at 5/5.5/6/7.5/10/12 ns
◆
Safe for mixed supply voltage system designs
◆
Bus-Friendly™ inputs and I/Os reduce risk of unwanted oscillatory outputs
◆
Programmable power-down mode results in power savings of up to 75%
◆
Supported by Vantis DesignDirect™ software for rapid logic development
— Supports HDL design methodologies with results optimized for Vantis
— Flexibility to adapt to user requirements
— Software partnerships that ensure customer success
◆
Lattice/Vantis and third-party hardware programming support
— Lattice/V antisPRO™ (formerly known as MACHPRO
®
) software for in-system programmability
support on PCs and Automated Test Equipment
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,
and System General
2 MACH 1 & 2 Families
Note:
1. Values in parentheses ( ) are for the SP version.
GENERAL DESCRIPTION
The MACH
®
1 & 2 families from Lattice/Vantis offer high-performance, low cost Complex
Programmable Logic Devices (CPLDs), addressing the growing need for speed in networking,
telecommunications and computing. MACH 1 & 2 devices are available in speeds as fast as 5.0-ns
t
PD
and in densities ranging from 32 to 128 macrocells (Tables 1 and 2). The overall benefits for
users include guaranteed high performance for entry-to-mid-level logic needs at a low cost.
Notes:
1. C = Commercial, I = Industrial
2. -5 speed grade for MACH111 (SP) = 5.0 ns t
PD
3. -5 speed grade for MACH131(SP) = 5.5 ns t
PD
The MACH 1 & 2 families consist of ten devices—five base options, each with a counterpart that
includes JT AG-compatible in-system programming (ISP). These devices offer five different density-
I/O combinations in Thin Quad Flat Pack (TQFP), Plastic Quad Flat Pack (PQFP), and Plastic
Leaded Chip Carrier (PLCC) packages from 44 to 100 pins (Table 3). Each MACH 1 & 2 device is
PCI compliant and includes other features such as SpeedLocking architecture for guaranteed fixed
timing, Bus-Friendly inputs and I/Os, and programmable power-down mode for extra power
savings.
Table 1. MACH 1 and 2 Family Device Features
1
Feature MACH111 (SP) MACH131 (SP) MACH211 (SP) MACH221 (SP) MACH231 (SP)
Macrocells
32 64 64 96 128
Maximum user I/O pins
32 64 32 48 64
t
PD
(ns)
5.0 5.5 7.5 (6.0) 7.5 6.0 (10)
t
S
(ns)
3.5 3.0 5.5 (5) 5.5 5 (6.5)
t
CO
(ns)
3.5 4 4.5 (4) 5 4 (6.5)
f
CNT
(MHz)
182 182 133 (166) 133 166 (100)
Table 2. MACH 1 and 2 Family Speed Grades
1
Device -5 -6 -7 -10 -12 -14 -15 -18
MACH111
C (Note 2) C, I C, I C, I I C I
MACH111SP
C (Note 2) C, I C, I C, I I C I
MACH131
C (Note 3) C, I C, I C, I I C I
MACH131SP
C (Note 3) C, I C, I C, I I C I
MACH211
C C, I C, I I C I
MACH211SP
C C C, I C, I I C I
MACH221
C C, I C, I I C I
MACH221SP
C C, I C, I I C I
MACH231
CCCC, IICI
MACH231SP
C C, I I C I
MACH 1 & 2 Families 3
Note:
1. The MACH110, MACH120, MACH130, MACH210, MACHL V210, MACH215, MACH220 and MACH230 are not listed above and
not recommended for new designs. However , they are still supported by Lattice/Vantis. For technical or sales support, please call
your local Lattice/Vantis sales office or visit our Web site at www.vantis.com for more information.
Lattice/Vantis offers software design support for MACH devices in both the MACHXL
®
and
DesignDirect development systems. The DesignDirect development system is the Lattice/Vantis
implementation software that includes support for all Lattice/Vantis CPLD, FPGA, and SPLD
devices. This system is supported under Windows ’95, ’98 and NT as well as Sun Solaris and HPUX.
DesignDirect software is designed for use with design entry, simulation and verification software
from leading-edge tool vendors such as Cadence, Exemplar Logic, Mentor Graphics, Model
Technology, Synopsys, Synplicity, Viewlogic and others. It accepts EDIF 2 0 0 input netlists,
generates JEDEC files for Lattice/Vantis PLDs and creates industry-standard EDIF, Verilog, VITAL
compliant VHDL and SDF simulation netlists for design verification.
DesignDirect software is also available in product configurations that include VHDL and Verilog
synthesis from Exemplar Logic and VHDL, V erilog RTL and gate level timing simulation from Model
Technology. Schematic capture and ABEL entry, as well as functional simulation, are also provided.
Table 3. MACH 1 and 2 Family Package and I/O Options
Device 44-pin PLCC 44-pin TQFP 68-pin PLCC 84-pin PLCC 100-pin TQFP 100-pin PQFP
MACH111
XX
MACH111SP
XX
MACH131
X
MACH131SP
XX
MACH211
XX
MACH211SP
XX
MACH221
X
MACH221SP
X
MACH231
X
MACH231SP
XX
4 MACH 1 & 2 Families
FUNCTIONAL DESCRIPTION
Each MACH 1 and 2 device consists of multiple, optimized P AL
®
blocks interconnected by a switch
matrix. The switch matrix allows communication between P AL blocks, and routes inputs to the P AL
blocks. Together , the P AL blocks and switch matrix allow the logic designer to create large designs
in a single device instead of using multiple devices.
The switch matrix takes all dedicated inputs and signals from the input switch matrices and routes
them as needed to the PAL blocks. Feedback signals that return to the same PAL block still must
go through the switch matrix. This mechanism ensures that PAL blocks in MACH devices
communicate with each other with guaranteed fixed timing (SpeedLocking).
The switch matrix makes a MACH device more advanced than simply several PAL devices on a
single chip. It allows the designer to think of the device not as a collection of blocks, but as a
single programmable device; the software partitions the design into PAL blocks through the
central switch matrix so that the designer does not have to be concerned with the inter nal
architecture of the device.
14051K-002
Figure 1. Overall Architecture of MACH 1 & 2 Devices
Array and
Allocator
Output
Macrocells
Buried
Macrocells
I/O Cells
Buried Macrocell Feedback
Output Macrocell Feedback
I/O Pin Feedback
I/O Pins
Switch Matrix
PAL Block I/O PinsPAL Block
PAL Block
Clock/Input Pins
Dedicated Input
Note:
1
. There are no buried macrocells in MACH 1 devices. All macrocells are output macrocells.
PAL Block
Device PAL Blocks Macrocells per Block I/Os per Block Product Terms per Block
MACH111(SP) 21616 70
MACH131(SP) 41616 70
MACH211(SP) 416 8 68
MACH221(SP) 812 6 52
MACH231(SP) 816 8 68
(note 1)
I/O Pins
I/O Pins
MACH 1 & 2 Families 5
Each PAL block consists of the following elements:
◆
Product-term array
◆
Logic Allocator
◆
Macrocells
◆
I/O cells
Each PAL block additionally contains an asynchronous reset product term and an asynchronous
preset product term. This allows the flip-flops within a single P AL block to be initialized as a bank.
There are also output enable product terms that provide tri-state control for the I/O cells.
Product-Term Array
The product-term array consists of a number of product terms that form the basis of the logic being
implemented. The inputs to the AND gates come from the switch matrix (Table 4), and are
provided in both true and complement forms for efficient logic implementation.
Because the number of product terms available for a given function is not fixed, the full sum of
products is not realized in the array. The product terms drive the logic allocator, which allocates
the appropriate number of product terms to generate the function.
Logic Allocator
The logic allocator (Figure 2) is a block within which different product terms are allocated to the
appropriate macrocells in groups of four product terms called “product term clusters”. The
availability and distribution of product term clusters is automatically considered by the software as
it fits functions within the PAL block. The size of the product term clusters has been designed to
provide high utilization of product terms. Complex functions using many product terms are
possible, and when few product terms are used, there will be a minimal number of unused, or
wasted, product terms left over.
The product term clusters do not “wrap” around the logic block. This means that the macrocells
at the ends of the block have fewer product terms available (Tables 5, 6, 7, 8).
Table 4. PAL Block Inputs
Device Number of Inputs to PAL Block Device Number of Inputs to PAL Block
MACH111
26
MACH211SP
26
MACH111SP
26
MACH221
26
MACH131
26
MACH221SP
26
MACH131SP
26
MACH231
32
MACH211
26
MACH231SP
32
6 MACH 1 & 2 Families
Table 5. Logic Allocation for MACH111(SP)
Output Macrocell Available Clusters Output Macrocell Available Clusters
M
0
C
0
, C
1
M
8
C
8,
C
9
M
1
C
0
, C
1
, C
2
M
9
C
8,
C
9,
C
10
M
2
C
1
, C
2
, C
3
M
10
C
9,
C
10,
C
11
M
3
C
2
, C
3
, C
4
M
11
C
10,
C
11,
C
12
M
4
C
3
, C
4
, C
5
M
12
C
11,
C
12,
C
13
M
5
C
4
, C
5
, C
6
M
13
C
12,
C
13,
C
14
M
6
C
5
, C
6
, C
7
M
14
C
13,
C
14,
C
15
M
7
C
6
, C
7
M
15
C
14,
C
15
Table 6. Logic Allocation for MACH131(SP)
Output Macrocell Available Clusters Output Macrocell Available Clusters
M
0
C
0
, C
1
M
8
C
7
, C
8
, C
9
M
1
C
0
, C
1
, C
2
M
9
C
8
, C
9
, C
10
M
2
C
1
, C
2
, C
3
M
10
C9, C10, C11
M3C2, C3, C4M11 C10, C11, C12
M4C3, C4, C5M12 C11, C12, C13
M5C4, C5, C6M13 C12, C13, C14
M6C5, C6, C7M14 C13, C14, C15
M7C6, C7, C8M15 C14, C15
*
*
*MACH 2 only
Product T erm
Cluster
Logic
Allocator
From
n+1 From
n+2
From
n-1
To
n-2 To
n-1
n
To
n+1
nTo Macrocell
n
Fi
g
ure 2. Product Term Clusters and the Lo
g
ic Allocator
14051K-003
MACH 1 & 2 Families 7
Macrocell
There are two fundamental types of macrocell: the output macrocell and the buried macrocell. The
buried macrocell is only found in MACH 2 devices. The use of buried macrocells effectively
doubles the number of macrocells available without increasing the pin count.
Both macrocell types can generate registered or combinatorial outputs. For the MACH 2 series,
a transparent-low latch configuration is provided. If the register is used, it can be configured as
a T-type or a D-type flip-flop. Register and latch functionality is defined in Table 9.
Programmable polarity (for output macrocells) and the T-type flip-flop both give the software a
way to minimize the number of product terms needed. These choices can be made automatically
by the software when it fits the design into the device.
Table 7. Logic Allocation for MACH211(SP) and MACH231(SP)
Macrocell
Available Clusters
Macrocell
Available ClustersOutput Buried Output Buried
M0M1
C0, C1, C2
C0, C1, C2, C3
M8M9
C7, C8, C9, C10
C8, C9, C10, C11
M2M3
C1, C2, C3, C4
C2, C3, C4, C5
M10 M11
C9, C10, C11, C12
C10, C11, C12, C13
M4M5
C3, C4, C5, C6
C4, C5, C6, C7
M12 M13
C11, C12, C13, C14
C12, C13, C14, C15
M6M7
C5, C6, C7, C8
C6, C7, C8, C9
M14 M15
C13, C14, C15
C14, C15
Table 8. Logic Allocation for MACH221(SP)
Macrocell
Available Clusters
Macrocell
Available ClustersOutput Buried Output Buried
M0M1
C0, C1, C2
C0, C1, C2, C3
M6M7
C5, C6, C7, C8
C6, C7, C8, C9
M2M3
C1, C2, C3, C4
C2, C3, C4, C5
M8M9
C7, C8, C9, C10
C8, C9, C10, C11
M4M5
C3, C4, C5, C6
C4, C5, C6, C7
M10 M11
C9, C10, C11
C10, C11
Table 9. Register/Latch Operation
Configuration D/T CLK/LE Q+
D-Register
X 0,1,↓Q
0↑0
1↑1
T-Register
X 0,1,↓Q
0↑Q
1↑Q
Latch
X1Q
000
101
8 MACH 1 & 2 Families
The output macrocell (Figure 3) sends its output back to the switch matrix, via internal feedback,
and to the I/O cell. The feedback is always available regardless of the configuration of the I/O cell.
This allows for buried combinatorial or registered functions, freeing up the I/O pins for use as
inputs if not needed as outputs. The basic output macrocell configurations are shown in Figure 4.
The buried macrocell (Figure 5) does not send its output to an I/O cell. The output of a buried
macrocell is provided only as an internal feedback signal which feeds the switch matrix. This
allows the designer to generate additional logic without requiring additional pins. The buried
macrocell can also be used to register or latch inputs. The input register is a D-type flip-flop; the
input latch is a transparent-low D-type latch. Once configured as a registered or latched input, the
buried macrocell cannot generate logic from the product-term array. The basic buried macrocell
configurations are shown in Figure 6.
Figure 3. Output Macrocell
Note:
1. Latch option available on MACH 2 devices only.
CLK0
CLKn
1
01
0
AR
AP QD/T/L1
To
Switch
Matrix
Sum of Products
from Logic
Allocator
PAL-Block
Asynchronous
Preset
To I/O
Cell
PAL-Block
Asynchronous
Reset
14051K-004
MACH 1 & 2 Families 9
n
From
Logic
Allocator
To Switch
Matrix
To
I/O
Cell
a. Combinatorial, active high
n
From
Logic
Allocator
To Switch
Matrix
To
I/O
Cell
b. Combinatorial, active low
n
To Switch
Matrix
c. D-type register, active high
AP
AR
DQ n
To Switch
Matrix
d. D-type register, active low
AP
AR
DQ
AP
AR
TQ
n
To Switch
Matrix
e. T-type register, active high f. T-type register, active low
AP
AR
TQ
n
To Switch
Matrix
n
To Switch
Matrix
g. Latch, active high (MACH 2 only)
n
To Switch
Matrix
h. Latch, active low (MACH 2 only)
AP
AR
LQ
G
CLKn
CLK0
CLKn
CLK0
CLKn
CLK0
CLKn
CLK0
CLKn
CLK0
CLKn
CLK0
AP
AR
LQ
G
Figure 4. Output Macrocell Configurations
From
Logic
Allocator To
I/O
Cell
From
Logic
Allocator To
I/O
Cell
From
Logic
Allocator To
I/O
Cell
From
Logic
Allocator To
I/O
Cell
From
Logic
Allocator To
I/O
Cell
From
Logic
Allocator To
I/O
Cell
14051K-005
10 MACH 1 & 2 Families
Fi
g
ure 5. Buried Macrocell (MACH 2 onl
y
)
1
0
1
0
AR
AP QD/T/L
To
Switch
Matrix
Sum of Products
From Logic
IC Allocator
PAL-Block
Asynchronous
Preset
PAL-Block
Asynchronous
Reset
From I/O Pin
CLK0
CLKn
14051K-030
n
From
Logic
Allocator
To Switch
Matrix
a. Combinatorial
n
From Logic
Allocator
To Switch
Matrix b. D-type register
AP
AR
DQ
AP
AR
TQ
n
From Logic
Allocator
To Switch
Matrix
c. T-type register d. Input register
AP
AR
DQ
To Switch
Matrix
From I/O
AP
AR
LQ
n
From
Logic
Allocator
To Switch
Matrix
e. Latch f. Input latch
AP
AR
LQ
To Switch
Matrix
From I/O
G
G
CLK0
CLKnCLK0
CLKn
CLK0
CLKnCLK0
CLKn
CLKÂ0
CLÂKn
Fi
g
ure 6. Buried Macrocell Confi
g
urations (MACH 2 onl
y
)
Cell
Cell
14051K-006
MACH 1 & 2 Families 11
The flip-flops in either macrocell type can be clocked by one of several clock pins (Table 10).
Registers are clocked on the rising edge of the clock input. Latches hold their data when the gate
input is HIGH. Clock pins are also available as inputs, although care must be taken when a signal
acts as both clock and input to the same device.
All flip-flops have asynchronous reset and preset. This is controlled by the common product terms
that control all flip-flops within a PAL block. For a single PAL block, all flip-flops, whether in an
output or a buried macrocell, are initialized together. The initialization functionality of the flip-flops
is illustrated in Table 11.
I/O Cells
The I/O cells (Figure 7) provide a three-state output buffer. The three-state buffer can be left
permanently enabled for use only as an output, permanently disabled for use as an input, or it can
be controlled by one of two product terms for bi-directional signals and bus connections. The two
product terms provided are common to a bank of I/O cells.
Table 10. Macrocell Clocks
Device Number of Clocks Available Device Number of Clocks Available
MACH111 4MACH211SP 2
MACH111SP 2MACH221 4
MACH131 4MACH221SP 4
MACH131SP 4MACH231 4
MACH211 4MACH231SP 4
Table 11. Asynchronous Reset/Preset Operation
Configuration AR AP CLK/LE Q+
Register
0 0 X See Table 9
01 X 1
10 X 0
11 X 0
Latch
0 0 X See Table 9
0 1 0 Illegal
01 1 1
1 0 0 Illegal
10 1 0
1 1 0 Illegal
11 1 0
12 MACH 1 & 2 Families
SPEEDLOCKING FOR GUARANTEED FIXED TIMING
The unique MACH 1 & 2 architecture is designed for high performance—a metric that is met in
both raw speed, and even more importantly, guaranteed fixed speed. The design of the switch
matrix and PAL blocks guarantee a fixed pin-to-pin delay that is independent of the logic required
by the design. Other non-Lattice/V antis CPLDs incur serious timing delays as product terms expand
beyond their typical 4 or 5 product term limits (Figure 8). Speed and SpeedLocking combine to
give designers easy access to the performance required in today’s designs.
VCC
01
11
10
00
Output Enable
Product Terms
(Common to bank of
I/O Cells)
From Output
Macrocell
To Switch
Matrix
To Buried
Macrocell
(MACH 2 only)
Figure 7. I/O Cell
14051K-007
SpeedLocking
Shared Expander Delay
Non-MACH
5 PT 10 PT 15 PT
tPD (ns) 7.4 ns
10.4 ns
MACH 1 & 2
8.8 ns
6.6 ns
5 ns
11
10
9
8
7
6
5
5.8 ns
Product Terms
Parallel Expander Delay
• Patented Architecture
• Path Independent
• Logic/Routing Independent
• Guaranteed Fixed Timing
• Up to 16 Product Terms per Output
• V ariable
• Path Dependent
• Logic/Routing Dependent Delays
• Unpredictable
• 4-5 Product Terms before Delays
Non-MACH
MACH 1 & 2 SpeedLocking
Figure 8. Timing in MACH 1 & 2 vs. Non-MACH Devices
14051K-001
MACH 1 & 2 Families 13
JTAG IN-SYSTEM PROGRAMMING
Programming devices in-system provides a number of significant benefits including: rapid
prototyping, lower inventory levels, higher quality, and the ability to make in-field modifications.
All MACHxxxSP devices provide in-system programming (ISP) capability through their JT AG ports.
This capability has been implemented in a manner that insures that the JTAG port remains
compliant to the IEEE 1149.1 standard. By using JTAG as the communication interface through
which ISP is achieved, customers benefit from a standard, well-defined interface.
MACHxxxSP devices can be programmed across the commercial temperature and voltage range.
These devices tristate the outputs during programming. Lattice/Vantis provides its free PC-based
Lattice/VantisPRO software to facilitate in-system programming. Lattice/VantisPRO software takes
the JEDEC file output produced by V antis’ design implementation software, along with information
about the JTAG chain, and creates a set of vectors that are used to drive the JTAG chain. Lattice/
VantisPRO software can use these vectors to drive a JTAG chain via the parallel port of a PC.
Alternatively, Lattice/VantisPRO software can output files in formats understood by common
automated test equipment. This equipment can then be used to program MACHxxxSP devices
during the testing of a circuit board. For more information about in-system programming, refer to
the separate document entitled MACH ISP Manual.
BUS-FRIENDLY INPUTS AND I/Os
The MACH 1 & 2 inputs and I/Os include two inverters in series which loop back to the input.
This double inversion weakly holds the input at its last driven logic state. For the circuit diagram,
please refer to the Input/Output Equivalent Schematics (page 393) in the General Information
Section of the Vantis 1999 Data Book.
PCI COMPLIANT
The MACH 1 & 2 families in -5/-6/-7/-10/-12 speed grades are fully compliant with the PCI Local
Bus Specification published by the PCI Special Interest Group. The MACH 1 & 2 families’
predictable timing ensures compliance with the PCI AC specifications independent of the design.
POWER-DOWN MODE
The MACH 1 & 2 families feature a programmable low-power mode in which individual signal
paths can be programmed for low power. These low-power speed paths will be slower than the
non-low-power paths. This feature allows speed critical paths to run at maximum frequency while
the rest of the paths operate in the low-power mode, resulting in power savings of up to 75%. If
all of the signals in a PAL block are in low-power mode, then the total power is reduced even
further.
SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS
All MACHxxxSP and most of the MACH 1 & 2 devices are safe for mixed supply voltage system
designs. These 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V,
while they can accept inputs from other 3.3-V devices. The MACH 1 & 2 families provide easy-to-
use mixed-voltage design compatibility. For more information, refer to the Technical Note entitled
Mixed Supply Design with MACH 1 & 2 SP Devices.
POWER-UP RESET
All flip-flops power-up to a logic LOW for predictable system initialization. The actual values of
the outputs of the MACH devices will depend on the configuration of the macrocell. T o guarantee
14 MACH 1 & 2 Families
initialization values, the VCC rise must be monotonic and the clock must be inactive until the reset
delay time has elapsed.
SECURITY BIT
A security bit is provided on the MACH devices as a deterrent to unauthorized copying of the array
configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by
a device programmer, securing proprietary designs from competitors. Programming and
verification are also defeated by the security bit. The bit can only be reset by erasing the entire
device.
MACH 1 & 2 Families 15
MACH111(SP) AND MACH131(SP) PAL BLOCK
0 4 8 12 16 20 24 28 4032 43
36
0 4 8 12 16 20 24 28 4032 43
36
I/O
Cell I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Switch
Matrix
Output Enable
Output Enable
Asynchronous Reset
Asynchronous Preset
Output Enable
Output Enable
CLK
16
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
16
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
2
4
for MACH111SP
for MACH111, MACH131, MACH131SP
47 51
47 51
0
Logic Allocator
63
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
M3
M6
M5
M4
M2
M1
M0
M9
M8
M7
M10
M11
M12
M13
M14
M15
14051K-013
16 MACH 1 & 2 Families
MACH211(SP) PAL BLOCK
0 4 8 12 16 20 24 28 4032 43
36
0 4 8 12 16 20 24 28 4032 43
36
I/O
Cell I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Switch
Matrix
Output Enable
Output Enable
Asynchronous Reset
Asynchronous Preset
16
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
8
Buried
Macro
Cell
Buried
Macro
Cell
Buried
Macro
Cell
Buried
Macro
Cell
Buried
Macro
Cell
Buried
Macro
Cell
Buried
Macro
Cell
Buried
Macro
Cell
47 51
47 51
CLK
2
4
for MACH211SP
for MACH211
0
Logic Allocator
63
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
M3
M6
M5
M4
M2
M1
M0
M9
M8
M7
M10
M11
M12
M13
M14
M15
14051K-015
MACH 1 & 2 Families 17
MACH221(SP) PAL BLOCK
Asynchronous Preset
0 4 8 12 16 20 24 28 4032 43
36
0 4 8 12 16 20 24 28 4032 43
36
Switch
Matrix
Output Enable
Output Enable
Asynchronous Reset
CLK
12
6
4
47 51
47 51
I/O
I/O
Cell
Output
Macro
Cell
Buried
Macro
Cell
I/O
I/O
Cell
Output
Macro
Cell
Buried
Macro
Cell
I/O
I/O
Cell
Output
Macro
Cell
Buried
Macro
Cell
I/O
I/O
Cell
Output
Macro
Cell
Buried
Macro
Cell
I/O
I/O
Cell
Output
Macro
Cell
Buried
Macro
Cell
Buried
Macro
Cell
I/O
I/O
Cell
Output
Macro
Cell
0
47
Logic Allocator
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
M3
M6
M5
M4
M2
M1
M0
M9
M8
M7
M10
M11
14051K-016
18 MACH 1 & 2 Families
MACH231(SP) PAL BLOCK
0 4 8 12 16 20 24 28 4032 43
36
0 4 8 12 16 20 24 28 4032 43
36
Switch
Matrix
16
8
47 59
47
I/O
Cell I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Output Enable
Output Enable
Asynchronous Reset
Asynchronous Preset
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
I/O
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Output
Macro
Cell
Buried
Macro
Cell
Buried
Macro
Cell
Buried
Macro
Cell
Buried
Macro
Cell
Buried
Macro
Cell
Buried
Macro
Cell
Buried
Macro
Cell
Buried
Macro
Cell
51
CLK
4
0
63
Logic Allocator
C
0
C
1
C
2
C
3
C
4
C
5
C
6
C
7
C
8
C
9
C
10
C
11
C
12
C
13
C
14
C
15
M
3
M
6
M
5
M
4
M
2
M
1
M
0
M
9
M
8
M
7
M
10
M
11
M
12
M
13
M
14
M
15
51 55 63
55 59 63
14051K-017
MACH 1 & 2 Families 19
BLOCK DIAGRAM (MACH111, MACH111SP)
52 x 70
AND Logic Array
and
Logic Allocator
I/O0 – I/O15
I/O Cells
Macrocells
Switch Matrix
16
OE
16
16
16
26
52 x 70
AND Logic Array
and
Logic Allocator
I/O16 – I/O31 I0
I3
I/O Cells
Macrocells
OE
26
16
16
16
16
Block A
Block B
4
4
14051K-008
MACH111
CLK0 /I1
CLK1 /I2
CLK2/I4
CLK3 /I5
MACH111
CLK0 /I0
CLK1 /I1MACH111SP
4 MACH111
2 MACH111SP
2 MACH111 Only
20 MACH 1 & 2 Families
BLOCK DIAGRAM (MACH131, MACH131SP)
I/O Cells
Macrocells
I/O48 – I/O63
52 x 70
AND Logic Array
and
Logic Allocator
OE
I/O Cells
Macrocells
I/O16 – I/O31
52 x 70
AND Logic Array
and
Logic Allocator
OE
16
16
26
Switch Matrix
I/O Cells
Macrocells
I/O0 – I/O15 I2, I5
52 x 70
AND Logic Array
and
Logic Allocator
CLK0/I0, CLK1/I1
CLK2/I3, CLK3/I4
OE
16
16
26
2
4
4
4
16
16
26
I/O Cells
Macrocells
I/O32 – I/O47
52 x 70
AND Logic Array
and
Logic Allocator
OE
16
16
26
44
4
4
4
4
Block A Block B
Block D Block C 14051K-009
16 16
16 16
MACH 1 & 2 Families 21
BLOCK DIAGRAM (MACH211, MACH211SP)
Switch Matrix
I/O Cells
Macrocells
I/O0–I/O7
Macrocells
8
8
8
I0
I3
52 x 68
AND Logic
Array
and
26
8
OE
I/O Cells
Macrocells
I/O8–I/O15
Macrocells
8
8
8
52 x 68
AND Logic
Amrray
and
26
8
OE
I/O Cells
Macrocells
I/O24–I/O31
Macrocells
8
8
8
52 x 68
AND Logic Array
and
Logic Allocator
26
8
OE
I/O Cells
Macrocells
I/O16–I/O23
Macrocells
8
8
8
52 x 68
AND Logic Array
and
Logic Allocator
26
8
OE
Block A Block B
Block D Block C
2 2
2 2
14051K-010
MACH211 only
MACH211
CLK0 /I1
CLK1 /I2
CLK2/I4
CLK3 /I5
MACH211
CLK0 /I0
CLK1 /I1MACH211SP
4 MACH211
2 MACH211SP
2 MACH211 only
22 MACH 1 & 2 Families
BLOCK DIAGRAM
(
MACH221, MACH221SP
)
CLK0/I0, CLK1/I1
CLK2/I4, CLK3/I5
I2–I3,
I6–I7
4
4
4
4
I/O Cells
Macrocells
6
Macrocells
66
52 x 52
AND Logic Array
and Logic Allocator
I/O18 – I/O23
6
26
O
I/O42 – I/O47
I/O Cells
Macrocells
6
Macrocells
66
52 x 52
AND Logic Array
and Logic Allocator
I/O0 – I/O5
Macrocells Macrocells
6
6
6
I/O Cells
Switch Matrix
6
6
26
26
52 x 52
AND Logic Array
and Logic Allocator
O
O
I/O36 – I/O41
I/O Cells
Macrocells
6
Macrocells
66
52 x 52
AND Logic Array
and Logic Allocator
I/O6 – I/O11
Macrocells Macrocells
6
6
6
I/O Cells
6
6
26
26
52 x 52
AND Logic Array
and Logic Allocator
O
O
I/O30 – I/O35
I/O Cells
Macrocells
6
Macrocells
66
52 x 52
AND Logic Array
and Logic Allocator
I/O12 – I/O17
Macrocells Macrocells
6
6
6
I/O Cells
6
6
26
26
52 x 52
AND Logic Array
and Logic Allocator
O
O
I/O24 – I/O29
Macrocells Macrocells
6
6
6
I/O Cells 6
26
52 x 52
AND Logic Array
and Logic Allocator
O
222
222 2
2
Block H Block G Block F Block E
Block DBlock CBlock BBlock A
14051K-011
MACH 1 & 2 Families 23
BLOCK DIAGRAM
(
MACH231, MACH231SP
)
CLK0/I0, CLK1/I1
CLK2/I3, CLK3/I4
I2, I5
4
2
4
4
I/O Cells
Macrocells
8
Macrocells
88
64 x 68
AND Logic Array
and Logic Allocator
I/O24 – I/O31 (Block D)
8
32
OE
I/O56 – /O63 (Block
I/O Cells
Macrocells
8
Macrocells
88
64 x 68
AND Logic Array
and Logic Allocator
I/O0 – I/O7 (Block A)
Macrocells Macrocells
8
8
8
I/O Cells
Switch Matrix
8
8
32
32
64 x 68
AND Logic Array
and Logic Allocator
OE
OE
I/O48 – I/O55 (Block G)
I/O Cells
Macrocells
8
Macrocells
88
64 x 68
AND Logic Array
and Logic Allocator
I/O8 – I/O15 (Block B)
Macrocells Macrocells
8
8
8
I/O Cells
8
8
32
32
64 x 68
AND Logic Array
and Logic Allocator
OE
OE
I/O40 – I/O47 (Block F)
I/O Cells
Macrocells
8
Macrocells
88
64 x 68
AND Logic Array
and Logic Allocator
I/O16 – I/O23 (Block C)
Macrocells Macrocells
8
8
8
I/O Cells
8
8
32
32
64 x 68
AND Logic Array
and Logic Allocator
OE
OE
I/O32 – I/O39 (Block E)
Macrocells Macrocells
8
8
8
I/O Cells 8
32
64 x 68
AND Logic Array
and Logic Allocator
OE
22 2 2
2222
14051K-012
24 MACH 1 & 2 Families
ABSOLUTE MAXIMUM RATINGS
Storage Temperature. . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature
With Power Applied . . . . . . . . . . . . . .-55°C to +125°C
Device Junction Temperature . . . . . . . . . . . . . +150°C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . . .-0.5 V to +7.0 V
DC Input Voltage . . . . . . . . . . . . -0.5 V to VCC +0.5 V
DC Output or I/O Pin Voltage . . -0.5 V to VCC +0.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latchup Current (TA = -40°C to +85°C). . . . . . . 200 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum Rat-
ings for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA)
Operating in Free Air. . . . . . . . . . . . . . . 0°C to +70°C
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
Industrial (I) Devices
Ambient Temperature (TA)
Operating in Free Air. . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
DC CHARACTERISTICS OVER OPERATING RANGES
Notes:
1. This applies to MACH111SP, MACH131SP, and die code “B” or later for MACH211(SP) and MACH231(SP). This does not apply
to MACH111, MACH131, MACH221(SP), and die code “A” for MACH211(SP) and MACH231(SP).
2. Total IOL for one PAL block should not exceed 64 mA.
3. These are absolute values with respect to device ground, and all overshoots due to system and/or tester noise are included.
4. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH).
5. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
6. For commercial temperature range only.
Parameter
Symbol Parameter Description Test Description Min Typ Max Unit
VOH Output HIGH Voltage IOH = –3.2 mA, VCC = Min, VIN = VIH or VIL 2.4 V
IOH = –300 µA, VCC = Max, VIN = VIH or VIL (Note 1) 3.5 V
VOL Output LOW Voltage IOL = 16 mA, VCC = Min, VIN = VIH or VIL (Note 2) 0.5 V
VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs
(Note 3) 2.0 V
VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs
(Note 3) 0.8 V
IIH Input HIGH Leakage Current VIN = 5.25 V, V VCC = Max (Note 4) 10 µA
IIL Input LOW Leakage Current VIN = 0 V, VCC = Max (Note 4) –10 µA
IOZH Off-State Output Leakage Current HIGH VOUT = 5.25 V, VCC = Max, VIN = VIH or VIL (Note 4) 10 µA
IOZL Off-State Output Leakage Current LOW VOUT = 0 V, VCC = Max, VIN = VIH or VIL (Note 4) –10 µA
ISC Output Short-Circuit Current VOUT = 0.5 V VCC = Max (Note 5) –30 –130 (Note 6),
–160 mA
MACH 1 & 2 Families 25
MACH111 AND MACH111SP
SWITCHING CHARACTERISTICS OVER OPERATING RANGES1
Notes:
1. See “Switching Test Circuit” in the General Information Section of the Vantis 1999 Data Book.
2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where this parameter may be affected.
3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
Parameter
Symbol Parameter Description
-5 -7 -10 -12 -14 -15 -18
UnitMin Max Min Max Min Max Min Max Min Max Min Max Min Max
tPD Input, I/O, or Feedback to Combinatorial Output 5 7.5 10 12 14 15 18 ns
tSSetup Time from Input, I/O, or Feedback
to Clock D-type 3.5 5.5 6.5 7 8.5 10 12 ns
T-type 4 6.5 7.5 8 10 11 13.5 ns
tHRegister Data Hold Time 0000000ns
tCO Clock to Output 3.5 5 6 8 10 10 12 ns
tWL Clock Width LOW2.5356667.5ns
tWH HIGH 2.5 356667.5ns
fMAX Maximum
Frequency
External
Feedback 1/(tS + tCO)D-type 143 95 80 66.7 54 50 42 MHz
T-type 133 87 74 62.5 50 47.6 39 MHz
Internal Feedback (fCNT)D-type 182 133 100 76.9 69 66.6 53 MHz
T-type 167 125 91 71.4 57 55.5 44 MHz
No Feedback 1/(tWL + tWH) 200 167 100 83.3 83.3 83.3 66.7 MHz
tAR Asynchronous Reset to Registered Output 7.5 9.5 11 16 19.5 20 24 ns
tARW Asynchronous Reset Width (Note 2) 4.5 5 7.5 12 14.5 15 18 ns
tARR Asynchronous Reset Recovery Time (Note 2) 4.5 5 7.5 8 10 10 12 ns
tAP Asynchronous Preset to Registered Output 7.5 9.5 11 16 19.5 20 24 ns
tAPW Asynchronous Preset Width (Note 2) 4.5 5 7.5 12 14.5 15 18 ns
tAPR Asynchronous Preset Recovery Time (Note 2) 4.5 5 7.5 8 10 10 12 ns
tEA Input, I/O, or Feedback to Output Enable 7.5 9.5 10 12 14.5 15 18 ns
tER Input, I/O, or Feedback to Output Disable 7.5 9.5 10 12 14.5 15 18 ns
tLP tPD Increase for Powered-down Macrocell (Note 3) 10 10 10 10 10 10 10 ns
tLPS tS Increase for Powered-down Macrocell (Note 3) 7777777ns
tLPCO tCO Increase for Powered-down Macrocell (Note 3) 3333333ns
tLPEA tEA Increase for Powered-down Macrocell (Note 3) 10 10 10 10 10 10 10 ns
26 MACH 1 & 2 Families
MACH131 AND MACH131SP
SWITCHING CHARACTERISTICS OVER OPERATING RANGES1
Notes:
1. See “Switching Test Circuit” in the General Information Section of the Vantis 1999 Data Book..
2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
this parameter may be affected.
3. If a signal is powered down, this parameter must be added to its respective high-speed parameter.
Parameter
Symbol Parameter Description
-5 -7 -10 -12 -14 -15 -18
UnitMin Max Min Max Min Max Min Max Min Max Min Max Min Max
tPD Input, I/O, or Feedback to Combinatorial Output 5.5 7.5 10 12 14 15 18 ns
tSSetup T ime from Input, I/O, or Feedback D-type 3.0 5.5 6.5 7 8.5 10 12 ns
T-type 3.5 6.5 7.5 8 10 11 13.5 ns
tHHold Time 0000000ns
tCO Clock to Output 4568101012ns
tWL Clock Width LOW2.5346667.5ns
tWH HIGH 2.5 346667.5ns
fMAX Maximum
Frequency
External
Feedback 1/(tS + tCO)D-type 143 95 80 66.7 54 50 42 MHz
T-type 133 87 74 62.5 50 47.6 39 MHz
Internal Feedback (fCNT)D-type 182 133 100 76.9 69 66.6 53 MHz
T-type 167 125 91 71.4 57 55.5 44 MHz
No
Feedback 1/(tWL + tWH) 200 167 125 83.3 83.3 83.3 66.7 MHz
tAR Asynchronous Reset to Registered Output 8.5 9.5 11 16 19.5 20 24 ns
tARW Asynchronous Reset Width (Note 2) 4.5 5 7.5 12 14.5 15 18 ns
tARR Asynchronous Reset Recovery Time (Note 2) 4.5 5 7.5 8 10 10 12 ns
tAP Asynchronous Preset to Registered Output 8.5 9.5 11 16 19.5 20 24 ns
tAPW Asynchronous Preset Width (Note 2) 4.5 5 7.5 12 14.5 15 18 ns
tAPR Asynchronous Preset Recovery Time (Note 2) 4.5 5 7.5 8 10 10 12 ns
tEA Input, I/O, or Feedback to Output Enable 7.5 9.5 10 12 14.5 15 18 ns
tER Input, I/O, or Feedback to Output Disable 7.5 9.5 10 12 14.5 15 18 ns
tLP tPD Increase for Powered-Down Macrocell (Note 3) 10 10 10 10 10 10 10 ns
tLPS tS Increase for Powered-Down Macrocell (Note 3) 7777777ns
tLPCO tCO Increase for Powered-Down Macrocell (Note 3) 3333333ns
tLPEA tEA Increase for Powered-Down Macrocell (Note 3) 10 10 10 10 10 10 10 ns
MACH 1 & 2 Families 27
MACH211 AND MACH211SP
SWITCHING CHARACTERISTICS OVER OPERATING RANGES 1
Parameter
Symbol Parameter Description
-6 -7 -10 -12 -14 -15 -18
UnitMin Max Min Max Min Max Min Max Min Max Min Max Min Max
tPD Input, I/O, or Feedback to Combinatorial
Output 6 7.5 10 12 14 15 18 ns
tSSetup T ime from Input, I/O, or Feedback
to Clock
D-type 5 5.5 6.5 7 8.5 10 12 ns
T-type 5.5 6.5 7.5 8 10 11 13.5 ns
tHRegister Data Hold Time 0 0 0 0000 ns
tCO Clock to Output 4 4.5 6 8 10 10 12 ns
tWL Clock Width LOW 2.5 3 5 6 6 6 7.5 ns
tWH HIGH 2.5 3 5 6 6 6 7.5 ns
fMAX Maximum
Frequency
External
Feedback 1/(tS + tCO)D-type 111 100 80 66.7 54 50 42 MHz
T-type 105 91 74 62.5 50 47.6 39 MHz
Internal Feedback (fCNT)D-type 166 133 100 83.3 69 66.6 55.6 MHz
T-type 150 125 91 76.9 62.5 62.5 51.3 MHz
No Feedback 1/(tWL + tWH) 200 167 100 83.3 83.3 83.3 66.7 MHz
tSL Setup Time from Input, I/O, or Feedback to Gate 5 5.5 6.5 7 8.5 10 12 ns
tHL Latch Data Hold Time 0 0 0 0000 ns
tGO Gate to Output 7 7
7.5
(note 4)
7
8
(note 5)
10 11 11 13
(note 6)
13.5 ns
tGWL Gate Width LOW 2.5 3 5 6 6 6 7.5 ns
tPDL Input, I/O, or Feedback to Output Through
Transparent Input or Output Latch 9 9.5 12 14 17 17 20
(note 6)
20.5 ns
tSIR Input Register Setup Time 1.5 2 2 2 2 2 2.5 ns
tHIR Input Register Hold Time 1.5 2 2 2 2.5 2.5 3.5 ns
tICO Input Register Clock to Combinatorial Output 10 11 13 15 18 18 20
(note 6)
22 ns
tICS Input Register Clock to Output Register
Setup
D-type 8 9 10 12 14.5 15 18 ns
T-type 9 10 11 13 16 16 19.5 ns
tWICL Input Register
Clock Width
LOW 2.5 3 5 6 6 6 7.5 ns
tWICH HIGH 2.5 3 5 6 6 6 7.5 ns
fMAXIR Maximum Input Register
Frequency 1/(tWICL + tWICH) 200 167 100 83.3 83.3 83.3 66.7 MHz
tSIL Input Latch Setup Time 1.5 2 2 2 2 2 2.5 ns
tHIL Input Latch Hold Time 1.5 2 2 2 2.5 2.5 3.5 ns
tIGO Input Latch Gate to Combinatorial Output 12 12 14 17 20 20 24 ns
tIGOL Input Latch Gate to Output Through Transparent
Output Latch 13 14 16 19 22 22 26.5 ns
tSLL Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate 7 7.5 8.5 9 11 12 14.5 ns
tIGS Input Latch Gate to Output Latch Setup 9 10 11 13 16 16 19.5 ns
tWIGL Input Latch Gate Width LOW 2.5 3 5 6 6 6 7.5 ns
tPDLL Input, I/O, or Feedback to Output Through
Transparent Input and Output Latches 12 12.5 14 16 19 19 23 ns
28 MACH 1 & 2 Families
Notes:
1. See “Switching Test Circuit” in the General Information Section of the Vantis 1999 Data Book.
2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
this parameter may be affected.
3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
4. MACH211 tGO = 7 ns. MACH211SP tGO = 7.5 ns.
5. MACH211, commercial tGO = 7 ns.
6. The faster -18 tGO, tPDL, tICO, apply to MACH211 only, not MACH211SP.
tAR Asynchronous Reset to Registered or Latched
Output 9 9.5 15 16 19.5 20 24 ns
tARW Asynchronous Reset Width (Note 2) 4 5 10 12 14.5 15 18 ns
tARR Asynchronous Reset Recovery Time (Note 2) 4 5 10 10 10 10 12 ns
tAP Asynchronous Preset to Registered or Latched
Output 9 9.5 15 16 19.5 20 24 ns
tAPW Asynchronous Preset Width (Note 2) 4 5 10 12 14.5 15 18 ns
tAPR Asynchronous Preset Recovery Time (Note 2) 4 5 10 10 10 10 12 ns
tEA Input, I/O, or Feedback to Output Enable 9 9.5 10 12 14 15 18 ns
tER Input, I/O, or Feedback to Output Disable 9 9.5 10 12 14 15 18 ns
tLP tPD Increase for Powered-down Macrocell (Note 3) 10 10 10 10 10 10 10 ns
tLPS tS Increase for Powered-down Macrocell (Note 3) 10 10 10 10 10 10 10 ns
tLPCO tCO Increase for Powered-down Macrocell (Note 3) 0 0 0 0 0 0 0 ns
tLPEA tEA Increase for Powered-down Macrocell (Note 3) 10 10 10 10 10 10 10 ns
MACH211 AND MACH211SP (CONTINUED)
SWITCHING CHARACTERISTICS OVER OPERATING RANGES 1
Parameter
Symbol Parameter Description
-6 -7 -10 -12 -14 -15 -18
UnitMin Max Min Max Min Max Min Max Min Max Min Max Min Max
MACH 1 & 2 Families 29
MACH221 and MACH221SP
SWITCHING CHARACTERISTICS OVER OPERATING RANGES 1
P arameter
Symbol Parameter Description
-7 -10 -12 -14 -15 -18
UnitMin Max Min Max Min Max Min Max Min Max Min Max
tPD Input, I/O, or Feedback to Combinatorial Output 7.5 10 12 14 15 18 ns
tsSetup Time from Input, I/O, or Feedback to
Clock
D-type 5.5 6.5 7 8.5 10 12 ns
T-type 6.5 7.5 8 10 11 13.5 ns
tHRegister Data Hold Time 000000ns
tCO Clock to Output 5 6 8 10 10 12 ns
tWL Clock Width LOW356667.5ns
tWH HIGH 356667.5ns
fMAX Maximum
Frequency
External
Feedback 1/(tS + tCO)D-type 95 80 66.7 54 50 42 MHz
T-type 87 74 62.5 50 47.6 39 MHz
Internal Feedback (fCNT)D-type 133 100 83.3 69 66.6 55.6 MHz
T-type 125 91 76.9 62.5 62.5 51.3 MHz
No Feedback 1/(tWL + tWH) 167 100 83.3 83.3 83.3 66.7 MHz
tSL Setup Time from Input, I/O, or Feedback to Gate 5.5 6.5 7 8.5 10 12 ns
tHL Latch Data Hold Time 000000ns
tGO Gate to Output 7 7
(note 2) 10 11 11 13.5 ns
tGWL Gate Width LOW 356667.5ns
tPDL Input, I/O, or Feedback to Output Through Transparent
Input or Output Latch 9.5 12 14 17 17 20.5 ns
tSIR Input Register Setup Time 222222.5ns
tHIR Input Register Hold Time 2 2 2 2.5 2.5 3.5 ns
tICO Input Register Clock to Combinatorial Output 11 13 15 18 18 22 ns
tICS Input Register Clock to Output Register Setup D-type 9 10 12 14.5 15 18 ns
T-type 10 11 13 16 16 19.5 ns
tWICL Input Register LOW 356667.5ns
tWICH Clock Width HIGH 356667.5ns
fMAXIR Maximum Input Register
Frequency 1/(tWICL + tWICH) 167 100 83.3 83.3 83.3 66.7 MHz
tSIL Input Latch Setup Time 222222.5ns
tHIL Input Latch Hold Time 2 2 2 2.5 2.5 3.5 ns
tIGO Input Latch Gate to Combinatorial Output 12 14 17 20 20 24 ns
tIGOL Input Latch Gate to Output Through Transparent Output
Latch 14 16 19 22 22 26.5 ns
tSLL Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate 7.5 8.5 9 11 12 14.5 ns
tIGS Input Latch Gate to Output Latch Setup 10 11 13 16 16 19.5 ns
tWIGL Input Latch Gate Width LOW 356667.5ns
tPDLL Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches 11.5 14 16 19 19 23 ns
tAR Asynchronous Reset to Registered or Latched Output 9.5 15 16 19.5 20 24 ns
tARW Asynchronous Reset Width (Note 3) 5 10 12 14.5 15 18 ns
tARR Asynchronous Reset Recovery Time (Note 3) 5 8 10 10 10 12 ns
tAP Asynchronous Preset to Registered or Latched Output 9.5 15 16 19.5 20 24 ns
30 MACH 1 & 2 Families
Notes:
1. See “Switching Test Circuits” in the General Information section of the Vantis 1999 Data Book.
2. MACH221 tGO = 7 ns. MACH221SP tGO = 8 ns.
3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
this parameter may be affected.
4. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
tAPW Asynchronous Preset Width (Note 3) 5 10 12 14.5 15 18 ns
tAPR Asynchronous Preset Recovery Time (Note 3) 5 8 10 10 10 12 ns
tEA Input, I/O, or Feedback to Output Enable 9.5 12 12 14 15 18 ns
tER Input, I/O, or Feedback to Output Disable 9.5 12 12 14 15 18 ns
tLP tPD Increase for Powered-down Macrocell (Note 4) 10 10 10 10 10 10 ns
tLPS tS Increase for Powered-down Macrocell (Note 4) 10 10 10 10 10 10 ns
tLPCO tCO Increase for Powered-down Macrocell (Note 4) 000000ns
tLPEA tEA Increase for Powered-down Macrocell (Note 4) 10 10 10 10 10 10 ns
MACH221 and MACH221SP (CONTINUED)
SWITCHING CHARACTERISTICS OVER OPERATING RANGES 1
P arameter
Symbol Parameter Description
-7 -10 -12 -14 -15 -18
UnitMin Max Min Max Min Max Min Max Min Max Min Max
MACH 1 & 2 Families 31
MACH231 AND MACH231SP
SWITCHING CHARACTERISTICS OVER OPERATING RANGES 1
Parameter
Symbol Parameter Description
-6 -7 -10 -12 -14 -15 -18
UnitMin Max Min Max Min Max Min Max Min Max Min Max Min Max
tPD Input, I/O, or Feedback to Combinatorial Output 6 7.5 10 12 14 15 18 ns
tSSetup T ime from Input, I/O, or Feedback
to Clock
D-type 5 5.5 6.5 7 8.5 10 12 ns
T-type 6 6.5 7.5 8 10 11 13.5 ns
tHRegister Data Hold Time 0000000ns
tCO Clock to Output 4 5 6.5 8 10 10 12 ns
tWL Clock Width LOW2.5346667.5ns
tWH HIGH 2.5 346667.5ns
fMAX Maximum
Frequency
External
Feedback 1/(tS + tCO)D-type 111 95 77 66.7 54 50 42 MHz
T-type 100 87 72 62.5 50 47.6 39 MHz
Internal Feedback (fCNT)D-type 166 133 100 83.3 69 66.6 55.6 MHz
T-type 150 125 91 76.9 62.5 62.5 51.3 MHz
No
Feedback 1/(tWL + tWH) 200 167 125 83.3 83.3 83.3 66.7 MHz
tSL Setup Time from Input, I/O, or Feedback to Gate 5 5.5 6.5 7 8.5 10 12 ns
tHL Latch Data Hold Time 0000000ns
tGO Gate to Output 5 6 7.5 8.5 11 11 13.5 ns
tGWL Gate Width LOW 2346667.5ns
tPDL Input, I/O, or Feedback to Output Through
Transparent Input or Output Latch 9 9.5 14 14.5 17 17 20.5 ns
tSIR Input Register Setup Time 1.5 222222.5ns
tHIR Input Register Hold Time 1.5 2 2.5 2.5 2.5 2.5 3.5 ns
tICO Input Register Clock to Combinatorial Output 10 11 15.5 16 18 18 22 ns
tICS Input Register Clock to output Register
Setup
D-type 8 9 11 12 14.5 15 18 ns
T-type 9 10 12 13 16 16 19.5 ns
tWICL Input Register
Clock Width
LOW2.5346667.5ns
tWICH HIGH 2.5 346667.5ns
fMAXIR Maximum Input Register Frequency 200 167 125 83.3 83.3 83.3 66.7 MHz
tSIL Input Latch Setup Time 1.5 2 2 2.5 2.5 2.5 2.5 ns
tHIL Input Latch Hold Time 1.5 2 2.5 3 3 3 3.5 ns
tIGO Input Latch Gate to Combinatorial Output 11 12 17 17 20 20 24 ns
tIGOL Input Latch Gate to Output Through Transparent
Output Latch 13 14 18 19.5 22 22 26.5 ns
tSLL Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate 7 7.5 10 10.5 11 12 14.5 ns
tIGS Input Latch Gate to Output Latch Setup 9 10 11 13.5 16 16 19.5 ns
32 MACH 1 & 2 Families
Notes:
1. See “Switching Test Circuit” in the General Information section of the Vantis 1999 Data Book.
2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
this parameter may be affected.
3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
CAPACITANCE 1
Note:
1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
these parameters may be affected.
tWIGL Input Latch Gate Width LOW 2346667.5ns
tPDLL Input, I/O, or Feedback to Output Through
Transparent Input and Output Latches 11 12.5 16 17 19 19 23 ns
tAR Asynchronous Reset to Registered or Latched
Output 9 9.5 13 16 19.5 20 24 ns
tARW Asynchronous Reset Width (Note 2) 4 5 10 12 14.5 15 18 ns
tARR Asynchronous Reset Recovery Time
(Note 2) 4 57.58 101012ns
tAP Asynchronous Preset to Registered or Latched
Output 9 9.5 13 16 19.5 20 24 ns
tAPW Asynchronous Preset Width (Note 2) 4 5 10 12 14.5 15 18 ns
tAPR Asynchronous Preset Recovery Time (Note 2) 4 5 7.5 8 10 10 12 ns
tEA Input, I/O, or Feedback to Output Enable 9 9.5 10 12 15 15 18 ns
tER Input, I/O, or Feedback to Output Disable 9 9.5 10 12 15 15 18 ns
tLP tPD Increase for Powered-down Macrocell (Note 3) 9 10 10 10 10 10 10 ns
tLPS tS Increase for Powered-down Macrocell (Note 3) 6777777ns
tLPCO tCO Increase for Powered-down Macrocell (Note 3) 0000000ns
tLPEA tEA Increase for Powered-down Macrocell (Note 3) 9 10 10 10 10 10 10 ns
Parameter Symbol Parameter Description Test Conditions Typ Unit
CIN Input Capacitance VIN = 2.0V VCC = 5.0V,
TA = 25°C
f = 1 MHz
6pF
COUT Output Capacitance VOUT = 2.0V 8 pF
MACH231 AND MACH231SP (CONTINUED)
SWITCHING CHARACTERISTICS OVER OPERATING RANGES 1
Parameter
Symbol Parameter Description
-6 -7 -10 -12 -14 -15 -18
UnitMin Max Min Max Min Max Min Max Min Max Min Max Min Max
MACH 1 & 2 Families 33
ICC vs. FREQUENCY
These curves represent the typical power consumption for a particular device at system frequency.
The selected “typical” pattern is a 16-bit up-down counter. This pattern fills the device and
exercises every macrocell. Maximum frequency shown uses internal feedback and a D-type
register.
TA = 25°C, VCC =5V
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
High Speed
Low Power
Frequency (MHz)
ICC (mA)
0
25
50
75
100
125
150
0102030405060708090
High Speed
Low Power
Frequency (MHz)
ICC (mA)
0
50
25
100
75
125
150
175
200
225
250
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Low Power
Frequency (MHz)
ICC (mA)
0
25
50
75
100
125
150 High Speed
MACH111(SP) MACH131(SP)
MACH211(SP)
0102030405060708090
High Speed
Low Power
Frequency (MHz)
ICC (mA)
0
50
25
100
75
125
150
175
200
225
250
MACH 221(SP)
275
Low Power
Frequency (MHz)
100
150
200
250
300
350
400
High Speed
MACH231
Low Power
Frequency (MHz)
50
100
150
200
250
300
350
High Speed
MACH231SP
400
01020304050607080
01020304050607080
ICC (mA)
ICC (mA)
00
34 MACH 1 & 2 Families
Table 12. ICC
Device Parameter Symbol Parameter
Description Test Description Typ Unit
MACH111(SP)
MACH211(SP)
ICC
Supply Current (Static) VCC = 5V,
TA = 25°C,
f = 0 MHz
40
mA
MACH221(SP) 70
MACH131(SP) 75
MACH231SP 80
MACH231 135
MACH111(SP)
MACH211(SP)
Supply Current (Active) VCC = 5V,
TA = 25°C,
f = 1 MHz
45
MACH221(SP) 75
MACH131(SP) 80
MACH231SP 100
MACH231 150
MACH 1 & 2 Families 35
44- PIN PLCC CONNECTION DIAGRAM (MACH111-5/7/10/12/15 AND
MACH111SP-5/7/10/12/15)
Top View
44-Pin PLCC
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
I = Input
I/O = Input/Output
VCC = Supply Voltage
TDI = Test Data In
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out
Note:
1. Pin designators in parentheses ( ) apply to the MACH111SP
144 43 42
5432
641
40
7
8
9
10
11
12
13
14
15
16
17 23 24 25 26
19 20 21 22
18 27 28
39
38
37
36
35
34
33
32
31
30
29
I/O5
I/O6
I/O7
(TDI) I0
(CLK 0/I0) CLK0/I1
GND
(TCK) CLK1/I2
I/O8
I/O9
I/O10
I/O11
I/O27
I/O26
I/O25
I/O24
CLK3/I5 (TDO)
GND
CLK2/I4 (CLK 1/I1)
I3 (TMS)
I/O23
I/O22
I/O21
I/O12
I/O13
I/O14
I/O15
VCC
GND
I/O16
I/O17
I/O18
I/O19
I/O20
I/O4
I/O3
I/O2
I/O1
I/O0
GND
VCC
I/O31
I/O30
I/O29
I/O28
Block B
Block A
14051K-018
36 MACH 1 & 2 Families
44-PIN TQFP CONNECTION DIAGRAM (MACH111-5/7/10/12/15 AND
MACH111SP-5/7/10/12/15)
Top View
44-Pin TQFP
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
I = Input
I/O = Input/Output
VCC = Supply Voltage
TDI = Test Data In
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out
Note:
1. Pin designators in parentheses ( ) apply to the MACH111SP
I/O12
I/O13
I/O14
I/O15
VCC
GND
I/O16
I/O17
I/O18
I/O19
I/O20
I/O4
I/O3
I/O2
I/O1
I/O0
GND
VCC
I/O31
I/O30
I/O29
I/O28
I/O27
I/O26
I/O25
I/O24
CLK3/I5 (TDO)
GND
CLK2/I4 (CLK 1/I1)
I3 (TMS)
I/O23
I/O22
I/O21
I/O5
I/O6
I/O7
(TDI) I0
(CLK 0/I0) CLK0/I1
GND
(TCK) CLK1/I2
I/O8
I/O9
I/O10
I/O11
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
44
43
42
41
40
39
38
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
Block B
Block A
14051K-019
MACH 1 & 2 Families 37
84-PIN PLCC CONNECTION DIAGRAM (MACH131-5/7/10/12/15)
Top View
84-Pin PLCC
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
I = Input
I/O = Input/Output
VCC = Supply Voltage
1
2
381
82
83
84
6
7
8
94
580 76
77
78
79 75
12
13
14
15
16
17
18
19
20
21
23
24
25
26
27
28
29
30
31
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
43
42
41
40 47
46
45
44
37
36
35
34 39
38
33 48 52
51
50
49
10
22
11
32 53
74
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
CLK0/I0
VCC
GND
CLK1/I1
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O8 GND
I/O55
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
CLK3/I4
VCC
CLK2/I3
I/O47
I/O46
I/O45
I/O44
I/O43
I/O42
I/O41
GND
I/O40
GND
VCC
I/O0
I/O62
I/O63
I5
VCC
I/O3
I/O4
I/O5
I/O6
I/O1
I/O2
I/O61
I/O57
I/O58
I/O59
I/O60
I/O56
I/O7
GND
GND
VCC
I2
I/O34
I/O33
I/O32
VCC
I/O29
I/O28
I/O27
I/O26
I/O31
I/O30
I/O35
I/O39
I/O38
I/O37
I/O36
GND
I/O25
I/O24
Block A Block D
Block B Block C 14051K-020
38 MACH 1 & 2 Families
100-PIN PQFP CONNECTION DIAGRAM (MACH131SP-5/7/10/12/15)
Top View
100-Pin PQFP
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
I = Input
I/O = Input/Output
VCC = Supply Voltage
TDI = Test Data In
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
GND
GND
I/O63
I/O62
I/O61
I/O60
I/O59
I/O58
I/O57
I/O56
GND
GND
TDI
I5
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
IO/CLK0
GND
GND
VCC
VCC
I1/CLK1
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
N/C
TCK
GND
GND
28
29
30
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
1
2
3
99
98
100
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
97
96
95
94
93
92
91
90
89
88
87
86
85
84
82
81
83
I/O46
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
I2
TMS
GND
GND
GND
TDO
N/C
I/O55
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
I4/CLK3
GND
GND
VCC
VCC
I3/CLK2
I/O47
GND
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
80
79
78
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
GND
VCC
GND
VCC
VCC
VCC
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
Block DBlock A
Block CBlock B 14051K-021
MACH 1 & 2 Families 39
100-PIN TQFP CONNECTION DIAGRAM (MACH131SP-5/7/10/12/15)
Top View
100-Pin TQFP
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
I = Input
I/O = Input/Output
VCC = Supply Voltage
TDI = Test Data In
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
TDI
I/5
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I0/CLK0
VCC
GND
GND
I1/CLK1
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
NC
TCK
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GND
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
NC
VCC
GND
GND
VCC
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
GND
GND
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
GND
GND
NC
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
VCC
GND
GND
VCC
NC
I/O63
I/O62
I/O61
I/O60
I/O59
I/O58
I/O57
I/O56
GND
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GND
TDO
NC
I/O55
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
I4/CLK3
GND
VCC
I3/CLK2
I/O47
I/O46
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
I2
TMS
Block DBlock A
Block CBlock B 14051K-022
40 MACH 1 & 2 Families
44-PIN PLCC CONNECTION DIAGRAM (MACH211-7/10/12/15 AND
MACH211SP-6/7/10/12/15)
Top View
44-Pin PLCC
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
I = Input
I/O = Input/Output
VCC = Supply Voltage
TDI = Test Data In
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out
Note:
1. Pin designators in parentheses ( ) apply to the MACH211SP
144 43 42
5432
641
40
7
8
9
10
11
12
13
14
15
16
17 23 24 25 26
19 20 21 22
18 27 28
39
38
37
36
35
34
33
32
31
30
29
I/O5
I/O6
I/O7
(TDI) I0
(CLK 0/I0) CLK0/I1
GND
(TCK) CLK1/I2
I/O8
I/O9
I/O10
I/O11
I/O27
I/O26
I/O25
I/O24
CLK3/I5 (TDO)
GND
CLK2/I4 (CLK 1/I1)
I3 (TMS)
I/O23
I/O22
I/O21
I/O12
I/O13
I/O14
I/O15
VCC
GND
I/O16
I/O17
I/O18
I/O19
I/O20
I/O4
I/O3
I/O2
I/O1
I/O0
GND
VCC
I/O31
I/O30
I/O29
I/O28
Block DBlock A
Block B Block C 14051K-023
MACH 1 & 2 Families 41
44-PIN TQFP CONNECTION DIAGRAM (MACH211-7/10/12/15 AND
MACH211SP-6/7/10/12/15)
Top View
44-Pin TQFP
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
I = Input
I/O = Input/Output
VCC = Supply Voltage
TDI = Test Data In
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out
Note:
1. Pin designators in parentheses ( ) apply to the MACH211SP
I/O12
I/O13
I/O14
I/O15
VCC
GND
I/O16
I/O17
I/O18
I/O19
I/O20
I/O4
I/O3
I/O2
I/O1
I/O0
GND
VCC
I/O31
I/O30
I/O29
I/O28
I/O27
I/O26
I/O25
I/O24
CLK3/I5 (TDO)
GND
CLK2/I4 (CLK 1/I1)
I3 (TMS)
I/O23
I/O22
I/O21
I/O5
I/O6
I/O7
(TDI) I0
(CLK 0/I0) CLK0/I1
GND
(TCK) CLK1/I2
I/O8
I/O9
I/O10
I/O11
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
44
43
42
41
40
39
38
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
Block B Block C
Block DBlock A
14051K-024
42 MACH 1 & 2 Families
68-PIN PLCC CONNECTION DIAGRAM (MACH221-7/10/12/15)
Top View
68-Pin PLCC
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
I = Input
I/O = Input/Output
VCC = Supply Voltage
Block G Block F
Block EBlock D
Block C
Block A
Block B
Block H
1 68 67 66 65 64 63 62 6176543298
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 35 36 37 38 39 40 41 42 4329 30 31 32 33 3427 28
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O7
I/O8
I/O9
I/O10
I/O11
CLK0/I0
CLK1/I1
I2
VCC
GND
I3
I/O12
I/O13
I/O14
I/O15
I/O16
I/O17
GND
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
VCC
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
GND
I/O30
I/O41
I/O40
I/O39
I/O38
I/O37
I/O36
I7
GND
VCC
I6
CLK3/I5
CLK2/I4
I/O35
I/O34
I/O33
I/O32
I/O31
I/O6
GND
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
GND
VCC
I/O47
I/O46
I/O45
I/O44
I/O43
I/O42
GND
14051K-025
MACH 1 & 2 Families 43
100-PIN PQFP CONNECTION DIAGRAM (MACH221SP-7/10/12/15)
Top View
100-Pin PQFP
PIN DESIGNATIONS
I/CLK = Input or Clock
GND = Ground
I = Input
I/O = Input/Output
VCC = Supply Voltage
TDI = Test Data In
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out
N/C
I/O5
N/C
I/O4
I/O3
I/O2
I/O1
I/O0
GND
GND
I/O47
I/O46
I/O45
I/O44
I/O43
N/C
I/O42
N/C
GND
GND
TDI
I7
N/C
I/O6
N/C
I/O7
I/O8
I/O9
I/O10
I/O11
IO/CLK0
GND
GND
VCC
VCC
I1/CLK1
I/O12
I/O13
I/O14
I/O15
I/O16
N/C
I/O17
I2
N/C
TCK
GND
GND
28
29
30
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
1
2
3
99
98
100
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
97
96
95
94
93
92
91
90
89
88
87
86
85
84
82
81
83
I/O34
I/O33
I/O32
I/O31
N/C
I/O30
N/C
I3
TMS
GND
GND
GND
TDO
N/C
I6
I/O41
N/C
I/O40
I/O39
I/O38
I/O37
I/O36
I5/CLK3
GND
GND
VCC
VCC
I4/CLK2
I/O35
GND
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
80
79
78
N/C
I/O18
N/C
I/O19
I/O20
I/O21
I/O22
I/O23
GND
VCC
GND
VCC
VCC
VCC
I/O24
I/O25
I/O26
I/O27
I/O28
N/C
I/O29
N/C
Block A Block H
Block D Block E
Block C Block B
Block G
Block F
14051K-026
44 MACH 1 & 2 Families
84-PIN PLCC CONNECTION DIAGRAM (MACH231-6/7/10/12/15)
Top View
84-Pin PLCC
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
I = Input
I/O = Input/Output
VCC = Supply Voltage
Block G
Block C
1
2
381
82
83
84
6
7
8
94
580 76
77
78
79 75
12
13
14
15
16
17
18
19
20
21
23
24
25
26
27
28
29
30
31
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
43
42
41
40 47
46
45
44
37
36
35
34 39
38
33 48 52
51
50
49
10
22
11
32 53
74
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
CLK0/I0
VCC
GND
CLK1/I1
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O8 GND
I/O55
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
CLK3/I4
VCC
CLK2/I3
I/O47
I/O46
I/O45
I/O44
I/O43
I/O42
I/O41
GND
I/O40
GND
VCC
I/O0
I/O62
I/O63
I5
VCC
I/O3
I/O4
I/O5
I/O6
I/O1
I/O2
I/O61
I/O57
I/O58
I/O59
I/O60
I/O56
I/O7
GND
GND
VCC
I2
I/O34
I/O33
I/O32
VCC
I/O29
I/O28
I/O27
I/O26
I/O31
I/O30
I/O35
I/O39
I/O38
I/O37
I/O36
GND
I/O25
I/O24
Block B
Block A Block H
Block D Block E
Block F
14051K-027
MACH 1 & 2 Families 45
100-PIN PQFP CONNECTION DIAGRAM (MACH231SP-10/12/15)
Top View
100-Pin PQFP
PIN DESIGNATIONS
I/CLK = Input or Clock
GND = Ground
I = Input
I/O = Input/Output
VCC = Supply Voltage
TDI = Test Data In
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out
Block E
Block B
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
GND
GND
I/O63
I/O62
I/O61
I/O60
I/O59
I/O58
I/O57
I/O56
GND
GND
TDI
I5
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
IO/CLK0
GND
GND
VCC
VCC
I1/CLK1
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
N/C
TCK
GND
GND
28
29
30
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
1
2
3
99
98
100
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
97
96
95
94
93
92
91
90
89
88
87
86
85
84
82
81
83
I/O46
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
I2
TMS
GND
GND
GND
TDO
N/C
I/O55
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
I4/CLK3
GND
GND
VCC
VCC
I3/CLK2
I/O47
GND
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
80
79
78
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
GND
VCC
GND
VCC
VCC
VCC
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
Block A Block H
Block D
Block C
Block F Block G
14051K-028
46 MACH 1 & 2 Families
100-PIN TQFP CONNECTION DIAGRAM (MACH231SP-10/12/15)
Top View
100-Pin TQFP
PIN DESIGNATIONS
CLK/I = Clock or Input
GND = Ground
I = Input
I/O = Input/Output
VCC = Supply Voltage
TDI = Test Data In
TCK = Test Clock
TMS = Test Mode Select
TDO = Test Data Out
Block BBlock C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
TDI
I5
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
I0/CLK0
VCC
GND
GND
I1/CLK1
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
NC
TCK
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GND
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
NC
VCC
GND
GND
VCC
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
GND
GND
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
GND
GND
NC
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
VCC
GND
GND
VCC
NC
I/O63
I/O62
I/O61
I/O60
I/O59
I/O58
I/O57
I/O56
GND
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GND
TDO
NC
I/O55
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
I4/CLK3
GND
VCC
I3/CLK2
I/O47
I/O46
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
I2
TMS
Block A Block H
Block D Block E
Block F Block G
14051K-029
MACH 1 & 2 Families 47
ORDERING INFORMATION
Lattice/Vantis programmable logic products are available with several ordering options. The order number (Valid Combination) is
formed by a combination of:
Valid Combinations
The Valid Combinations list configurations planned to be
supported in volume for this device. Consult the local Lattice/
Vantis sales office to confirm availability of specific valid
combinations and to check on newly released combinations.
Note:
1. All MACH devices are dual-marked with both Commercial and Industrial grades. The Industrial grade is slower, i.e.
MACH131SP-5YC-7YI
SP
F AMIL Y TYPE
M
ACH = Macro Array CMOS High-Density
MACH 131 Y C
MACROCELL DENSITY
1
11 = 32 Macrocells, 32 I/Os
1
31 = 64 Macrocells, 64 I/Os
2
11 = 64 Macrocells, 32 I/Os
2
21 = 96 Macrocells, 48 I/Os
2
31 = 128 Macrocells, 64 I/Os
PRODUCT DESIGNATION
S
P = JTAG-compatible, In-system Programmable
OPERATING CONDITIONS
C = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)
P ACKAGE TYPE
J = Plastic Leaded Chip Carrier
(PLCC)
V = Thin Quad Flat Pack (TQFP)
Y = Plastic Quad Flat Pack (PQFP)
SPEED
-5 = 5.0 or 5.5 ns tPD
-6 = 6.0 ns tPD
-7 = 7.5 ns tPD
-10 = 10 ns tPD
-12 = 12 ns tPD
-14 = 14 ns tPD
-15 = 15 ns tPD
-18 = 18 ns tPD
-5
PROGRAMMING DESIGNATOR
Blank = Initial Algorithm
/1 = First Revision
Valid Combinations – Commercial
MACH111 -5, -7, -10, -12, -15 JC, VC
MACH111SP -5, -7, -10, -12, -15 JC, VC
MACH131 -5, -7, -10, -12, -15 JC/1
MACH131SP -5, -7, -10, -12, -15 VC, YC
MACH211 -7, -10, -12, -15 JC, VC
MACH211SP -6, -7, -10, -12, -15 JC, VC
MACH221 -7, -10, -12, -15 JC
MACH221SP -7, -10, -12, -15 YC
MACH231 -6, -7 JC
-10, -12, -15 JC/1
MACH231SP -10, -12, -15 VC, YC
Valid Combinations – Industrial
MACH111 -7, -10, -12, -14, -18 JI
MACH111SP -7, -10, -12, -14, -18 JI
MACH131 -7, -10, -12, -14, -18 JI/1
MACH131SP -7, -10, -12, -14, -18 YI
MACH211 -10, -12, -14, -18 JI
MACH211SP -10, -12, -14, -18 JI
MACH221 -10, -12, -14, -18 JI
MACH221SP -10, -12, -14, -18 YI
MACH231 -12, -14, -18 JI/1
MACH231SP -12, -14, -18 YI
48 MACH 1 & 2 Families
