Tiny 16-/14-/12-Bit SPI nano
DAC+, with
±2 (16-Bit) LSB INL and 2 ppm/°C Reference
Data Sheet
AD5683R/AD5682R/AD5681R/AD5683
Rev. D Document Feedback
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Technical Support www.analog.com
FEATURES
Ultrasmall package: 2 mm × 2 mm, 8-lead LFCSP
High relative accuracy (INL): ±2 LSB maximum at 16 bits
AD5683R/AD5682R/AD5681R
Low drift, 2.5 V reference: 2 ppm/°C typical
Selectable span output: 2.5 V or 5 V
AD5683
External reference only
Selectable span output: VREF or 2 × VREF
Total unadjusted error (TUE): 0.06% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.05% of FSR maximum
Low glitch: 0.1 nV-sec
High drive capability: 20 mA
Low power: 1.2 mW at 3.3 V
Independent logic supply: 1.62 V logic compatible
Wide operating temperature range: −40°C to +105°C
Robust 4 kV HBM ESD protection
APPLICATIONS
Process controls
Data acquisition systems
Digital gain and offset adjustment
Programmable voltage sources
FUNCTIONAL BLOCK DIAGRAM
AD5683R/
AD5682R/
AD5681R
VREF
GND
LDAC
REF
VDD
VLOGIC*
POWER-DOWN
CONTROL LOGIC
DAC
REGISTER
POWER-ON
RESET 2.5V
REF
OUTPUT
BUFFER
16-/14-/12-BIT
DAC
INPUT
CONTROL LOGIC
VOUT
SCLK SDISYNC
RESET
*NOT AVAILABLE IN ALL THE MODELS
SDO*
RESISTOR
NETWORK
11955-001
Figure 1. AD5683R/AD5682R/AD5681R MSOP
(For more information, see the Functional Block Diagrams—LFCSP section.)
GENERAL DESCRIPTION
The AD5683R/AD5682R/AD5681R/AD5683, members of the
nanoDAC+® family, are low power, single-channel, 16-/14-/12-bit
buffered voltage out digital-to-analog converters (DACs). The
devices, except the AD5683, include an enabled by default internal
2.5 V reference, offering 2 ppm/°C drift. The output span can be
programmed to be 0 V to VREF or 0 V to 2 × VREF. All devices
operate from a single 2.7 V to 5.5 V supply and are guaranteed
monotonic by design. The devices are available in a 2.00 mm ×
2.00 mm, 8-lead LFCSP or a 10-lead MSOP.
The internal power-on reset circuit ensures that the DAC register
is written to zero scale at power-up while the internal output
buffer is configured in normal mode. The AD5683R/AD5682R
/AD5681R/AD5683 contain a power-down mode that reduces
the current consumption of the device to 2 µA (maximum) at 5 V
and provides software selectable output loads while in power-
down mode.
The AD5683R/AD5682R/AD5681R/AD5683 use a versatile
3-wire serial interface that operates at clock rates of up to 50 MHz.
Some devices also include asynchronous RESET pin and VLOGIC
pin options, allowing 1.8 V compatibility.
Table 1. Single-Channel nanoDAC+ Portfolio
Interface Reference 16-Bit 14-Bit 12-Bit
SPI Internal AD5683R AD5682R AD5681R
External AD5683
I2C Internal AD5693R AD5692R AD5691R
External AD5693
PRODUCT HIGHLIGHTS
1. High Relative Accuracy (INL).
AD5683R/AD5683 (16-bit): ±2 LSB maximum.
2. Low Drift, 2.5 V On-Chip Reference.
2 ppm/°C typical temperature coefficient.
5 ppm/°C maximum temperature coefficient.
3. Two Package Options.
2.00 mm × 2.00 mm, 8-lead LFCSP.
10-lead MSOP.
AD5683R/AD5682R/AD5681R/AD5683 Data Sheet
Rev. D | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagrams—LFCSP............................................. 3
Specifications ..................................................................................... 4
AC Characteristics ........................................................................ 6
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings ............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution .................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 17
Theory of Operation ...................................................................... 19
Digital-to-Analog Converter .................................................... 19
Transfer Function ....................................................................... 19
DAC Architecture....................................................................... 19
Serial Interface ................................................................................ 21
SPI Serial Data Interface ............................................................ 21
Short Write Operation (AD5681R Only) ................................ 21
Internal Registers ........................................................................ 23
Commands .................................................................................. 23
Hardware LDAC ......................................................................... 25
Hardware RESET ........................................................................ 25
Thermal Hysteresis .................................................................... 26
Power-Up Sequence ................................................................... 26
Recommended Regulator .......................................................... 26
Layout Guidelines....................................................................... 26
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 28
REVISION HISTORY
12/2016—Rev. C to Rev. D
Changed 1.8 V to 1.62 V, 1.8 V – 10% to 1.62 V, 5 V + 10% to 5.5 V,
and 1.8 V ≤ VLOGIC ≤ 2.7 V to 1.62 V ≤ VLOGIC ≤ 2.7 V ..... Throughout
Changes to DC Power Supply Rejection Ratio, PSRR, Test
Conditions/Comments Column, Table 2 ......................................... 4
3/2016—Rev. B to Rev. C
Changes to Features Section............................................................ 1
Changes to Specifications Section .................................................. 4
Changes to Table 2 ............................................................................ 5
Changes to AC Characteristics Section, Timing Characteristics
Section, and Table 4 .......................................................................... 6
Changes to Figure 4 .......................................................................... 7
Changes to Table 7 ............................................................................ 9
Changes to Table 8 .......................................................................... 10
Changes to Terminology Section.................................................. 17
Changes to SPI Serial Data Interface Section ............................. 21
10/2014—Rev. A to Rev. B
Changes to Table 1 ............................................................................. 1
Changes to Figure 14 ...................................................................... 11
Added Recommended Regulator Section ................................... 26
Changes to Ordering Guide .......................................................... 28
1/2014—Rev. 0 to Rev. A
Change to Features Section .............................................................. 1
Removed Endnote 2, Endnote 3, Endnote 5, and Endnote 6,
Table 2; Renumbered Sequentially .................................................. 5
Removed Endnote 2, Table 3; Renumbered Sequentially ............ 6
Removed Endnote 1, Table 4; Renumbered Sequentially ............ 6
Changes to Table 5 ............................................................................. 8
Removed Solder Heat Reflow Section and Figure 53;
Renumbered Sequentially ............................................................. 25
12/2013—Revision 0: Initial Version
Data Sheet AD5683R/AD5682R/AD5681R/AD5683
Rev. D | Page 3 of 28
FUNCTIONAL BLOCK DIAGRAMS—LFCSP
AD5683R/
AD5682R/
AD5681R
V
REF
GND
LDAC*
REF
V
DD
V
LOGIC
*
POWER-DOWN
CONTROL LOGIC
DAC
REGISTER
POWER-ON
RESET 2.5V
REF
OUTPUT
BUFFER
16-/14-/12-BIT
DAC
INPUT
CONTROL LOGIC
V
OUT
SCLK SDISYNC
RESET*
*NOT AVAILABLE IN ALL THE MODELS
RESISTOR
NETWORK
11955-002
Figure 2. AD5683R/AD5682R/AD5681R LFCSP
AD5683
VREF
GND
LDAC*
REF
VDD
POWER-DOWN
CONTROL LOGIC
DAC
REGISTER
POWER-ON
RESET
OUTPUT
BUFFER
16-BIT
DAC
INPUT
CONTROL LOGIC
VOUT
SCLK SDISYNC
RESISTOR
NETWORK
11955-003
Figure 3. AD5683 LFCSP
AD5683R/AD5682R/AD5681R/AD5683 Data Sheet
Rev. D | Page 4 of 28
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREF = 2.5 V, VLOGIC= 1.62 V to 5.5 V, −40°C < TA < +105°C, unless otherwise
noted.
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
STATIC PERFORMANCE
1
AD5683R
Resolution 16 Bits
Relative Accuracy, INL LSB
A Grade ±8 LSB
B Grade
±2
LSB
Gain = 2
±3 Gain = 1
Differential Nonlinearity, DNL ±1 LSB Guaranteed monotonic by design
AD5683
Resolution 16 Bits
Relative Accuracy, INL ±2 LSB Gain = 2
±3 LSB Gain =1
Differential Nonlinearity, DNL ±1 LSB Guaranteed monotonic by design
AD5682R
Resolution 14 Bits
Relative Accuracy, INL ±1 LSB
Differential Nonlinearity, DNL ±1 LSB Guaranteed monotonic by design
AD5681R
Resolution 12 Bits
Relative Accuracy, INL ±1 LSB
Differential Nonlinearity, DNL ±1 LSB Guaranteed monotonic by design
Zero-Code Error 1.25 mV All 0s loaded to DAC register
Offset Error
±1.5
mV
Full-Scale Error ±0.075 % of FSR All 1s loaded to DAC register
Gain Error ±0.05 % of FSR
Total Unadjusted Error, TUE ±0.16 % of FSR Internal reference, gain = 1
±0.14 % of FSR Internal reference, gain = 2
±0.075 % of FSR External reference, gain = 1
±0.06 % of FSR External reference, gain = 2
Zero-Code Error Drift ±1 µV/°C
Offset Error Drift ±1 µV/°C
Gain Temperature Coefficient ±1 ppm/°C
DC Power Supply Rejection Ratio, PSRR 0.2 mV/V DAC code = midscale; VDD = 5 V
OUTPUT CHARACTERISTICS
Output Voltage Range 0 VREF V Gain = 1
0 2 × VREF V Gain = 2
Capacitive Load Stability
2
nF
R
L
= ∞
10 nF RL = 2 kΩ
Resistive Load 1 kΩ CL = 0 µF
Load Regulation 10 µV/mA 5 V, DAC code = midscale; −30 mA ≤ IOUT ≤ +30 mA
10 µV/mA 3 V, DAC code = midscale; −20 mA ≤ IOUT ≤ +20 mA
Short-Circuit Current 20 30 50 mA
Load Impedance at Rails2 20 Ω
Data Sheet AD5683R/AD5682R/AD5681R/AD5683
Rev. D | Page 5 of 28
Parameter Min Typ Max Unit Test Conditions/Comments
REFERENCE OUTPUT
Output Voltage 2.4975 2.5025 V
At ambient
Voltage Reference TC3 See the Terminology section
A-Grade 5 20 ppm/°C
B-Grade
2
5
ppm/°C
Output Impedance 0.05 Ω
Output Voltage Noise 16.5 µV p-p 0.1 Hz to 10 Hz
Output Voltage Noise Density 250 nV/√Hz At ambient; f = 10 kHz, CL = 10 nF
Capacitive Load Stability 5 µF RL = 2 kΩ
Load Regulation Sourcing 50 µV/mA At ambient; VDD ≥ 3 V
Load Regulation Sinking 30 µV/mA At ambient
Output Current Load Capability ±5 mA VDD ≥ 3 V
Line Regulation 80 µV/V At ambient
Thermal Hysteresis 125 ppm First cycle
25 ppm Additional cycles
REFERENCE INPUT
Reference Current 26 µA VREF = VDD = VLOGIC = 5 V, gain = 1
47 µA VREF = VDD = VLOGIC = 5 V, gain = 2
Reference Input Range
1
V
DD
V
Reference Input Impedance 120 kΩ Gain = 1
60 kΩ Gain = 2
LOGIC INPUTS
IIN, Input Current ±1 µA Per pin
VINL, Input Low Voltage4 0.3 × VDD V
VINH, Input High Voltage4 0.7 × VDD V
CIN, Pin Capacitance 2 pF
LOGIC OUTPUTS (SDO)5
Output Low Voltage, VOL 0.4 V ISINK = 200 μA
Output High Voltage, VOH VDD − 0.4 V ISOURCE = 200 μA
Pin Capacitance
4
pF
POWER REQUIREMENTS
VLOGIC5 1.62 5.5 V
ILOGIC5 0.25 3 µA VIH = VLOGIC or VIL = GND
VDD 2.7 5.5 V Gain = 1
VREF + 1.5 5.5 V Gain = 2
IDD6 VIH = VDD, VIL = GND
Normal Mode7 350 500 µA Internal reference enabled
110 180 µA Internal reference disabled
Power-Down Modes
8
2
µA
1 Linearity is calculated using a reduced code range: AD5683R and AD5683 (Code 512 to Code 65,535); AD5682R (Code 128 to Code 16,384); AD5681R (Code 32 to
Code 4096). Output unloaded.
2 When drawing a load current at either rail, the output voltage headroom, with respect to that rail, is limited by the 20 Ω typical channel resistance of the output
devices; for example, when sinking 1 mA, the minimum output voltage = 20 Ω, 1 mA generates 20 mV. See Figure 38 (Headroom/Footroom vs. Load Current).
3 Reference temperature coefficient is calculated as per the box method. See the Terminology section for more information.
4 Substitute VLOGIC for VDD if device includes a VLOGIC pin.
5 The VLOGIC and SDO pins are not available on all models.
6 If the VLOGIC pin is not available, IDD = IDD + ILOGIC.
7 Interface inactive. DAC active. DAC output unloaded.
8 DAC powered down.
AD5683R/AD5682R/AD5681R/AD5683 Data Sheet
Rev. D | Page 6 of 28
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREF = 2.5 V, VLOGIC= 1.62 V to 5.5 V, −40°C < TA < +105°C, unless otherwise
noted.1
Table 3.
Parameter Typ Max Unit Test Conditions/Comments
Output Voltage Settling Time2, 3 5 7 µs Gain = 1
Slew Rate 0.7 V/µs
Digital-to-Analog Glitch Impulse2 0.1 nV-sec ±1 LSB change around major carry, gain = 2
Digital Feedthrough2 0.1 nV-sec
Total Harmonic Distortion2 −83 dB VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz
Output Noise Spectral Density 200 nV/√Hz DAC code = midscale, 10 kHz
Output Noise 6 µV p-p 0.1 Hz to 10 Hz; internal reference, DAC = zero scale
SNR 90 dB At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
SFDR 88 dB At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
SINAD 82 dB At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
1 Temperature range = −40°C to +105°C, typical at 25°C.
2 See the Terminology section.
3 AD5683R/AD5683 to ±2 LSB, AD5682R to ±1 LSB, AD5681R to ±0.5 LSB.
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V, VLOGIC= 1.62 V to 5.5 V, −40°C < TA < +105°C, unless otherwise noted.
Table 4.
Parameter 1 Symbol
1.62 V ≤ VLOGIC ≤ 2.7 V 2.7 V ≤ VLOGIC2 ≤ 5.5 V Daisy Chain and Readback
Unit
Min Typ Max Min Typ Max Min Typ Max
SCLK Cycle Time
t
1
33
20
40
ns
SCLK High Time t2 16 10 20 ns
SCLK Low Time t3 16 10 20 ns
SYNC to SCLK Falling Edge Setup Time t4 15 10 20 ns
Data Setup Time t5 5 5 5 ns
Data Hold Time t6 5 5 5 ns
SCLK Falling Edge to
SYNC
Rising Edge
t
7
15
10
10
ns
Minimum SYNC High Time t8 20 20 40 ns
SYNC Falling Edge to SCLK Fall Ignore t9 16 10 10 ns
SDO Data Valid from SCLK Rising Edge t10 35 ns
SYNC Rising Edge to SCLK Falling Edge t11 10 ns
SYNC Rising Edge to SDO Disabled t12 60 ns
SYNC Rising Edge to LDAC Falling Edge t13 25 25 25 ns
LDAC Pulse Width Low t14 20 15 15 ns
RESET Minimum Pulse Width Low t15 75 75 75 ns
RESET Pulse Activation Time t16 150 150 150 ns
SYNC Rising Edge to SYNC Rising Edge
(DAC Updates)
t17 1.9 1.7 1.7 µs
LDAC Falling Edge to SYNC Rising Edge t18 1.8 1.65 1.65 µs
Reference Power-Up3 tREF_POWER_UP4 600 600 600 µs
Exit Shutdown3 tSHUTDOWN5 6 6 6 µs
1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2 Substitute VDD for VLOGIC on devices that do not include a VLOGIC pin.
3 Not shown in Figure 4.
4 Same timing must be expected when powering up the device after VDD = 2.7 V.
5 Time required to exit power-down to normal mode of AD5683R/AD5682R/AD5681R operation; SYNC rising edge to 90% of DAC midscale value, with output unloaded.
Data Sheet AD5683R/AD5682R/AD5681R/AD5683
Rev. D | Page 7 of 28
Timing and Circuit Diagrams
DB23 DB22 DB21 DB20 DB2 DB1 DB0
SCLK
SDO
SDI
SYNC
t
7
t
9
t
1
t
2
t
3
t
8
t
5
t
6
DB23 DB22 DB21 DB20 DB2 DB1 DB0
t
10
t
11
t
4
t
14
LDAC
t
12
RESET
t
16
V
OUT
t
13
t
17
t
18
t
15
11955-004
Figure 4. SPI Timing Diagram, Compatible with Mode 1 and Mode 2 (See the AN-1248 Application Note)
200µA I
OL
200µA I
OH
V
OH
(MIN)
TO OUTPUT
PIN C
L
90pF
11955-005
Figure 5. Load Circuit for Digital Output (SDO) Timing Specifications
AD5683R/AD5682R/AD5681R/AD5683 Data Sheet
Rev. D | Page 8 of 28
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter Rating
VDD to GND −0.3 V to +7 V
VLOGIC to GND −0.3 V to +7 V
VOUT to GND −0.3 V to VDD + 0.3 V or +7 V
(whichever is less)
VREF to GND −0.3 V to VDD + 0.3 V or +7 V
(whichever is less)
Digital Input Voltage to GND1 −0.3 V to VDD + 0.3 V or +7 V
(whichever is less)
Operating Temperature Range
Industrial −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 135°C
Power Dissipation (TJ max − TA)/θJA
ESD2 4 kV
FICDM3 1.25 kV
1 Substitute VDD with VLOGIC on devices that include a VLOGIC pin.
2 Human body model (HBM) classification.
3 Field-Induced Charged-Device Model classification.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is defined by the JEDEC JESD51 standard, and the value is
dependent on the test board and test environment.
Table 6. Thermal Resistance1
Package Type θJA θJC Unit
8-Lead LFCSP 90 25 °C/W
10-Lead MSOP 135 N/A °C/W
1 JEDEC 2S2P test board, still air (0 m/sec airflow).
ESD CAUTION
Data Sheet AD5683R/AD5682R/AD5681R/AD5683
Rev. D | Page 9 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
3GND
4SCLK
1V
DD
2LDAC
6SDI
5 SYNC
8V
OUT
7V
REF
AD5681R/
AD5682R/
AD5683R/
AD5683
TOP VIEW
(Not to Scale)
NOTES
1. CONNECT THE EXPOSED PAD TO GND.
11955-006
Figure 6. Pin Configuration, 8-Lead LFCSP, LDAC Option
3GND
4SCLK
1V
DD
2
V
LOGIC
6SDI
5 SYNC
8V
OUT
7V
REF
AD5683R-1/
AD5681R-1
TOP VIEW
(Not to Scale)
NOTES
1. CONNECT THE EXPOSED PAD TO GND.
11955-007
Figure 7. Pin Configuration, 8-Lead LFCSP, VLOGIC Option
3GND
4SCLK
1V
DD
2RESET
6SDI
5SYNC
8V
OUT
7V
REF
AD5683R-2
TOP VIEW
(Not to Scale)
NOTES
1. CONNECT THE EXPOSED PAD TO GND.
11955-008
Figure 8. Pin Configuration, 8-Lead LFCSP, RESET Option
Table 7. Pin Function Descriptions, 8-Lead LFCSP
Pin No.
Mnemonic Description
LDAC VLOGIC RESET
1 1 1 VDD Power Supply Input. These devices can be operated from 2.7 V to 5.5 V. Decouple the supply to GND.
2 N/A N/A
LDAC LDAC can be operated in asynchronous mode (see Figure 4). Pulsing this pin low allows the DAC
register to be updated if the input register has new data. This pin can be tied permanently low; in
this case, the DAC is automatically updated when new data is written to the input register.
N/A 2 N/A VLOGIC Digital Power Supply. Voltage ranges from 1.62 V to 5.5 V.
N/A N/A 2 RESET Asynchronous Reset Input. The RESET input is low level sensitive. When RESET is low, all LDAC pulses
are ignored, the input and DAC registers are at their default values, and the output is connected to
GND. Data written to the AD5683R is ignored. If not used, this pin can be tied to VLOGIC.
3 3 3 GND Ground Reference Point for All Circuitry on the Device.
4 4 4 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates of up to 50 MHz.
5 5 5 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC
goes low, it powers on the SCLK and SDI buffers and enables the input shift register. Data is
transferred in on the falling edges of the next 24 clocks.
6 6 6 SDI Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the
falling edge of the serial clock input.
7 7 7 VREF AD5683R/AD5682R/AD5681R Reference Output. When using the internal reference, this is the
reference output pin. The default for this pin is as a reference output. It is recommended that this
pin be decoupled to GND with a 10 nF capacitor.
8 8 8 VOUT Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.
0 0 0 EPAD Exposed Pad. Connect the exposed pad to GND.
AD5683R/AD5682R/AD5681R/AD5683 Data Sheet
Rev. D | Page 10 of 28
V
DD 1
V
LOGIC 2
RESET
3
LDAC
4
GND
5
V
OUT
10
V
REF
9
SDI
8
SYNC
7
SCLK
6
AD5683R/
AD5681R
TOP VIEW
(Not to Scale)
11955-009
Figure 9. Pin Configuration, 10-Lead MSOP, VLOGIC Option
V
DD 1
RESET
2
SDO
3
LDAC
4
GND
5
V
OUT
10
V
REF
9
SDI
8
SYNC
7
SCLK
6
AD5683R-3
TOP VIEW
(Not to Scale)
11955-010
Figure 10. Pin Configuration, 10-Lead MSOP, SDO Option
Table 8. Pin Function Descriptions, 10-Lead MSOP
VLOGIC SDO Mnemonic Description
1 1 VDD Power Supply Input. These devices can be operated from 2.7 V to 5.5 V. Decouple this pin to GND.
2 N/A VLOGIC Digital Power Supply. Voltage ranges from 1.62 V to 5.5 V. Decouple this pin to GND.
3 2
RESET Hardware Reset Pin. The RESET input is low level sensitive. When RESET is low, the device is reset and
external pins are ignored. The input and DAC registers are loaded with a zero-scale value, and the write
control register is loaded with default values. If not used, tie this pin to VLOGIC.
N/A 3 SDO Serial Data Output. Can be used for daisy chaining or readback commands.
4 4
LDAC Load DAC. Transfers the content of the input register to the DAC register. It can be operated in
asynchronous mode (see Figure 4). This pin can be tied permanently low; in this case, the DAC register is
automatically updated when new data is written to the input register.
5 5 GND Ground Reference.
6 6 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates of up to 50 MHz.
7 7
SYNC Synchronization Data Input. When SYNC goes low, it enables the SCLK and SDI buffers and the input
shift register.
8 8 SDI Serial Data Input. Data is sampled on the falling edge of SCLK.
9 9 VREF Reference Input/Output. When using the internal reference, this is the reference output pin. The default
for this pin is as a reference output. It is recommended that this pin be decoupled to GND with a 10 nF
capacitor.
10 10 VOUT Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.
Data Sheet AD5683R/AD5682R/AD5681R/AD5683
Rev. D | Page 11 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
2
1
0
–1
–2 0
INL (LSB)
CODE 50000 60000 6553540000300002000010000
11955-011
VDD = 5V
TA = 25° C
VREF = 2. 5V
Figure 11. AD5683R/AD5683 INL
2
1
0
–1
–2 0
INL (LSB)
CODE 100008000600040002000 12000 14000 16383
11955-012
VDD = 5V
TA = 25° C
VREF = 2. 5V
Figure 12. AD5682R INL
2.0
1.0
0
–1.0
1.5
0.5
–0.5
–1.5
–2.0 0500 1000 1500 2000 2500 3000 3500 4000
INL (LSB)
CODE
11955-013
VDD = 5V
TA = 25° C
VREF = 2. 5V
Figure 13. AD5681R INL
2
1
0
–1
–2
DNL ( LSB)
CODE
11955-014
050000 60000 65535
4000030000
20000
10000
V
DD
= 5V
T
A
= 25° C
V
REF
= 2. 5V
Figure 14. AD5683R/AD5683 DNL
1.0
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
DNL ( LSB)
CODE
11955-015
0100008000600040002000 12000 14000 16383
V
DD
= 5V
T
A
= 25° C
V
REF
= 2. 5V
Figure 15. AD5682R DNL
1.0
0.6
0
–0.6
0.8
0.2
–0.4
0.4
–0.2
–0.8
–1.0 0500 1000 1500 2000 2500 3000 3500 4000
DNL ( LSB)
CODE
11955-016
VDD = 5V
TA = 25° C
VREF = 2. 5V
Figure 16. AD5681R DNL
AD5683R/AD5682R/AD5681R/AD5683 Data Sheet
Rev. D | Page 12 of 28
1.2
–0.2
0
0.2
0.4
0.6
0.8
1.0
–40 –20 020 40 60 80 105
INL AND DNL E RROR (LSB)
TEMPERATURE (°C)
U1_DNL_INT
U3_DNL_INT
U2_DNL_EXT
U1_INL_INT
U3_INL_INT
U2_INL_EXT
U2_DNL_INT
U1_DNL_EXT
U3_DNL_EXT
U2_INL_INT
U1_INL_EXT
U3_INL_EXT
11955-017
VDD = 5V
VREF = 2. 5V
Figure 17. INL and DNL Error vs. Temperature (AD5683R/AD5683)
1.4
1.2
–0.2
0
0.2
0.4
0.6
0.8
1.0
2.70 3.30 3.75 4.25 4.75 5.25
INL AND DNL E RROR (LSB)
V
DD
(V)
U1_DNL_INT
U3_DNL_INT
U2_DNL_EXT
U1_INL_INT
U3_INL_INT
U2_INL_EXT
U2_DNL_INT
U1_DNL_EXT
U3_DNL_EXT
U2_INL_INT
U1_INL_EXT
U3_INL_EXT
11955-018
T
A
= 25° C
Figure 18. INL and DNL Error vs. Supply Voltage
0.06
–0.04
–0.02
0
0.02
0.04
–40 040 80
TUE ( % FSR)
TEMPERATURE (°C)
U1_EXT
U2_EXT
U3_EXT
U1_INT
U2_INT
U3_INT
V
DD
= 5V
GAIN = 1
V
REF
= 2. 5V
11955-019
Figure 19. TUE vs. Temperature
1.4
1.2
–0.2
0
0.2
0.4
0.6
0.8
1.0
2 3 4 5
INL AND DNL ERROR (LSB)
V
REF
(V)
U1_DNL
U3_DNL
U2_INL
U2_DNL
U1_INL
U3_INL
V
DD
= 5V
T
A
= 25° C
11955-020
Figure 20. INL Error and DNL Error vs. VREF (AD5683R/AD5683)
(AD5682R)
(AD5681R)
0
0
0(AD5683/AD5683R)
10000
2500
50000 12000
3000
60000 16383
4095
65535
8000
2000
40000
6000
1500
30000
4000
1000
20000
2000
500
10000
0.02
–0.04
–0.03
–0.02
–0.01
0
0.01
TUE ( % FSR)
CODE
11955-021
Figure 21. TUE vs. Code
0.04
–0.02
–0.01
0
0.01
0.02
0.03
2.70 3.30 3.75 4.25 4.75 5.25
TUE ( % FSR)
V
DD
(V)
U1_INT
U2_INT
U3_INT
U1_EXT
U2_EXT
U3_EXT
T
A
= 25° C
GAIN = 1
V
REF
= 2. 5V
11955-022
Figure 22. TUE vs. Supply
Data Sheet AD5683R/AD5682R/AD5681R/AD5683
Rev. D | Page 13 of 28
0.03
–0.04
–0.03
–0.02
–0.01
0
0.01
0.02
–40 040 80
ERROR ( % FSR)
TEMPERATURE (°C)
U1_INT
U2_INT
U3_INT
U1_EXT
U2_EXT
U3_EXT
V
DD
= 5V
GAIN = 1
V
REF
= 2. 5V
11955-023
Figure 23. Gain Error and Full-Scale Error vs. Temperature
350
0
50
100
150
200
250
300
ERROR ( µV)
TEMPERATURE (°C) 105
806040200–20–40
U1_INT
U2_INT
U3_INT
U1_EXT
U2_EXT
U3_EXT
V
DD
= 5V
GAIN = 1
V
REF
= 2. 5V
11955-024
Figure 24. Zero Code Error and Offset Error vs. Temperature
V
REF
(V)
TEMPERATURE (°C)60
10–40
2.495
2.497
2.499
2.501
2.503
2.505 U1
U2
U3
11955-025
V
DD
= 5V
Figure 25. Internal Reference Voltage vs. Temperature (Grade B)
2.70 3.30 3.75 4.25 4.75 5.25 5.50
ERROR (% FS R)
V
DD
(V)
–0.025
–0.020
–0.015
–0.010
–0.005
0
0.005
0.010
0.015
0.020
0.025
0.030
U1_INT
U2_INT
U3_INT
U1_EXT
U2_EXT
U3_EXT
T
A
= 25° C
GAIN = 1
V
REF
= 2. 5V
11955-026
Figure 26. Gain Error and Full-Scale Error vs. Supply
2.70 3.30 3.75 4.25 4.75 5.25 5.50
ERROR (µV )
VDD (V)
0
500
400
300
200
100
U1_INT
U2_INT
U3_INT
U1_EXT
U2_EXT
U3_EXT
11955-027
TA = 25° C
GAIN = 1
VREF = 2. 5V
Figure 27. Zero Code Error and Offset Error vs. Supply
NUMBER O F HI TS
VREF (V)
0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
2.50001
2.50004
2.50007
2.50010
2.50013
2.50016
2.50019
2.50022
2.50025
2.50028
2.50031
2.50034
2.50037
2.50040
2.50043
2.50046
2.50049
2.50052
2.50055
2.50058
2.50061
2.50064
2.50067
2.50070
2.50073
2.50076
2.50079
2.50082
2.50085
2.50088
2.50091
2.50094
2.50097
2.50100
VDD = 5V
TA = 25° C
GAI N = 1
11955-028
Figure 28. Reference Output Spread
AD5683R/AD5682R/AD5681R/AD5683 Data Sheet
Rev. D | Page 14 of 28
2.5 5.54.53.5
VREF (V)
VDD (V)
2.49980
2.49985
2.49990
2.49995
2.50000
2.50005
2.50010
2.50015
D11
D12
D13
11955-029
TA = 25°C
Figure 29. Internal Reference Voltage vs. Supply Voltage
CH1 10µV M1.00s A CH1 2.00µV
1
T
11955-030
T
A
= 25°C
V
DD
= 5V
Figure 30. Internal Reference Noise, 0.1 Hz to 10 Hz
CH1 10µV M1.00s A CH1 2.00µV
1
T
11955-031
T
A
= 25°C
V
DD
= 5V
Figure 31. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference On
–0.005 –0.003 –0.001 0.001 0.003 0.005
V
REF
(V)
LOAD CURRENT (A)
2.5003
2.5004
2.5005
2.5006
2.5007
2.5008
2.5009 5.5V
5.0V
3.0V
2.7V
11955-032
T
A
= 25°C
Figure 32. Internal Reference Voltage vs. Load Current
10 100 1k 10k 100k 1M
INTERNAL REFERENCE NSD (nV/√Hz)
FREQUENCY (Hz)
0
200
400
600
800
1000
1200
1400
1600
1800 V
DD
= 5V
T
A
= 25°C
11955-033
Figure 33. Internal Reference Noise Spectral Density vs. Frequency
CH1 10µV M1.00s A CH1 2.00µV
1
T
11955-034
T
A
= 25°C
V
DD
= 5V
Figure 34. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
Data Sheet AD5683R/AD5682R/AD5681R/AD5683
Rev. D | Page 15 of 28
10 100 1k 10k 100k 1M
NSD (nV/√Hz)
FRE QUENCY ( Hz )
0
200
400
600
800
1000
1200 V
DD
= 5V
T
A
= 25° C
GAIN = 1
FULL-SCALE
MIDSCALE
ZEROSCALE
11955-035
Figure 35. Noise Spectral Density vs. Frequency, Gain = 1
–50 050
V
OUT
(V)
LOAD CURRENT ( mA)
–1
0
6
5
4
3
2
1
V
DD
= 5V
T
A
= 25° C
GAIN = 1
0x4000
0xC000
0x0000
0x8000
0xFFFF
11955-036
Figure 36. Source and Sink Capability, Gain = 1
500
450
400
350
300
250
200
150
100
50
0–40 –20 020 40 60 80 105
I
DD
(µA)
TEMPERATURE (°C)
ZS _INT_GAI N = 1
FS _E X T_GAIN = 2
FS _INT_GAI N = 2
ZS _INT_GAI N = 2
FS _INT_GAI N = 1
FS _E X T_GAIN = 1
11955-037
V
DD
= 5V
Figure 37. Supply Current vs. Temperature
1.4
1.0
0.6
0.2
–0.2
–0.6
–1.0
–1.4 00.01 0.02 0.03
ΔV
OUT
(V)
LOAD CURRENT ( A)
SINKING, V
DD
= 3V
SO URCING, V
DD
= 5V
SINKING, V
DD
= 5V
SO URCING, V
DD
= 3V
11955-038
T
A
= 25° C
Figure 38. Headroom/Footroom vs. Load Current
–50 050
V
OUT
(V)
LOAD CURRENT ( mA)
–2
–1
0
7
6
5
4
3
2
1
V
DD
= 5V
T
A
= 25° C
GAIN = 2
0x4000
0xC000
0x0000
0x8000
0xFFFF
11955-039
Figure 39. Source and Sink Capability, Gain = 2
0 7654321
VOUT (V)
TIME (µs)
–0.0025
–0.0020
–0.0015
–0.0010
–0.0005
0
0.0005
0.0010
0.0015
GAIN = 2
GAIN = 1 VDD = 5V
TA = 25° C
REF E RE NCE = 2.5V
CODE = 0x7FFF T O 0x8000
11955-040
Figure 40. Digital-to-Analog Glitch Impulse
AD5683R/AD5682R/AD5681R/AD5683 Data Sheet
Rev. D | Page 16 of 28
00.01 0.02
V
OUT
(V)
TIME (ms)
0
0.5
1.0
1.5
2.0
2.5
V
DD
= 5V
T
A
= 25° C
GAIN = 1
R
L
= 2kΩ
INTERNAL RE FERE NCE = 2.5V
0nF
0.2nF
1nF
4.7nF
10nF
11955-041
Figure 41. Capacitive Load vs. Settling Time, Gain = 1
010 20515
HARMO NIC DI S TO RTI ON (dBV)
FRE QUENCY ( kHz )
–180
–130
–80
–30
20 V
DD
= 5V
T
A
= 25° C
INTERNAL REFERE NCE = 2.5V
11955-042
Figure 42. Total Harmonic Distortion at 1 kHz
0 4 82 6
3 71 5
V
DD
(V)
V
OUT
(V)
TIME (ms)
–1
6
5
4
3
2
1
0
–0.01
0.06
0.05
0.04
0.03
0.02
0.01
0
V
DD
V
OUT
11955-043
Figure 43. Power-On Reset to 0 V
00.01 0.02
V
OUT
(V)
TIME (ms)
0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
V
DD
= 5V
T
A
= 25° C
GAIN = 2
R
L
= 2kΩ
INTERNAL RE FERE NCE = 2.5V
0nF
0.2nF
1nF
4.7nF
10nF
11955-044
Figure 44. Capacitive Load vs. Settling Time, Gain = 2
1k 10k 100k 10M1M
BANDWIDT H ( dB)
FRE QUENCY ( Hz )
–80
–10
–20
–30
–40
–50
–60
–70
0
VDD = 5V
TA = 25° C
VOUT = M IDSCAL E
EXTERNAL REF E RE NCE = 2.5V, ±0.1V p-p
GAIN = 2
GAIN = 1
11955-045
Figure 45. Multiplying Bandwidth, External Reference 2.5 V ± 0.1 V p-p,
10 kHz to 10 MHz
–5 0 5 15
SYNC
10
V
OUT
(V)
TIME (µs)
0
2
1
3
11955-046
MI DS CALE, GAI N = 2
MI DS CALE, GAI N = 1
V
DD
= 5V
T
A
= 25° C
Figure 46. Exiting Power-Down to Midscale
Data Sheet AD5683R/AD5682R/AD5681R/AD5683
Rev. D | Page 17 of 28
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
See Figure 11, Figure 12, and Figure 13 for typical INL vs.
code plots.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. See Figure 14, Figure 15, and Figure 16 for typical DNL
vs. code plots.
Zero Code Error
Zero code error is a measurement of the output error when zero
code (0x0000) is loaded to the DAC register. Ideally, the output
must be 0 V. The zero code error is always positive in the
AD5683R/AD5682R/AD5681R because the output of the DAC
cannot fall below 0 V due to a combination of the offset errors
in the DAC and the output amplifier. Zero code error is expressed
in mV. A plot of zero code error vs. temperature is shown in
Figure 24.
Full-Scale Error
Full-scale error is a measurement of the output error when full-
scale code (0xFFFF) is loaded to the DAC register. Ideally, the
output must be VREF – 1 LSB or |2 × VREF| – 1 LSB. Full-scale error is
expressed in percent of full-scale range (% of FSR). See Figure 23
and Figure 26 for plots of full-scale error.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal expressed as % of FSR.
Zero-Code Error Drift
Zero-code error drift is a measurement of the change in zero-
code error with a change in temperature. It is expressed in µV/°C.
Gain Temperature Coefficient
Gain temperature coefficient is a measurement of the change in
gain error with changes in temperature. It is expressed in ppm
of FSR/°C.
Offset Error
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the
transfer function. Offset error is measured on the AD5683R with
Code 512 loaded in the DAC register. It can be negative or positive.
DC Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for mid-scale output of the DAC. It is measured
in dB. VREF is held at 2 V, and VDD is varied by ±10%.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output of a DAC to settle to a specified level for a ¼ to ¾
scale input change.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec
and is measured when the digital input code is changed by 1 LSB
at the major carry transition (0x7FFF to 0x8000), as shown in
Figure 40.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but it is measured when the DAC output is not updated.
Digital feedthrough is specified in nV-sec and measured with
a full-scale code change on the data bus, that is, from all 0s to all
1s and vice versa.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated. It is expressed in dB.
Output Noise Spectral Density
Noise spectral density is a measurement of the internally generated
random noise. Random noise is characterized as a spectral density
(nV/√Hz). It is measured by loading the DAC to midscale and
measuring noise at the output. It is measured in nV/√Hz. See
Figure 31, Figure 34, and Figure 35 for a plot of noise spectral
density. The noise spectral density for the internal reference is
shown in Figure 30 and Figure 33.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this finite bandwidth.
A sine wave on the reference (with full-scale code loaded to the
DAC) appears on the output. The multiplying bandwidth is the
frequency at which the output amplitude falls to 3 dB below
the input.
Total Harmonic Distortion (THD)
THD is the difference between an ideal sine wave and the
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measurement of the
harmonics present on the DAC output. It is measured in dB.
AD5683R/AD5682R/AD5681R/AD5683 Data Sheet
Rev. D | Page 18 of 28
Voltage Reference Temperature Coefficient (TC)
Voltage reference TC is a measure of the change in the reference
output voltage with a change in temperature. The reference TC
is calculated using the box method, which defines the TC as the
maximum change in the reference output over a given tempera-
ture range expressed in ppm/°C, as follows:
6
10×
×
−
=TempRangeV
VV
TC
REFnom
REFminREFmax
where:
VREFmax is the maximum reference output measured over the
total temperature range.
VREFmin is the minimum reference output measured over the total
temperature range.
VREFnom is the nominal reference output voltage, 2.5 V.
TempRange is the specified temperature range, −40°C to
+105°C.
Thermal Hysteresis
Thermal hysteresis is the voltage difference induced on the
reference voltage by sweeping the temperature from ambient
to cold, to hot, and then back to ambient.
Data Sheet AD5683R/AD5682R/AD5681R/AD5683
Rev. D | Page 19 of 28
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER
The AD5683R/AD5682R/AD5681R are single 16-bit, 14-bit, and
12-bit, serial input, voltage output DACs with a 2.5 V internal
reference. The devices operate from supply voltages of 2.7 V to
5.5 V. Data is written to the AD5683R/AD5682R/AD5681R in
a 24-bit word format via a 3-wire serial interface. The AD5683R/
AD5682R/AD5681R incorporate a power-on reset circuit that
ensures that the DAC output powers up to a zero scale. The devices
also have a software power-down mode that reduces the typical
current consumption to 2 µA maximum.
TRANSFER FUNCTION
The internal reference is on by default. For users that need an
external reference, the AD5683 is available. The input coding to
the DAC is straight binary. The ideal output voltage is given by
the following equations:
For the AD5683R,
VOUT(D) = Gain × VREF ×
536,65
D
For the AD5682R,
VOUT(D) = Gain × VREF ×
384,16
D
For the AD5681R,
VOUT(D) = Gain × VREF ×
4096
D
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register.
Gain is the gain of the output amplifier. By default, it is set to
×1. The gain can also be set to ×2 using the gain bit in the write
control register.
DAC ARCHITECTURE
The AD5683R/AD5682R/AD5681R/AD5683 implements
segmented string DAC architecture with an internal output
buffer. Figure 47 shows the internal block diagram.
INPUT
REGISTER DAC
REGISTER
2.5V
REF
RESISTOR
STRING
REF (+)
REF ( –)
GND
V
OUT
V
REF
11955-047
Figure 47. DAC Channel Architecture Block Diagram
The simplified segmented resistor string DAC structure is
shown in Figure 48. The code loaded to the DAC register
determines the switch on the string that is connected to the
output buffer.
Because each resistance in the string has same value, R, the
string DAC is guaranteed monotonic.
R
R
R
R
RTO OUTPUT
BUFFER
11955-048
VREF
Figure 48. Simplified Resistor String Structure
Internal Reference
The AD5683R/AD5682R/AD5681R on-chip reference is on at
power-up but can be disabled via a write to the write control
register.
The AD5683R/AD5682R/AD5681R each have a 2.5 V, 2 ppm/°C
reference, giving a full-scale output of 2.5 V or 5 V, depending
on the state of the gain bit.
The internal reference is available at the VREF pin. It is internally
buffered and capable of driving external loads of up to 50 mA.
External Reference
The VREF pin is an input pin in the AD5683. It can also be con-
figured as an input pin on the AD5683R/AD5682R/AD5681R,
allowing the use of an external reference if the application
requires it.
In the AD5683R/AD5682R/AD5681R, the default condition of
the on-chip reference is on at power-up. Before connecting an
external reference to the pin, disable the internal reference by
writing to the REF bit (Bit DB16) in the write control register.
AD5683R/AD5682R/AD5681R/AD5683 Data Sheet
Rev. D | Page 20 of 28
Output Buffer
The output buffer is designed as an input/output rail-to-rail,
which gives a maximum output voltage range of up to VDD.
The gain bit sets the segmented string DAC gain to ×1 or ×2,
as shown in Table 12.
The output buffer voltage is determined by VREF, the gain bit,
and the offset and gain errors.
The output buffer can drive a 10 nF capacitance with a 2 kΩ
resistor in parallel, as shown in Figure 41 and Figure 44. If
a higher capacitance load is required, use the snubber method
or a shunt resistor to isolate the load from the output amplifier.
The slew rate is 0.7 V/µs with a ¼ to ¾ scale settling time of 5 µs.
Data Sheet AD5683R/AD5682R/AD5681R/AD5683
Rev. D | Page 21 of 28
SERIAL INTERFACE
The AD5683R/AD5682R/AD5681R/AD5683 uses a 3-wire
serial interface that is compatible with some SPI modes, Mode 1
and Mode 2, as well as with completely synchronous interfaces
such as SPORT. See Figure 4 for a timing diagram of a typical
write sequence. See the AN-1248 Application Note for more
information about the SPI interface.
SPI SERIAL DATA INTERFACE
Pulling low SYNC pin, the internal input shift register is
enabled, the data in the SDI pin is sampled into the input shift
register on the falling edge of SCLK. The SYNC pin must be
held low until the complete data-word (24-bits) is loaded from
the SDI pin (see Figure 4). When SYNC returns high, the serial
data-word is decoded, following the instructions in Table 9.
Between consecutive data-words, SYNC must be held high for a
minimum of 20 ns. Between consecutive DAC updates, SYNC
must be held high for more than 20 ns to satisfy the DAC
update condition as shown in Figure 4.
If SYNC is brought high after 24 falling clock edges, it is interpreted
as a valid write, and the first 24 bits are loaded to the input shift
register.
To minimize power consumption, it is recommended that all
serial interface pins be operated close to the supply rails.
SHORT WRITE OPERATION (AD5681R ONLY)
The AD5681R SPI serial interface allows data to be transferred
using a smaller number of clocks, if required. The last eight bits
are don’t care bits if the input or DAC registers are written as
shown in Table 9. To increase the DAC update rate, the size of
the data-word can be reduced.
If SYNC is brought high between 16 and 24 clock edges, this is
interpreted as a valid write and only the first 16 bits are decoded,
as shown in Figure 49. If SYNC is brought high before 16 falling
clock edges, the serial write is ignored and the write sequence is
considered invalid. If the DCEN bit is enabled, this functionality
is not available (see Table 11).
SDO Pin
The serial data output pin (SDO), which is available only in the
AD5683R, serves two purposes: to read back the contents of the
DAC registers and to connect the device in daisy-chain mode.
The SDO pin contains a push-pull output that internally includes
a weak pull-down resistor. The data is clocked out of SDO on
the rising edge of SCLK, as shown in Figure 4, and the pin is
active only when the DCEN bit is enabled in the write control
register or automatically enabled during a readback command. In
standby mode, the internal pull-down resistor forces a Logic 0 on
the bus. Due to the high value of the internal pull-down resistor,
other devices can have control over the SDO line if a parallel
connection is made.
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X X X X X X X
SDI
S
YNC
SCLK
11955-049
Figure 49. Short Write on the AD5681R
AD5683R/AD5682R/AD5681R/AD5683 Data Sheet
Rev. D | Page 22 of 28
Daisy-Chain Connection
Daisy chaining minimizes the number of pins required from the
controlling IC. As shown in Figure 50, the SDO pin of one package
must be tied to the SDI pin of the next package. The clock period
may need to be increased, as shown in Table 4, because of the
propagation delay of the line between subsequent devices.
By default, the SDO pin is disabled. To enable daisy-chain
operation, the DCEN bit must be set in the write control
register (see Table 10).
When the daisy-chain mode is enabled (DCEN = 1), the
AD5683R/AD5682R/AD5681R/AD5683 accept as a valid
frame any data-word larger than 24 bits, decoding the last
24 bits received, as shown in Figure 51.
MISO
SDI
SCLK
MOSI
SCLK
SDO
SDO
SCLK
SDI
SYNC
SYNC
AD5683R
AD5683R
CONTROLLER
SS
U1
U2
11955-050
Figure 50. Daisy-Chain Connection
SDO_U1
MOSI
SYNC
SCLK 4824
DB23 DB0 DB23 DB0
DB23
INPUT WORD FOR DAC 2UNDEFINED
INPUT WORD FOR DAC 2
DB0
INPUT WORD FOR DAC 1
11955-051
Figure 51. Daisy-Chain Timing Diagram
Data Sheet AD5683R/AD5682R/AD5681R/AD5683
Rev. D | Page 23 of 28
INTERNAL REGISTERS
Input Shift Register
The shift register of the AD5683R/AD5682R/AD5681R/AD5683
is 24 bits wide. Serial data is loaded MSB first (DB23) and the
first four bits are the command bits, C3 to C0, followed by the
data bits.
The data bits comprise a 20-bit, 18-bit, or 16-bit input code,
followed by a number of don’t care bits as shown in Table 9.
The command is decoded on the rising edge of SYNC.
Input Register
The input register acts as a buffer to preload new data. This
register does not control the voltage in the VOUT pin. There are
two different ways to transfer the contents of the input register
to the DAC register: by software or by hardware.
DAC Register
The DAC register controls the voltage in the VOUT pin. This
register can be updated by issuing a command or by
transferring the contents of the input register to the DAC
register.
COMMANDS
Write Input Register
The input register allows the preloading of a new value for the
DAC register. The transfer from the input register to the DAC
register can be triggered by hardware, by the LDAC pin, or by
software using Command 2.
If new data is loaded into the DAC register directly using
Command 3, the DAC register automatically overwrites the
input register.
Update DAC Register
This command transfers the contents of the input register to the
DAC register and, consequently, the VOUT pin is updated.
This operation is equivalent to a software LDAC.
Write DAC Register
The DAC register controls the output voltage in the DAC. This
command updates the DAC register on completion of the write
operation. The input register is refreshed automatically with the
DAC register value.
Table 9. Command Operation
Command
[DB23:DB20] Data Bits [DB19:DB0]1
Operation
C3 C2 C1 C0 DB19 DB18 DB17 DB16 DB15 DB14 [DB13:DB8] DB7 DB6 DB5 DB4 [DB3:DB0]
0 0 0 0 X X X X X X X…X X X X X X…X Do nothing
0 0 0 1 DB15 DB14 DB13 DB12 DB11 DB10 DB9…DB4 DB32 DB22 DB12, 3 DB02, 3 X…X Write input register
0 0 1 0 X X X X X X X…X X X X X X…X Update DAC register
(software LDAC)
0 0 1 1 DB15 DB14 DB13 DB12 DB11 DB10 DB9…DB4 DB32 DB22 DB12, 3 DB02, 3 X…X Write DAC and input
register
0 1 0 0 DB19 DB18 DB17 DB16 DB15 DB14 0…0 0 0 0 0 0…0 Write control register
0 1 0 1 X X X X X X X…X X X X X X…X
Readback input
register
1 X means don’t care.
2 This bit is a don’t care bit for the AD5681R only.
3 This bit is a don’t care bit for the AD5682R only.
AD5683R/AD5682R/AD5681R/AD5683 Data Sheet
Rev. D | Page 24 of 28
Write Control Register
The write control register sets the power-down and gain
functions. It also enables/disables the internal reference and
perform a software reset. See Table 10 for the write control
register functionality.
Table 10. Write Control Register Bits
DB19 DB18 DB17 DB16 DB15 DB14
Reset PD1 PD0 REF Gain DCEN
DCEN Bit
The daisy-chain enable bit (DCEN, Bit DB14) enables the SDO pin,
allowing the device to operate in daisy-chain mode. This bit is
automatically disabled when a readback command is executed.
Enabling this bit disables the write short command feature in the
AD5681R.
Table 11. Daisy-Chain Enable Bit (DCEN)
DB0 Mode
0 Standalone mode (default)
1 DCEN mode
Gain Bit
The gain bit selects the gain of the output amplifier. Table 12
shows how the output voltage range corresponds to the state of
the gain bit.
Table 12. Gain Bit
Gain Output Voltage Range
0 0 V to VREF (default)
1 0 V to 2 × VREF
REF Bit
The on-chip reference is on at power-up by default. This reference
can be turned on or off by setting a software-programmable bit,
DB16, in the write control register. Table 13 shows how the state
of the bit corresponds to the mode of operation.
To reduce the power consumption, it is recommended to
disable the internal reference if the device is placed in power-
down mode.
Table 13. Reference Bit (REF)
REF Reference Function
0 Reference enabled (default)
1 Reference disabled
PD0 and PD1 Bits
The AD5683R/AD5682R/AD5681R contain two separate mode of
operation that are accessed by writing to the write control register.
In normal mode, the output buffer is directly connected to the
VOUT pin.
In power-down mode, the output buffer is internally disabled
and the VOUT pin output impedance can be selected to a well-
known value, as shown in Table 14.
Table 14. Operation Modes
Operating Mode PD1 PD0
Normal Mode 0 0
Power-Down Modes
1 kΩ Output Impedance 0 1
100 kΩ Output Impedance 1 0
Three-State Output Impedance 1 1
In power-down mode, the device disables the output buffer but
does not disable the internal reference. To achieve maximum
power savings, it is recommend to disable the REF bit, if
possible.
Disabling both the internal reference and the output buffer
results in the supply current falling to 2 A at 5 V.
The output stage is shown in Figure 52.
RESISTOR
NETWORK
V
OUT
DAC
POWER-DOWN
CIRCUITRY
AMPLIFIER
11955-052
Figure 52. Output Stage During Power-Down
The output amplifier is shut down when the power-down mode
is activated. However, unless the internal reference is powered
down (using Bit DB16 in the write control register), the bias
generator, reference, and resistor string remain on. When in
power-down mode, the weak SDO resistor is also disconnected.
The supply current falls to 2 A at 5 V. The contents of the DAC
register are unaffected when in power-down mode, and the DAC
register can continue to be updated. The time that is required to
exit power-down is typically 4 µs for VDD = 5 V, or 600 µs if the
reference is disabled.
Reset Bit
The write control register of the AD5683R/AD5682R/AD5681R
contains a software reset function that resets the input and DAC
registers to zero scale and resets the write control register to the
default value. A software reset is initiated by setting the reset bit
(Bit DB19) in the write control register to 1. When the software
reset is complete, the reset bit is cleared to 0 automatically.
Data Sheet AD5683R/AD5682R/AD5681R/AD5683
Rev. D | Page 25 of 28
Readback Input Register
The AD5683R allows readback of the contents of the input
register through the SDO pin by using Command 5 (see Table 9),
as shown in Figure 53.
The SDO pin is automatically enabled for the duration of the
read operation, after which it is disabled again, as shown in
Table 15. If the DCEN bit was enabled before the read operation,
the bit is reset after a readback operation. If the AD5683R was
operating in daisy-chain mode, the user must enable the DCEN
bit again.
Table 15. Write and Readback sequence
SDI SDO Action
0x180000 0x000000 Write 0x8000 to the input register
0x500000 0x000000 Prepare data read from the input register
0x000000 0xX8000X1 Clock out the data
1 X mean don’t care.
HARDWARE LDAC
The DACs of the AD5683R/AD5682R/AD5681R/AD5683 have
a double buffered interface consisting of an input register and a
DAC register. The LDAC transfers data from the input register
to the DAC register and, consequently, the output is updated.
Hold LDAC high while data is clocked into the input shift
register. The DAC output is updated by taking LDAC low after
SYNC is taken high. The output DAC is updated on the falling
edge of LDAC.
If LDAC is pulsed while the data is being clocked, the pulse is
ignored.
HARDWARE RESET
RESET is an active low signal that sets the input and DAC
registers to zero scale and the control registers to their default
values. It is necessary to keep RESET low for 75 ns to complete
the operation. When the RESET signal returns high, the output
remains at the zero scale until a new value is programmed.
While the RESET pin is low, the AD5683R/AD5681R ignore
any new command.
If RESET is held low at power-up, the internal reference is not
initialized correctly until the RESET pin is released.
SYNC
SCLK 24
124
1
DB23 DB0 DB23 DB0
SDI
NOP CONDITION
READBACK COM MAND
DB23 DB0
SDO
DATA
11955-054
Figure 53. Readback Operation
AD5683R/AD5682R/AD5681R/AD5683 Data Sheet
Rev. D | Page 26 of 28
THERMAL HYSTERESIS
Thermal hysteresis is the voltage difference induced on the
reference voltage by sweeping the temperature from ambient
to cold, to hot, and then back to ambient.
The thermal hysteresis data is shown in Figure 54. It is measured by
sweeping the temperature from ambient to −40°C, then to +105°C,
and finally returning to ambient. The VREF delta is next measured
between the two ambient measurements; the result is shown in a
solid line in Figure 54. The same temperature sweep and measure-
ments were immediately repeated; the results are shown in a
patterned line in Figure 54.
6
4
5
3
2
1
0
–100 6020–20–60 400–40–80
NUMBER OF HIT S
DISTORTION (ppm)
FIRST T EMPERATURE SWEEP
SUBSEQUENT…
11955-055
Figure 54. Thermal Hysteresis
POWER-UP SEQUENCE
Because there are diodes to limit the voltage compliance at the
digital pins and analog pins, it is important to power GND first
before applying any voltage to VDD, VOUT, and VLOGIC. Otherwise,
the diode is forward-biased such that VDD is powered uninten-
tionally. The ideal power-up sequence is GND, VDD, VLOGIC,
VREF, followed by the digital inputs.
RECOMMENDED REGULATOR
The AD5683R/AD5682R/AD5681R/AD5683 use a 5 V (VDD)
supply as well as a digital logic supply (VLOGIC).
The analog and digital supplies required for the AD5683R/
AD5682R/AD5681R/AD5683 can be generated using Analog
Devices, Inc., low dropout (LDO) regulators such as the ADP7118
and the ADP162, respectively, for analog and digital supplies.
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful consideration of
the power supply and ground return layout helps to ensure the
rated performance. The printed circuit board (PCB) on which the
ADCs are mounted must be designed such that the AD5683R/
AD5682R/AD5681R/AD5683 lie on the analog plane.
Ensure that the AD5683R/AD5682R/AD5681R/AD5683 have
ample supply bypassing of 10 µF, in parallel with a 0.1 µF capacitor
on each supply that is located as near to the package as possible
(ideally, right up against the device). The 10 µF capacitors are
of the tantalum bead type. The 0.1 µF capacitor must have
low effective series resistance (ESR) and low effective series
inductance (ESI), such as the common ceramic types, which
provide a low impedance path to ground at high frequencies to
handle transient currents due to internal logic switching.
In systems where there are many devices on one board, it is
often useful to provide some heat sinking capability to allow
the power to dissipate easily.
The LFCSP packages of the AD5683R/AD5682R/AD5681R/
AD5683 have an exposed pad beneath the device. Connect this
pad to the GND supply of the device. For optimum performance,
use special consideration when designing the motherboard and
mounting the package. For enhanced thermal, electrical, and
board level performance, solder the exposed pad on the bottom
of the package to the corresponding thermal land pad on the
PCB. Design thermal vias into the PCB land pad area to further
improve heat dissipation.
The GND plane on the device can be increased (as shown in
Figure 55) to provide a natural heat sinking effect.
AD5683R/
AD5682R/
AD5681R/
AD5683
GND
PLANE
BOARD
11955-056
Figure 55. Pad Connection to Board
Data Sheet AD5683R/AD5682R/AD5681R/AD5683
Rev. D | Page 27 of 28
OUTLINE DIMENSIONS
1.70
1.60
1.50
0.425
0.350
0.275
TOP VIEW
8
1
5
4
0.30
0.25
0.20
BOTTOM VIEW
PIN 1 INDEX
AREA
SEATING
PLANE
0.60
0.55
0.50
1.10
1.00
0.90
0.20 REF
0.15 REF
0.05 M AX
0.02 NO M
0.50 BSC
EXPOSED
PAD
PIN 1
INDICATOR
(R 0. 15)
FOR PRO P E R CONNECTI ON OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFI GURAT ION AND
FUNCTION DES CRIPTIONS
SECTION OF THIS DATA SHEET.
01-14-2013-C
2.10
2.00 SQ
1.90
Figure 56. 8-Lead Lead Frame Chip Scale Package [LFCSP_UD]
2.00 mm × 2.00 mm Body, Ultrathin, Dual Lead
(CP-8-10)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
6°
0°
0.70
0.55
0.40
5
10
1
6
0.50 BSC
0.30
0.15
1.10 MAX
3.10
3.00
2.90
COPLANARITY
0.10
0.23
0.13
3.10
3.00
2.90
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
Figure 57. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
AD5683R/AD5682R/AD5681R/AD5683 Data Sheet
Rev. D | Page 28 of 28
ORDERING GUIDE
Model1
Resolution
(Bits) Pinout Temperature Range Performance
Package
Description
Package
Option Branding
AD5683RACPZ-RL7 16 LDAC −40°C to +105°C A Grade 8-Lead LFCSP_UD CP-8-10 94
AD5683RACPZ-1RL7 16 VLOGIC −40°C to +105°C A Grade 8-Lead LFCSP_UD CP-8-10 95
AD5683RACPZ-2RL7 16 RESET −40°C to +105°C A Grade 8-Lead LFCSP_UD CP-8-10 96
AD5683RARMZ 16 VLOGIC −40°C to +105°C A Grade 10-Lead MSOP RM-10 DHY
AD5683RARMZ-RL7 16 VLOGIC −40°C to +105°C A Grade 10-Lead MSOP RM-10 DHY
AD5683RBRMZ 16 VLOGIC −40°C to +105°C B Grade 10-Lead MSOP RM-10 DHZ
AD5683RBRMZ-RL7 16 VLOGIC −40°C to +105°C B Grade 10-Lead MSOP RM-10 DHZ
AD5683RBRMZ-3 16 SDO −40°C to +105°C B Grade 10-Lead MSOP RM-10 DJ0
AD5683RBRMZ-3-RL7 16 SDO −40°C to +105°C B Grade 10-Lead MSOP RM-10 DJ0
AD5683RBCPZ-RL7 16 LDAC −40°C to +105°C B Grade 8-Lead LFCSP_UD CP-8-10 97
AD5683RBCPZ-1RL7
16
V
LOGIC
−40°C to +105°C
B Grade
8-Lead LFCSP_UD
CP-8-10
DX
AD5683BCPZ-RL7 16 LDAC −40°C to +105°C B Grade 8-Lead LFCSP_UD CP-8-10 9A
AD5682RBCPZ-RL7 14 LDAC −40°C to +105°C B Grade 8-Lead LFCSP_UD CP-8-10 9B
AD5681RBCPZ-RL7 12 LDAC −40°C to +105°C B Grade 8-Lead LFCSP_UD CP-8-10 98
AD5681RBCPZ-1RL7 12 VLOGIC −40°C to +105°C B Grade 8-Lead LFCSP_UD CP-8-10 99
AD5681RBRMZ 12 VLOGIC −40°C to +105°C B Grade 10-Lead MSOP RM-10 DHX
AD5681RBRMZ-RL7 12 VLOGIC −40°C to +105°C B Grade 10-Lead MSOP RM-10 DHX
EVAL-AD5683RSDZ Evaluation Board
1 Z = RoHS Compliant Part.
©2013–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11955-0-12/16(D)
