Tiny 16-/14-/12-Bit SPI nanoDAC+, with 2 (16-Bit) LSB INL and 2 ppm/C Reference AD5683R/AD5682R/AD5681R/AD5683 FEATURES FUNCTIONAL BLOCK DIAGRAM Ultrasmall package: 2 mm x 2 mm, 8-lead LFCSP High relative accuracy (INL): 2 LSB maximum at 16 bits AD5683R/AD5682R/AD5681R Low drift, 2.5 V reference: 2 ppm/C typical Selectable span output: 2.5 V or 5 V AD5683 External reference only Selectable span output: VREF or 2 x VREF Total unadjusted error (TUE): 0.06% of FSR maximum Offset error: 1.5 mV maximum Gain error: 0.05% of FSR maximum Low glitch: 0.1 nV-sec High drive capability: 20 mA Low power: 1.2 mW at 3.3 V Independent logic supply: 1.62 V logic compatible Wide operating temperature range: -40C to +105C Robust 4 kV HBM ESD protection VLOGIC* VREF VDD POWER-ON RESET LDAC DAC REGISTER RESET AD5683R/ AD5682R/ AD5681R 2.5V REF REF 16-/14-/12-BIT DAC INPUT CONTROL LOGIC OUTPUT BUFFER POWER-DOWN CONTROL LOGIC VOUT RESISTOR NETWORK *NOT AVAILABLE IN ALL THE MODELS SYNC SCLK SDI SDO* 11955-001 Data Sheet GND Figure 1. AD5683R/AD5682R/AD5681R MSOP (For more information, see the Functional Block Diagrams--LFCSP section.) APPLICATIONS Process controls Data acquisition systems Digital gain and offset adjustment Programmable voltage sources GENERAL DESCRIPTION Table 1. Single-Channel nanoDAC+ Portfolio The AD5683R/AD5682R/AD5681R/AD5683, members of the nanoDAC+(R) family, are low power, single-channel, 16-/14-/12-bit buffered voltage out digital-to-analog converters (DACs). The devices, except the AD5683, include an enabled by default internal 2.5 V reference, offering 2 ppm/C drift. The output span can be programmed to be 0 V to VREF or 0 V to 2 x VREF. All devices operate from a single 2.7 V to 5.5 V supply and are guaranteed monotonic by design. The devices are available in a 2.00 mm x 2.00 mm, 8-lead LFCSP or a 10-lead MSOP. Interface SPI The internal power-on reset circuit ensures that the DAC register is written to zero scale at power-up while the internal output buffer is configured in normal mode. The AD5683R/AD5682R /AD5681R/AD5683 contain a power-down mode that reduces the current consumption of the device to 2 A (maximum) at 5 V and provides software selectable output loads while in powerdown mode. 2. I2 C Reference Internal External Internal External 16-Bit AD5683R AD5683 AD5693R AD5693 14-Bit AD5682R 12-Bit AD5681R AD5692R AD5691R PRODUCT HIGHLIGHTS 1. 3. High Relative Accuracy (INL). AD5683R/AD5683 (16-bit): 2 LSB maximum. Low Drift, 2.5 V On-Chip Reference. 2 ppm/C typical temperature coefficient. 5 ppm/C maximum temperature coefficient. Two Package Options. 2.00 mm x 2.00 mm, 8-lead LFCSP. 10-lead MSOP. The AD5683R/AD5682R/AD5681R/AD5683 use a versatile 3-wire serial interface that operates at clock rates of up to 50 MHz. Some devices also include asynchronous RESET pin and VLOGIC pin options, allowing 1.8 V compatibility. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2013-2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5683R/AD5682R/AD5681R/AD5683 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Digital-to-Analog Converter .................................................... 19 Applications ....................................................................................... 1 Transfer Function ....................................................................... 19 Functional Block Diagram .............................................................. 1 DAC Architecture....................................................................... 19 General Description ......................................................................... 1 Serial Interface ................................................................................ 21 Product Highlights ........................................................................... 1 SPI Serial Data Interface ............................................................ 21 Revision History ............................................................................... 2 Short Write Operation (AD5681R Only) ................................ 21 Functional Block Diagrams--LFCSP............................................. 3 Internal Registers........................................................................ 23 Specifications..................................................................................... 4 Commands .................................................................................. 23 AC Characteristics ........................................................................ 6 Hardware LDAC ......................................................................... 25 Timing Characteristics ................................................................ 6 Hardware RESET ........................................................................ 25 Absolute Maximum Ratings ............................................................ 8 Thermal Hysteresis .................................................................... 26 Thermal Resistance ...................................................................... 8 Power-Up Sequence ................................................................... 26 ESD Caution .................................................................................. 8 Recommended Regulator .......................................................... 26 Pin Configurations and Function Descriptions ........................... 9 Layout Guidelines....................................................................... 26 Typical Performance Characteristics ........................................... 11 Outline Dimensions ....................................................................... 27 Terminology .................................................................................... 17 Ordering Guide .......................................................................... 28 Theory of Operation ...................................................................... 19 REVISION HISTORY 12/2016--Rev. C to Rev. D Changed 1.8 V to 1.62 V, 1.8 V - 10% to 1.62 V, 5 V + 10% to 5.5 V, and 1.8 V VLOGIC 2.7 V to 1.62 V VLOGIC 2.7 V.....Throughout Changes to DC Power Supply Rejection Ratio, PSRR, Test Conditions/Comments Column, Table 2......................................... 4 10/2014--Rev. A to Rev. B Changes to Table 1.............................................................................1 Changes to Figure 14...................................................................... 11 Added Recommended Regulator Section ................................... 26 Changes to Ordering Guide .......................................................... 28 3/2016--Rev. B to Rev. C Changes to Features Section............................................................ 1 Changes to Specifications Section .................................................. 4 Changes to Table 2 ............................................................................ 5 Changes to AC Characteristics Section, Timing Characteristics Section, and Table 4 .......................................................................... 6 Changes to Figure 4 .......................................................................... 7 Changes to Table 7 ............................................................................ 9 Changes to Table 8 .......................................................................... 10 Changes to Terminology Section.................................................. 17 Changes to SPI Serial Data Interface Section ............................. 21 1/2014--Rev. 0 to Rev. A Change to Features Section ..............................................................1 Removed Endnote 2, Endnote 3, Endnote 5, and Endnote 6, Table 2; Renumbered Sequentially ..................................................5 Removed Endnote 2, Table 3; Renumbered Sequentially ............6 Removed Endnote 1, Table 4; Renumbered Sequentially ............6 Changes to Table 5.............................................................................8 Removed Solder Heat Reflow Section and Figure 53; Renumbered Sequentially ............................................................. 25 12/2013--Revision 0: Initial Version Rev. D | Page 2 of 28 Data Sheet AD5683R/AD5682R/AD5681R/AD5683 FUNCTIONAL BLOCK DIAGRAMS--LFCSP VLOGIC* LDAC* VREF VDD POWER-ON RESET DAC REGISTER RESET* AD5683R/ AD5682R/ AD5681R 2.5V REF REF 16-/14-/12-BIT DAC INPUT CONTROL LOGIC OUTPUT BUFFER POWER-DOWN CONTROL LOGIC VOUT RESISTOR NETWORK 11955-002 *NOT AVAILABLE IN ALL THE MODELS GND SYNC SCLK SDI Figure 2. AD5683R/AD5682R/AD5681R LFCSP VREF VDD AD5683 POWER-ON RESET DAC REGISTER REF 16-BIT DAC OUTPUT BUFFER INPUT CONTROL LOGIC POWER-DOWN CONTROL LOGIC SYNC SCLK SDI GND Figure 3. AD5683 LFCSP Rev. D | Page 3 of 28 VOUT RESISTOR NETWORK 11955-003 LDAC* AD5683R/AD5682R/AD5681R/AD5683 Data Sheet SPECIFICATIONS VDD = 2.7 V to 5.5 V, RL = 2 k to GND, CL = 200 pF to GND, VREF = 2.5 V, VLOGIC= 1.62 V to 5.5 V, -40C < TA < +105C, unless otherwise noted. Table 2. Parameter STATIC PERFORMANCE1 AD5683R Resolution Relative Accuracy, INL A Grade B Grade Differential Nonlinearity, DNL AD5683 Resolution Relative Accuracy, INL Differential Nonlinearity, DNL AD5682R Resolution Relative Accuracy, INL Differential Nonlinearity, DNL AD5681R Resolution Relative Accuracy, INL Differential Nonlinearity, DNL Zero-Code Error Offset Error Full-Scale Error Gain Error Total Unadjusted Error, TUE Zero-Code Error Drift Offset Error Drift Gain Temperature Coefficient DC Power Supply Rejection Ratio, PSRR OUTPUT CHARACTERISTICS Output Voltage Range Min Typ Max 16 8 2 3 1 LSB 2 3 1 Bits LSB LSB LSB Gain = 2 Gain =1 Guaranteed monotonic by design 1 1 Bits LSB LSB Guaranteed monotonic by design 14 12 1 1 1.25 1.5 0.075 0.05 0.16 0.14 0.075 0.06 1 1 1 0.2 Capacitive Load Stability VREF 2 x VREF 2 10 Resistive Load Load Regulation 1 Short-Circuit Current Load Impedance at Rails2 20 10 10 30 20 Bits LSB LSB LSB Test Conditions/Comments Gain = 2 Gain = 1 Guaranteed monotonic by design 16 0 0 Unit 50 Bits LSB LSB mV mV % of FSR % of FSR % of FSR % of FSR % of FSR % of FSR V/C V/C ppm/C mV/V V V nF nF k V/mA V/mA mA Rev. D | Page 4 of 28 Guaranteed monotonic by design All 0s loaded to DAC register All 1s loaded to DAC register Internal reference, gain = 1 Internal reference, gain = 2 External reference, gain = 1 External reference, gain = 2 DAC code = midscale; VDD = 5 V Gain = 1 Gain = 2 RL = RL = 2 k CL = 0 F 5 V, DAC code = midscale; -30 mA IOUT +30 mA 3 V, DAC code = midscale; -20 mA IOUT +20 mA Data Sheet Parameter REFERENCE OUTPUT Output Voltage Voltage Reference TC3 A-Grade B-Grade Output Impedance Output Voltage Noise Output Voltage Noise Density Capacitive Load Stability Load Regulation Sourcing Load Regulation Sinking Output Current Load Capability Line Regulation Thermal Hysteresis AD5683R/AD5682R/AD5681R/AD5683 Min 2.4975 5 2 0.05 16.5 250 5 50 30 5 80 125 25 REFERENCE INPUT Reference Current Reference Input Range Reference Input Impedance LOGIC INPUTS IIN, Input Current VINL, Input Low Voltage4 VINH, Input High Voltage4 CIN, Pin Capacitance LOGIC OUTPUTS (SDO)5 Output Low Voltage, VOL Output High Voltage, VOH Pin Capacitance POWER REQUIREMENTS VLOGIC5 ILOGIC5 VDD IDD6 Normal Mode7 Power-Down Modes8 Typ Max Unit Test Conditions/Comments 2.5025 V At ambient See the Terminology section 20 5 ppm/C ppm/C V p-p nV/Hz F V/mA V/mA mA V/V ppm ppm 26 47 1 VDD 120 60 Per pin 0.4 V V pF ISINK = 200 A ISOURCE = 200 A 5.5 3 5.5 5.5 V A V V 500 180 2 A A A VDD - 0.4 4 2.7 VREF + 1.5 350 110 Gain = 1 Gain = 2 A V V pF 2 0.25 VREF = VDD = VLOGIC = 5 V, gain = 1 VREF = VDD = VLOGIC = 5 V, gain = 2 1 0.3 x VDD 0.7 x VDD 1.62 A A V k k 0.1 Hz to 10 Hz At ambient; f = 10 kHz, CL = 10 nF RL = 2 k At ambient; VDD 3 V At ambient VDD 3 V At ambient First cycle Additional cycles VIH = VLOGIC or VIL = GND Gain = 1 Gain = 2 VIH = VDD, VIL = GND Internal reference enabled Internal reference disabled Linearity is calculated using a reduced code range: AD5683R and AD5683 (Code 512 to Code 65,535); AD5682R (Code 128 to Code 16,384); AD5681R (Code 32 to Code 4096). Output unloaded. When drawing a load current at either rail, the output voltage headroom, with respect to that rail, is limited by the 20 typical channel resistance of the output devices; for example, when sinking 1 mA, the minimum output voltage = 20 , 1 mA generates 20 mV. See Figure 38 (Headroom/Footroom vs. Load Current). 3 Reference temperature coefficient is calculated as per the box method. See the Terminology section for more information. 4 Substitute VLOGIC for VDD if device includes a VLOGIC pin. 5 The VLOGIC and SDO pins are not available on all models. 6 If the VLOGIC pin is not available, IDD = IDD + ILOGIC. 7 Interface inactive. DAC active. DAC output unloaded. 8 DAC powered down. 1 2 Rev. D | Page 5 of 28 AD5683R/AD5682R/AD5681R/AD5683 Data Sheet AC CHARACTERISTICS VDD = 2.7 V to 5.5 V, RL = 2 k to GND, CL = 200 pF to GND, VREF = 2.5 V, VLOGIC= 1.62 V to 5.5 V, -40C < TA < +105C, unless otherwise noted.1 Table 3. Parameter Output Voltage Settling Time2, 3 Slew Rate Digital-to-Analog Glitch Impulse2 Digital Feedthrough2 Total Harmonic Distortion2 Output Noise Spectral Density Output Noise SNR SFDR SINAD Typ 5 0.7 0.1 0.1 -83 200 6 90 88 82 Max 7 Unit s V/s nV-sec nV-sec dB nV/Hz V p-p dB dB dB Test Conditions/Comments Gain = 1 1 LSB change around major carry, gain = 2 VREF = 2 V 0.1 V p-p, frequency = 10 kHz DAC code = midscale, 10 kHz 0.1 Hz to 10 Hz; internal reference, DAC = zero scale At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz Temperature range = -40C to +105C, typical at 25C. See the Terminology section. 3 AD5683R/AD5683 to 2 LSB, AD5682R to 1 LSB, AD5681R to 0.5 LSB. 1 2 TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V, VLOGIC= 1.62 V to 5.5 V, -40C < TA < +105C, unless otherwise noted. Table 4. Parameter SCLK Cycle Time SCLK High Time SCLK Low Time SYNC to SCLK Falling Edge Setup Time Data Setup Time Data Hold Time SCLK Falling Edge to SYNC Rising Edge Minimum SYNC High Time SYNC Falling Edge to SCLK Fall Ignore SDO Data Valid from SCLK Rising Edge SYNC Rising Edge to SCLK Falling Edge SYNC Rising Edge to SDO Disabled SYNC Rising Edge to LDAC Falling Edge LDAC Pulse Width Low RESET Minimum Pulse Width Low RESET Pulse Activation Time SYNC Rising Edge to SYNC Rising Edge (DAC Updates) LDAC Falling Edge to SYNC Rising Edge Reference Power-Up3 Exit Shutdown3 1 Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 1.62 V VLOGIC 2.7 V Min Typ Max 33 16 16 15 5 5 15 20 16 2.7 V VLOGIC2 5.5 V Min Typ Max 20 10 10 10 5 5 10 20 10 25 20 75 150 1.9 25 15 75 150 1.7 t18 1.8 tREF_POWER_UP4 tSHUTDOWN5 1.65 600 1.65 600 6 Daisy Chain and Readback Min Typ Max 40 20 20 20 5 5 10 40 10 35 10 60 25 15 75 150 1.7 600 6 6 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s s s All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Substitute VDD for VLOGIC on devices that do not include a VLOGIC pin. Not shown in Figure 4. 4 Same timing must be expected when powering up the device after VDD = 2.7 V. 5 Time required to exit power-down to normal mode of AD5683R/AD5682R/AD5681R operation; SYNC rising edge to 90% of DAC midscale value, with output unloaded. 1 2 3 Rev. D | Page 6 of 28 Data Sheet AD5683R/AD5682R/AD5681R/AD5683 Timing and Circuit Diagrams t4 t9 t7 t1 t2 SCLK t11 t3 t8 t17 SYNC t5 t6 SDI DB23 DB22 DB21 DB20 SDO DB23 DB22 DB21 DB20 DB2 DB1 DB0 t12 t10 DB2 DB1 DB0 t13 t14 t18 LDAC t15 RESET 11955-004 t16 VOUT Figure 4. SPI Timing Diagram, Compatible with Mode 1 and Mode 2 (See the AN-1248 Application Note) 200A VOH (MIN) CL 90pF 200A IOH 11955-005 TO OUTPUT PIN IOL Figure 5. Load Circuit for Digital Output (SDO) Timing Specifications Rev. D | Page 7 of 28 AD5683R/AD5682R/AD5681R/AD5683 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 5. Parameter VDD to GND VLOGIC to GND VOUT to GND VREF to GND Digital Input Voltage to GND1 Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ max) Power Dissipation ESD2 FICDM3 Rating -0.3 V to +7 V -0.3 V to +7 V -0.3 V to VDD + 0.3 V or +7 V (whichever is less) -0.3 V to VDD + 0.3 V or +7 V (whichever is less) -0.3 V to VDD + 0.3 V or +7 V (whichever is less) -40C to +105C -65C to +150C 135C (TJ max - TA)/JA 4 kV 1.25 kV Substitute VDD with VLOGIC on devices that include a VLOGIC pin. Human body model (HBM) classification. 3 Field-Induced Charged-Device Model classification. 1 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE JA is defined by the JEDEC JESD51 standard, and the value is dependent on the test board and test environment. Table 6. Thermal Resistance1 Package Type 8-Lead LFCSP 10-Lead MSOP 1 JA 90 135 JEDEC 2S2P test board, still air (0 m/sec airflow). ESD CAUTION 2 Rev. D | Page 8 of 28 JC 25 N/A Unit C/W C/W Data Sheet AD5683R/AD5682R/AD5681R/AD5683 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS LDAC 2 GND 3 SCLK 4 AD5681R/ AD5682R/ AD5683R/ AD5683 TOP VIEW (Not to Scale) 8 VOUT 7 VREF 6 SDI 5 SYNC NOTES 1. CONNECT THE EXPOSED PAD TO GND. 11955-006 VDD 1 Figure 6. Pin Configuration, 8-Lead LFCSP, LDAC Option VDD 1 GND 3 SCLK 4 AD5683R-1/ AD5681R-1 TOP VIEW (Not to Scale) 7 VREF 6 SDI 5 SYNC NOTES 1. CONNECT THE EXPOSED PAD TO GND. 11955-007 VLOGIC 2 8 VOUT Figure 7. Pin Configuration, 8-Lead LFCSP, VLOGIC Option VDD 1 GND 3 SCLK 4 AD5683R-2 TOP VIEW (Not to Scale) 7 VREF 6 SDI 5 SYNC NOTES 1. CONNECT THE EXPOSED PAD TO GND. 11955-008 RESET 2 8 VOUT Figure 8. Pin Configuration, 8-Lead LFCSP, RESET Option Table 7. Pin Function Descriptions, 8-Lead LFCSP Pin No. LDAC RESET 1 2 VLOGIC 1 N/A 1 N/A Mnemonic VDD LDAC N/A N/A 2 N/A N/A 2 VLOGIC RESET 3 4 3 4 3 4 GND SCLK 5 5 5 SYNC 6 6 6 SDI 7 7 7 VREF 8 0 8 0 8 0 VOUT EPAD Description Power Supply Input. These devices can be operated from 2.7 V to 5.5 V. Decouple the supply to GND. LDAC can be operated in asynchronous mode (see Figure 4). Pulsing this pin low allows the DAC register to be updated if the input register has new data. This pin can be tied permanently low; in this case, the DAC is automatically updated when new data is written to the input register. Digital Power Supply. Voltage ranges from 1.62 V to 5.5 V. Asynchronous Reset Input. The RESET input is low level sensitive. When RESET is low, all LDAC pulses are ignored, the input and DAC registers are at their default values, and the output is connected to GND. Data written to the AD5683R is ignored. If not used, this pin can be tied to VLOGIC. Ground Reference Point for All Circuitry on the Device. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and SDI buffers and enables the input shift register. Data is transferred in on the falling edges of the next 24 clocks. Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. AD5683R/AD5682R/AD5681R Reference Output. When using the internal reference, this is the reference output pin. The default for this pin is as a reference output. It is recommended that this pin be decoupled to GND with a 10 nF capacitor. Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation. Exposed Pad. Connect the exposed pad to GND. Rev. D | Page 9 of 28 AD5683R/AD5682R/AD5681R/AD5683 LDAC 4 TOP VIEW (Not to Scale) GND 5 10 VOUT VDD 1 9 VREF RESET 2 8 SDI 7 SYNC 6 SCLK SDO 3 LDAC 4 GND 5 10 VOUT AD5683R-3 TOP VIEW (Not to Scale) 9 VREF 8 SDI 7 SYNC 6 SCLK 11955-010 RESET 3 AD5683R/ AD5681R 11955-009 VDD 1 VLOGIC 2 Data Sheet Figure 10. Pin Configuration, 10-Lead MSOP, SDO Option Figure 9. Pin Configuration, 10-Lead MSOP, VLOGIC Option Table 8. Pin Function Descriptions, 10-Lead MSOP VLOGIC 1 2 3 SDO 1 N/A 2 Mnemonic VDD VLOGIC RESET N/A 4 3 4 SDO LDAC 5 6 5 6 GND SCLK 7 7 SYNC 8 9 8 9 SDI VREF 10 10 VOUT Description Power Supply Input. These devices can be operated from 2.7 V to 5.5 V. Decouple this pin to GND. Digital Power Supply. Voltage ranges from 1.62 V to 5.5 V. Decouple this pin to GND. Hardware Reset Pin. The RESET input is low level sensitive. When RESET is low, the device is reset and external pins are ignored. The input and DAC registers are loaded with a zero-scale value, and the write control register is loaded with default values. If not used, tie this pin to VLOGIC. Serial Data Output. Can be used for daisy chaining or readback commands. Load DAC. Transfers the content of the input register to the DAC register. It can be operated in asynchronous mode (see Figure 4). This pin can be tied permanently low; in this case, the DAC register is automatically updated when new data is written to the input register. Ground Reference. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. Synchronization Data Input. When SYNC goes low, it enables the SCLK and SDI buffers and the input shift register. Serial Data Input. Data is sampled on the falling edge of SCLK. Reference Input/Output. When using the internal reference, this is the reference output pin. The default for this pin is as a reference output. It is recommended that this pin be decoupled to GND with a 10 nF capacitor. Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation. Rev. D | Page 10 of 28 Data Sheet AD5683R/AD5682R/AD5681R/AD5683 TYPICAL PERFORMANCE CHARACTERISTICS 2 2 VDD = 5V TA = 25C VREF = 2.5V 1 DNL (LSB) 1 0 0 -1 -1 10000 0 20000 30000 40000 50000 60000 65535 CODE -2 11955-011 -2 0 30000 40000 50000 60000 65535 CODE Figure 11. AD5683R/AD5683 INL 2 20000 10000 11955-014 INL (LSB) VDD = 5V TA = 25C VREF = 2.5V Figure 14. AD5683R/AD5683 DNL 1.0 VDD = 5V TA = 25C VREF = 2.5V VDD = 5V 0.8 TA = 25C VREF = 2.5V 0.6 1 DNL (LSB) INL (LSB) 0.4 0 0.2 0 -0.2 -0.4 -1 -0.6 2000 4000 6000 8000 10000 12000 14000 16383 CODE -1.0 11955-012 0 0 2000 4000 6000 8000 10000 12000 14000 16383 CODE Figure 12. AD5682R INL 11955-015 -0.8 -2 Figure 15. AD5682R DNL 2.0 1.0 VDD = 5V TA = 25C 1.5 V REF = 2.5V VDD = 5V 0.8 TA = 25C VREF = 2.5V 0.6 1.0 0.4 DNL (LSB) 0 -0.5 0.2 0 -0.2 -0.4 -1.0 -0.6 -1.5 0 500 1000 1500 2000 2500 CODE 3000 3500 4000 Figure 13. AD5681R INL -1.0 0 500 1000 1500 2000 2500 CODE Figure 16. AD5681R DNL Rev. D | Page 11 of 28 3000 3500 4000 11955-016 -0.8 -2.0 11955-013 INL (LSB) 0.5 AD5683R/AD5682R/AD5681R/AD5683 1.4 VDD = 5V VREF = 2.5V 1.2 INL AND DNL ERROR (LSB) INL AND DNL ERROR (LSB) 1.0 0.8 0.6 U1_DNL_INT U3_DNL_INT U2_DNL_EXT U1_INL_INT U3_INL_INT U2_INL_EXT 0.4 0.2 U2_DNL_INT U1_DNL_EXT U3_DNL_EXT U2_INL_INT U1_INL_EXT U3_INL_EXT VDD = 5V TA = 25C U2_DNL U1_INL U3_INL 1.0 0.8 0.6 0.4 0.2 0 0 -40 -20 0 20 40 60 80 105 TEMPERATURE (C) -0.2 11955-017 -0.2 2 3 4 5 VREF (V) Figure 17. INL and DNL Error vs. Temperature (AD5683R/AD5683) Figure 20. INL Error and DNL Error vs. VREF (AD5683R/AD5683) 0.02 1.4 U1_DNL_INT U3_DNL_INT U2_DNL_EXT U1_INL_INT U3_INL_INT U2_INL_EXT 1.2 1.0 U2_DNL_INT U1_DNL_EXT U3_DNL_EXT U2_INL_INT U1_INL_EXT U3_INL_EXT TA = 25C 0.01 0 TUE (% FSR) INL AND DNL ERROR (LSB) U1_DNL U3_DNL U2_INL 11955-020 1.2 Data Sheet 0.8 0.6 -0.01 -0.02 0.4 -0.03 0.2 10000 2000 500 0 0 0 2.70 3.30 3.75 4.25 4.75 5.25 VDD (V) 30000 40000 6000 8000 1500 2000 CODE 50000 10000 2500 60000 65535 (AD5683/AD5683R) 12000 16383 (AD5682R) 3000 4095 (AD5681R) 11955-018 -0.2 20000 4000 1000 Figure 18. INL and DNL Error vs. Supply Voltage Figure 21. TUE vs. Code 0.04 0.06 VDD = 5V GAIN = 1 VREF = 2.5V U1_EXT U2_EXT U3_EXT U1_INT U2_INT U3_INT 0.04 TA = 25C GAIN = 1 VREF = 2.5V 0.03 TUE (% FSR) TUE (% FSR) 0.02 0.02 0 0.01 0 -0.02 -0.01 -40 0 40 TEMPERATURE (C) 80 U1_EXT U2_EXT U3_EXT -0.02 2.70 3.30 3.75 4.25 4.75 VDD (V) Figure 22. TUE vs. Supply Figure 19. TUE vs. Temperature Rev. D | Page 12 of 28 5.25 11955-022 -0.04 11955-019 U1_INT U2_INT U3_INT 11955-021 -0.04 0 Data Sheet AD5683R/AD5682R/AD5681R/AD5683 0.030 0.03 TA = 25C GAIN = 1 VREF = 2.5V 0.025 0.02 0.020 0.015 ERROR (% FSR) 0 -0.01 U1_INT U2_INT U3_INT U1_EXT U2_EXT U3_EXT -0.03 -0.04 -40 0.010 0.005 0 -0.005 -0.010 -0.015 VDD = 5V GAIN = 1 VREF = 2.5V 0 40 80 TEMPERATURE (C) -0.025 2.70 4.25 4.75 5.25 5.50 500 VDD = 5V GAIN = 1 VREF = 2.5V U1_INT U2_INT U3_INT U1_EXT U2_EXT U3_EXT 400 ERROR (V) 250 200 150 U1_INT U2_INT U3_INT U1_EXT U2_EXT U3_EXT 50 0 -40 -20 0 20 40 60 80 105 TEMPERATURE (C) 300 200 100 0 2.70 3.30 3.75 4.25 4.75 5.25 5.50 VDD (V) Figure 24. Zero Code Error and Offset Error vs. Temperature Figure 27. Zero Code Error and Offset Error vs. Supply 2.505 4.5 VDD = 5V U1 U2 U3 TA = 25C GAIN = 1 VREF = 2.5V 11955-027 100 11955-024 4.0 2.503 VDD = 5V TA = 25C GAIN = 1 NUMBER OF HITS 3.5 2.501 2.499 3.0 2.5 2.0 1.5 1.0 2.497 0 10 60 TEMPERATURE (C) 11955-025 2.495 -40 Figure 25. Internal Reference Voltage vs. Temperature (Grade B) VREF (V) Figure 28. Reference Output Spread Rev. D | Page 13 of 28 11955-028 0.5 2.50001 2.50004 2.50007 2.50010 2.50013 2.50016 2.50019 2.50022 2.50025 2.50028 2.50031 2.50034 2.50037 2.50040 2.50043 2.50046 2.50049 2.50052 2.50055 2.50058 2.50061 2.50064 2.50067 2.50070 2.50073 2.50076 2.50079 2.50082 2.50085 2.50088 2.50091 2.50094 2.50097 2.50100 ERROR (V) 3.75 Figure 26. Gain Error and Full-Scale Error vs. Supply 350 VREF (V) 3.30 U1_EXT U2_EXT U3_EXT VDD (V) Figure 23. Gain Error and Full-Scale Error vs. Temperature 300 U1_INT U2_INT U3_INT -0.020 11955-026 -0.02 11955-023 ERROR (% FSR) 0.01 AD5683R/AD5682R/AD5681R/AD5683 Data Sheet 2.50015 2.5009 TA = 25C 5.5V 5.0V 3.0V 2.7V TA = 25C 2.50010 2.5008 2.50005 VREF (V) 2.49995 2.5006 2.5005 2.49990 D11 2.49985 2.5004 D12 4.5 5.5 2.5003 -0.005 VDD (V) -0.003 -0.001 0.001 0.003 Figure 29. Internal Reference Voltage vs. Supply Voltage Figure 32. Internal Reference Voltage vs. Load Current 1800 TA = 25C VDD = 5V INTERNAL REFERENCE NSD (nV/Hz) T M1.00s A CH1 2.00V VDD = 5V TA = 25C 1600 1400 1200 1000 800 600 400 200 11955-030 1 CH1 10V 0.005 LOAD CURRENT (A) 0 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 30. Internal Reference Noise, 0.1 Hz to 10 Hz Figure 33. Internal Reference Noise Spectral Density vs. Frequency T T TA = 25C VDD = 5V TA = 25C VDD = 5V CH1 10V M1.00s A CH1 2.00V CH1 10V M1.00s A CH1 2.00V 11955-034 1 1 Figure 34. 0.1 Hz to 10 Hz Output Noise Plot, External Reference Figure 31. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference On Rev. D | Page 14 of 28 11955-033 3.5 11955-032 D13 11955-029 2.49980 2.5 11955-031 VREF (V) 2.5007 2.50000 Data Sheet AD5683R/AD5682R/AD5681R/AD5683 1200 1.4 VDD = 5V TA = 25C GAIN = 1 FULL-SCALE MIDSCALE ZEROSCALE 1000 TA = 25C SINKING, VDD = 3V SOURCING, VDD = 5V SINKING, VDD = 5V SOURCING, VDD = 3V 1.0 0.6 VOUT (V) NSD (nV/Hz) 800 600 0.2 -0.2 400 -0.6 200 100 1k 10k 100k 1M FREQUENCY (Hz) -1.4 11955-035 0 10 0 0.01 Figure 35. Noise Spectral Density vs. Frequency, Gain = 1 6 5 0.03 Figure 38. Headroom/Footroom vs. Load Current 7 VDD = 5V TA = 25C GAIN = 1 0xFFFF 0xC000 0x8000 0x4000 0x0000 0.02 LOAD CURRENT (A) 11955-038 -1.0 VDD = 5V TA = 25C GAIN = 2 0xFFFF 0xC000 0x8000 0x4000 0x0000 6 5 4 VOUT (V) VOUT (V) 4 3 2 3 2 1 1 0 0 0 50 LOAD CURRENT (mA) -2 -50 11955-036 -1 -50 50 LOAD CURRENT (mA) Figure 36. Source and Sink Capability, Gain = 1 500 0 11955-039 -1 Figure 39. Source and Sink Capability, Gain = 2 0.0015 VDD = 5V 450 GAIN = 1 GAIN = 2 VDD = 5V TA = 25C REFERENCE = 2.5V CODE = 0x7FFF TO 0x8000 0.0010 400 0.0005 350 0 250 VOUT (V) ZS_INT_GAIN = 1 FS_EXT_GAIN = 2 FS_INT_GAIN = 2 ZS_INT_GAIN = 2 FS_INT_GAIN = 1 FS_EXT_GAIN = 1 200 -0.0005 -0.0010 150 -0.0015 100 0 -40 -20 0 20 40 60 80 TEMPERATURE (C) 105 Figure 37. Supply Current vs. Temperature -0.0025 0 1 2 3 4 5 TIME (s) Figure 40. Digital-to-Analog Glitch Impulse Rev. D | Page 15 of 28 6 7 11955-040 -0.0020 50 11955-037 IDD (A) 300 AD5683R/AD5682R/AD5681R/AD5683 Data Sheet 2.5 4.5 0nF 0.2nF 1nF 4.7nF 10nF 2.0 0nF 0.2nF 1nF 4.7nF 10nF 4.0 3.5 3.0 VOUT (V) VOUT (V) 1.5 1.0 2.5 2.0 1.5 0 0.01 0.02 TIME (ms) 0.5 0 11955-041 0 0 0.02 Figure 44. Capacitive Load vs. Settling Time, Gain = 2 0 20 VDD = 5V TA = 25C INTERNAL REFERENCE = 2.5V GAIN = 2 GAIN = 1 -10 -20 -30 BANDWIDTH (dB) -80 -30 -40 -50 -60 -70 VDD = 5V TA = 25C VOUT = MIDSCALE EXTERNAL REFERENCE = 2.5V, 0.1V p-p -80 0 5 10 15 20 FREQUENCY (kHz) 1k 11955-042 -180 10k 100k 1M 10M FREQUENCY (Hz) Figure 45. Multiplying Bandwidth, External Reference 2.5 V 0.1 V p-p, 10 kHz to 10 MHz Figure 42. Total Harmonic Distortion at 1 kHz 6 0.06 5 0.05 3 VDD = 5V TA = 25C MIDSCALE, GAIN = 2 0.04 4 2 0.03 2 0.02 1 0.01 VOUT (V) 3 VOUT (V) VDD SYNC MIDSCALE, GAIN = 1 1 VOUT -0.01 -1 0 1 2 3 4 5 6 TIME (ms) 7 8 11955-043 0 0 0 -5 0 5 10 TIME (s) Figure 46. Exiting Power-Down to Midscale Figure 43. Power-On Reset to 0 V Rev. D | Page 16 of 28 15 11955-045 -130 11955-046 HARMONIC DISTORTION (dBV) 0.01 TIME (ms) Figure 41. Capacitive Load vs. Settling Time, Gain = 1 VDD (V) VDD = 5V TA = 25C GAIN = 2 RL = 2k INTERNAL REFERENCE = 2.5V 1.0 11955-044 VDD = 5V TA = 25C GAIN = 1 RL = 2k INTERNAL REFERENCE = 2.5V 0.5 Data Sheet AD5683R/AD5682R/AD5681R/AD5683 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. See Figure 11, Figure 12, and Figure 13 for typical INL vs. code plots. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. See Figure 14, Figure 15, and Figure 16 for typical DNL vs. code plots. Zero Code Error Zero code error is a measurement of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output must be 0 V. The zero code error is always positive in the AD5683R/AD5682R/AD5681R because the output of the DAC cannot fall below 0 V due to a combination of the offset errors in the DAC and the output amplifier. Zero code error is expressed in mV. A plot of zero code error vs. temperature is shown in Figure 24. Full-Scale Error Full-scale error is a measurement of the output error when fullscale code (0xFFFF) is loaded to the DAC register. Ideally, the output must be VREF - 1 LSB or |2 x VREF| - 1 LSB. Full-scale error is expressed in percent of full-scale range (% of FSR). See Figure 23 and Figure 26 for plots of full-scale error. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal expressed as % of FSR. Zero-Code Error Drift Zero-code error drift is a measurement of the change in zerocode error with a change in temperature. It is expressed in V/C. Gain Temperature Coefficient Gain temperature coefficient is a measurement of the change in gain error with changes in temperature. It is expressed in ppm of FSR/C. Offset Error Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal) expressed in mV in the linear region of the transfer function. Offset error is measured on the AD5683R with Code 512 loaded in the DAC register. It can be negative or positive. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output of a DAC to settle to a specified level for a 1/4 to 3/4 scale input change. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-sec and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000), as shown in Figure 40. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but it is measured when the DAC output is not updated. Digital feedthrough is specified in nV-sec and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. Reference Feedthrough Reference feedthrough is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated. It is expressed in dB. Output Noise Spectral Density Noise spectral density is a measurement of the internally generated random noise. Random noise is characterized as a spectral density (nV/Hz). It is measured by loading the DAC to midscale and measuring noise at the output. It is measured in nV/Hz. See Figure 31, Figure 34, and Figure 35 for a plot of noise spectral density. The noise spectral density for the internal reference is shown in Figure 30 and Figure 33. Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this finite bandwidth. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Total Harmonic Distortion (THD) THD is the difference between an ideal sine wave and the attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measurement of the harmonics present on the DAC output. It is measured in dB. DC Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for mid-scale output of the DAC. It is measured in dB. VREF is held at 2 V, and VDD is varied by 10%. Rev. D | Page 17 of 28 AD5683R/AD5682R/AD5681R/AD5683 Data Sheet Voltage Reference Temperature Coefficient (TC) Voltage reference TC is a measure of the change in the reference output voltage with a change in temperature. The reference TC is calculated using the box method, which defines the TC as the maximum change in the reference output over a given temperature range expressed in ppm/C, as follows: Thermal Hysteresis Thermal hysteresis is the voltage difference induced on the reference voltage by sweeping the temperature from ambient to cold, to hot, and then back to ambient. VREFmax - VREFmin 6 TC = x 10 VREFnom x TempRange where: VREFmax is the maximum reference output measured over the total temperature range. VREFmin is the minimum reference output measured over the total temperature range. VREFnom is the nominal reference output voltage, 2.5 V. TempRange is the specified temperature range, -40C to +105C. Rev. D | Page 18 of 28 Data Sheet AD5683R/AD5682R/AD5681R/AD5683 THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER The AD5683R/AD5682R/AD5681R are single 16-bit, 14-bit, and 12-bit, serial input, voltage output DACs with a 2.5 V internal reference. The devices operate from supply voltages of 2.7 V to 5.5 V. Data is written to the AD5683R/AD5682R/AD5681R in a 24-bit word format via a 3-wire serial interface. The AD5683R/ AD5682R/AD5681R incorporate a power-on reset circuit that ensures that the DAC output powers up to a zero scale. The devices also have a software power-down mode that reduces the typical current consumption to 2 A maximum. The simplified segmented resistor string DAC structure is shown in Figure 48. The code loaded to the DAC register determines the switch on the string that is connected to the output buffer. Because each resistance in the string has same value, R, the string DAC is guaranteed monotonic. VREF R R TRANSFER FUNCTION The internal reference is on by default. For users that need an external reference, the AD5683 is available. The input coding to the DAC is straight binary. The ideal output voltage is given by the following equations: R TO OUTPUT BUFFER For the AD5683R, VOUT(D) = Gain x VREF x D 65,536 R For the AD5682R, VOUT(D) = Gain x VREF x 11955-048 R D 16,384 Figure 48. Simplified Resistor String Structure For the AD5681R, Internal Reference VOUT(D) = Gain x VREF x D 4096 where: D is the decimal equivalent of the binary code that is loaded to the DAC register. Gain is the gain of the output amplifier. By default, it is set to x1. The gain can also be set to x2 using the gain bit in the write control register. DAC ARCHITECTURE The AD5683R/AD5682R/AD5681R/AD5683 implements segmented string DAC architecture with an internal output buffer. Figure 47 shows the internal block diagram. VREF 2.5V REF INPUT REGISTER DAC REGISTER REF (+) RESISTOR STRING VOUT GND 11955-047 REF (-) The AD5683R/AD5682R/AD5681R on-chip reference is on at power-up but can be disabled via a write to the write control register. The AD5683R/AD5682R/AD5681R each have a 2.5 V, 2 ppm/C reference, giving a full-scale output of 2.5 V or 5 V, depending on the state of the gain bit. The internal reference is available at the VREF pin. It is internally buffered and capable of driving external loads of up to 50 mA. External Reference The VREF pin is an input pin in the AD5683. It can also be configured as an input pin on the AD5683R/AD5682R/AD5681R, allowing the use of an external reference if the application requires it. In the AD5683R/AD5682R/AD5681R, the default condition of the on-chip reference is on at power-up. Before connecting an external reference to the pin, disable the internal reference by writing to the REF bit (Bit DB16) in the write control register. Figure 47. DAC Channel Architecture Block Diagram Rev. D | Page 19 of 28 AD5683R/AD5682R/AD5681R/AD5683 Data Sheet Output Buffer The output buffer is designed as an input/output rail-to-rail, which gives a maximum output voltage range of up to VDD. The gain bit sets the segmented string DAC gain to x1 or x2, as shown in Table 12. The output buffer can drive a 10 nF capacitance with a 2 k resistor in parallel, as shown in Figure 41 and Figure 44. If a higher capacitance load is required, use the snubber method or a shunt resistor to isolate the load from the output amplifier. The slew rate is 0.7 V/s with a 1/4 to 3/4 scale settling time of 5 s. The output buffer voltage is determined by VREF, the gain bit, and the offset and gain errors. Rev. D | Page 20 of 28 Data Sheet AD5683R/AD5682R/AD5681R/AD5683 SERIAL INTERFACE The AD5683R/AD5682R/AD5681R/AD5683 uses a 3-wire serial interface that is compatible with some SPI modes, Mode 1 and Mode 2, as well as with completely synchronous interfaces such as SPORT. See Figure 4 for a timing diagram of a typical write sequence. See the AN-1248 Application Note for more information about the SPI interface. SHORT WRITE OPERATION (AD5681R ONLY) SPI SERIAL DATA INTERFACE If SYNC is brought high between 16 and 24 clock edges, this is interpreted as a valid write and only the first 16 bits are decoded, as shown in Figure 49. If SYNC is brought high before 16 falling clock edges, the serial write is ignored and the write sequence is considered invalid. If the DCEN bit is enabled, this functionality is not available (see Table 11). The AD5681R SPI serial interface allows data to be transferred using a smaller number of clocks, if required. The last eight bits are don't care bits if the input or DAC registers are written as shown in Table 9. To increase the DAC update rate, the size of the data-word can be reduced. Pulling low SYNC pin, the internal input shift register is enabled, the data in the SDI pin is sampled into the input shift register on the falling edge of SCLK. The SYNC pin must be held low until the complete data-word (24-bits) is loaded from the SDI pin (see Figure 4). When SYNC returns high, the serial data-word is decoded, following the instructions in Table 9. SDO Pin Between consecutive data-words, SYNC must be held high for a minimum of 20 ns. Between consecutive DAC updates, SYNC must be held high for more than 20 ns to satisfy the DAC update condition as shown in Figure 4. The serial data output pin (SDO), which is available only in the AD5683R, serves two purposes: to read back the contents of the DAC registers and to connect the device in daisy-chain mode. The SDO pin contains a push-pull output that internally includes a weak pull-down resistor. The data is clocked out of SDO on the rising edge of SCLK, as shown in Figure 4, and the pin is active only when the DCEN bit is enabled in the write control register or automatically enabled during a readback command. In standby mode, the internal pull-down resistor forces a Logic 0 on the bus. Due to the high value of the internal pull-down resistor, other devices can have control over the SDO line if a parallel connection is made. If SYNC is brought high after 24 falling clock edges, it is interpreted as a valid write, and the first 24 bits are loaded to the input shift register. To minimize power consumption, it is recommended that all serial interface pins be operated close to the supply rails. SCLK DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 SYNC Figure 49. Short Write on the AD5681R Rev. D | Page 21 of 28 DB0 X X X X X X X X 11955-049 SDI AD5683R/AD5682R/AD5681R/AD5683 Data Sheet Daisy-Chain Connection Daisy chaining minimizes the number of pins required from the controlling IC. As shown in Figure 50, the SDO pin of one package must be tied to the SDI pin of the next package. The clock period may need to be increased, as shown in Table 4, because of the propagation delay of the line between subsequent devices. By default, the SDO pin is disabled. To enable daisy-chain operation, the DCEN bit must be set in the write control register (see Table 10). When the daisy-chain mode is enabled (DCEN = 1), the AD5683R/AD5682R/AD5681R/AD5683 accept as a valid frame any data-word larger than 24 bits, decoding the last 24 bits received, as shown in Figure 51. AD5683R U1 CONTROLLER MOSI SDI SCLK SCLK SS SYNC SDO MISO SDI AD5683R U2 SCLK SDO 11955-050 SYNC Figure 50. Daisy-Chain Connection SCLK 24 48 SYNC DB23 DB0 DB23 DB0 INPUT WORD FOR DAC 1 INPUT WORD FOR DAC 2 DB23 SDO_U1 UNDEFINED DB0 INPUT WORD FOR DAC 2 Figure 51. Daisy-Chain Timing Diagram Rev. D | Page 22 of 28 11955-051 MOSI Data Sheet AD5683R/AD5682R/AD5681R/AD5683 INTERNAL REGISTERS COMMANDS Input Shift Register Write Input Register The shift register of the AD5683R/AD5682R/AD5681R/AD5683 is 24 bits wide. Serial data is loaded MSB first (DB23) and the first four bits are the command bits, C3 to C0, followed by the data bits. The input register allows the preloading of a new value for the DAC register. The transfer from the input register to the DAC register can be triggered by hardware, by the LDAC pin, or by software using Command 2. The data bits comprise a 20-bit, 18-bit, or 16-bit input code, followed by a number of don't care bits as shown in Table 9. The command is decoded on the rising edge of SYNC. If new data is loaded into the DAC register directly using Command 3, the DAC register automatically overwrites the input register. Input Register Update DAC Register The input register acts as a buffer to preload new data. This register does not control the voltage in the VOUT pin. There are two different ways to transfer the contents of the input register to the DAC register: by software or by hardware. This command transfers the contents of the input register to the DAC register and, consequently, the VOUT pin is updated. This operation is equivalent to a software LDAC. Write DAC Register DAC Register The DAC register controls the output voltage in the DAC. This command updates the DAC register on completion of the write operation. The input register is refreshed automatically with the DAC register value. The DAC register controls the voltage in the VOUT pin. This register can be updated by issuing a command or by transferring the contents of the input register to the DAC register. Table 9. Command Operation C3 0 0 0 Command [DB23:DB20] C2 C1 C0 0 0 0 0 0 1 0 1 0 DB19 X DB15 X DB18 X DB14 X DB17 X DB13 X DB16 X DB12 X DB15 X DB11 X Data Bits [DB19:DB0]1 DB14 [DB13:DB8] DB7 X X...X X DB10 DB9...DB4 DB32 X X...X X DB6 X DB22 X DB5 X DB12, 3 X DB4 X DB02, 3 X [DB3:DB0] X...X X...X X...X Operation Do nothing Write input register Update DAC register (software LDAC) Write DAC and input register Write control register Readback input register 0 0 1 1 DB15 DB14 DB13 DB12 DB11 DB10 DB9...DB4 DB32 DB22 DB12, 3 DB02, 3 X...X 0 0 1 1 0 0 0 1 DB19 X DB18 X DB17 X DB16 X DB15 X DB14 X 0...0 X...X 0 X 0 X 0 X 0 X 0...0 X...X X means don't care. This bit is a don't care bit for the AD5681R only. 3 This bit is a don't care bit for the AD5682R only. 1 2 Rev. D | Page 23 of 28 AD5683R/AD5682R/AD5681R/AD5683 Data Sheet Write Control Register In power-down mode, the output buffer is internally disabled and the VOUT pin output impedance can be selected to a wellknown value, as shown in Table 14. The write control register sets the power-down and gain functions. It also enables/disables the internal reference and perform a software reset. See Table 10 for the write control register functionality. Table 14. Operation Modes DCEN Bit Operating Mode Normal Mode Power-Down Modes 1 k Output Impedance 100 k Output Impedance Three-State Output Impedance The daisy-chain enable bit (DCEN, Bit DB14) enables the SDO pin, allowing the device to operate in daisy-chain mode. This bit is automatically disabled when a readback command is executed. Enabling this bit disables the write short command feature in the AD5681R. In power-down mode, the device disables the output buffer but does not disable the internal reference. To achieve maximum power savings, it is recommend to disable the REF bit, if possible. Table 11. Daisy-Chain Enable Bit (DCEN) Disabling both the internal reference and the output buffer results in the supply current falling to 2 A at 5 V. Table 10. Write Control Register Bits DB0 0 1 DB18 PD1 DB17 PD0 DB16 REF DB15 Gain DB14 DCEN Mode Standalone mode (default) DCEN mode PD0 0 0 1 1 1 0 1 The output stage is shown in Figure 52. DAC Gain Bit The gain bit selects the gain of the output amplifier. Table 12 shows how the output voltage range corresponds to the state of the gain bit. AMPLIFIER POWER-DOWN CIRCUITRY VOUT RESISTOR NETWORK Table 12. Gain Bit Gain 0 1 Output Voltage Range 0 V to VREF (default) 0 V to 2 x VREF Figure 52. Output Stage During Power-Down REF Bit The on-chip reference is on at power-up by default. This reference can be turned on or off by setting a software-programmable bit, DB16, in the write control register. Table 13 shows how the state of the bit corresponds to the mode of operation. To reduce the power consumption, it is recommended to disable the internal reference if the device is placed in powerdown mode. The output amplifier is shut down when the power-down mode is activated. However, unless the internal reference is powered down (using Bit DB16 in the write control register), the bias generator, reference, and resistor string remain on. When in power-down mode, the weak SDO resistor is also disconnected. The supply current falls to 2 A at 5 V. The contents of the DAC register are unaffected when in power-down mode, and the DAC register can continue to be updated. The time that is required to exit power-down is typically 4 s for VDD = 5 V, or 600 s if the reference is disabled. Reset Bit The write control register of the AD5683R/AD5682R/AD5681R contains a software reset function that resets the input and DAC registers to zero scale and resets the write control register to the default value. A software reset is initiated by setting the reset bit (Bit DB19) in the write control register to 1. When the software reset is complete, the reset bit is cleared to 0 automatically. Table 13. Reference Bit (REF) REF 0 1 11955-052 DB19 Reset PD1 0 Reference Function Reference enabled (default) Reference disabled PD0 and PD1 Bits The AD5683R/AD5682R/AD5681R contain two separate mode of operation that are accessed by writing to the write control register. In normal mode, the output buffer is directly connected to the VOUT pin. Rev. D | Page 24 of 28 Data Sheet AD5683R/AD5682R/AD5681R/AD5683 Readback Input Register HARDWARE LDAC The AD5683R allows readback of the contents of the input register through the SDO pin by using Command 5 (see Table 9), as shown in Figure 53. The DACs of the AD5683R/AD5682R/AD5681R/AD5683 have a double buffered interface consisting of an input register and a DAC register. The LDAC transfers data from the input register to the DAC register and, consequently, the output is updated. The SDO pin is automatically enabled for the duration of the read operation, after which it is disabled again, as shown in Table 15. If the DCEN bit was enabled before the read operation, the bit is reset after a readback operation. If the AD5683R was operating in daisy-chain mode, the user must enable the DCEN bit again. Table 15. Write and Readback sequence SDI 0x180000 0x500000 0x000000 Action Write 0x8000 to the input register Prepare data read from the input register Clock out the data X mean don't care. If LDAC is pulsed while the data is being clocked, the pulse is ignored. HARDWARE RESET RESET is an active low signal that sets the input and DAC registers to zero scale and the control registers to their default values. It is necessary to keep RESET low for 75 ns to complete the operation. When the RESET signal returns high, the output remains at the zero scale until a new value is programmed. While the RESET pin is low, the AD5683R/AD5681R ignore any new command. If RESET is held low at power-up, the internal reference is not initialized correctly until the RESET pin is released. SCLK 24 1 24 1 SYNC SDI DB23 DB0 DB23 DB0 NOP CONDITION READBACK COMMAND DB23 SDO DB0 DATA Figure 53. Readback Operation Rev. D | Page 25 of 28 11955-054 1 SDO 0x000000 0x000000 0xX8000X1 Hold LDAC high while data is clocked into the input shift register. The DAC output is updated by taking LDAC low after SYNC is taken high. The output DAC is updated on the falling edge of LDAC. AD5683R/AD5682R/AD5681R/AD5683 Data Sheet THERMAL HYSTERESIS LAYOUT GUIDELINES Thermal hysteresis is the voltage difference induced on the reference voltage by sweeping the temperature from ambient to cold, to hot, and then back to ambient. In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board (PCB) on which the ADCs are mounted must be designed such that the AD5683R/ AD5682R/AD5681R/AD5683 lie on the analog plane. The thermal hysteresis data is shown in Figure 54. It is measured by sweeping the temperature from ambient to -40C, then to +105C, and finally returning to ambient. The VREF delta is next measured between the two ambient measurements; the result is shown in a solid line in Figure 54. The same temperature sweep and measurements were immediately repeated; the results are shown in a patterned line in Figure 54. 6 FIRST TEMPERATURE SWEEP SUBSEQUENT... NUMBER OF HITS 5 In systems where there are many devices on one board, it is often useful to provide some heat sinking capability to allow the power to dissipate easily. 4 3 2 -80 -60 -40 -20 0 DISTORTION (ppm) 20 40 60 11955-055 1 0 -100 Ensure that the AD5683R/AD5682R/AD5681R/AD5683 have ample supply bypassing of 10 F, in parallel with a 0.1 F capacitor on each supply that is located as near to the package as possible (ideally, right up against the device). The 10 F capacitors are of the tantalum bead type. The 0.1 F capacitor must have low effective series resistance (ESR) and low effective series inductance (ESI), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. Figure 54. Thermal Hysteresis POWER-UP SEQUENCE Because there are diodes to limit the voltage compliance at the digital pins and analog pins, it is important to power GND first before applying any voltage to VDD, VOUT, and VLOGIC. Otherwise, the diode is forward-biased such that VDD is powered unintentionally. The ideal power-up sequence is GND, VDD, VLOGIC, VREF, followed by the digital inputs. The LFCSP packages of the AD5683R/AD5682R/AD5681R/ AD5683 have an exposed pad beneath the device. Connect this pad to the GND supply of the device. For optimum performance, use special consideration when designing the motherboard and mounting the package. For enhanced thermal, electrical, and board level performance, solder the exposed pad on the bottom of the package to the corresponding thermal land pad on the PCB. Design thermal vias into the PCB land pad area to further improve heat dissipation. The GND plane on the device can be increased (as shown in Figure 55) to provide a natural heat sinking effect. AD5683R/ AD5682R/ AD5681R/ AD5683 RECOMMENDED REGULATOR The analog and digital supplies required for the AD5683R/ AD5682R/AD5681R/AD5683 can be generated using Analog Devices, Inc., low dropout (LDO) regulators such as the ADP7118 and the ADP162, respectively, for analog and digital supplies. Rev. D | Page 26 of 28 GND PLANE BOARD Figure 55. Pad Connection to Board 11955-056 The AD5683R/AD5682R/AD5681R/AD5683 use a 5 V (VDD) supply as well as a digital logic supply (VLOGIC). Data Sheet AD5683R/AD5682R/AD5681R/AD5683 OUTLINE DIMENSIONS 1.70 1.60 1.50 2.10 2.00 SQ 1.90 0.50 BSC 8 5 PIN 1 INDEX AREA 0.15 REF 1.10 1.00 0.90 EXPOSED PAD 0.425 0.350 0.275 BOTTOM VIEW 0.60 0.55 0.50 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.30 0.25 0.20 01-14-2013-C 0.05 MAX 0.02 NOM SEATING PLANE PIN 1 INDICATOR (R 0.15) 1 4 TOP VIEW 0.20 REF Figure 56. 8-Lead Lead Frame Chip Scale Package [LFCSP_UD] 2.00 mm x 2.00 mm Body, Ultrathin, Dual Lead (CP-8-10) Dimensions shown in millimeters 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15 MAX 1.10 MAX 0.30 0.15 6 0 0.23 0.13 0.70 0.55 0.40 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 57. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters Rev. D | Page 27 of 28 091709-A 0.15 0.05 COPLANARITY 0.10 AD5683R/AD5682R/AD5681R/AD5683 Data Sheet ORDERING GUIDE Model1 AD5683RACPZ-RL7 AD5683RACPZ-1RL7 AD5683RACPZ-2RL7 AD5683RARMZ AD5683RARMZ-RL7 AD5683RBRMZ AD5683RBRMZ-RL7 AD5683RBRMZ-3 AD5683RBRMZ-3-RL7 AD5683RBCPZ-RL7 AD5683RBCPZ-1RL7 AD5683BCPZ-RL7 Resolution (Bits) 16 16 16 16 16 16 16 16 16 16 16 16 Pinout LDAC VLOGIC RESET VLOGIC VLOGIC VLOGIC VLOGIC SDO SDO LDAC VLOGIC LDAC Temperature Range -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C Performance A Grade A Grade A Grade A Grade A Grade B Grade B Grade B Grade B Grade B Grade B Grade B Grade Package Description 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 8-Lead LFCSP_UD 8-Lead LFCSP_UD 8-Lead LFCSP_UD Package Option CP-8-10 CP-8-10 CP-8-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 CP-8-10 CP-8-10 CP-8-10 Branding 94 95 96 DHY DHY DHZ DHZ DJ0 DJ0 97 DX 9A AD5682RBCPZ-RL7 14 LDAC -40C to +105C B Grade 8-Lead LFCSP_UD CP-8-10 9B AD5681RBCPZ-RL7 AD5681RBCPZ-1RL7 AD5681RBRMZ AD5681RBRMZ-RL7 EVAL-AD5683RSDZ 12 12 12 12 LDAC VLOGIC VLOGIC VLOGIC -40C to +105C -40C to +105C -40C to +105C -40C to +105C B Grade B Grade B Grade B Grade 8-Lead LFCSP_UD 8-Lead LFCSP_UD 10-Lead MSOP 10-Lead MSOP Evaluation Board CP-8-10 CP-8-10 RM-10 RM-10 98 99 DHX DHX 1 Z = RoHS Compliant Part. (c)2013-2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11955-0-12/16(D) Rev. D | Page 28 of 28