CCD image sensors S11071/S10420-01 series
2
Structure
Absolute maximum ratings (Ta=25 °C)
Operating conditions (MPP mode, Ta=25 °C)
Parameter S11071 series S10420-01 series
Pixel size (H × V) 14 × 14 μm
Vertical clock phase 2-phase
Horizontal clock phase 4-phase
Output circuit Two-stage MOSFET source follower One-stage MOSFET source follower
Package 24-pin ceramic DIP (refer to dimensional outline)
Window material*1Quartz glass*2
Cooling Non-cooled
*1: Temporary window type (ex: S11071-1106N, S10420-1106N-01) is available upon request.
*2: Resin sealing
Parameter Symbol Min. Typ. Max. Unit
Operating temperature*3Topr -50 - +50 °C
Storage temperature Tstg -50 - +70 °C
Output transistor
drain voltage
S11071 series VOD -0.5 - +25 V
S10420-01 series -0.5 - +30
Reset drain voltage VRD -0.5 - +18 V
Output amplifi er return voltage Vret -0.5 - +18 V
Overfl ow drain voltage VOFD -0.5 - +18 V
Vertical input source voltage VISV -0.5 - +18 V
Horizontal input source voltage VISH -0.5 - +18 V
Overfl ow gate voltage VOFG -10 - +15 V
Vertical input gate voltage VIG1V, VIG2V -10 - +15 V
Horizontal input gate voltage VIG1H, VIG2H -10 - +15 V
Summing gate voltage VSG -10 - +15 V
Output gate voltage VOG -10 - +15 V
Reset gate voltage VRG -10 - +15 V
Transfer gate voltage VTG -10 - +15 V
Vertical shift register clock voltage VP1V, VP2V -10 - +15 V
Horizontal shift register clock voltage VP1H, VP2H
VP3H, VP4H -10 - +15 V
Note: Exceeding the absolute maximum ratings even momentarily may cause a drop in product quality. Always be sure to use the
product within the absolute maximum ratings.
*3: Package temperature
Parameter Symbol S11071 series S10420-01 series Unit
Min. Typ. Max. Min. Typ. Max.
Output transistor drain voltage VOD 12 15 18 23 24 25 V
Reset drain voltage VRD 14 15 16 11 12 13 V
Overfl ow drain voltage VOFD 11 12 13 11 12 13 V
Overfl ow gate voltage VOFG 0 13 14 0 12 13 V
Output gate voltage VOG 4 56456 V
Substrate voltage VSS - 0 - - 0 - V
Output amplifi er return voltage Vret - 1 2 V
Test point
Input source VISV, VISH - VRD - - VRD - V
Vertical input gate VIG1V, VIG2V -9 -8 - -9 -8 - V
Horizontal input gate VIG1H, VIG2H -9 -8 - -9 -8 - V
Vertical shift register clock voltage High VP1VH, VP2VH 4 68468 V
Low VP1VL, VP2VL -9 -8 -7 -9 -8 -7
Horizontal shift register clock voltage
High VP1HH, VP2HH
VP3HH, VP4HH 468468
V
Low VP1HL, VP2HL
VP3HL, VP4HL -6 -5 -4 -6 -5 -4
Summing gate voltage High VSGH 4 68468 V
Low VSGL -6 -5 -4 -6 -5 -4
Reset gate voltage High VRGH 468468 V
Low VRGL -6 -5 -4 -6 -5 -4
Transfer gate voltage High VTGH 468468 V
Low VTGL -9 -8 -7 -9 -8 -7
External load resistance RL
2.0 2.2 2.4 90 100 110 k
Ω