1
FN8230.4
ISL90462
Single Volatile 32-tap XDCP
Digitally Controlled Potentiometer
(XDCP™)
The Intersil ISL90462 is a digitally controlled potentiometer
(XDCP). Configured as a variable resistor, the device
consists of a resistor array, wiper switches, a control section,
and volatile memory. The wiper position is controlled by a 2-
pin Up /Down interface.
The potentiometer is implemented by a resistor array
composed of 31 resistive elements and a wiper switching
network. Between each element and at either end are tap
points accessible to the wiper terminal. The position of the
wiper element is controlled by the CS and U/D inputs.
The device can be used in a wide variety of applications
including:
• LCD contrast control
• Parameter and bias adjustments
• Industrial and Automotive Control
• Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
• Laser Diode driver biasing
• Gain control and offset adjustment
Features
• Volatile Solid-State Potentiometer
• 2-pin UP/DN Interface
• DCP Terminal Voltage, 2.7V to 5.5V
• Tempco 35ppm/°C Typical
• 32 Wiper Tap Points
• Low Power CMOS
- Active current, 25µA max.
- Supply current 0.3µA
• Available RTOTAL Values = 10k50k100k
• Temperature Range -40°C to +85°C
• Packages
- 6 Ld SC-70, SOT-23
• Pb-Free Plus Anneal Available (RoHS Compliant)
Pinout
ISL90462
(SOT23, SC70)
TOP VIEW
VDD
GND
U/D CS
RW
RH
Ordering Information
PART NUMBER PART MARKING RTOTAL (K) TEMP RANGE (°C) PACKAGE (Tape and Reel) PKG. DWG. #
ISL90462WIE627Z-TK (See Note) DEK 10 -40 to +85 6 Ld SC-70 (Pb-free) P6.049
ISL90462WIH627Z-TK (See Note) DEL -40 to +85 6 Ld SOT-23 (Pb-free) P6.064
ISL90462UIE627Z-TK (See Note) DEI 50 -40 to +85 6 Ld SC-70 (Pb-free) P6.049
ISL90462UIH627Z-TK (See Note) DEJ -40 to +85 6 Ld SOT-23 (Pb-free) P6.064
ISL90462TIE627Z-TK (See Note) DEG 100 -40 to +85 6 Ld SC-70 (Pb-free) P6.049
ISL90462TIH627Z-TK See Note)
(No longer available,
recommended replacement:I
SL90462UIE627Z-TK)
DEH -40 to +85 6 Ld SOT-23 (Pb-free) P6.064
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are
RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020
Data Sheet October 20, 2015
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas LLC 2005, 2015. All Rights Reserved
XDCP and Intersil (and design) are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
2FN8230.4
October 20, 2015
Block Diagram
CONTROL
AND
MEMORY
UP/DOWN
(U/D)
DEVICE SELECT
(CS)
GND (GROUND)
RH
RW
GENERAL
VCC
Pin Descriptions
6-PIN SYMBOL DESCRIPTION
1 VDD Supply voltage
2 GND Ground/Low terminal
3U/D
Up - Down
4CSChip select
5 RW Wiper terminal
6 RH High terminal
ISL90462
3FN8230.4
October 20, 2015
Equivalent Circuit
Absolute Maximum Ratings Recommended Operating Conditions
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on CS, U/D and VCC With Respect to GND. . . . -1V to +7V
Lead Temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . . . 300°C
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1mW
Temperature Range (Industrial) . . . . . . . . . . . . . . . . . . -40°C to 85°C
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may c ause permanent damage to the device . This i s a stress rating only; functional operation
of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating
conditions f or exten ded period s may af fect devi ce re lia bili ty.
Potentiometer Specifications Over recommended operating conditions unless otherwise stated.
SYMBOL PARAMETER TEST CONDITIONS MIN
TYP
(Note 4) MAX UNIT
RTOT End to end resistance W version 8 10 12 k
U version 40 50 60 k
T version 80 100 120 k
VRRH, RL terminal voltages 0 VCC V
Noise Ref: 1kHz -120 dBV
RW Wiper Resistance 600
IWWiper Current 0.6 mA
Resolution 132Taps
Absolute linearity (Note 1) RH(n)(actual) -R
H(n)(expected) ±1 MI
(Note 3)
Relative linearity (Note 2) RH(n+1) -[R
H(n) + MI]±0.5MI
(Note 3)
RTOTAL temperature coefficient ±35 ppm/°C
CH/CL/CWPotentiometer capacitances See Equivalent Circuit 10/10/25 pF
NOTES:
1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = (RH(n)(actual)-RH(n)(expected)) = ±1 Ml Maximum.
n = 1 .. 29 only
2. Relative linearity is a measure of the error in step size between taps = RH(n+1)-[RH(n) + Ml] = ±0.5 Ml, n = 1 .. 29 only.
3. 1 Ml = Minimum Increment = RTOT/31.
4. Typical values are for TA = 25°C and nominal supply voltage.
CHCL
RW
RTOTAL
CW
RHRL
ISL90462
4FN8230.4
October 20, 2015
DC Electrical Specifications Over recommended operating conditions unless otherwise specified.
SYMBOL PARAMETER TEST CONDITIONS MIN
TYP
(NOTE 4) MAX UNIT
ICC VCC active current (Increment) CS = 0V, U/D = fclock = 1MHz and VCC = 3V 25 µA
ISB Standby supply current CS = VCC, U/D = GND or VCC = 3V 0.3 1 µA
ILI CS input leakage current VIN = GND to VCC ±1 µA
VIH CS, U/D input HIGH voltage VCC x 0.7 V
VIL CS, U/D input LOW voltage VCC x 0.3 V
CIN CS, U/D input capacitance VCC = 3V, VIN = GND, TA= 25°C, f = 1MHz 10 pF
Timing Specifications Over recommended operating conditions unless otherwise specified
SYMBOL PARAMETER MIN TYP (Note 4) MAX UNIT
tCU U/D to CS setup 25 ns
tCI CS to U/D setup 50 ns
tIC CS to U/D hold 25 ns
tlL U/D LOW period 300 ns
tlH U/D HIGH period 300 ns
fTOGGLE Up/Down toggle Rate 1 MHz
tSETTLE Output settling time 1 µs
CS
U/D
RW
tCU
tCI
tIL
tIH
tIC
tSETTLE
FIGURE 1. SERIAL INTERFACE TIMING DIAGRAM, INCREMENT
ISL90462
5FN8230.4
October 20, 2015
Pin Descriptions
RH and RW
The ISL90462 contains a digital potentiometer with one
terminal tied to the ground pin (GND) of the device. The RH
pin is the other potentiometer terminal, and the RW pin is the
wiper terminal. The position of the wiper is controlled by the
CS- and U/D- inputs, with a movement "up" connecting the
wiper closer to the RH pin, and movement "down"
connection the wiper closer to the GND pin.
Up/Down (U/D)
The U/D input controls the direction of the wiper movement
and whether the counter is incremented or decremented.
Chip Select (CS)
The device is selected when the CS input is LOW. The
current counter value is stored in volatile memory when CS
is returned HIGH. When CS is high, the device is placed in
low power standby mode.
Principles of Operation
There are two sections of the ISL90462: the input control,
counter and decode section; and the resistor array. The input
control section operates just like an up/down counter. The
output of this counter is decoded to turn on a single
electronic switch connecting a point on the resistor array to
the wiper output. The resistor array is comprised of 31
individual resistors connected in series. At either end of the
array and between each resistor is an electronic switch that
transfers the connection at that point to the wiper. The RH
and RW terminals are uncommitted, and can for a variable
voltage divider if RH is connected to a voltage source.
The direction of the wiper movement is defined when the
device is selected. If during CS transition from High to Low
the U/D input is LOW, the wiper will move down on each
rising edge of U/D toggling. Similarly, the wiper will move up
on each rising edge of U/D toggling if, during CS transition
from High to Low, the U/D input is High.
The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.
If the wiper is moved several positions, multiple taps are
connected to the wiper for tSETTLE (U/D to RW change).
The 2-terminal resistance value for the device can
temporarily change by a significant amount if the wiper is
moved several positions.
CS
U/D
RW
tCU
tCI
tIL
tIH
tIC
tSETTLE
FIGURE 2. SERIAL INTERFACE TIMING DIAGRAM DECREMENT
ISL90462
6FN8230.4
October 20, 2015
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE REVISION CHANGE
October 20, 2015 FN8230.4 - Updated Ordering Information Table on page 1.
- Added Revision History.
- Added About Intersil Verbiage.
- Updated POD P6.064 to latest revision changes are as follow:
Update to new format (same dimensions, added land pattern and moved dimensions from table onto
drawing)
- Updated POD P6.049 to latest revision changes are as follow:
Added pin 1 cross-hatched index area to top view.
Added Note 8, it reference to Pin 1 Index Area.
A2 minimum measurement changed from 0.00 to 0.79.
ISL90462
7FN8230.4
October 20, 2015
ISL90462
Package Outline Drawing
P6.064
6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 4, 2/10
Dimension is exclusive of mold flash, protrusions or gate burrs.
Package conforms to JEDEC MO-178AB.
Foot length is measured at reference to guage plane.
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to ASME Y14.5M-1994.
5.
3.
4.
2.
Dimensions are in millimeters.1.
NOTES:
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
END VIEW
INDEX AREA
PIN 1
SEATING PLANE
GAUGE
0.45±0.1
(2 PLCS)
10° TYP
4
1.90
0.40 ±0.10
2.90 ±0.10
0.95
1.60 +0.15/-0.10
2.80
0.00-0.15
1.15 +0.15/-0.25
0.20 CA-B DM
(1.20)
(0.60)
(0.95)
(2.40)
0.10 C
0.08-0.22
SEE DETAIL X
(0.25)
1.45 MAX
(0.60)
0-8°
C
B
A
D
3
3
3
3
0.20 C
2x
123
654
PLANE
8
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of I nter sil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8230.4
October 20, 2015
ISL90462
Small Outline Transistor Plastic Packages (SC70-6)
D
e1
E
C
L
e
b
C
L
A2
AA1
C
L
0.20 (0.008) M
0.10 (0.004) C
C
-C-
SEATING
PLANE
12 3
456
E1
C
L
C
VIEW C
VIEW C
L
R1
R
4X 1
4X 1
GAUGE PLANE
L1
SEATING
L2
C
PLANE
c
BASE METAL
WITH
c1
b1
PLATING
b
PIN 1
INDEX AREA
8
P6.049
6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.031 0.043 0.80 1.10 -
A1 0.000 0.004 0.00 0.10 -
A2 0.031 0.039 0.79 1.00 -
b 0.006 0.012 0.15 0.30 -
b1 0.006 0.010 0.15 0.25
c 0.003 0.009 0.08 0.22 6
c1 0.003 0.009 0.08 0.20 6
D 0.073 0.085 1.85 2.15 3
E 0.071 0.094 1.80 2.40 -
E1 0.045 0.053 1.15 1.35 3
e 0.0256 Ref 0.65 Ref -
e1 0.0512 Ref 1.30 Ref -
L 0.010 0.018 0.26 0.46 4
L1 0.017 Ref. 0.420 Ref.
L2 0.006 BSC 0.15 BSC
N665
R 0.004 - 0.10 -
R1 0.004 0.010 0.15 0.25
0o8o0o8o-
Rev. 4 12/12
NOTES:
1. Dimensioning and tolerance per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC70 and JEDEC MO203AB.
3. Dimensions D and E1 are exclusive of mold flash, protrusions,
or gate burrs.
4. Footlength L measured at reference to gauge plane.
5. “N” is the number of terminal positions.
6. These Dimensions apply to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
7. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only.
8. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
