5
dc1338af
DEMO MANUAL DC1338A
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represent a-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
SCHEMATIC DIAGRAM
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+5V
VUNREG
SCK/SCL
EEGND
EESDA
EESCL
EEVCC
REVISION HISTORY
DESCRIPTION DATE
APPROVED
ECO REV
REVISION HISTORY
DESCRIPTION DATE
APPROVED
ECO REV
REVISION HISTORY
DESCRIPTION DATE
APPROVED
ECO REV
TECHNOLOGY
Leo C.
TECHNOLOGY
Leo C.
TECHNOLOGY
Leo C.
E7
V4
E7
V4 C2
0.1uF
C2
0.1uF
TP2
SDA
TP2
SDA
JP4
1
0
ADR0
JP4
1
0
ADR0
1
3
2
Q1
FMMT3906
Q1
FMMT3906
E1
VCC
EXT
E1
VCC
EXT
JP7
TEMP
VOLT
V4
JP7
TEMP
VOLT
V4
1
3
2
TP1
SCL
TP1
SCL
J1J1
1
3
2
4
5
6
7
8
9
10
11
13
12
14
R1
4.99K
1%
R1
4.99K
1%
E6
V3
E6
V3
E8
GND
E8
GND
JP2
EXT
INT
VCC
JP2
EXT
INT
VCC
1
3
2
JP6
TEMP
VOLT
V3
JP6
TEMP
VOLT
V3
1
3
2
C4
470pF
C4
470pF
E3
V+
E3
V+
E4
V1
E4
V1
V3
3
SDA 6
V2
2
ADR0 8
V4
4
SCL 7
V1
1
VCC 10
ADR1 9
GND 5
E2
GND
E2
GND
Q2
FMMT3904
Q2
FMMT3904
JP5
TEMP
VOLT
V2
JP5
TEMP
VOLT
V2
1
3
2
JP1
1
0
ADR1
JP1
1
0
ADR1
1
3
2
C3
470pF
C3
470pF
E5
V2
E5
V2
U2
24LC025-I/ST
U2
24LC025-I/ST
A0 1
A1 2
A2 3
VSS 4
VCC
8
WP
7
SCL
6
SDA
5
R2
4.99K
1%
R2
4.99K
1%
JP3
TEMP
VOLT
V1
JP3
TEMP
VOLT
V1
1
3
2
C1
0.1uF
C1
0.1uF